Array substrate, display panel, and display apparatus

Abstract

The present application provides an array substrate, a display panel, and a display apparatus. The array substrate comprises a substrate, a driver circuit layer, and a light-shielding layer. The driver circuit layer is disposed on a side of the substrate and comprises a plurality of signal traces disposed in an array area. The light-shielding layer is disposed between the substrate and the driver circuit layer, and comprises at least two conductive layers arranged in a stacked configuration, and further comprises a plurality of connecting lines located in a peripheral area, wherein the plurality of connecting lines are respectively connected to the plurality of signal tracings.

Description

Array substrate, display panel and display device TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to an array substrate, a display panel and a display device. BACKGROUND

[0002] At present, the performance improvement demand of display panel for notebook computers, tablets and vehicle-mounted display products is urgent, and the display product application end puts forward higher challenges to narrow frame.

[0003] Therefore, how to realize the narrow frame of product application end is a technical problem to be solved. SUMMARY

[0004] The present application provides an array substrate, a display panel and a display device to reduce the size of the peripheral area of the array substrate, thereby reducing the size of the frame of the display panel.

[0005] In a first aspect, the present application provides an array substrate, the array substrate has an array area and a peripheral area surrounding the array area, and the array substrate comprises:

[0006] a substrate;

[0007] a driving circuit layer arranged on one side of the substrate and comprising a plurality of signal traces arranged in the array area; and

[0008] a light shielding layer arranged between the substrate and the driving circuit layer, comprising at least two layers of stacked conductive layers, and comprising a plurality of connection lines in the peripheral area, and the plurality of connection lines are respectively connected with the plurality of signal traces.

[0009] In a second aspect, the present application further provides a display panel, which comprises the array substrate of any of the above embodiments.

[0010] In a third aspect, the present application further provides a display device, which comprises the display panel of any of the above embodiments. ADVANTAGEOUS EFFECTS

[0011] In some embodiments of the array substrate, the display panel and the display device, the light shielding layer comprises at least two conductive layers stacked, and comprises a plurality of connection lines in the peripheral area. The plurality of connection lines are respectively connected with a plurality of signal lines in the array area. In this way, the plurality of connection lines comprise at least two conductive layers stacked, the impedance of the plurality of connection lines is small, the speed of the connection lines transmitting signals to the signal lines is fast, and the performance of the display panel is improved. Moreover, the signal lines in the peripheral area can be routed by the connection lines of the light shielding layer, which facilitates the multi-layer routing of the signal lines in the peripheral area, thereby reducing the space occupied by the signal lines in the peripheral area, and the display panel can realize a narrow frame. BRIEF DESCRIPTION OF DRAWINGS

[0012] FIG. 1 is a schematic plan view of an array substrate according to some embodiments of the present application;

[0013] FIG. 2 is a schematic plan view of an array substrate according to other embodiments of the present application;

[0014] FIG. 3 is a schematic plan view of an array substrate according to further embodiments of the present application;

[0015] FIG. 4 is a schematic cross-sectional view taken along the A-A' line in FIG. 1;

[0016] FIG. 5 is a schematic cross-sectional view taken along the B-B' line in FIG. 1;

[0017] FIG. 6 is another schematic cross-sectional view taken along the A-A' line in FIG. 1;

[0018] FIG. 7 is another schematic cross-sectional view taken along the B-B' line in FIG. 1;

[0019] FIG. 8 is a partial schematic plan view of an array substrate according to some embodiments of the present application;

[0020] FIG. 9 is a partial schematic plan view of an array substrate according to other embodiments of the present application;

[0021] FIG. 10 is a partial schematic plan view of an array substrate according to further embodiments of the present application;

[0022] FIG. 11 is a partial schematic plan view of an array substrate according to further embodiments of the present application;

[0023] FIG. 12 is a partial schematic plan view of an array substrate according to further embodiments of the present application;

[0024] FIG. 13 is a partial schematic plan view of an array substrate according to further embodiments of the present application;

[0025] FIG. 14 is a partial schematic plan view of an array substrate according to further embodiments of the present application;

[0026] FIG. 15 is a partial plan view of an array substrate of some embodiments of the present application;

[0027] FIG. 16 is a schematic view of a display panel of some embodiments of the present application;

[0028] FIG. 17 is a schematic view of a display device of some embodiments of the present application.

[0029] Reference signs are as follows:

[0030] 300, display panel; 400, backlight module; 500, display device;

[0031] 100, array substrate; 100a, array region; 100b, peripheral region;

[0032] 200, counter substrate;

[0033] 1, substrate;

[0034] 2, drive circuit layer;

[0035] 21, first conductive layer; 211, scan line;

[0036] 22, second conductive layer;

[0037] 23, third conductive layer;

[0038] 24, first transparent conductive layer; 241, pixel electrode;

[0039] 25, second transparent conductive layer; 251, common electrode block; 252, touch electrode;

[0040] 26, semiconductor layer; 261, active layer; 2611, channel portion; 2612, lightly doped portion; 2613, heavily doped portion;

[0041] 27, black matrix;

[0042] 281, first insulating layer; 282, second insulating layer; 283, third insulating layer; 284, fourth insulating layer; 285, fifth insulating layer; 286, sixth insulating layer;

[0043] 3, light shielding layer;

[0044] 31, first metal layer; 32, second metal layer; 33, third metal layer; 34, fourth metal layer;

[0045] 35, connection line; 351, first connection line; 352, second connection line; 36, light shielding portion; 36A, light shielding portion group; 37, light shielding connection portion; 371, hollow portion; 3711, first hollow portion; 3712, second hollow portion;

[0046] 4, signal line; 41, data line; 42, touch line;

[0047] 5, driving unit;

[0048] H1, first via hole; H2, second via hole; H3, third via hole;

[0049] 61, bridge line;

[0050] x, first direction; y, second direction; w, third direction. Embodiments of the present application

[0051] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0052] As shown in FIGS. 1-7, the present application provides an array substrate 100. The array substrate 100 is applied to a display panel 300, which includes at least one of a liquid crystal display panel, an organic light emitting diode display panel, a micro light emitting diode display panel, and a sub-millimeter light emitting diode display panel. The array substrate 100 has an array region 100a and a peripheral region 100b arranged around the array region 100a. The array region 100a overlaps with a display region of the display panel 300. The peripheral region 100b overlaps with a non-display region of the display panel 300.

[0053] The array substrate 100 includes a substrate 1, a driving circuit layer 2, and a light shielding layer 3.

[0054] The substrate 1 can include a hard substrate such as a glass substrate. The substrate 1 can also include a flexible substrate such as a polymer substrate.

[0055] The driving circuit layer 2 includes a plurality of driving circuits. As shown in FIGS. 1-3, 5, and 7, the driving circuit layer 2 is arranged on one side of the substrate 1 and includes a plurality of signal lines 4 arranged in the array region 100a. The plurality of signal lines 4 are used to transmit signals.

[0056] As shown in FIGS. 4-7, the light shielding layer 3 is arranged between the substrate 1 and the driving circuit layer 2. The light shielding layer 3 includes at least two layers of conductive layers arranged in a stack. In this way, the light shielding layer 3 not only has a light shielding effect, but also has a low impedance.

[0057] As shown in FIGS. 1-3, 5, and 7, the light shielding layer 3 includes a plurality of connection lines 35 in the peripheral area 100b. The plurality of connection lines 35 are respectively connected with the plurality of signal lines 4. In this way, the plurality of connection lines 35 include at least two layers of stacked conductive layers, and the connection lines 35 with smaller impedance transmit signals to the signal lines 4 in the array area 100a at a faster speed, thereby improving the performance of the display panel 300. In addition, the signal lines 4 can be routed in the peripheral area 100b by using the connection lines 35 of the light shielding layer 3 in addition to being routed in the peripheral area 100b by using the film layer in which the signal lines 4 are located, which facilitates the multi-layer routing of the signal lines 4 in the peripheral area 100b, thereby reducing the space occupied by the signal lines 4 in the peripheral area 100b, and the display panel 300 can achieve a narrow frame design. In addition, since the light shielding layer 3 is located below the driving circuit layer 2, the light shielding layer 3 is not easily damaged, which reduces the risk of damage to the connection lines 35 connected with the signal lines 4, thereby improving the performance stability of the display panel 300.

[0058] It should be noted that, in the related art, in order to reduce the thickness of the light shielding layer to reduce the risk of fracture of the film layer above the light shielding layer due to climbing, the light shielding layer is usually designed as a single metal layer. In some embodiments of the present application, in order to reduce the impedance of the light shielding layer when applied to routing in the peripheral area 100b, the light shielding layer 3 is adjusted to include at least two conductive layers.

[0059] In some embodiments, the plurality of connection lines 35 are also connected with the driving units 5. In this way, the driving units 5 and the signal lines 4 are connected through the plurality of connection lines 35.

[0060] In some embodiments, as shown in FIGS. 1-3, the plurality of signal lines 4 include at least one of a data line 41 and a touch line 42. It can be understood that the plurality of signal lines 4 can also be other signal lines.

[0061] The data line 41 is used to transmit a data signal. The plurality of data lines 41 extend along the second direction y and are arranged at intervals along the first direction x. The first direction x intersects the second direction y.

[0062] The touch line 42 is used to transmit a touch signal. The plurality of touch lines 42 are insulated from the plurality of data lines 41. The plurality of touch lines 42 extend along the second direction y and are arranged at intervals along the first direction x.

[0063] In some embodiments, the first direction x is perpendicular to the second direction y, but is not limited thereto. The included angle between the first direction x and the second direction y can be an acute angle or an obtuse angle.

[0064] As shown in FIGS. 1-3, the array substrate 100 can further include a plurality of touch electrodes 252, and one touch line 42 is connected with one touch electrode 252. In the figures, the black dots P1 represent the connection positions between the touch lines 42 and the touch electrodes 252.

[0065] In some embodiments, the plurality of data lines 41 and the plurality of touch lines 42 can be located in one conductive layer. In this way, the plurality of data lines 41 and the plurality of touch lines 42 can be formed simultaneously, simplifying the manufacturing process of the plurality of data lines 41 and the plurality of touch lines 42.

[0066] In other embodiments, the data lines 41 and the touch lines 42 can be located in different conductive layers to increase the layout space of the data lines 41 and the touch lines 42.

[0067] In some embodiments, as shown in FIG. 1, the plurality of connection lines 35 are connected with the plurality of data lines 41, respectively, and the connection positions between the connection lines 35 and the data lines 41 are represented by the black dots P2. The plurality of touch lines 42 extend from the array area 100a to the peripheral area 100b and are connected with the driving unit 5. In this way, on the basis of realizing a narrow frame of the display panel 300, the impedance of the wire for transmitting the data signal is reduced, and the refresh rate of the display panel 300 is improved.

[0068] In other embodiments, as shown in FIG. 2, the plurality of connection lines 35 are connected with the plurality of touch lines 42, respectively, and the connection positions between the connection lines 35 and the touch lines 42 are represented by the black dots P2. The plurality of data lines 41 extend from the array area 100a to the peripheral area 100b and are connected with the driving unit 5. In this way, on the basis of realizing a narrow frame of the display panel 300, the impedance of the wire for transmitting the touch signal is reduced, and the touch sensitivity of the display panel 300 is improved.

[0069] In yet other embodiments, as shown in FIG. 3, the plurality of connection lines 35 include a plurality of first connection lines 351 and a plurality of second connection lines 352 arranged at intervals. The plurality of first connection lines 351 are connected with the plurality of data lines 41, respectively. The plurality of second connection lines 352 are connected with the plurality of touch lines 42, respectively. The connection positions between the first connection lines 351 and the data lines 41 and the connection positions between the second connection lines 352 and the touch lines 42 are represented by the black dots P2. In this way, on the basis of realizing a narrow frame of the display panel 300, the impedance of the wire for transmitting the data signal and the touch signal is reduced simultaneously, and the refresh rate and the touch sensitivity of the display panel 300 are improved.

[0070] In some embodiments, as shown in FIG. 5, the connection lines 35 of the peripheral area 100b and the signal wires 4 of the array area 100a can be connected through the first via holes H1.

[0071] In other embodiments, as shown in FIG. 7, the connecting lines 35 of the peripheral area 100b and the signal traces 4 of the array area 100a can be bridged by a bridge line 61. The bridge line 61 is connected with the connecting line 35 through a second via hole H2, and the bridge line 61 is connected with the signal trace 4 through a third via hole H3.

[0072] As shown in FIG. 4 and FIG. 5, in some embodiments, the at least two conductive layers arranged in a stack include a first metal layer 31 and a second metal layer 32, the first metal layer 31 is located between the substrate 1 and the second metal layer 32, and the reflectivity of the first metal layer 31 to light is greater than the reflectivity of the second metal layer 32 to light. In this way, when the array substrate 100 is applied to a liquid crystal display device, the first metal layer 31 reflects the backlight of different directions emitted by the backlight module of the liquid crystal display device, and the reflected backlight is reused after being incident into the backlight module, thereby improving the utilization rate of the backlight and the light efficiency of the panel, and finally improving the display brightness of the display panel 300.

[0073] In some embodiments, the material of the first metal layer 31 is selected from at least one of aluminum, aluminum alloy, copper, and copper alloy. The material of the second metal layer 32 is selected from at least one of molybdenum, molybdenum alloy, titanium, and titanium alloy. In this way, the light shielding layer 3 has low impedance, and the reflectivity of the first metal layer 31 to light is greater than the reflectivity of the second metal layer 32 to light. In addition, the second metal layer 32 protects the first metal layer 31 and reduces the risk of corrosion of the first metal layer 31.

[0074] For example, the first metal layer 31 includes aluminum, and the second metal layer 32 includes molybdenum. In this way, the first metal layer 31 has high reflectivity and low impedance to light, the second metal layer 32 protects the first metal layer 31, and the second metal layer 32 also has high temperature resistance.

[0075] In some embodiments, the thickness of the first metal layer 31 can be greater than the thickness of the second metal layer 32. In this way, the reflection effect of the first metal layer 31 to the backlight is improved, and the utilization rate of the backlight is improved.

[0076] In other embodiments, the thickness of the first metal layer 31 can also be less than or equal to the thickness of the second metal layer 32. In this way, the utilization rate of the backlight is improved, the impedance of the light shielding layer 3 is reduced, and the risk of climbing and disconnection of other film layers caused by the over-thickness of the light shielding layer 3 is reduced.

[0077] As shown in FIG. 6 and FIG. 7, in some embodiments, the at least two conductive layers arranged in a stack include two third metal layers 33 and a fourth metal layer 34, the fourth metal layer 34 is located between the two third metal layers 33, and the conductivity of the material of the fourth metal layer 34 is greater than the conductivity of the material of the third metal layer 33. In this way, the impedance of the light shielding layer 3 is reduced.

[0078] In some embodiments, the material of the third metal layer 33 is selected from at least one of molybdenum, molybdenum alloy, titanium and titanium alloy, and the material of the fourth metal layer 34 is selected from at least one of aluminum, aluminum alloy, copper and copper alloy. In this way, the light shielding layer 3 has low impedance, and meanwhile, the two third metal layers 33 protect the fourth metal layer 34, reducing the risk of corrosion of the fourth metal layer 34.

[0079] For example, the light shielding layer 3 can include, but is not limited to, any one of the three-layer laminated metals such as MoAlMo, TiAlTi, MoCuMo, TiCuTi, etc. In this way, the light shielding layer 3 has low impedance, and meanwhile, the two third metal layers 33 protect the fourth metal layer 34, reducing the risk of corrosion of the fourth metal layer 34.

[0080] In some embodiments, the thickness of the fourth metal layer 34 is greater than the thickness of the third metal layer 33. In this way, the impedance of the light shielding layer 3 is further reduced.

[0081] In some embodiments, the thickness of the fourth metal layer 34 is 1500 angstroms to 5000 angstroms, and the thickness of the third metal layer 33 is 200 angstroms to 1000 angstroms.

[0082] As shown in FIGS. 1, 4 and 6, the driving circuit layer 2 includes a plurality of thin film transistors T arranged in an array along a first direction x and a second direction y.

[0083] In some embodiments, the thin film transistor T can be selected from any one of a metal oxide transistor, a low-temperature polysilicon transistor and an amorphous silicon transistor. For example, the thin film transistor T is a low-temperature polysilicon transistor, improving the stability of the thin film transistor T under high temperature and high humidity conditions.

[0084] It should be noted that, in the case that the thin film transistor T is a low-temperature polysilicon transistor, the light shielding layer 3 adopts the design of the first metal layer 31 and the second metal layer 32 or the two third metal layers 33 and the fourth metal layer 34 described above, which can improve the high temperature resistance of the light shielding layer 3 during the formation of the low-temperature polysilicon transistor.

[0085] In some embodiments, the thin film transistor T can include at least one of a driving transistor and a switching transistor. The current when the driving transistor is turned on can be used to drive the light emitting device to emit light. The switching transistor can transmit the data signal transmitted by the data line 41 to the driving transistor when it is turned on. For example, the plurality of thin film transistors T can be driving transistors.

[0086] In some embodiments, as shown in FIG. 1, a column of thin film transistors T arranged along the second direction y is connected with a data line 41.

[0087] As shown in FIGS. 4, 6, and 8-12, the drive circuit layer 2 further includes a semiconductor layer 26. The semiconductor layer 26 includes a plurality of active layers 261 arranged in an array along the first direction x and the second direction y, and the plurality of active layers 261 are located in the array region 100a. The plurality of thin film transistors T include the plurality of active layers 261. The active layer 261 includes a channel portion 2611.

[0088] In some embodiments, the active layer 261 can include at least one of a low-temperature polysilicon active layer, an amorphous silicon active layer, and a metal oxide active layer, but is not limited thereto. Illustratively, the active layer 261 is a low-temperature polysilicon active layer. In this way, the high-temperature resistance and other properties of the active layer 261 are improved.

[0089] In some embodiments, as shown in FIGS. 4 and 6, in the case where the active layer 261 is a low-temperature polysilicon active layer, the active layer 261 further includes a doped portion located on both sides of the channel portion 2611, and the channel portion 2611 is connected between the two doped portions. One doped portion includes a lightly doped portion 2612 and a heavily doped portion 2613, and the lightly doped portion 2612 is connected between the channel portion 2611 and the heavily doped portion 2613.

[0090] In some embodiments, as shown in FIGS. 8-12, the active layer 261 is in a U shape, and in this case, the two portions of one active layer 261 that overlap the scan line 211 are two channel portions. In other embodiments, the active layer 261 can also be in other shapes, such as a straight line shape or an irregular shape, etc.

[0091] As shown in FIGS. 4, 6, 8-12, the light shielding layer 3 further includes a plurality of light shielding portions 36 arranged in an array along the first direction x and the second direction y in the array region 100a. The plurality of channel portions 2611 have a plurality of orthographic projections on the substrate, and the orthographic projections of the plurality of channel portions 2611 on the substrate are respectively located within the orthographic projections of the plurality of light shielding portions 36 on the substrate. In this way, the plurality of light shielding portions 36 shield the incident light, and the problem of the active layer 261 generating photo-generated carriers due to the incident light is improved. Furthermore, on the basis of the light shielding layer 3 including at least two conductive layers, the area of the light shielding portion 36 is increased, and the problem of the active layer 261 climbing and breaking due to the increase in the thickness of the light shielding layer 3 is reduced.

[0092] As shown in FIG. 8, in some embodiments, the orthographic projection of the channel portion 2611 of one active layer 261 on the substrate 1 is located within the orthographic projection of the light shielding portion 36 on the substrate 1, and the orthographic projection of the other portion of the active layer 261 on the substrate 1 other than the channel portion 2611 does not overlap the orthographic projection of the light shielding portion 36 on the substrate 1. In this way, the light shielding portion 36 partially shields the active layer 261, and the effect of the channel portion 2611 of the active layer 261 generating photo-generated carriers is reduced.

[0093] As shown in FIGS. 9-12, in some embodiments, the orthographic projection of one active layer 261 on the substrate 1 is located within the orthographic projection of one light-shielding portion 36 on the substrate 1. In this way, each light-shielding portion 36 covers one active layer 261, so that the plurality of light-shielding portions 36 better shield the incident light while reducing the risk of the active layer 261 being disconnected due to the increased thickness of the light-shielding layer 3.

[0094] In some embodiments, as shown in FIGS. 8-15, the light-shielding layer 3 further comprises a light-shielding connecting portion 37, and at least two light-shielding portions 36 are connected by the at least one light-shielding connecting portion 37. In this way, when the area of the light-shielding portion 36 increases, the coupling between the at least two light-shielding portions 36 connected to each other and the at least two signal lines cancels each other out, thereby improving the problem of signal crosstalk.

[0095] In some embodiments, as shown in FIGS. 8-15, the light-shielding layer 3 comprises at least two light-shielding portion groups 36A, and any two light-shielding portion groups 36A are arranged to be insulated from each other, and one light-shielding portion group 36A comprises at least two light-shielding portions 36 connected to each other by at least one light-shielding connecting portion 37. In this way, the coupling between the at least two light-shielding portions 36 connected to each other in one light-shielding portion group 36A and the signal lines cancels each other out, thereby improving the problem of signal crosstalk. Any two light-shielding portions 36 in any two light-shielding portion groups 36A are disconnected from each other.

[0096] In some embodiments, as shown in FIGS. 8-12, in the first direction x, any two adjacent light-shielding portions 36 in an even number of adjacent light-shielding portions 36 are connected by one light-shielding connecting portion 37. In this way, the problem of signal crosstalk caused by the coupling between the light-shielding portion 36 and the data line 41 transmitting data of the opposite polarity is improved when the area of the light-shielding portion 36 increases.

[0097] In some embodiments, in the first direction x, any two adjacent light-shielding portions 36 in 2n adjacent light-shielding portions 36 are connected by one light-shielding connecting portion 37, and n is an integer greater than or equal to 2 and less than or equal to 5. In this way, while improving the problem of crosstalk caused by the coupling between the light-shielding portion 36 and the data line 41, the risk of the light-shielding connecting portion 37 being broken due to process reasons and thus causing the failure of the connection between the adjacent light-shielding portions 36 is reduced, and the controllability of improving the problem of crosstalk is improved.

[0098] In some embodiments, in the first direction x, two adjacent light-shielding portions 36 are connected by a light-shielding connecting portion 37; and / or, any two adjacent light-shielding portions 36 in four adjacent light-shielding portions 36 are connected by a light-shielding connecting portion 37; and / or, any two adjacent light-shielding portions 36 in six adjacent light-shielding portions 36 are connected by a light-shielding connecting portion 37.

[0099] Exemplarily, as shown in FIGS. 8-12, in the first direction x, any two adjacent light-shielding portions 36 of the four adjacent light-shielding portions 36 are connected by a light-shielding connection portion 37.

[0100] It should be noted that when the array substrate 100 is applied to a liquid crystal display panel, the liquid crystal display panel can adopt column inversion technology or dot inversion technology to reduce damage to liquid crystal molecules. When the column inversion technology or the dot inversion technology is adopted, adjacent data lines 41 can transmit data signals of opposite polarities. Specifically, when the data voltage transmitted by one of the two adjacent data lines 41 is greater than the common voltage, the data voltage transmitted by the data line 41 is a positive data voltage, which is represented by “+”. When the data voltage transmitted by the other of the two adjacent data lines 41 is less than the common voltage, the data voltage transmitted by the data line 41 is a negative data voltage, which is represented by “-”.

[0101] As shown in FIGS. 13 and 14, when the liquid crystal display panel 300 adopts the column inversion technology or the dot inversion technology, the light-shielding portion 36 coupled to the data line 41 transmitting the positive data voltage is marked with “+”, and the light-shielding portion 36 coupled to the data line 41 transmitting the negative data voltage is marked with “-”.

[0102] For the design shown in FIGS. 8-13, that is, any two adjacent light-shielding portions 36 of the even number of adjacent light-shielding portions 36 are connected by the light-shielding connection portion 37 in the first direction x, the coupling effect between the even number of adjacent light-shielding portions 36 and the data lines 41 transmitting opposite polarities of data is counteracted, and the signal crosstalk problem caused by the coupling effect between the light-shielding portion 36 and the data line 41 is improved.

[0103] For the design shown in FIG. 14, in the third direction w, any two adjacent light-shielding portions 36 of the even number of adjacent light-shielding portions 36 are connected by a light-shielding connection portion 37, and the third direction w intersects the first direction x and the second direction y. In this way, the coupling effect between the even number of adjacent light-shielding portions 36 in the third direction w and the data lines 41 transmitting opposite polarities of data is counteracted, and the crosstalk problem caused by the coupling effect between the light-shielding portion 36 and the data line 41 is improved.

[0104] Exemplarily, the angle between the third direction w and one of the first direction x and the second direction y is 45 degrees, but is not limited thereto.

[0105] In some embodiments, as shown in FIGS. 8-12, the drive circuit layer 2 further includes a plurality of scan lines 211. The plurality of scan lines 211 are insulated from the plurality of data lines 41 and the plurality of touch lines 42. The plurality of scan lines 211 extend along the first direction x and are arranged at intervals along the second direction y.

[0106] In some embodiments, as shown in FIG. 14, in the second direction y, the at least two light shielding portions 36 are connected by the at least one light shielding connecting portion 37. In this way, the signal crosstalk problem caused by the coupling between the light shielding portions 36 and the plurality of scan lines 211 due to the increase in the area of the light shielding portions 36 is improved.

[0107] In some embodiments, in the second direction y, any two adjacent light shielding portions 36 of the m adjacent light shielding portions 36 are connected by one light shielding connecting portion 37, and m is an integer greater than or equal to 2 and less than or equal to 10. In this way, while the signal crosstalk problem caused by the coupling between the light shielding portions 36 and the data lines 41 is improved, the risk of the light shielding connecting portion 37 breaking due to the process and thus causing the failure of the connection between the adjacent light shielding portions 36 is reduced, and the controllability of improving the crosstalk problem is also improved. For example, m can be 2, 3, 4, 5, 6, 7, 8, 9, or 10.

[0108] In some embodiments, the orthogonal projection of the light shielding connecting portion 37 on the substrate is offset from the orthogonal projection of at least one of the signal lines 4 and the scan lines 211 on the substrate. In this way, the overlapping area between the light shielding connecting portion 37 and at least one of the signal lines 4 and the scan lines 211 is reduced, the coupling capacitance generated by the overlapping area is reduced, and the risk of signal crosstalk caused by the coupling capacitance is reduced.

[0109] In one exemplary embodiment, as shown in FIG. 9, the light shielding connecting portion 37 extends along the first direction x and connects the two adjacent light shielding portions 36 in the first direction x, and the orthogonal projection of the light shielding connecting portion 37 on the substrate 1 is offset from the orthogonal projection of the scan lines 211 on the substrate 1. In this way, the light shielding connecting portion 37 does not overlap with the scan lines 211, the coupling capacitance formed between the light shielding connecting portion 37 and the scan lines 211 is reduced, and the signal crosstalk problem is further improved.

[0110] In another exemplary embodiment, the light shielding connecting portion 37 extends along the second direction y and connects the two adjacent light shielding portions 36 in the second direction y, and the orthogonal projection of the light shielding connecting portion 37 on the substrate 1 is offset from the orthogonal projection of the data lines 41 and the touch control lines 42 on the substrate 1. In this way, the light shielding connecting portion 37 does not overlap with the data lines 41 and the touch control lines 42, the coupling capacitance formed between the light shielding connecting portion 37 and the data lines 41 and the touch control lines 42 is reduced, and the signal crosstalk problem is further improved.

[0111] In some embodiments, as shown in FIG. 8 and FIG. 9, the area of one light shielding connecting portion 37 is smaller than the area of one light shielding portion 36. In this way, the area of the light shielding connecting portion 37 is small, the signal crosstalk problem caused by the coupling between the light shielding connecting portion 37 and other signal lines is improved, and the light transmittance of the array substrate 100 is improved.

[0112] As shown in FIGS. 10-12, the light-shielding connecting portion 37 includes a hollow portion 371, which penetrates the light-shielding connecting portion 37 along the thickness direction of the light-shielding layer 3. In this way, light can pass through the hollow portion 371, more light can be incident into the array substrate 100, and the display brightness of the display panel can be improved.

[0113] In some embodiments, as shown in FIGS. 10-12, the plurality of hollow portions 371 are arranged at intervals. In this way, the light incident into the array substrate 100 can pass through the plurality of hollow portions 371.

[0114] In some embodiments, as shown in FIG. 10, the plurality of hollow portions 371 can be the same. In this way, the manufacturing process of the plurality of hollow portions 371 can be simplified.

[0115] In some embodiments, the shapes of the plurality of hollow portions 371 can be the same, so as to simplify the forming process of the hollow portions 371. In other embodiments, the shapes of at least two hollow portions 371 can be different.

[0116] As shown in FIGS. 10-12, the orthogonal projection of the hollow portion 371 on the substrate overlaps with the orthogonal projection of at least one of the signal lines 4 and the scan lines 211 on the substrate. In this way, on the basis of improving the light transmittance of the array substrate 100, the overlapping area between the light-shielding connecting portion 37 and at least one of the signal lines 4 and the scan lines 211 is reduced, the coupling capacitance generated due to the overlapping area is reduced, and the risk of signal crosstalk caused by the coupling capacitance is reduced.

[0117] In some embodiments, as shown in FIGS. 11 and 12, the plurality of hollow portions 371 include a first hollow portion 3711 and a second hollow portion 3712, the area of the first hollow portion 3711 is greater than the area of the second hollow portion 3712. The first hollow portion 3711 overlaps with the data lines 41 and the scan lines 211, and the second hollow portion 3712 overlaps with one of the data lines 41 and the scan lines 211. In this way, the first hollow portion 3711 with a larger area overlaps with the data lines 41 and the scan lines 211 at the same time, the overlapping area between the light-shielding connecting portion 37 and the data lines 41 and the scan lines 211 is reduced, and the second hollow portion 3712 with a smaller area overlaps with one of the data lines 41 and the scan lines 211.

[0118] In some embodiments, the number of the second hollow portions 3712 is greater than the number of the first hollow portions 3711. In this way, the coupling capacitance between one of the data lines 41 and the scan lines 211 and the light-shielding connecting portion 37 can be more flexibly reduced.

[0119] In some embodiments, the plurality of light-shielding portions 36 can not be connected to a voltage. In other embodiments, the plurality of light-shielding portions 36 can also be connected to a constant voltage.

[0120] As shown in FIG. 12, the array substrate 100 further includes a black matrix 27. The black matrix 27 shields light. The black matrix 27 is located on the side of the light shielding layer 3 away from the substrate 1. The orthographic projection of the black matrix 27 on the substrate 1 overlaps the orthographic projection of the light shielding connecting portion 37 on the substrate. In this way, the black matrix 27 shields the light shielding connecting portion 37. The orthographic projection of the black matrix 27 on the substrate 1 can also cover the orthographic projection of the scan line 211 and the data line 41 on the substrate.

[0121] In some embodiments, as shown in FIGS. 4 and 6, the array substrate 100 further includes a first insulating layer 281, which is located between the driving circuit layer 2 and the light shielding layer 3.

[0122] In some embodiments, as shown in FIGS. 4 and 6, the driving circuit layer 2 includes a first conductive layer 21. The first conductive layer 21 is located on the side of the light shielding layer 3 away from the substrate.

[0123] As shown in FIG. 4, the first conductive layer 21 can include the scan line 211 and the gate of the thin film transistor T. As shown in FIG. 7, the first conductive layer 21 can also include the signal line 4.

[0124] As shown in FIGS. 4 and 6, in some embodiments, the first conductive layer 21 can be located on the side of the semiconductor layer 26 away from the light shielding layer 3, and the corresponding thin film transistor T includes a top gate. In other embodiments, the first conductive layer 21 can be located between the semiconductor layer 26 and the light shielding layer 3, and the corresponding thin film transistor T includes a bottom gate.

[0125] In some embodiments, a second insulating layer 282 is provided between the first conductive layer 21 and the semiconductor layer 26.

[0126] In some embodiments, as shown in FIGS. 4 and 6, the driving circuit layer 2 includes a second conductive layer 22. The second conductive layer 22 is located on the side of the first conductive layer 21 away from the substrate. As shown in FIGS. 4 and 5, in some embodiments, the second conductive layer 22 can include the data line 41 and the touch line 42 and other signal lines 4 and the source of the thin film transistor T. As shown in FIG. 6, in other embodiments, the second conductive layer 22 includes the data line 41, the touch line 42, and the source and the drain of the thin film transistor T.

[0127] In some embodiments, a third insulating layer 283 is provided between the second conductive layer 22 and the first conductive layer 21.

[0128] As shown in FIG. 4, in some embodiments, the driving circuit layer 2 further includes a third conductive layer 23. The third conductive layer 23 is located on the side of the second conductive layer 22 away from the substrate 1. The third conductive layer 23 can include the touch line 42 and the drain of the thin film transistor T.

[0129] In some embodiments, a fourth insulating layer 284 is arranged between the third conductive layer 23 and the second conductive layer 22.

[0130] In some embodiments, the array substrate 100 further comprises a first transparent conductive layer 24 and a second transparent conductive layer 25. The first transparent conductive layer 24 is located on the side of the driving circuit layer 2 away from the substrate. The second transparent conductive layer 25 is located on the side of the first transparent conductive layer 24 away from the substrate.

[0131] One of the first transparent conductive layer 24 and the second transparent conductive layer 25 comprises a pixel electrode 241 connected with the drain of the thin film transistor T. The other of the first transparent conductive layer 24 and the second transparent conductive layer 25 comprises a plurality of common electrode blocks 251. Exemplarily, the first transparent conductive layer 24 comprises the pixel electrode 241, and the second transparent conductive layer 25 comprises the common electrode blocks 251.

[0132] In some embodiments, the plurality of common electrode blocks 251 are connected with the touch lines 42 through vias, so that the common electrode blocks 251 are multiplexed as touch electrodes 252.

[0133] As shown in FIG. 4 and FIG. 6, in some embodiments, a fifth insulating layer 285 is arranged between the first transparent conductive layer 24 and the second conductive layer 22 or the third conductive layer 23. A sixth insulating layer 286 is arranged between the first transparent conductive layer 24 and the second transparent conductive layer 25.

[0134] In some embodiments, the first insulating layer 281 to the fourth insulating layer 284 and the sixth insulating layer 286 can all be inorganic insulating layers. The inorganic insulating layer can comprise at least one of silicon oxide, silicon nitride and silicon oxynitride. The fifth insulating layer 285 can be an organic insulating layer. The organic insulating layer can comprise at least one of polyimide and polyacrylate.

[0135] Based on the same inventive concept, as shown in FIG. 16, the present application further provides a display panel 300. The display panel 300 comprises the above-mentioned array substrate 100.

[0136] In some embodiments, the display panel 300 further comprises an opposite substrate 200 arranged opposite to the array substrate 100. The opposite substrate 200 can be any one of a color filter substrate and an encapsulation substrate.

[0137] In some embodiments, in the case where the display panel 300 is a liquid crystal display panel, a black matrix 27 is arranged on the surface of the opposite substrate 200 facing the array substrate 100. In the case where the light shielding layer 3 of the array substrate 100 comprises a light shielding connection portion 37, the black matrix 27 covers the light shielding connection portion 37 in orthographic projection on the array substrate 100.

[0138] As shown in FIG. 17, based on the same inventive concept, the present application also provides a display device 500. The display device 500 comprises the display panel 300 described above.

[0139] In some embodiments, in the case where the display device 500 is a liquid crystal display device, the display device 500 further comprises a backlight module 400, which is located at the light-incident side of the display panel 300.

[0140] The above description of the embodiments is only used to help understand the technical solutions of the present application and the core ideas thereof; it should be understood by those skilled in the art that the technical solutions recorded in the foregoing embodiments can still be modified, or some technical features thereof can be replaced equivalently; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An array substrate, wherein, The array substrate has an array region and a peripheral region surrounding the array region, and comprises: a substrate; a drive circuit layer disposed on one side of the substrate and comprising a plurality of signal lines disposed in the array region; and a light shielding layer disposed between the substrate and the drive circuit layer, comprising at least two layers of conductive layers stacked, and comprising a plurality of connection lines in the peripheral region, each of the plurality of connection lines being connected to a corresponding one of the plurality of signal lines.

2. The array substrate according to claim 1, wherein, The drive circuit layer further comprises a semiconductor layer, the semiconductor layer comprising a plurality of active layers spaced apart, each of the active layers comprising a channel portion. The light shielding layer further comprises a plurality of light shielding portions, and a plurality of orthographic projections of the channel portions on the substrate are each located within an orthographic projection of a corresponding one of the light shielding portions on the substrate.

3. The array substrate of claim 2, wherein, An orthographic projection of one of the active layers on the substrate is located within an orthographic projection of one of the light shielding portions on the substrate.

4. The array substrate of claim 2, wherein, The light shielding layer further comprises a light shielding connection portion, and at least two of the light shielding portions are connected by the light shielding connection portion.

5. The array substrate according to claim 4, wherein, The drive circuit layer further comprises a plurality of data lines spaced apart, the plurality of data lines being arranged along a first direction and extending along a second direction. In the first direction, any two adjacent ones of the even-numbered adjacent light shielding portions are connected by one of the light shielding connection portions; and / or, In a third direction, any two adjacent ones of the even-numbered adjacent light shielding portions are connected by one of the light shielding connection portions, the third direction intersecting the first direction and the second direction.

6. The array substrate of claim 4, wherein, The drive circuit layer further comprises a plurality of scan lines spaced apart, the plurality of scan lines extending along a first direction and being arranged along a second direction. In the second direction, at least two of the light shielding portions are connected by the light shielding connection portion.

7. The array substrate according to claim 4, wherein, The signal lines comprise at least one of a data line and a touch control line, and the drive circuit layer further comprises a scan line. An orthographic projection of the light shielding connection portion on the substrate is offset from an orthographic projection of at least one of the signal lines and the scan line on the substrate.

8. The array substrate according to claim 4, wherein, The light shielding connection portion comprises a hollow portion, the hollow portion penetrating through the light shielding connection portion along a thickness direction of the light shielding layer.

9. The array substrate of claim 8, wherein, The signal lines comprise at least one of a data line and a touch control line, and the drive circuit layer further comprises a scan line. An orthographic projection of the hollow portion on the substrate overlaps an orthographic projection of at least one of the scan line and the signal line on the substrate.

10. The array substrate of claim 4, wherein, The light shielding layer comprises at least two groups of light shielding portions, any two of the groups of light shielding portions being insulated from each other, and one of the groups of light shielding portions comprising at least two of the light shielding portions connected to each other by at least one of the light shielding connection portions.

11. The array substrate of claim 1, wherein, The at least two layers of conductive layers stacked comprise a first metal layer and a second metal layer, the first metal layer being located between the substrate and the second metal layer, and a reflectivity of the first metal layer to light being greater than a reflectivity of the second metal layer to light.

12. The array substrate of claim 11, wherein, The first metal layer is made of at least one of aluminum, an aluminum alloy, copper, and a copper alloy, and the second metal layer is made of at least one of molybdenum, a molybdenum alloy, titanium, and a titanium alloy.

13. The array substrate of claim 1, wherein, The at least two layers of the conductive layer arranged in a stack include two third metal layers and a fourth metal layer between the two third metal layers, and the fourth metal layer has a material with a conductivity greater than that of the third metal layer.

14. The array substrate of claim 13, wherein, The material of the third metal layer is selected from at least one of molybdenum, a molybdenum alloy, titanium, and a titanium alloy, and the material of the fourth metal layer is selected from at least one of aluminum, an aluminum alloy, copper, and a copper alloy; and / or, the fourth metal layer has a thickness greater than that of the third metal layer.

15. The array substrate of claim 4, wherein, The array substrate further includes: A black matrix is located on a side of the light-shielding layer away from the substrate, and a projection of the black matrix on the substrate overlaps a projection of the light-shielding connection portion on the substrate.

16. A display panel, wherein, An array substrate includes an array region and a peripheral region arranged around the array region, and the array substrate includes: A substrate; A drive circuit layer is arranged on a side of the substrate and includes a plurality of signal lines arranged in the array region; and A light-shielding layer is arranged between the substrate and the drive circuit layer, includes at least two layers of conductive layers arranged in a stack, and includes a plurality of connection lines arranged in the peripheral region, and the plurality of connection lines are respectively connected to the plurality of signal lines.

17. The display panel of claim 16, wherein, The drive circuit layer further includes a semiconductor layer, and the semiconductor layer includes a plurality of active layers arranged at intervals, and the active layer includes a channel portion; The light-shielding layer further includes a plurality of light-shielding portions, and a plurality of projections of the channel portions on the substrate are respectively located within a plurality of projections of the light-shielding portions on the substrate.

18. The display panel of claim 17, wherein, A projection of one of the active layers on the substrate is located within a projection of one of the light-shielding portions on the substrate.

19. The display panel of claim 17, wherein, The light-shielding layer further includes a light-shielding connection portion, and at least two of the light-shielding portions are connected through at least one of the light-shielding connection portions.

20. A display device comprising: A display device includes a display panel, and the display panel includes an array substrate, and the array substrate includes: A substrate; A drive circuit layer is arranged on a side of the substrate and includes a plurality of signal lines arranged in the array region; and A light-shielding layer is arranged between the substrate and the drive circuit layer, includes at least two layers of conductive layers arranged in a stack, and includes a plurality of connection lines arranged in the peripheral region, and the plurality of connection lines are respectively connected to the plurality of signal lines.

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