Chip system and electronic device

Abstract

The present application relates to the technical field of chips. Provided are a chip system and an electronic device, which improve the utilization rate of the area of a chip, and increase the capacity of a shared cache in a system-on-chip. The specific solution involves: the chip system comprises: a logic computing die and a memory die, wherein the logic computing die and the memory die are stacked; the logic computing die comprises a first logic functional region and a second logic functional region, the first logic functional region being provided with a first logic functional unit, and the second logic functional region being provided with a second logic functional unit; and the memory die comprises a first memory region and a second memory region, the first logic functional region and the first memory region correspond to each other in the stacking direction, and the second logic functional region and the second memory region correspond to each other in the stacking direction. The first memory region comprises a first memory array and a second memory array, wherein the first memory array is used for storing first data of the first logic functional unit, and the second memory array is used for storing second data of the second logic functional unit.

Description

Chip system and electronic device

[0001] The present application claims priority to the Chinese patent application No. 202411261893.5, filed on September 9, 2024, and entitled "Chip system and electronic device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] Embodiments of the present application relate to the chip technology field, and in particular to a chip system and an electronic device. BACKGROUND

[0003] With the continuous development of integrated electronic technology, the performance requirements of chips are also increasingly improved, such as function enhancement, size reduction, energy consumption and cost reduction, etc., thereby giving birth to three-dimensional integrated circuit (3D IC) technology. In 3D IC technology, multiple dies (referred to as dies) are stacked together to form a vertical structure, rather than the traditional two-dimensional planar layout, which has the advantages of higher storage capacity, lower energy consumption, and smaller area, etc.

[0004] Among them, the system on chip (SoC) also begins to evolve to 3D IC technology, and the system on chip usually integrates multiple intellectual property (IP) components, such as central processing unit (CPU), graphics processing unit (GPU), image signal processor (ISP), and system cache (SC), etc. Among them, the system cache can also be referred to as a system shared cache, which is usually used as the last level cache, and the larger the capacity of the system shared cache, the higher the access efficiency of the system on chip.

[0005] However, 3D IC technology usually requires the area shape (harden) of the logic circuit of each IP to overlap with the area shape of the static random access memory (SRAM) in the vertical direction, so as to realize the read and write access of the control logic to the SRAM through the high-density interconnection signals between the dies and the dies. This results in that for the compute intensive (CI) IP with high logic area ratio, the utilization rate of the die area of the SRAM part is low, which limits the cost advantage and scalability of the 3D IC technology. SUMMARY

[0006] The chip system and the electronic device provided by the embodiments of the present application improve the utilization of the die area.

[0007] To achieve the above object, the embodiments of the present application adopt the following technical solutions.

[0008] In a first aspect, the embodiments of the present application provide a chip system, which comprises a logic computing die and a storage die, and the logic computing die and the storage die are arranged in a stacked manner. The logic computing die comprises a first logic function area and a second logic function area, and the first logic function area is provided with a first logic function unit, and the second logic function area is provided with a second logic function unit. The storage die comprises a first storage area and a second storage area, and the first logic function area corresponds to the first storage area in a stacking direction, and the second logic function area corresponds to the second storage area in the stacking direction. The first storage area comprises a first storage array and a second storage array, the first storage array is used to store first data of the first logic function unit, and the second storage array is used to store second data of the second logic function unit.

[0009] Thus, in the chip system provided by the embodiments of the present application, the second logic function unit can store the second data in the second storage array of the first storage area corresponding to the first logic function unit, that is, the second logic function unit can borrow the storage capacity of the first logic function unit. That is, for the second logic function unit, in addition to the second storage area itself, the second storage array in the first storage area is also included. Among them, for the second logic function unit, the second storage area can be referred to as local storage, and the second storage array can be referred to as remote storage. The second logic function unit can improve the storage capacity by borrowing the storage array of other logic function units as remote storage, and at the same time, the utilization of the die area of the entire chip system is improved.

[0010] In a possible design, the second logic function unit is a system shared cache on the logic computing die. Thus, the chip system increases the storage capacity of the system shared cache, can improve the hit rate of each logic function unit accessing the system shared cache, improves the access efficiency of the chip system, improves the performance of the chip system, and reduces the power consumption of the chip system.

[0011] In a possible design, the second storage area comprises a tag array and a data array, and the tag array is used to store tag information of the data array and the second storage array.

[0012] In a possible design, the system shared cache is configured to index the tag array by tag information to access the data array or the second storage array. In this way, each logical function unit can access the local storage and the remote storage of the system shared cache by accessing the tag array of the system shared cache on the system on chip. Each logical function unit is not aware of the local storage and the remote storage in terms of service, and no additional delay cost is added when a cache miss occurs.

[0013] In a possible design, the system shared cache is configured to access the second storage array through a transmission channel. The transmission channel is a transmission channel from the second logical function region, through the first logical function region, to the second storage array, or the transmission channel is a transmission channel from the second logical function region, through the second storage region, to the second storage array. In this way, the system shared cache can locally perform distribution and convergence scheduling of read and write requests of the second storage array, and access the second storage array through the transmission channel. The transmission channel can be implemented on the logic computing die, or the transmission channel can be implemented on the storage die.

[0014] In a possible design, the first storage array and the second storage array have different power supply configurations, including at least one of a power domain or a clock domain. In this way, the first storage array and the second storage array use different power domains and / or clock domains, facilitating physical decoupling, that is, the working state of the first logical function unit does not affect the working state of the system shared cache on chip, and the normal working of the system shared cache on chip can be ensured.

[0015] In a possible design, the data array and the second storage array have the same power supply configuration. In this way, the entire system shared cache can use the same power domain and / or clock domain, facilitating timing convergence.

[0016] In a possible design, the logic computing die further includes a third logical function region, and the third logical function region is provided with a third logical function unit. The storage die further includes a third storage region, and the third logical function region and the third storage region correspond in the stacking direction. That is, the chip system can include a plurality of logical function units.

[0017] In a possible design, the third storage region includes a third storage array and a fourth storage array. The third storage array is configured to store third data of the third logical function unit, and the fourth storage array is configured to store second data of the second logical function unit. In this way, the system shared cache can borrow storage arrays of a plurality of logical function units to improve storage capacity, and at the same time, improve the utilization rate of the chip area of the entire chip system.

[0018] In a possible design, the first logic function unit includes at least one of the following: a central processing unit (CPU), a graphics processing unit (GPU), an image signal processor (ISP), a coding module, a modem, and a display module. That is, the first logic function unit can be a plurality of types of intellectual property components.

[0019] In a possible design, at least one of the first storage array and the second storage array is a continuous region. In this way, the first logic function unit can leave a continuous and complete free region for borrowing, and the capacity of the system shared cache can be further improved, and the utilization of the chip area can be improved.

[0020] In a second aspect, an embodiment of the present application provides an electronic device, including a circuit board and the chip system in the first aspect, and the chip system is arranged on the circuit board.

[0021] These or other aspects of the present application will become apparent from the following description of the application. BRIEF DESCRIPTION OF DRAWINGS

[0022] FIG. 1 is a structural schematic diagram of an SoC according to an embodiment of the present application;

[0023] FIG. 2 is a structural schematic diagram of a cache according to an embodiment of the present application;

[0024] FIG. 3 is a structural diagram of a chip system according to an embodiment of the present application;

[0025] FIG. 4 is a structural schematic diagram of an SoC based on a 3D IC technology according to an embodiment of the present application;

[0026] FIG. 5 is a structural schematic diagram of a CI-IP according to an embodiment of the present application;

[0027] FIG. 6 is a structural schematic diagram of a MI-IP according to an embodiment of the present application;

[0028] FIG. 7 is a structural schematic diagram of another chip system according to an embodiment of the present application;

[0029] FIG. 8 is a structural schematic diagram of a system shared cache according to an embodiment of the present application;

[0030] FIG. 9 is a schematic diagram of a transmission channel according to an embodiment of the present application;

[0031] FIG. 10 is a schematic diagram of a power supply configuration according to an embodiment of the present application;

[0032] FIG. 11 is a structural schematic diagram of another chip system according to an embodiment of the present application;

[0033] FIG. 12 is a structural diagram of a system shared cache according to an embodiment of the present application;

[0034] FIG. 13 is a diagram of an arrangement of a first storage area according to an embodiment of the present application;

[0035] FIG. 14 is a diagram of another arrangement of a first storage area according to an embodiment of the present application. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings. In the description of the embodiments of the present application, unless otherwise specified, " / " means "or", for example, A / B can mean A or B; "and / or" in the present application is merely a description of the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which means that there are three cases of A alone, A and B together, and B alone.

[0037] Hereinafter, the terms "first" and "second" are used only for descriptive purposes, and should not be construed or implied to indicate or imply relative importance or implicitly indicate the number of indicated technical features. Therefore, the features defined with "first" and "second" can explicitly or implicitly include one or more features. In the description of the embodiments, unless otherwise specified, the meaning of "multiple" is two or more.

[0038] In addition, the term "coupled" is used to mean an electrical connection, including direct connection or indirect connection through other devices by wire or connection terminal. Therefore, "coupled" should be regarded as a broad sense of electronic communication connection.

[0039] It should be noted that in the present application, the words "exemplary" or "for example" are used to mean serving as an example, illustration, or description. Any embodiment or design solution described as "exemplary" or "for example" in the present application should not be interpreted as more preferred or more advantageous than other embodiments or design solutions. Rather, the use of "exemplary" or "for example" is intended to present the relevant concept in a specific manner.

[0040] In order to facilitate understanding, the structure of a system on chip (SoC) and a cache involved in the embodiments of the present application will be introduced first.

[0041] As shown in FIG. 1, a structural diagram of an SoC is shown in FIG. 1. The SoC can include a central processing unit (CPU), a graphics processing unit (GPU), an image signal processor (ISP), a neural processing unit (NPU), an encoding module, a display module, a modem, and various other intellectual property (IP) components. Each IP can interact with off-chip memory, usually a dynamic random access memory (DRAM), through a system bus and an input / output (I / O) interface for program and data. The bandwidth, latency, and power consumption of each IP accessing the DRAM greatly limit the performance and energy efficiency of each IP.

[0042] Most IPs implement on-chip memory (OCM) based on a static random access memory (SRAM). According to the working behavior of the IP, the on-chip memory can be constructed in the form of a tightly coupled memory (TCM), a scratch pad memory (SPM), a buffer, and a cache. The IP reduces the access demand for the DRAM through the on-chip memory, and improves the performance and energy efficiency through the high bandwidth, low latency, and low power consumption of the on-chip memory.

[0043] However, due to cost and other factors, the storage capacity of the on-chip memory implemented by the IP is limited, which results in a large access demand for the DRAM for data interaction between each IP. The power consumption of the SoC is a key indicator of terminal equipment, which determines the battery life, and the access power consumption of the SoC for the DRAM accounts for a large proportion in the terminal equipment. Referring back to FIG. 1, a large-capacity system cache (SC), which can also be referred to as a system shared cache, can be constructed in the SoC to further improve the IP performance, reduce the DRAM access bandwidth, and optimize the system energy efficiency. The larger the capacity of the system shared cache, the more effectively the DRAM access bandwidth can be reduced, but the large-capacity system shared cache also significantly increases the chip cost.

[0044] Currently, a cache is usually implemented in a way of N-way set-associative, as shown in FIG. 2. FIG. 2 shows a structure diagram of a cache. The cache can include a tag array and a data array. The tag array is used to store address / status information of a cache block, and the data array is used to store data of the cache block. The tag array can include N ways and M set indexes. The N ways can be numbered as way 0, way 1, …, and way N-1. The M set indexes can be numbered as 0 to M-1. In addition, each way can store tag information, which can include a valid bit, a tag address, and others.

[0045] When a user accesses the cache, an address carried in an access request of the user can include a tag address, a set index, and a byte offset. Specifically, a flow of accessing the cache can include that the cache reads tag information of N ways according to the set index in the address, and determines whether the data to be accessed exists in the cache by comparing the tag address in the address with the tag addresses of the N ways. If the data to be accessed exists in the cache, it is determined as a hit, and a read / write is performed on a corresponding cache block in the data array. Finally, output data is selected by a multiplexer (mux). If the data to be accessed does not exist in the cache, it is determined as a miss, and the data is read from an off-chip memory, and a way is selected from the N ways for replacement. In the area overhead of a chip implementing the cache, the data array accounts for a large proportion, and the tag array accounts for a small proportion.

[0046] With the application of three dimensional integrated circuit (3D IC) technology to SoC, the performance, energy consumption, and area of the SoC are further optimized. As shown in FIG. 3, the chip system can include a substrate, a bottom die, and a top die stacked in sequence. There is a via between the bottom die and the substrate, which is also called a 3D interconnection component. The via can be obtained based on packaging technologies such as through silicon via (TSV), hybrid bonding (HB), and micro bump of the chip.

[0047] As shown in FIG. 4, a structural diagram of an SoC based on a 3D IC technology is shown in FIG. 4. Among them, the top die can also be referred to as a logic die or a logic computing die, and the bottom die can also be referred to as a storage die or an SRAM die. The top die can include the logic circuit part of the CPU, GPU, ISP, NPU, SC, encoding module, modem, display module and other IP in the SoC, and the bottom die can include the SRAM part of each IP in the SoC, which is named by each IP respectively, to represent the corresponding storage area part. In the figure, the logic die is located on the upper layer of the 3D IC, and the storage die is located on the lower layer of the 3D IC. The actual layout relationship is not limited by this, and the relationship between the two can be flexibly exchanged.

[0048] With the evolution of the process, the micro-fraction of SRAM and analog IP slows down or even stagnates, and the cost per unit area of advanced processes continues to rise. Currently, the logic die is usually implemented by an advanced process, and the storage die is implemented by a mature process, and then 3D IC technology is used for sealing to realize a larger scale chip and a technical direction of reducing the cost of a super large scale chip.

[0049] The computing behaviors and characteristics of different IPs in the SoC are different. Some are compute intensive (CI) IPs with high logic area ratio, that is, CI-IPs, such as image processors, etc. Some are memory intensive (MI) IPs with high SRAM area ratio, that is, MI-IPs, such as system cache, etc.

[0050] As shown in FIGS. 5 and 6, for a certain IP in the 3D IC, a structural diagram of a CI-IP is shown in FIG. 5, and a structural diagram of a MI-IP is shown in FIG. 6. It is assumed that each IP can include a logic part and a storage part, the logic part is located on the upper layer logic die, and the storage part is located on the lower layer storage die. As can be seen, the storage part of the CI-IP has idle area, and the area utilization rate of the CI-IP is low. In addition, the logic part of the MI-IP has idle area, and the storage capacity of the MI-IP is limited. Among them, the area shape of the logic circuit of each IP of the logic die in the 3D IC technology and the area shape of the storage circuit overlap in the vertical direction, so as to realize the read and write access of the control logic to the SRAM through the high-density interconnection signals between the dies and the dies. This results in low die area utilization rate of the lower layer storage die of the CI-IP, which limits the cost advantage and scalability of the 3D IC technology.

[0051] In a possible implementation, in order to solve the problem of low chip area utilization, the industry proposes a conventional two-dimensional chip solution. Specifically, the chip solution stacks two two-dimensional (2D) dies after design and implementation. However, in this solution, it is difficult to design the module division, power supply, and thermal design.

[0052] In another possible implementation, in order to solve the problem of low chip area utilization, the industry proposes another chip solution. Specifically, in the chip solution, the upper and lower dies are divided into logic dies and storage dies, and the two dies can use different process nodes. For example, the storage die can use a mature process to solve the cost problem of SRAM with process scaling. The power density of SRAM is low, which can reduce the risk of thermal design, and the timing between SRAM and logic is simple, which is convenient for timing convergence. However, the chip solution is suitable for the case where the area of the IP logic part and the storage part is balanced. For CI-IP and other IPs, the storage die will have more area waste.

[0053] In yet another possible implementation, in order to solve the problem of low chip area utilization, the industry proposes yet another chip solution. Specifically, in the chip solution, the logic is arranged in the upper and lower dies. However, in the chip solution, the upper and lower dies may face different process corners, and the timing convergence of the logic path between the upper and lower dies will actually have problems, which will affect the actual design performance.

[0054] Therefore, the embodiments of the present application provide a chip system, which includes a logic computing die and a storage die. The chip system can improve the area utilization of the chip system by borrowing the storage array.

[0055] In the above scenarios, the chip system provided by the embodiments of the present application can be applied to electronic devices, including but not limited to: mobile phones, tablet computers, personal computers, palm computers, mobile internet devices (MID), cameras, wearable devices (such as smart watches, smart bracelets, pedometers, etc.), sound equipment, audio and video players, set-top boxes, game consoles, printers, mice, keyboards, vehicle-mounted devices (such as devices on vehicles such as cars, airplanes, ships, trains, and high-speed rails), virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, smart home devices (such as refrigerators, televisions, air conditioners, electricity meters, etc.), smart robots, plant equipment, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, or wireless terminals in smart homes, flight equipment (such as smart robots, hot air balloons, drones, airplanes), and the like.

[0056] In some embodiments, the chip system provided by the embodiments of the present application can be a system-on-chip, which can integrate multiple types of IP to adapt to multiple application scenarios such as games, photography, and media.

[0057] The chip system provided by the embodiments of the present application will be further described below with reference to the accompanying drawings.

[0058] The embodiments of the present application provide a chip system, as shown in FIG. 7, which shows a structural schematic diagram of another chip system. The chip system includes a logic computing die and a storage die, and the logic computing die and the storage die are stacked. The logic computing die can also be referred to as a logic die, and the storage die can also be referred to as an SRAM die.

[0059] The logic computing die includes a first logic function area and a second logic function area, the first logic function area is provided with a first logic function unit, and the second logic function area is provided with a second logic function unit. The storage die includes a first storage area and a second storage area, the first logic function area and the first storage area correspond in the stacking direction, and the second logic function area and the second storage area correspond in the stacking direction.

[0060] The logic function units can be IP cores or processor cores, and the logic functions include computing functions, control functions and storage functions related to logic computing. The chip system can integrate multiple logic function units according to requirements, and has good scalability and flexibility.

[0061] Optionally, the first logic function unit includes at least one of a central processing unit, an image processor, an image signal processor, a coding module, a modem and a display module. It can be understood that the first logic function unit can also include other modules, which can be referred to in detail in FIG. 4, and the present application does not limit this.

[0062] Taking the image processor as an example, the image processor is a hardware component for processing graphics and video data, and can perform image rendering, image processing, machine learning, video encoding and decoding, and artificial intelligence computing functions. The image processor is arranged on the logic computing die, and the storage unit of the image processor is arranged on the storage die, and the storage unit can be SRAM. Since the image processor is mainly used for image processing, the circuit area of the image processor on the logic computing die is large, and the storage unit of the image processor has a large idle area in the storage die, which is a computing-intensive IP.

[0063] Optionally, the second logic function unit is a system shared cache on the logic computing die. The system shared cache can not only cache data of one or more IPs on the logic computing die, but also control and read and write data. For example, one or more IPs on the logic computing die can access the storage space on the storage die through the system shared cache.

[0064] Optionally, the system shared cache corresponds to a storage die that can include a tag array storing address / status information and a data array storing data of the storage cache. In addition, the logic computing die can include processing logic of the system shared cache, such as caching and scheduling access requests (also referred to as read / write requests), reading data of the tag array, judging hit / miss of the tag data, and generating access requests for the data array or DRAM. Since the system shared cache is mainly used for storage, the storage array corresponding to the storage unit of the system shared cache has a large circuit area, and the logic function area corresponding to the logic function unit of the system shared cache has a large idle area, which is a memory-intensive IP.

[0065] Optionally, the first storage area includes a first storage array and a second storage array, the first storage array is used to store first data of the first logic function unit, and the second storage array is used to store second data of the second logic function unit.

[0066] For example, the second data of the second logical function unit is stored in the second storage array of the first storage area corresponding to the first logical function unit, that is, the second logical function unit can borrow the storage capacity of the first logical function unit. That is, for the second logical function unit, in addition to the second storage area itself, the second storage array of the first storage area is also included. Among them, the second storage area can be referred to as the local storage of the second logical function unit, and the second storage array can be referred to as the remote storage of the second logical function unit, which is located in the first storage area of the first logical function unit. When the storage capacity of the second logical function unit is insufficient, the storage capacity can be increased by borrowing the storage array of other logical function units, and at the same time, the utilization rate of the die area of the entire chip system can be improved.

[0067] When the second logical function unit is a system shared cache, the data array of the system shared cache can also be arranged in the second storage array as a remote data array of the system shared cache. Thus, the chip system increases the storage capacity of the system shared cache, the system shared cache can cache more data, the hit rate of each logical function unit accessing the system shared cache can be improved, the access efficiency of the chip system is improved, the performance of the chip system is improved, and the power consumption of the chip system is reduced.

[0068] Optionally, the second storage area includes a tag array and a data array, and the tag array is used to store tag information of the data array and the second storage array.

[0069] For example, the tag array can include N ways of the data array. Specifically, assuming that the capacity of the data array of the system shared cache is 8M, and the capacity of a cache block is 128 bytes, the total number of cache blocks can be 64K. Assuming that the data array includes multiple regions, and the number of cache blocks of a certain region is 16K, then the number of ways N = 16, and the number of group indexes is 1K.

[0070] For example, the tag array can also include M ways of the second storage array, and the ways of the second storage array are arranged in the same way as the ways of the data array, which will not be described here.

[0071] Exemplarily, the system shared cache can pre-establish a mapping relationship between cache locations in the tag array and cache blocks of the data array. As shown in FIG. 8, the tag array and the data array can be an m*n array respectively, each element in the tag array is a tag information, and each element in the data array is a cache block. FIG. 8 schematically shows that the tag array is a 4*4 array, the data array is a 2*4 array, and the second storage array is a 2*4 array. In the tag array, the data array or the second storage array, each row represents a group, and each column represents a way.

[0072] Continuing to refer to FIG. 8, it can be simply understood that the tag information 00 is stored at the (group 0, way 0) location of the tag array, and the data indexed by the corresponding tag information is stored at the corresponding cache block of (group 0, way 0) in the data array, that is, data A. Alternatively, the tag information 02 is stored at the (group 0, way 2) location of the tag array, and the data indexed by the corresponding tag information is stored at the corresponding cache block of (group 0, way 2) in the second storage array, that is, data I.

[0073] Optionally, the system shared cache is configured to index the tag array by the tag information to access the data array or the second storage array.

[0074] Exemplarily, after the system shared cache receives an access request of any IP, the access request is parsed to obtain a tag address. If the tag address is the same as the tag address in any way of any tag array, it is determined as a hit, and read-write operation is performed on the corresponding data array or second storage array according to the hit way. If the tag address is different from the tag address in all ways of all tag arrays, it is determined as a miss, at this time, whether to need to be resident can be determined according to a resident policy, when it is needed to be resident, a victim way, that is, a replaced way, is selected according to a replacement algorithm, and read-write operation is performed on the data array or the second storage array corresponding to the replaced way. When it is not needed to be resident, a read-write request is initiated to the off-chip memory. The resident policy can be that the data frequently accessed by each IP or the data shared by each IP is determined as needing to be resident, and the data not frequently accessed by each IP or the data unique to each IP is determined as not needing to be resident.

[0075] Exemplarily, the access of each logical function unit to the system shared cache is converged and routed to the local node of the system shared cache through the system bus, and a single system shared cache processing node is presented at the system level, and whether the remote expansion capacity is used does not change the routing strategy of the access request. Among them, whether the system shared cache uses remote expansion capacity and how much remote expansion capacity is used can not be perceived by each logical function unit in terms of business. When the system shared cache uses more remote storage capacity, the hit rate of each logical function unit is improved, and the performance and power consumption of the chip system are more optimized. In addition, when each logical function unit misses the system shared cache, no additional delay cost is added.

[0076] Optionally, as shown in FIG. 9, the system shared cache is configured to access the second storage array through a transmission channel.

[0077] Exemplarily, the transmission channel can include a 3D interconnection component between the logic computing die and the storage die, and an interconnection interface between the logical function units arranged on the logic computing die or the storage die.

[0078] Among them, as shown in (a) of FIG. 9, the transmission channel is a transmission channel from the second logical function area, through the first logical function area, to the second storage array. Exemplarily, the system shared cache can first pass through the horizontal wiring (which can also be referred to as an interconnection interface) of the second logical function area and the first logical function area, and then pass through the 3D interconnection component (i.e., TSV or HB, etc.) of the first logical function area and the second storage array, to access the second storage array.

[0079] Alternatively, as shown in (b) of FIG. 9, the transmission channel is a transmission channel from the second logical function area, through the second storage area, to the second storage array. Exemplarily, the system shared cache can first pass through the 3D interconnection component of the second logical function area and the second storage area, and then pass through the horizontal wiring of the second storage area and the second storage array, to access the second storage array.

[0080] Exemplarily, since the system shared cache can access the second storage array through the transmission channel, the distance between the second storage array and the system shared cache is not limited. In addition, assuming that the system shared cache borrows the storage array of multiple logical function units at the same time, and the system shared cache also accesses the storage array of other logical function units through the transmission channel, the distances from the multiple borrowed storage arrays to the system shared cache can be the same or different. In addition, since the transmission channel is arranged, different remote storage arrays can work in the same or different power domains and clock domains, and the read-write delay and bandwidth of the interface of each transmission channel can also be the same or different.

[0081] Optionally, the first storage array and the second storage array have different power supply configurations, the power supply configurations including at least one of a power domain or a clock domain. In one possible example, since the system shared cache is used to store data frequently accessed or shared by multiple logical function units, the system shared cache is usually in an active state. Assuming that the first logical function unit is in a sleep state, at this time, the power supply of the power domain has less power consumption, and can only support the first logical function unit to process simple services, at this time, if the first storage array and the second storage array adopt the same power domain, it will affect the normal use of the second storage array. Therefore, the first storage array and the second storage array can adopt different power domains and / or clock domains, which facilitates physical decoupling, that is, the working state of the first logical function unit will not affect the working state of the system-on-chip shared cache, and the normal working of the system-on-chip shared cache can be ensured. For example, as shown in (a) of FIG. 10, the first storage array and the first logical function area can adopt the same power supply configuration, for example, adopt the first power domain / clock domain, and the second storage array, the second storage area and the second logical function area can adopt the same power supply configuration, for example, adopt the second power domain / clock domain. For the first storage area, the first storage array and the second storage array adopt different power domains / clock domains.

[0082] It can be understood that the amplitude of the power supply voltage of the power domain of the first storage array and the amplitude of the power supply voltage of the power domain of the second storage array can be the same or different.

[0083] In another example, the first storage array and the second storage array can also have the same power supply configuration, so as to reduce the complexity of the power domain and / or the clock domain. As shown in (b) of FIG. 10, the first storage array, the second storage array and the first logical function area can adopt the same power supply configuration, for example, adopt the first power domain / clock domain. The second logical function area and the second storage area adopt the same power supply configuration, for example, adopt the second power domain / clock domain.

[0084] Optionally, the data array and the second storage array have the same power supply configuration. For example, the entire system shared cache can adopt the same power domain / clock domain, which facilitates timing convergence. In another example, the data array and the second storage array can also have different power supply configurations, so as to reduce the complexity of the power domain and / or the clock domain.

[0085] Optionally, as shown in FIG. 11, the logic computing die can further include a third logical function area, and a third logical function unit is arranged on the third logical function area. The storage die further includes a third storage area, and the third logical function area and the third storage area correspond in the stacking direction.

[0086] The third logic function unit can also include at least one of a central processing unit, an image processor, an image signal processor, a coding module, a modem, and a display module.

[0087] It can be understood that, in addition to the first logic function unit, the second logic function unit, and the third logic function unit, the chip system can further include a larger number of logic function units, such as a fourth logic function unit, and the like, which are not limited in the embodiments of the present application.

[0088] Optionally, continuing to refer to FIG. 11, the third storage area includes a third storage array and a fourth storage array, the third storage array is used to store third data of the third logic function unit, and the fourth storage array is used to store second data of the second logic function unit.

[0089] The third storage array is a local storage array of the third logic function unit, and the fourth storage array can also be a remote data array borrowed by the system shared cache as a system shared cache. The tag array can also store tag information of the fourth storage array, and the system shared cache can index the tag array through the tag information to access the fourth storage array.

[0090] In addition, the system shared cache can also access the fourth storage array through the transmission channel, and at this time, the transmission channel can be a transmission channel from the second logic function area, through the third logic function area, to the fourth storage array; or the transmission channel can be a transmission channel from the first logic function area, through the second storage area, to the fourth storage array, which can be referred to FIG. 9, and will not be repeated here.

[0091] In addition, the third storage array and the fourth storage array can have the same or different power supply configurations, and the data array and the fourth storage array have the same or different power supply configurations.

[0092] For example, as shown in FIG. 12, a structure diagram of a system shared cache is shown in FIG. 12. The tag array of the system shared cache includes a local tag array, remote tag arrays_1 to remote tag arrays_N, and the data array of the system shared cache includes a local data array, remote data arrays_1 to remote data arrays_N. The local tag array and the local data array correspond to each other, and the remote tag array and the remote data array correspond to each other one by one, for example, the remote tag array_1 and the remote data array_1 correspond to each other.

[0093] For example, the process of the user accessing the system shared cache can include: indexing the local tag array and the remote tag array based on the tag information of the access request, if the tag information corresponds to the tag information in the local tag array, performing data read / write from the local data array corresponding to the way; if the tag information corresponds to the tag information in the remote tag array, performing data read / write from the remote data array corresponding to the way through the transmission channel; and if the tag information does not correspond to the tag information in the local tag array and the remote tag array, initiating an access request for accessing the off-chip memory.

[0094] Optionally, at least one of the first storage array and the second storage array is a continuous region.

[0095] In a possible implementation, as shown in FIG. 13, (a) of FIG. 13 shows a schematic diagram of the arrangement region and the "forbidden arrangement region" of the first storage region of the first logic function unit, and (b) of FIG. 13 shows a schematic diagram of the arrangement region and the "forbidden arrangement region" of the system shared cache in the first storage region.

[0096] The first logic function unit includes a plurality of sub-regions in the first storage region, and the plurality of sub-regions can be arranged in a centralized manner and avoid having interconnection signals therebetween, so as to reduce the influence on the physical arrangement and timing convergence of the second storage array. The interconnection signals of the plurality of sub-regions are implemented through the first logic function region of the first logic function unit. The plurality of sub-regions are the arrangement region of the first storage array of the first logic function unit, and the idle region between the plurality of sub-regions is the "forbidden arrangement region" of the first logic function unit, which is the physical implementation region of the second storage array set by the system shared cache.

[0097] In addition, for the system shared cache, the plurality of sub-regions are the "forbidden arrangement region" of the system shared cache, and the idle region between the plurality of sub-regions is the "arrangement region" of the system shared cache.

[0098] The first storage array and the second storage array of the first logic function unit are in a mutually overlapping and mutually exclusive relationship, so that the first storage array and the second storage array can adopt the same power domain.

[0099] In another possible implementation, as shown in FIG. 14, (a) of FIG. 14 shows a schematic diagram of the arrangement of the first storage region of a first logic function unit, and (b) of FIG. 14 shows a schematic diagram of the arrangement of the first storage region of another first logic function unit.

[0100] As shown in (a) of FIG. 14, the first storage array can be arranged along the four sides, leaving a relatively complete free area in the center for physical implementation of the second storage array. As shown in (b) of FIG. 14, the first storage array can be arranged along some sides, for example, arranged along the upper side and arranged along the right side, leaving a relatively complete free area on the left side and the lower side for physical implementation of the second storage array.

[0101] That is, the first storage array and the second storage array can be arranged in a 2D manner, and the first storage array and the second storage array are not coupled. Since the areas of the first storage array and the second storage array do not overlap each other, the first storage array and the second storage array can work in different power domains, facilitating physical implementation decoupling.

[0102] The embodiments of the present application also provide an electronic device, which includes a circuit board and a chip system, and the chip system is arranged on the circuit board.

[0103] The above is merely specific implementation of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A chip system, characterized by The chip system comprises: a logic computing die and a storage die, the logic computing die and the storage die being arranged in a stack; the logic computing die comprises a first logic function area and a second logic function area, a first logic function unit being arranged on the first logic function area, and a second logic function unit being arranged on the second logic function area; the storage die comprises a first storage area and a second storage area, the first logic function area corresponding to the first storage area in a stacking direction, and the second logic function area corresponding to the second storage area in the stacking direction; the first storage area comprises a first storage array and a second storage array, the first storage array being used for storing first data of the first logic function unit, and the second storage array being used for storing second data of the second logic function unit.

2. The chip system according to claim 1, wherein the second logic function unit is a system shared cache on the logic computing die.

3. The chip system according to claim 2, wherein the second storage area comprises a tag array and a data array, the tag array being used for storing tag information of the data array and the second storage array.

4. The chip system according to claim 3, wherein the system shared cache is configured to index the tag array by the tag information to access the data array or the second storage array.

5. The chip system according to any one of claims 2-4, wherein the system shared cache is configured to access the second storage array through a transmission channel; wherein the transmission channel is a transmission channel from the second logic function area, through the first logic function area, to the second storage array; or the transmission channel is a transmission channel from the second logic function area, through the second storage area, to the second storage array.

6. The chip system according to any one of claims 1-5, wherein the first storage array and the second storage array have different power supply configurations, the power supply configurations comprising at least one of a power domain or a clock domain.

7. The chip system according to claim 6, wherein the data array and the second storage array have the same power supply configuration.

8. The chip system according to any one of claims 1-7, wherein the logic computing die further comprises a third logic function area, and a third logic function unit is arranged on the third logic function area; the storage die further comprises a third storage area, and the third logic function area corresponds to the third storage area in the stacking direction.

9. The chip system according to claim 8, wherein the third storage area comprises a third storage array and a fourth storage array, the third storage array being used for storing third data of the third logic function unit, and the fourth storage array being used for storing the second data of the second logic function unit.

10. The chip system according to any one of claims 1-9, wherein ​ The first logic function unit comprises at least one of the following: a central processing unit (CPU), a graphics processing unit (GPU), an image signal processor (ISP), an encoding module, a modem, and a display module.

11. The chip system according to any one of claims 1 to 10, wherein At least one of the first memory array and the second memory array is a contiguous region.

12. An electronic device, comprising: A circuit board and a chip system according to any one of claims 1 to 11, the chip system being arranged on the circuit board.

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