Data receiving circuit, offset calibration circuit, data receiving system and storage apparatus

Abstract

A data receiving circuit, comprising a data receiving module, a data inversion module, a feedback equalization module and a data decision module, wherein the feedback equalization module and the data receiving module are independently arranged, and the feedback equalization module is configured to execute decision feedback equalization on the basis of an enable signal and a feedback signal, with the feedback signal being obtained on the basis of previously received data, such that a first voltage signal and a second voltage signal which have a first time difference are adjusted to be a third voltage signal and a fourth voltage signal which have a second time difference; and by means of the data decision module, the third voltage signal and the fourth voltage signal are sequentially received in chronological order of arrival at a third node and a fourth node, and a first output signal and a second output signal are respectively output by means of a fifth node and a sixth node.

Description

Data receiving circuit, offset calibration circuit, data receiving system and storage device

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411260963.5, filed September 9, 2024, entitled “Data receiving circuit, offset calibration circuit, data receiving system and storage device,” the entire contents of which are incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a data receiving circuit, an offset calibration circuit, a data receiving system and a storage device. BACKGROUND

[0004] In memory applications, as signal transmission rates become faster, channel loss has a greater impact on signal quality, which can easily lead to inter-symbol interference. Currently, equalization circuits are commonly used to compensate for channels, and the equalization circuit can select a CTLE (Continuous Time Linear Equalizer) or a DFE (Decision Feedback Equalizer). However, when sampling data, the DFE will not only be limited by the data sampling time, but also be affected by the feedback signal of the previous stage, resulting in a decrease in discrimination sensitivity, a delay in discrimination time, and a decrease in discrimination speed. SUMMARY

[0005] To solve the above problems, an embodiment of the present disclosure provides a data receiving circuit, comprising:

[0006] a data receiving module configured to receive a data signal and a reference signal, and charge a first node and a second node in response to a sampling clock signal to output a first voltage signal and a second voltage signal, the first voltage signal and the second voltage signal having a first time difference therebetween;

[0007] a data inversion module connected between a power supply node and a ground terminal, configured to receive the first voltage signal and the second voltage signal and output a third voltage signal and a fourth voltage signal;

[0008] a feedback equalization module connected with the data inversion module, configured to perform decision feedback equalization based on an enable signal and a feedback signal to adjust the third voltage signal or the fourth voltage signal, so that the third voltage signal and the fourth voltage signal have a second time difference therebetween, wherein the feedback signal is obtained based on previously received data;

[0009] a data decision module configured to receive the third voltage signal and the fourth voltage signal in sequence according to the time of arrival at the third node and the fourth node, and output a first output signal and a second output signal through a fifth node and a sixth node respectively.

[0010] In some embodiments, the first time difference is less than the second time difference when the previously received data signal is at a low level and the data signal is at a high level.

[0011] In some embodiments, the data receiving module comprises: a first current source connected between a power supply node and a seventh node, configured to provide a current to the seventh node in response to the sampling clock signal;

[0012] a charging unit connected to the seventh node, the first node and the second node, configured to receive the data signal and the reference signal and output the first voltage signal through the first node and the second voltage signal through the second node when the first current source provides the current to the seventh node in response to the sampling clock signal.

[0013] In some embodiments, the first current source comprises:

[0014] a first transistor group connected between the power supply node and the seventh node, the first transistor group comprising a main transistor and a plurality of secondary transistors connected in parallel with the main transistor, configured to provide a current to the seventh node in response to a first control signal; a first switch unit connected to the first transistor group, configured to output the first control signal in response to the sampling clock signal and a first logic signal, to control the switching of the main transistor and / or the secondary transistors in the first transistor group; an adjusting unit connected to the first switch unit, configured to output the first logic signal in response to a reference signal.

[0015] In some embodiments, the first control signal comprises a main control signal and a secondary control signal, and the first switch unit comprises: a first inverter connected to the gate of the main transistor and configured to output the main control signal in response to the sampling clock signal; and a plurality of first NAND gates connected in parallel with the first inverter, each output terminal of the first NAND gates being connected to the gate of a corresponding secondary transistor and configured to output a plurality of secondary control signals in response to the sampling clock signal and the first logic signal, the secondary transistors being configured to provide a current to the seventh node in response to the secondary control signals and according to the secondary control signals.

[0016] In some embodiments, the data inversion module comprises: a first inversion unit connected between the first node and an eighth node, configured to receive the first voltage signal and output the third voltage signal; and a second inversion unit connected between the second node and a ninth node, configured to receive the second voltage signal and output the fourth voltage signal.

[0017] In some embodiments, the feedback signal comprises a first feedback signal and a second feedback signal, and the feedback equalization module comprises: a second current source connected between the power supply node and a tenth node, configured to provide a current to the tenth node in response to the second logic signal and the first feedback signal; a first decision feedback unit connected between the third node and the eighth node, configured to perform decision feedback equalization on the eighth node based on the second logic signal and the first feedback signal to adjust a time for the third voltage signal to reach the third node when the second current source provides the current to the tenth node in response to the second logic signal and the first feedback signal; a third current source connected between the power supply node and an eleventh node, configured to provide a current to the eleventh node in response to the second logic signal and the second feedback signal; and a second decision feedback unit connected between the fourth node and the ninth node, configured to perform decision feedback equalization on the ninth node based on the second logic signal and the second feedback signal to adjust a time for the fourth voltage signal to reach the fourth node when the third current source provides the current to the eleventh node in response to the second logic signal and the second feedback signal.

[0018] In some embodiments, the second current source comprises: a second transistor group connected between the power supply node and the tenth node, the second transistor group comprising a plurality of first transistors connected in parallel, configured to provide the current to the tenth node in response to a second control signal and according to the second control signal; and a first control unit connected to gates of the plurality of first transistors in the second transistor group, configured to output the second control signal in response to the second logic signal and the first feedback signal to control switching of the plurality of first transistors in the second transistor group; and the third current source comprises: a third transistor group connected between the power supply node and the eleventh node, the third transistor group comprising a plurality of second transistors connected in parallel, configured to provide the current to the eleventh node in response to a third control signal and according to the third control signal; and a second control unit connected to gates of the plurality of second transistors in the third transistor group, configured to output the third control signal in response to the second logic signal and the second feedback signal to control switching of the plurality of second transistors in the third transistor group.

[0019] In some embodiments, the first control unit comprises a plurality of second NAND gates connected in parallel, an output of each of the second NAND gates is connected to a gate of the first transistor correspondingly, each of the second NAND gates is configured to output the second control signal to control switching of the first transistor in response to the first feedback signal and the second logic signal; the second control unit comprises a plurality of third NAND gates connected in parallel, an output of each of the third NAND gates is connected to a gate of the second transistor correspondingly, each of the third NAND gates is configured to output the third control signal to control switching of the second transistor in response to the second feedback signal and the second logic signal.

[0020] In some embodiments, the feedback balancing module further comprises an enabling unit configured to receive the enabling signal and output the second logic signal, the enabling unit is connected to the first control unit and the second control unit respectively.

[0021] In some embodiments, the first decision feedback unit comprises a first PMOS transistor connected between the power supply node and the third node, a first NMOS transistor connected between the third node and the ground terminal, a second PMOS transistor connected between the third node and the tenth node, gates of the first PMOS transistor, the first NMOS transistor and the second PMOS transistor simultaneously receive the third voltage signal; the second decision feedback unit comprises a third PMOS transistor connected between the power supply node and the fourth node, a second NMOS transistor connected between the fourth node and the ground terminal, a fourth PMOS transistor connected between the fourth node and the eleventh node, gates of the third PMOS transistor, the second NMOS transistor and the fourth PMOS transistor simultaneously receive the fourth voltage signal.

[0022] In some embodiments, the charging unit comprises a first comparison unit connected between the seventh node and the first node, a gate of the first comparison unit is configured to receive the data signal; a second comparison unit connected between the seventh node and the second node, a gate of the second comparison unit is configured to receive the reference signal; a first reset unit connected between the first node and the ground terminal, configured to reset the first node in response to the sampling clock signal; a second reset unit connected between the second node and the ground terminal, configured to reset the second node in response to the sampling clock signal.

[0023] In some embodiments, the data decision module comprises a decision unit connected between the third node and the fourth node, the decision unit comprising: a third reset unit connected between a power supply node and a fifth node, configured to reset the fifth node in response to the sampling clock signal; a fourth reset unit connected between the power supply node and a sixth node, configured to reset the sixth node in response to the sampling clock signal; a first input unit connected between a twelfth node and the ground, a gate of the first input unit configured to receive the third voltage signal adjusted by the feedback equalization module; a second input unit connected between a thirteenth node and the ground, a gate of the second input unit configured to receive the fourth voltage signal adjusted by the feedback equalization module; a fifth PMOS transistor connected between the power supply node and the fifth node, a gate of the fifth PMOS transistor configured to receive the second output signal; a sixth PMOS transistor connected between the power supply node and the sixth node, a gate of the sixth PMOS transistor configured to receive the first output signal; a third NMOS transistor connected between the fifth node and the twelfth node, a gate of the third NMOS transistor configured to receive the second output signal; and a fourth NMOS transistor connected between the sixth node and the thirteenth node, a gate of the fourth NMOS transistor configured to receive the first output signal. In some embodiments, the data receiving circuit further comprises a calibration module configured to calibrate the data receiving circuit in response to a calibration signal.

[0024] According to some embodiments of the present disclosure, another aspect of the embodiments of the present disclosure further provides an offset calibration circuit configured to output a calibration signal in response to a phase signal and an oscillation clock signal, the data receiving circuit being configured to calibrate the data receiving circuit in response to the calibration signal.

[0025] According to some embodiments of the present disclosure, a third aspect of the embodiments of the present disclosure further provides a data receiving system, comprising:

[0026] a plurality of cascaded data transmission circuits, each of the data transmission circuits comprising the data receiving circuit, each of the data receiving circuits being connected to a data port to receive the data signal; a decision feedback equalization module of a previous stage data transmission circuit being connected to a decision feedback equalization module of a next stage data transmission circuit, an output of the previous stage data transmission circuit being used as the feedback signal of the decision feedback equalization module of the next stage data transmission circuit; a decision feedback equalization module of a last stage data transmission circuit being connected to a decision feedback equalization module of a first stage data transmission circuit, an output of the last stage data transmission circuit being used as the feedback signal of the decision feedback equalization module of the first stage data transmission circuit; the data receiving circuit receiving data in response to the sampling clock signal; and the data receiving system comprising four cascaded data transmission circuits, a phase difference between the sampling clock signals of adjacent stages of the data receiving circuits being 90°.

[0027] According to some embodiments of the present disclosure, the present disclosure further provides a storage device, comprising: a plurality of data ports; and a plurality of the data receiving systems, each of the data receiving systems corresponding to one of the data ports.

[0028] The technical solutions provided by the embodiments of the present disclosure have at least the following advantages:

[0029] On one hand, according to the embodiments of the present disclosure, the feedback equalization module is arranged after the data receiving module and is configured to perform decision feedback equalization based on the enable signal and the feedback signal, wherein the feedback signal is obtained based on previously received data to adjust the first voltage signal and the second voltage signal having a first time difference into a third voltage signal and a fourth voltage signal having a second time difference; the third voltage signal and the fourth voltage signal are received in sequence by the data decision module according to the time of reaching the third node and the fourth node, and the first output signal and the second output signal are output through the fifth node and the sixth node respectively, thereby avoiding the influence of inter-symbol interference on data receiving, improving the success rate of data sampling and improving the eye diagram quality.

[0030] On the other hand, by charging the first node and the second node in the data receiving module and adjusting the third voltage signal and the fourth voltage signal in the feedback equalization module, i.e., separating the voltage time conversion process from performing decision feedback equalization, the feedback equalization module is no longer affected by the input current of the data receiving module, and by separately controlling the feedback equalization module, the size of the current in the feedback equalization process can be effectively changed according to the feedback signal, thereby effectively improving the sensitivity and speed of the feedback equalization module in operation, and reducing the time for performing decision feedback equalization. BRIEF DESCRIPTION OF DRAWINGS

[0031] One or more embodiments are illustrated by way of example in the drawings and specification hereof, which constitute part of this patent document, illustrate embodiments in which the principles of the disclosure can be employed, and are not intended to limit the scope of the disclosure unless otherwise specifically indicated herein. In the drawings:

[0032] Fig. 1 is a functional block diagram of a data receiving circuit according to an embodiment of the present disclosure;

[0033] Fig. 2 is another functional block diagram of a data receiving circuit according to an embodiment of the present disclosure;

[0034] Fig. 3 is a schematic diagram of a circuit structure of a data receiving circuit according to an embodiment of the present disclosure;

[0035] Fig. 4 is a schematic diagram of signal time variation before and after adjustment of a data receiving module and a feedback equalization module according to an embodiment of the present disclosure;

[0036] Figs. 5(a)-5(c) are schematic diagrams of a circuit structure of an enabling unit, a second current source and a third current source, respectively, in a feedback equalization module according to an embodiment of the present disclosure;

[0037] Fig. 6 is a comparison diagram of eye diagrams when a feedback equalization module is in an active state (DFE ON) and in an inactive state (DFE OFF) according to an embodiment of the present disclosure;

[0038] Fig. 7(a) is a diagram of a relationship between a reference voltage and a time gain corresponding to a data receiving circuit according to an embodiment of the present disclosure, Fig. 7(b) is a diagram of a relationship between a gear of an enabling unit and a feedback voltage corresponding to a data receiving circuit according to an embodiment of the present disclosure, and Fig. 7(c) is a diagram of a change in eye height before and after adjustment of a DFE switch and a gear according to an embodiment of the present disclosure;

[0039] Fig. 8 is a functional block diagram of a data receiving system according to an embodiment of the present disclosure;

[0040] Fig. 9 is a functional block diagram of a data receiving system including an offset calibration circuit according to an embodiment of the present disclosure;

[0041] Fig. 10 is a schematic diagram of a circuit structure of an offset calibration circuit according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0042] In a high-speed receiving circuit, the DFE (Decision Feedback Equalizer) function can effectively reduce the influence of ISI (Inter-Symbol Interference) and improve the accuracy and reliability of data reception. In the circuit design in the prior art, the receiving circuit based on a double-tail dynamic comparator generally completes the discrimination of the input voltage and the application of the DFE function at the first stage to offset the ISI through the DFE algorithm and ensure the correct decoding of the data. However, when sampling data, the DFE is not only limited by the data sampling time, but also needs to complete the sampling of the current data within the time of one data width and feed back the result to the next sampling. The speed is accelerated by increasing the input current of the charging unit, which will cause the discrimination sensitivity to decrease and then affect the working speed of the subsequent decision unit. Moreover, the DFE feedback capability is affected by the reference voltage, and the feedback capability is quite different at different VREF voltages, which affects the symmetry of the shmoo eye diagram.

[0043] To solve the above technical problems, the embodiments of the present disclosure provide a data receiving circuit, a data receiving system and a storage device, which will be described in detail below in combination with the drawings. However, those skilled in the art can understand that in the embodiments of the present disclosure, many technical details are proposed in order to enable the readers to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed by the present disclosure can be implemented.

[0044] FIG. 1 is a functional block diagram of a data receiving circuit according to an embodiment of the present disclosure; FIG. 2 is another functional block diagram of a data receiving circuit according to an embodiment of the present disclosure; FIG. 3 is a schematic diagram of a circuit structure of a data receiving circuit according to an embodiment of the present disclosure; and FIG. 4 is a schematic diagram of signal time changes before and after the adjustment of a data receiving module and a feedback equalization module according to an embodiment of the present disclosure.

[0045] Referring to FIGS. 1-4, the embodiment of the present disclosure provides a data receiving circuit 10, comprising: a data receiving module 100 configured to receive a data signal DQ and a reference signal Vref, and charge a first node n_stg1 and a second node p_stg1 in response to a sampling clock signal CLK to output a first voltage signal and a second voltage signal, the first voltage signal and the second voltage signal having a first time difference Δt1; a data inversion module 200 connected between a power supply node Vcc and a ground terminal, configured to receive the first voltage signal and the second voltage signal, and output a third voltage signal and a fourth voltage signal; a feedback equalization module 300 connected with the data inversion module 200, configured to perform decision feedback equalization based on an enable signal DFE[0:2] and a feedback signal fdata / fdatan to adjust the third voltage signal or the fourth voltage signal, so that the third voltage signal and the fourth voltage signal have a second time difference Δt2, wherein the feedback signal fdata / fdatan is obtained based on previously received data; and a data decision module 400 configured to receive the fourth voltage signal and the third voltage signal in turn according to the time of reaching a third node net3 and a fourth node net4, and output a first output signal Vout and a second output signal VoutN through a sixth node net6 and a fifth node net5, respectively.

[0046] It can be understood that the feedback equalization module 300 is arranged after the data receiving module 100, and is configured to perform decision feedback equalization based on the enable signal DFE[0:2] and the feedback signal fdata / fdatan, wherein the feedback signal fdata / fdatan is obtained based on previously received data, so that the first voltage signal and the second voltage signal having the first time difference Δt1 are adjusted to the third voltage signal and the fourth voltage signal having the second time difference Δt2; the third voltage signal and the fourth voltage signal are received in turn by the data decision module 400 according to the time of reaching the third node net3 and the fourth node net4, and the first output signal Vout and the second output signal VoutN are output through the fifth node net5 and the sixth node net6, respectively, so that the time difference of the voltage signal is increased, the success rate of data sampling is improved, and the influence of intersymbol interference is avoided.

[0047] In addition, by charging the first node n_stg1 and the second node p_stg1 in the data receiving module 100 and adjusting the third voltage signal and the fourth voltage in the feedback equalization module 300, that is, separating the voltage time conversion process from the decision feedback equalization process, the feedback equalization module 300 is no longer affected by the input current of the data receiving module 100, and by separately controlling the feedback equalization module 300, the size of the current in the feedback equalization process can be effectively changed according to the feedback signal fdata / fdatan, thereby effectively improving the sensitivity and speed of the feedback equalization module 300, and reducing the time of executing the decision feedback equalization.

[0048] In some embodiments, the data receiving module 100 can include: a first current source 101 connected between a power supply node Vcc and a seventh node net7, configured to provide a current to the seventh node net7 in response to a sampling clock signal CLK; and a charging unit 102 connected to the seventh node net7, the first node n_stg1 and the second node p_stg1, configured to receive a data signal DQ and a reference signal Vref when the first current source 101 provides a current to the seventh node net7 in response to the sampling clock signal CLK, and output a first voltage signal through the first node n_stg1 and a second voltage signal through the second node n_stg1.

[0049] In some embodiments, the first current source 101 can include: a first transistor group 1011 connected between the power supply node Vcc and the seventh node net7, the first transistor group 1011 including a main transistor 1011a and a plurality of secondary transistors 1011b connected in parallel with the main transistor 1011a, configured to provide a current to the seventh node net7 in response to a first control signal; a first switch unit 1012 connected to the first transistor group 1011, configured to output the first control signal in response to the sampling clock signal CLK and a first logic signal, to control the switching of the main transistor 1011a and / or the secondary transistors 1011b in the first transistor group 1011; and an adjustment unit 1013 connected to the first switch unit 1012, configured to output the first logic signal in response to the reference signal Vref, and the adjustment unit 1013 can be a register, and the first logic signal includes at least one of ad1, ad2 and ad3 obtained by voltage decoding of the register.

[0050] In some embodiments, the first control signal can include a main control signal dr0 and a plurality of secondary control signals dr1, dr2 and dr3, wherein the main control signal dr0 is used to control the switching of the main transistor 1011a, and the secondary control signals dr1, dr2 and dr3 are used to control the switching of the plurality of secondary transistors 1011b, respectively.

[0051] The first switch unit 1012 can include a first inverter 1012a connected with the gate of the main transistor 1011a and configured to output a main control signal dr0 in response to a sampling clock signal CLK, and a plurality of first NAND gates 1012b connected in parallel with the first inverter 1012a and configured to output a plurality of secondary control signals in response to the sampling clock signal CLK and a first logic signal including at least one of ad1, ad2 and ad3, wherein the secondary control signal includes at least one of dr1, dr2 and dr3 to determine whether the corresponding plurality of secondary transistors 1011b controlled by the plurality of secondary control signals are turned on, i.e., the secondary transistors 1011b are responsive to the secondary control signal and determine whether to provide a current to the seventh node net7 according to the secondary control signal.

[0052] In some embodiments, the channel equivalent width-length ratios of the plurality of secondary transistors 1011b can be different from that of the main transistor 1011a, for example, the channel equivalent width-length ratio of the main transistor 1011a is twice that of the secondary transistor 1011b, and the channel equivalent width-length ratios of the plurality of secondary transistors 1011b are the same. In this way, the ratio of the equivalent resistance of the main transistor 1011a to that of the secondary transistor 1011b is 1:2, so that the total equivalent resistance of the first current source 101 can be adjusted by controlling whether the secondary transistor 1011b is turned on, thereby achieving adjustment of the current at the first node n_stg1 and the current at the second node p_stg1 in the charging unit 102.

[0053] In some embodiments, referring to FIGS. 1-5, the feedback signal includes a first feedback signal fdata and a second feedback signal fdatan, wherein the first feedback signal fdata and the second feedback signal fdatan are differential signals, and the feedback equalization module 300 includes a second current source 301 configured to be connected between a power supply node Vcc and a tenth node net10 and to provide a current to the tenth node net10 in response to a second logic signal and the first feedback signal fdata, and a first decision feedback unit 302 connected between a third node net3 and an eighth node net8 and configured to perform decision feedback equalization on the eighth node net8 based on an enable signal and the first feedback signal fdata to adjust the time for the third voltage signal to reach the third node net3 when the second current source 301 provides the current to the tenth node net10 in response to the enable signal and the first feedback signal fdata.

[0054] The third current source 303 is configured to be connected between the power supply node Vcc and the eleventh node net11, and to provide a current to the eleventh node net11 in response to the second logic signal and the second feedback signal fdatan; and the second decision feedback unit 304 is connected between the fourth node net4 and the ninth node net9, and is configured to perform decision feedback equalization on the ninth node net9 based on the second logic signal and the second feedback signal fdatan, so as to adjust the time for the fourth voltage signal to reach the fourth node net4, when the third current source 303 provides the current to the eleventh node net11 in response to the second logic signal and the second feedback signal fdatan.

[0055] In some embodiments, referring to FIG. 5, the second current source 301 can include: a second transistor group 3011 connected between the power supply node Vcc and the tenth node net10, the second transistor group 3011 including a plurality of parallel first transistors 3011a configured to determine whether to provide a current to the tenth node net10 in response to a second control signal according to the second control signal, wherein the second control signal can be at least one of D11, D12, D13, and D14; and a first control unit 3012 connected to the gates of the plurality of parallel first transistors 3011a in the second transistor group 3011, and configured to output at least one second control signal in response to a second logic signal and a first feedback signal, so as to control the switching of the plurality of first transistors 3011a in the second transistor group 3011, wherein the second logic signal can be at least one of DR11, DR21, DR22, and DR23.

[0056] The third current source 303 can include: a third transistor group 3031 connected between the power supply node Vcc and the eleventh node net11, the third transistor group 3031 including a plurality of parallel second transistors 3031a configured to determine whether to provide a current to the eleventh node net11 in response to a third control signal according to the third control signal, wherein the third control signal can be at least one of D21, D22, D23, and D24; and a second control unit 3032 connected to the gates of the plurality of parallel second transistors 3031a in the third transistor group 3031, and configured to output at least one third control signal in response to a second logic signal and a second feedback signal, so as to control the switching of the plurality of second transistors 3031a in the third transistor group 3031.

[0057] In some embodiments, the first control unit 3012 can include a plurality of second NAND gates 3012b connected in parallel, the output of each second NAND gate 3012b is connected to the gate of the first transistor 3011a, and each second NAND gate 3012b is configured to output a second control signal to control the switching of the first transistor 3011a in response to the first feedback signal fdata and the second logic signal.

[0058] The second control unit 3032 includes a plurality of third NAND gates 3032b connected in parallel, the output of each third NAND gate 3032b is connected to the gate of the second transistor 3031a, and each third NAND gate 3032b is configured to output a third control signal to control the switching of the second transistor 3031a in response to the second feedback signal fdatan and the second logic signal.

[0059] In some embodiments, the feedback equalization module 300 further includes an enabling unit 305 configured to receive an enabling signal DFE[0:2] and output a second logic signal, and the enabling unit 305 is connected to the first control unit 3012 and the second control unit 2032, respectively. Referring to FIG. 5(a), the enabling unit 305 can be composed of a plurality of NAND gates and inverters, for example, the enabling signal DFE0 is outputted as the second logic signal DR11 after passing through an inverter, and the enabling signal DFE[0:2] is outputted as the second logic signal DR21, DR21, and DR23 after passing through inverters and NAND gates. The enabling signal can be at least one of DFO, DF1, and DF2, for example, as shown in Table 1, the enabling unit 305 outputs different second logic signals under different enabling signals, and the enabling unit 305 has different gears under different enabling signals, the higher the gear, the more transistors are turned on under the corresponding feedback signal, as shown in Table 1.

[0060] Table 1

[0061] In some embodiments, the first decision feedback unit 302 includes a first PMOS transistor MP1 connected between a power supply node Vcc and a third node net3, a first NMOS transistor MN1 connected between the third node net3 and a ground terminal, and a second PMOS transistor MP2 connected between the third node net3 and a tenth node net10, the gates of the first PMOS transistor MP1, the first NMOS transistor MN1, and the second PMOS transistor MP2 are configured to simultaneously receive the third voltage signal.

[0062] The second decision feedback unit 304 includes a third PMOS transistor MP3 connected between a power supply node Vcc and a fourth node net4, a second NMOS transistor MN2 connected between the fourth node net4 and a ground terminal, and a fourth PMOS transistor MP4 connected between the fourth node net4 and an eleventh node net11, the gates of the third PMOS transistor MP3, the second NMOS transistor MN2, and the fourth PMOS transistor MP4 being configured to simultaneously receive the fourth voltage signal.

[0063] In some embodiments, referring to FIGS. 1-3, the charging unit 102 can include a first comparison unit 1021 connected between the seventh node net7 and a first node n_stg1, the gate of the first comparison unit 1021 being configured to receive the data signal DQ; a second comparison unit 1022 connected between the seventh node net7 and a second node p_stg1, the gate of the second comparison unit 1022 being configured to receive the reference signal Vref; a first reset unit 1023 connected between the first node n_stg1 and the ground terminal, the first reset unit 1023 being configured to reset the first node n_stg1 in response to the sampling clock signal CLK; and a second reset unit 1024 connected between the second node p_stg1 and the ground terminal, the second reset unit 1024 being configured to reset the second node p_stg1 in response to the sampling clock signal CLK.

[0064] In some embodiments, referring to FIG. 1-3, the data decision module 400 can include a decision unit 401 connected between the third node net3 and the fourth node net4, the decision unit 401 can include: a third reset unit 4011 connected between the power supply node Vcc and a fifth node net5, configured to reset the fifth node net5 in response to the sampling clock signal CLK; a fourth reset unit 4012 connected between the power supply node Vcc and a sixth node net6, configured to reset the sixth node net6 in response to the sampling clock signal CLK; a first input unit 4013 connected between the twelfth node net12 and the ground, a gate of the first input unit 4013 connected to the third node net3, for receiving the third voltage signal adjusted by the feedback equalization module 300; a second input unit 4014 connected between the thirteenth node net13 and the ground, a gate of the second input unit 4014 connected to the fourth node net4, for receiving the fourth voltage signal adjusted by the feedback equalization module 300; a fifth PMOS tube MP5 connected between the power supply node Vcc and the fifth node net5, a gate of the fifth PMOS tube MP5 for receiving the second output signal VoutN; a sixth PMOS tube MP6 connected between the power supply node Vcc and the sixth node net6, a gate of the sixth PMOS tube MP6 for receiving the first output signal Vout; a third NMOS tube MN3 connected between the fifth node net5 and the twelfth node net12, a gate of the third NMOS tube MN3 connected to the sixth node net6, for receiving the second output signal VoutN; a fourth NMOS tube MN4 connected between the sixth node net6 and the thirteenth node net13, a gate of the fourth NMOS tube MN4 connected to the fifth node net5, for receiving the first output signal Vout.

[0065] In some embodiments, the data receiving module 100, the feedback equalization module 400 and the data decision module 400 are further configured to, before receiving the data signal DQ, reset the first node n_stg1, the second node p_stg1, the fifth node net5 and the sixth node net6 in response to the sampling clock signal CLK, specifically, before receiving the data signal DQ, the first comparison unit 1021 and the second comparison unit 1022 are both in the off state in response to the data signal DQ and the reference signal Vref respectively; the first reset unit 1023 and the second reset unit 1024 reset the first node n_stg1 and the second node p_stg1 in response to the sampling clock signal CLK, that is, the first node n_stg1 and the second node p_stg1 are both pulled low to the low level state, the second current source 301 and the third current source 303 in the feedback equalization module 300 are both in the off state, and the voltage signal from the first node n_stg1 and the second node p_stg1 continues to maintain the low level state after passing through the data inversion module 200 and the feedback equalization module 300, so that the third reset unit 4011 and the fourth reset unit 4012 are opened, and the first input unit 4013 and the second input unit 4014 are closed, thereby resetting the fifth node net5 and the sixth node net6, that is, the fifth node net5 and the sixth node net6 are both pulled high to the high level state, so as to facilitate the next data receiving and processing of the subsequent data receiving circuit. No additional sampling clock signal is needed during the process of resetting the first node n_stg1, the second node p_stg1, the fifth node net5 and the sixth node net6, which simplifies the circuit design.

[0066] In some embodiments, the data inversion module 200 comprises: a first inversion unit 201 connected between the first node n_stg1 and the eighth node net8, configured to receive the first voltage signal and output a third voltage signal; and a second inversion unit 202 connected between the second node p_stg1 and the ninth node net9, configured to receive the second voltage signal and output a fourth voltage signal. The arrangement of the data inversion module 200 ensures that at least one of the first input unit 4013 and the second input unit 4014 is in the open state, and the data signal DQ and the reference signal Vref can cause the corresponding rising edge signal to flip after passing through the data inversion module 200, and still in the form of a rising edge to trigger the data decision module 400 after passing through the feedback equalization module 300, so that the first input unit 4013 and the second input unit 4014 in the data decision module 400 can still be designed with NMOS, thereby avoiding the increase in size caused by PMOS and effectively saving the circuit layout area.

[0067] In some embodiments, the first comparison unit 1021 and the second comparison unit 1022 can be PMOS transistors, and when the first current source 1011 provides current to the seventh node net7, the first comparison unit 1021 and the second comparison unit 1022 are in working state, thereby comparing the received data signal DQ and the reference signal Vref.

[0068] It should be noted that due to the increase of signal transmission rate and the influence of channel loss on signal quality, it is easy to cause inter-symbol interference, so that the data signal DQ does not have enough time to rise or fall to the preset potential. When the first current source 101 provides current to the seventh node net7 in response to the sampling clock signal CLK, due to the influence of the level value of the data signal DQ, as the potential of the seventh node net7 gradually rises, the turn-on time of the first comparison unit 1021 receiving the data signal DQ is different from the turn-on time of the second comparison unit 1022 receiving the reference signal Vref, and at the same time, the turn-on degree of the first comparison unit 1021 is different from the turn-on degree of the second comparison unit 1022. For example, referring to FIG. 4, when the voltage of the data signal DQ is greater than the voltage of the reference signal Vref, the turn-on degree of the first comparison unit 1021 is less than the turn-on degree of the second comparison unit 1022, so that the current at the seventh node net7 flows more into the path where the second comparison unit 1022 is located, and the current at the first node n_stg1 is less than the current at the second node p_stg1, thereby further making the second voltage signal output by the second node p_stg1 reach the turn-on threshold of the NMOS transistor in the second inverting unit 202 or the first inverting unit 201 earlier than the first voltage signal, that is, there is a first time difference Δt1 between the first voltage signal and the second voltage signal.

[0069] The first voltage signal and the second voltage signal are output as a third voltage signal and a fourth voltage signal after passing through the data inverting module 200, and then transmitted to the feedback equalization module 300, and then the second current source 301 provides current to the tenth node net10 in response to the second logic signal and the first feedback signal fdata, and the eighth node net8 is judged and feedback equalized based on the second logic signal and the first feedback signal fdata, so as to adjust the time when the third voltage signal reaches the third node net3; the third current source 303 provides current to the eleventh node net11 in response to the second logic signal and the second feedback signal fdatan, and the ninth node net9 is judged and feedback equalized based on the second logic signal and the second feedback signal fdatan, so as to adjust the time when the fourth voltage signal reaches the fourth node net4.

[0070] Exemplarily, with reference to FIGS. 1-6, after receiving the third voltage signal, the first NMOS transistor MN1 is turned off, the first PMOS transistor MP1 and the second PMOS transistor MP2 are turned on, and after receiving the fourth voltage signal, the second NMOS transistor MN2 is turned off, the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are turned on. When the first output signal Vout output by the previous-stage data receiving circuit 10, i.e., the first feedback signal fdata of the next-stage data receiving circuit 10, is at a low level, the second output signal VoutN output by the previous-stage data receiving circuit 10, i.e., the second feedback signal fdatan of the next-stage data receiving circuit 10, is at a high level, and when the enable unit 305 is at the first gear, the second control signals D11, D12, D13, and D14 output by the plurality of second NAND gates 3012a in the second current source 301 are all at high levels, at this time, the plurality of first transistors 3011a in the second transistor group 3011 are all turned off after receiving the second control signals D11, D12, D13, and D14, and no current flows through the tenth node connected with the second current source 301; the third control signal D21 output by the third NAND gate 3032b in the third current source 303 in response to the second logic signal DR11 is at a low level, the third control signals D22, D23, and D24 output by the third NAND gates 3032b receiving the second logic signals DR22, DR23, and DR24 are at high levels, at this time, the second transistor 3031a in the third transistor group 3031 controlled by the third control signal D21 is turned on, the second transistors 3031a controlled by the third control signals D22, D23, and D24 are turned off, and the current flows through the eleventh node connected with the third current source 303, compared with the third voltage signal, the fourth voltage signal reaches the fourth node net4 earlier, i.e., the second time difference Δt2 between the third voltage signal and the fourth voltage signal is greater than the first time difference Δt1 between the first voltage signal and the second voltage signal, with reference to FIG. 4, due to the influence of the inter-symbol interference, when the first output signal Vout output by the previous-stage data receiving circuit 10 is at a low level and the first output signal Vout to be output by the current-stage data receiving circuit 10 is at a high level, i.e., the data signal output by the data receiving circuit 10 jumps from “0” to “1”, the generated Δt1 is limited in size, after passing through the feedback equalization module 300, the value is amplified to Δt2, thereby making up for the problem that the inter-symbol interference caused by the transmission of “0” of the previous bit makes Δt1 smaller, thereby ensuring the correct reading out of the current-stage data receiving circuit 10.The channel equivalent width-length ratios of the plurality of first transistors 3011a in the second transistor group 3011 can be different, and the channel equivalent width-length ratios of the plurality of second transistors 3031a in the third transistor group 3031 can also be different. By adjusting the channel equivalent width-length ratios of the plurality of first transistors 3011a in the second transistor group 3011 and the plurality of second transistors 3031a in the third transistor group 3031, linear adjustment of the current at the tenth node net10 or the eleventh node net11 in the feedback equalization module 300 can be achieved.

[0071] For example, the channel equivalent width-length ratios of the plurality of first transistors 3011a in the second transistor group 3011 can be different, for example,

[0072] The channel equivalent width-length ratios of the first transistors 3011a controlled by the second control signals D12, D13, and D14 are twice the channel equivalent width-length ratios of the first transistors 3011a controlled by the second control signal D11. In this way, the enable unit 305 has different gears according to different enable signals DFE[2:0]. The higher the gear, the more transistors that are turned on under the corresponding feedback signal. The ratio of the equivalent resistance of the first transistors 3011a controlled by the second control signal D11, the equivalent resistance of the first transistors 3011a controlled by the second control signal D12, the equivalent resistance of the first transistors 3011a controlled by the second control signal D13, and the equivalent resistance of the first transistors 3011a controlled by the second control signal D14 is 2:1:1:1, so that the total equivalent resistance of the second current source 301 can be linearly adjusted, thereby achieving linear adjustment of the current at the tenth node net10 in the feedback equalization module 300.

[0073] It should be noted that the above is only an exemplary description in which the channel equivalent width-length ratios of the first transistors 3011a controlled by the second control signals D12, D13, and D14 are twice the channel equivalent width-length ratios of the first transistors 3011a controlled by the second control signal D11. In actual applications, the ratio of the channel equivalent width-length ratios of the first transistors 3011a controlled by the second control signals D12, D13, and D14 to the channel equivalent width-length ratios of the first transistors 3011a controlled by the second control signal D11 can also be other values, for example, 3 or 4, etc.

[0074] In some embodiments, the length of the channel of the corresponding first transistor 3011a controlled by the second control signal D11, D12, D13, D14 can be equal, or the width of the channel of the first transistor 3011a controlled by the second control signal D12, D13, D14 can be twice the width of the channel of the first transistor 3011a controlled by the second control signal D11. It should be noted that in actual applications, while keeping the width of the channel of the first transistor 3011a controlled by the second control signal D11, the first transistor 3011a controlled by the second control signal D12, the first transistor 3011a controlled by the second control signal D13, and the first transistor 3011a controlled by the second control signal D14 the same, the ratio relationship of the length of the channel of the first transistor 3011a controlled by the second control signal D11, the first transistor 3011a controlled by the second control signal D12, D13, D14 can be adjusted, or both the ratio relationship of the width of the channel of the first transistor 3011a controlled by the second control signal D11, the first transistor 3011a controlled by the second control signal D12, D13, D14 and the ratio relationship of the length of the channel of the first transistor 3011a controlled by the second control signal D11, the first transistor 3011a controlled by the second control signal D12, D13, D14 are adjusted to achieve the ratio relationship between the equivalent width-length ratios of the first transistor 3011a controlled by the second control signal D11, the first transistor 3011a controlled by the second control signal D12, D13, D14.

[0075] It should be noted that the first transistor 3011a controlled by the second control signal D11, D12, D13, D14 can be a PMOS tube, and the on-off state of the first transistor 3011a corresponding to the second control signal D11, D12, D13, D14 can be adjusted by controlling the high and low levels of the second control signal D11, D12, D13, D14. For example, when the second control signal D11, D12 is at a low level and the second control signal D13, D14 is at a high level, the first transistor 3011a controlled by the second control signal D11, D12 is turned on, and the first transistor 3011a controlled by the second control signal D13, D14 is turned off, thereby changing the current size at the tenth node net10 in the feedback equalization module 300. In addition, when the second control signals D11, D12, D13, D14 are the same, the current size at the tenth node net10 can also be changed by changing the length of the channel of the first transistor 3011a corresponding to the second control signal D11, D12, D13, D14. The equivalent width-length ratio of the channels of the plurality of second transistors 3031a in the third transistor group 3031 can also be different to achieve linear regulation of the current at the eleventh node net11 in the feedback equalization module 300. For details, refer to the length-width ratio setting mode of the channels of the plurality of first transistors 3011a in the second transistor group 3011, which will not be described here.

[0076] The fourth voltage signal adjusted by the first decision feedback unit 302 reaches the decision unit 401 earlier than the third voltage signal. At this time, the fifth node net5 and the sixth node net6 after reset are both at a high level, that is, the third NMOS tube MN3 and the fourth NMOS tube MN4 are both in a conducting state. Since the fourth voltage signal reaches the fourth node net4 earlier than the third voltage signal reaches the third node net3, the second input unit 4014 is turned on earlier than the first input unit 4013, the potential of the sixth node net6 drops earlier than the potential of the fifth node net5, and a positive feedback is formed between the third NMOS tube MN3, the fourth NMOS tube, the fifth PMOS tube MP5, and the sixth PMOS tube MP6. The potential of the sixth node net6 drops, causing the fifth PMOS tube MP5 to gradually conduct and the third NMOS tube MN3 to gradually turn off, thereby hindering the drop of the potential of the fifth node net5. Finally, the sixth node net6 is pulled to a low level earlier than the fifth node net5, and the second output signal VoutN is output as a low level. The first output signal Vout is output as a high level due to the conduction of the fifth PMOS tube MP5 and the turn-off of the third transistor MN3. In other embodiments, the voltage of the data signal DQ received by the current data receiving circuit 10 can also be higher than the logic level value of the reference signal Vref. The adjustment of the third voltage signal and the fourth voltage signal by the feedback equalization module 300 can refer to the above steps, which will not be described here.

[0077] Figure 6(c) is a comparison of eye diagrams of the feedback equalization module 300 in the working state (DFE ON) and the non-working state (DFE OFF). The data signal quality of the data receiving circuit can be analyzed through the signal eye diagram. It can be seen that when the enabling unit 305 is in the first gear (DFE = 1), the overlapping part (OVERLAP) is the eye diagram area when the feedback equalization module 300 is in the non-working state (DFE OFF). That is, the eye diagram area when the feedback equalization module 300 is in the working state (DFE ON) is greater than the eye diagram area when the feedback equalization module 300 is in the non-working state (DFE OFF). That is, after the adjustment of the feedback equalization module 300, the influence of the inter-symbol interference on the data receiving circuit 10 is effectively avoided, and the sampling success rate of the data signal DQ is improved. In other embodiments, the enabling unit 305 can also be set to other gears as needed to achieve current regulation at the tenth node net10 or the eleventh node net11.

[0078] In addition, the time difference value of charging the first node n_stg1 and the second node p_stg1 in the data receiving module 100 to the threshold voltage of the NMOS transistor in the first inverting unit 201 or the second inverting unit 202, that is, the gain of converting voltage to time The first time difference Δt1 between the first voltage signal and the second voltage signal can be calculated by formula (1):

[0079] Wherein, C N , C P respectively represent the current at the first node n_stg1 and the parasitic capacitance value at the second node p_stg1, C P,N represents the parasitic capacitance value of the first node n_stg1 or the second node p_stg1, C P =C N =C P,N , V thn* represents the threshold voltage of the NMOS transistor in the first inverting unit 201 or the second inverting unit 202, I tail1 , I B1 , I B2 respectively represent the current values at the seventh node net7, the first node n_stg1 and the second node p_stg1, g m1,2 represents the equivalent transconductance.

[0080] After the feedback equalization module 300, the first time difference Δt1 of the third voltage signal and the fourth voltage signal is amplified to the second time difference Δt2. This process can be achieved by adjusting the charging current of the third node net3 and the fourth node net4. The second time difference Δt2 can be calculated by formula (2):

[0081] wherein C 3,4 represents the parasitic capacitance at node net3 or net4, I tail2 represents the average current flowing through the first PMOS transistor MP1 or the third PMOS transistor MP3, V TH represents the threshold voltage of the post-stage NMOS transistor. ΔI represents the additional current provided by the second current source 301 or the third current source 303 according to the time difference of the second control signal or the third control signal adjusting the third voltage signal and the fourth voltage signal to reach the threshold voltage of the first input unit 4013 and the second input unit 4014 transistor.

[0082] According to formula (1), when the data receiving module 100 is in a working state, the change of the reference signal Vref will affect the size of the current I tail1 at the seventh node net7 in the transient process, and further affect the size of the first time difference Δt1. Exemplarily, as shown in FIG. 7(a), in the case of ensuring that the voltage difference between the data signal DQ and the reference signal Vref is fixed, for example, the voltage difference between the data signal DQ and the reference signal Vref can be 30mv, gradually increasing the value of the reference signal Vref, the first time difference Δt1 rapidly rises with the increase of the reference signal Vref.

[0083] Let Δt1 and Δt2-Δt1 be equal, the feedback voltage provided by the feedback equalization module 300 can be investigated. It can be understood that the feedback voltage V feedback is the voltage value corresponding to the current compensation provided by the feedback equalization module 300, which can be calculated by formula (3):

[0084] Since the charging unit 102 and the feedback equalization module 300 are separated, the change of the reference signal Vref will not affect the working state of the feedback equalization module 300, so the second time difference Δt2 is also certain when the input of the enable signal DFE[0:2] is certain. In the process of increasing the reference signal Vref, the current I tail1 at the seventh node net7 becomes smaller, so that the feedback voltage V feedback becomes smaller. As shown in FIG. 7(b), under different reference signals Vref, for example, when the reference signal Vref has voltages of 100mv and 250mv respectively, the feedback voltage V feedback has different change curves when the enable unit 305 is in different gears, which further causes the height of the upper and lower edges of the eye diagram to be inconsistent with the change of the gear of the enable unit 305. Therefore, in order to improve the quality of the eye diagram, according to the above analysis and formula (1), the number of turned-on sub-transistors 1011b in the first transistor group 1011 can be controlled according to the voltage size of the reference signal Vref, so as to adjust the current Itail1 value, thereby reducing the impact on the feedback voltage V feedback to a certain extent.

[0085] Exemplarily, the current I tail1 With the change of Vref, referring to Table 2, when the value of the reference signal Vref is less than 100 mv, the first logic signals ad1, ad2 and ad3 are all low; when the value of the reference signal Vref is greater than or equal to 100 mv and less than 200 mv, the first logic signal ad1 is high, and the first logic signals ad2 and ad3 are all low; when the value of the reference signal Vref is greater than or equal to 200 mv and less than 300 mv, the first logic signals ad1 and ad2 are high, and the first logic signal ad3 is low; when the value of the reference signal Vref is greater than or equal to 300 mv, the first logic signals ad1, ad2 and ad3 are all high.

[0086] Table 2

[0087] Exemplarily, when the sampling clock signal CLK is at a logic high level, and the value of the reference signal Vref is greater than or equal to 100 mv and less than 200 mv, the first logic signal ad1 is high, and the first logic signals ad2 and ad3 are all low. After passing through the first inverter 1012a and the plurality of first NAND gates 1012b connected in parallel with the first inverter 1012a, the output main control signal dr0 is low, the secondary control signal dr1 is low, and the secondary control signals dr2 and dr3 are high. At this time, the main transistor 1011a is turned on after receiving the main control signal dr0, the secondary transistor 1011b controlled by the secondary control signal dr1 is also turned on, and the secondary transistors 1011b controlled by the secondary control signals dr2 and dr3 are turned off, thereby increasing the current I tail1 value at the seventh node net7, and achieving the adjustment of the current size at the seventh node net7. Since the channel equivalent width-length ratios of the plurality of secondary transistors 1011b can be different, the channel length-width ratio of the secondary transistor 1011b can be changed to achieve the adjustment of the current size at the seventh node net7. Therefore, according to the foregoing analysis and formula (1), it can be judged that when the difference between the logic level values of the data signal DQ and the reference signal Vref is fixed, the value of the reference signal Vref is gradually increased, and the channel length-width ratio of the secondary transistor 1011b is adjusted to increase the current I tail1 value at the seventh node net7, thereby ensuring that the first time difference Δt1 does not increase rapidly with the change of the reference signal Vref. Referring to FIG. 7(a), it can be seen that the change range of the adjusted time gain curve is smaller than that of the unadjusted time gain curve, thereby effectively reducing the impact on the feedback voltage Vfeedback the impact of the reference signal Vref.

[0088] Referring to FIG. 7(b), the current I tail1 After the value adjustment, the logic level values of different reference signals Vref, for example, can be 100mv and 250mv, and with the increase of the gear of the enable unit 305, the feedback voltage V feedback The curves of the change of the gears tend to be consistent, that is, the size of the logic level value of the reference signal Vref has little effect on the feedback voltage V feedback The impact is reduced, thereby improving the symmetry of the upper and lower edges of the eye diagram, as shown in FIG. 7(c). For example, when the gear of the first enable unit 3012 or the second enable unit 3032 is set to "7", the upper and lower edges of the eye diagram of the feedback equalization module 300 in the working state (DFE ON) or the non-working state (DFE OFF) are changed from the asymmetry before the adjustment to the symmetry after the adjustment, and the symmetry of the upper and lower edges of the eye diagram is improved.

[0089] In some embodiments, referring to FIGS. 1-3, due to the fixed mismatch voltage between the various transistors caused by the differences in the preparation process and structure during the circuit manufacturing process, that is, the mismatch between the transistors is converted to the first comparison unit 1021 and the second comparison unit 1022, there is an equivalent mismatch voltage between the first comparison unit 1021 and the second comparison unit 1022. Therefore, the data receiving circuit 10 can further include a calibration module 500 configured to, in response to a calibration signal offset[5:0], calibrate the data receiving circuit 10 to reduce the mismatch voltage and improve the success rate of data sampling.

[0090] In some embodiments, referring to FIG. 3, the calibration module 500 can include a first calibration unit 501 and a second calibration unit 502, wherein the first calibration unit 501 can include a first calibration circuit 5011 disposed between the first node n_stg1 and the first inverting unit 201 and a second calibration circuit 5012 disposed between the third node net3 and the first decision feedback unit 302; the second calibration unit 502 can include a third calibration circuit 5021 disposed between the second node p_stg1 and the second inverting unit 201 and a fourth calibration circuit 5022 disposed between the fourth node net4 and the second decision feedback unit 304, wherein the first calibration circuit 5011 and the second calibration circuit 5012 can also be disposed between the first node n_stg1 and the first inverting unit 201 or between the third node net3 and the first decision feedback unit 302, and the third calibration circuit 5021 and the fourth calibration circuit 5022 can also be disposed between the second node p_stg1 and the second inverting unit 201 or between the fourth node net4 and the second decision feedback unit 304, which is not limited herein, and exemplarily, the first calibration unit 501 and the second calibration unit 502 can be composed of NMOS transistors and MOS capacitors.

[0091] The first calibration circuit 5011 is responsive to a first calibration signal offset[0], the second calibration circuit 5012 is responsive to a second calibration signal offset[1] and a third calibration signal offset[2], to calibrate the first voltage signal and the second voltage signal or the third voltage signal and the fourth voltage signal; the third calibration circuit 5021 is responsive to a fourth calibration signal offset[3], and the second calibration circuit 5022 is responsive to a fifth calibration signal offset[4] and a sixth calibration signal offset[5], to calibrate the first voltage signal and the second voltage signal or the third voltage signal and the fourth voltage signal.

[0092] Correspondingly, another embodiment of the present disclosure provides a data receiving system. The data receiving system provided by the embodiment of the present disclosure will be described below in combination with the accompanying drawings. FIG. 8 is a functional block diagram of the data receiving system in the embodiment of the present disclosure.

[0093] Referring to FIG. 8, the data receiving system provided by the embodiment of the present disclosure includes a plurality of cascaded data transmission circuits 20, each of which includes the data receiving circuit 10 and the latch circuit 30 according to the embodiment of the present disclosure, each of the data receiving circuits 10 is connected to a data port to receive a data signal DQ; the feedback equalization module 300 of the previous stage data transmission circuit 20 is connected to the feedback equalization module 300 of the next stage data transmission circuit 20, and the output of the previous stage data transmission circuit 20 is used as the feedback signal fdata / fdatan of the feedback equalization module 300 of the next stage data transmission circuit 20; the feedback equalization module 300 of the first stage data transmission circuit 20 is connected to the feedback equalization module 300 of the last stage data transmission circuit 20, and the output of the last stage data transmission circuit 20 is used as the feedback signal fdata / fdatan of the feedback equalization module 300 of the first stage data transmission circuit 20. The latch circuit 30 is used to latch the first output signal Vout and the second output signal VoutN, and output the first output signal Vout and the second output signal VoutN as a phase signal. The phase signals of the plurality of cascaded data transmission circuits 20 can be represented as Er, Ef, Or and Of respectively. In some embodiments, the latch circuit 30 can be a latch with a storage function, which can store the collected data signal DQ, and when the data receiving circuit 10 is reset, the latch can save the original data and is not reset.

[0094] In some embodiments, the data receiving circuit 10 receives data in response to a sampling clock signal CLK, and the data receiving system includes four cascaded data receiving circuits 10, and the phase difference of the sampling clock signals CLK of the adjacent stages of data receiving circuits 10 is 90°. In this way, the period of the sampling clock signal CLK is twice the period of the data signal DQ received by the data port, which is beneficial to clock wiring and saves power consumption.

[0095] It should be noted that the data receiving system includes four cascaded data receiving circuits 10, and the phase difference of the sampling clock signals CLK of the adjacent stages of data receiving circuits 10 is 90° in FIG. 8 as an example. In actual application, the number of cascaded data receiving circuits 10 included in the data receiving system 20 is not limited, and the phase difference of the sampling clock signals CLK of the adjacent stages of data receiving circuits 10 can be reasonably set based on the number of cascaded data receiving circuits 10.

[0096] In other embodiments, the feedback equalization module 300 of the current stage data receiving circuit 10 is connected to the output end of the previous stage data decision module 400, and the signal output by the previous stage data decision module 400 is used as the feedback signal fdata / fdatan of the next stage data receiving circuit 10.

[0097] Accordingly, the embodiment of the present disclosure also provides an offset calibration circuit to provide a calibration signal for the calibration module 500 in the data receiving circuit 10. The offset calibration circuit and the calibration method provided by the embodiment of the present disclosure will be described below in combination with the drawings. FIG. 9 is a functional schematic diagram of a circuit including the offset calibration circuit according to an embodiment of the present disclosure, and FIG. 10 is a schematic diagram of the offset calibration circuit according to an embodiment of the present disclosure.

[0098] Referring to FIG. 9, the offset calibration circuit 40 is configured to output a calibration signal offset[5:0] in response to a phase signal and an oscillation clock signal OSC, wherein the phase signal can be one of Er, Ef, Or, Of; the data receiving circuit 10 calibrates the equivalent mismatch voltage of the data receiving circuit 10 in response to the calibration signal offset[5:0] of the offset calibration circuit 40, and receives the enable signal DFE[0:2] and the first output signal Vout and the second output signal Voutn of the data receiving circuit 10 of the previous stage as the feedback signal fdata / fdatan, adjusts the third voltage signal and the fourth voltage signal, and latches the first output signal Vout and the second output signal Voutn through the latch circuit 30, and outputs the first output signal Vout and the second output signal Voutn as the phase signal.

[0099] In some embodiments, referring to FIG. 10, the offset calibration circuit 40 comprises an oscillation signal receiving unit 701, a calibration decision unit 702, and an offset calibration unit 703, wherein the oscillation signal receiving unit 701 comprises a selector 7011, a first counter 7012, and a multiplexer 7013. The selector 7011 is composed of an OR gate 7011a, a first delay circuit 7011b, and a second delay circuit 7011c, wherein the first delay circuit 7011b and the second delay circuit 7011c can be composed of a circuit comprising a capacitor and an inverter. The first counter 7012, connected between the OR gate 7011a and the first delay circuit 7011b, is configured to count the number of edges (rising edges or falling edges) of an oscillation clock signal OSC in response to a first reset signal rstn to generate a first count result cnt[5], a second count result cnt[0:2], and a third count result cnt[4:3]; the selector 7011 outputs a first oscillation clock signal OSC1 in response to the oscillation clock signal OSC and the first count result cnt[5] of the first counter 7012, and outputs a second oscillation clock signal OSC2 after the first delay circuit 7011b, and outputs a third oscillation clock signal OSC3 after the second delay circuit 7011c; the multiplexer 7013 is configured to generate a plurality of calibration enable signals Eren, Efen, Oren, Ofen in response to the third count result cnt[4:3] and a plurality of phase signals Er, Ef, Or, Of, and selectively output one of the calibration enable signals as a calibration decision signal Din.

[0100] With continued reference to FIG. 10, the calibration decision unit 702 comprises a first calibration decision unit 7021, a second inverter 7023, a second calibration decision unit 7024, and an XOR gate 7022, wherein the first calibration decision unit 7021 is configured to sample the calibration decision signal Din in response to the second oscillation clock signal OSC2 and output a first decision signal Vout1; the second calibration decision unit 7024 is configured to sample the calibration decision signal Din in response to the second oscillation clock signal OSC2 after the second inverter 7023 and output a second selection signal Vout2; and the XOR gate 7022 is used to receive the first decision signal Vout1 and the second selection signal Vout2 to output a toggle signal flag.

[0101] The offset calibration unit 703 includes a first three-input NOR gate 7031 configured to receive the second count result cnt[0:2]; a third inverter 7032 configured to receive the calibration enable signal (one of Eren, Efen, Oren, Ofen); an NOR gate 7033 connected to the output of the first three-input NOR gate 7031 and the third inverter 7032, respectively; a fourth inverter 7034 connected to the output of the NOR gate 7033 to output a lock signal lock; a fifth inverter 7035 connected to the output of the first three-input NOR gate 7031 and configured to output a second reset signal rst; a third calibration decision unit 7036 configured to output a third decision signal Vout3 in response to the jump signal flag and the second reset signal rst; a sixth inverter 7037 configured to receive the third decision signal Vout3; a second three-input NOR gate 7038 configured to receive the inverted third decision signal Vout3, the calibration enable signal (one of Eren, Efen, Oren, Ofen), and a third oscillation clock signal OSC3 to output a fourth decision signal Vout4; a third three-input NOR gate 7039 configured to receive the fourth decision signal Vout4, the lock signal lock, and a first decision signal Vout1; a second counter 7040 connected to the output of the third three-input NOR gate 7039 and configured to output a first calibration signal offset[0], a second calibration circuit 5012 configured to receive the second calibration signal offset[1] and a third calibration signal offset[2]; a seventh inverter 7041 configured to receive the first decision signal Vout1; a fourth three-input NOR gate 7042 configured to receive the fourth decision signal Vout4, the lock signal lock, and the inverted first decision signal Vout1; and a third counter 7043 connected to the output of the fourth three-input NOR gate 7042 and configured to output a fourth calibration signal offset[3], a fifth calibration signal offset[4], and a sixth calibration signal offset[5]. The first calibration decision unit 7021, the second calibration decision unit 7024, and the third calibration decision unit 7036 can be registers.

[0102] Exemplarily, when the oscillation clock signal OSC is at a rising edge, the first counter 7012 counts the number of rising edges of the oscillation clock signal OSC in response to the first reset signal rstn to generate a count result cnt[5:0], which can be all low levels, i.e., "000000", after reset; when the first count result cnt[5] is low, the oscillation signal receiving unit 701 receives the oscillation clock signal OSC and outputs the first oscillation clock signal OSC1 at a rising edge, and the second oscillation clock signal OSC2 and the third oscillation clock signal OSC3 outputted after the first delay circuit 7011b and the second delay circuit 7011b are also rising edge signals, i.e., the calibration of the data receiving circuit 10 starts; when the first count result cnt[5] is high, the oscillation signal receiving unit 701 stops receiving the oscillation clock signal, i.e., the calibration of the data receiving circuit 10 stops. When the second count result cnt[2:0] is in the state of "000", the lock signal lock is high, in the locked state, and the rising edge of the oscillation clock signal OSC is no longer received, and at the same time, the first decision Vout1 and the second decision signal Vout2 are also sampled as the same value during the "000" state of the second count result cnt[2:0].

[0103] The multiplexer 7013 generates corresponding calibration enable signals Eren, Efen, Oren, Ofen by enabling the calibration of the four phase signals in turn in response to the third count result cnt[4:3] and the plurality of phase signals Er, Ef, Or, Of, and selectively outputs one of the calibration enable signals as the calibration decision signal Din, as shown in Table 3, different cnt[4:3] corresponds to different calibration enable signals Eren, Efen, Oren, Ofen, when the cnt[4:3] combination is all low "00", the calibration enable signal Eren is generated.

[0104] Table 3

[0105] When calibrating the phase signal Er, for example, when the equivalent mismatch voltage of the data receiving circuit 10 is 25mv, when the voltage value of the data signal DQ input by the first comparison unit 1021 is slightly greater than 125mv, due to the existence of the mismatch voltage, the voltage value of the input data signal DQ is actually equivalent to slightly greater than 150mv, when the voltage value of the reference signal Vref is 150mv, the phase signal Er is fixedly output as a logic high level "1", and the multiplexer 7013 selectively outputs the calibration enable signal Eren as the calibration decision signal Din, at this time, the calibration enable signal Eren and the calibration decision signal Din are both logic high levels.

[0106] When the offset calibration circuit 40 is reset, at this time, the lock signal lock is low, that is, the lock state of the lock signal lock is released, the first count result cnt[5] is low, and the second count result cnt[2:0] after reset is “0 0 1”. At this time, the lock signal lock is low, the oscillation signal receiving unit 701 receives the oscillation clock signal OSC and outputs the first oscillation clock signal OSC1 at the rising edge, and the second oscillation clock signal OSC2 and the third oscillation clock signal OSC3 after the first delay circuit 7011b and the second delay circuit 7011b are also rising edge signals, that is, the calibration of the data receiving circuit 10 is started; the first calibration decision unit 7021 receives the second oscillation clock signal OSC2, samples the calibration decision signal Din, and outputs the first decision signal Vout1. At this time, the first decision signal Vout1 and the calibration decision signal Din have the same logic level and are high; the second oscillation clock signal OSC2 after the second inverter 7023 becomes a falling edge, and the second calibration decision unit 7024 does not sample the calibration decision signal Din; the oscillation clock signal OSC is at the rising edge, the offset calibration unit 703 receives the second count result cnt[2:0], the third inverter 7032 receives the high-level calibration enable signal Eren, and the second reset signal rst is output after the first three-input NOR gate 7031 and the fifth inverter 7035. At this time, the second reset signal rst is high, and the third decision signal Vout3 is also low; the second three-input NAND gate 7038 receives the third decision signal Vout3 after the sixth inverter 7037, the calibration enable signal Eren, and the third oscillation clock signal OSC3, outputs the fourth decision signal Vout4, and the fourth decision signal Vout4 follows the third oscillation clock signal OSC3 to jump the edge; the third three-input NOR gate 7039 receives the fourth decision signal Vout4, the lock signal lock, and the first decision signal Vout1, controls the second counter 7040 to be in an inactive state, that is, does not output the calibration signal offset[2:0]; the fourth three-input NOR gate 7042 receives the fourth decision signal Vout4, the lock signal lock, and the inverted first decision signal Vout1, controls the third counter 7043 to be in an active state, and the third counter 7043 counts the number of edge changes of the fourth decision signal Vout4, for example, the number of rising edges of the fourth decision signal Vout4, generates and outputs the fourth calibration signal offset[3], the fifth calibration signal offset[4], and the sixth calibration signal offset[5]. Exemplarily, the fourth calibration signal offset[3] can be high, and the fifth calibration signal offset[4] and the sixth calibration signal offset[5] can be low.At this time, the third calibration circuit 5021 responds to the fourth calibration signal offset[3], thereby calibrating the mismatch voltage of the data receiving circuit 10 corresponding to the phase signal Er.

[0107] The data receiving circuit 10 corresponding to the phase signal Er can be calibrated at least once at the stage when the oscillation clock signal OSC is at the rising edge, that is, the above process can be repeated multiple times, and the data receiving circuit 10 corresponding to the phase signal Er is calibrated by changing the level value of the calibration signal offset[5:3] until the phase signal Er output jumps from the logic high level "1" to the logic high level "0". For example, when the equivalent mismatch voltage of the data receiving circuit 10 is 25mv, the calibration voltage generated by the second calibration unit 502 in response to the calibration signal offset[5:3] is 27mv, the voltage of the data signal DQ input by the first comparison unit 1021 is slightly greater than 152mv, and the actual equivalent voltage value of the input data signal DQ is slightly greater than 150mv (152mv+25mv-27mv), when the voltage value of the reference signal Vref is 150mv, the output is logic high level "1". It can be seen that the mismatch voltage is reduced from 25mv to -2mv, thereby making the sampling result more accurate. The logic level value of the calibration signal offset[5:3] can also be "010", "011", etc., which is not limited here.

[0108] After the calibration of the data receiving circuit 10 corresponding to the phase signal Er is completed, the oscillation clock signal OSC is at the falling edge, the phase signal Er output jumps from the logic high level "1" to the logic high level "0", the multiplexer 7013 still responds to the third count result cnt[4:3] and the phase signals Er, Ef, Or, Of, and selectively outputs the calibration enable signal Eren as the calibration decision signal Din, and the first decision signal Vout1 output by the first calibration decision unit 7021 still remains at the high level; at this time, the second oscillation clock signal OSC2 after the second inverter 7023 turns to the rising edge, the second calibration decision unit 7024 samples the calibration decision signal Din and outputs the second decision signal Vout2, the second decision signal Vout2 is the same as the calibration decision signal Din, both are at the low level, and the exclusive-OR gate 7022 responds to the second decision signal Vout2 and the first decision signal Vout1 and outputs the jump signal flag, at this time the jump signal flag is at the high level; the third calibration decision unit 7036 responds to the jump signal flag and outputs the third decision signal Vout3 at the high level; the second three-input NAND gate 7038 receives the third decision signal Vout3 after the sixth inverter 7037, the calibration enable signal Eren and the third oscillation clock signal OSC3, and outputs the fourth decision signal Vout4, since Vout3 is at the high level, after inversion it is at the low level, input into the second three-input NAND gate 7038, so that the output Vout4 is fixed at the high level, at this time the third three-input NOR gate 7039 and the fourth three-input NOR gate 7042 output are fixed at the low level, and the subsequent edge signals of OSC3 no longer act on the second counter 7040 and the third counter 7043, thereby stopping the calibration of the data receiving circuit 10 corresponding to the phase signal Er.

[0109] When the data receiving circuit 10 corresponding to the phase signal Er completes the mismatch calibration, the multiplexer 7013 responds to the third count result cnt[4:3] and the plurality of phase signals Er, Ef, Or, Of, and sequentially selects and outputs the calibration enable signals Efen, Oren, Ofen to calibrate the corresponding data receiving circuit 10, after the calibration of the data receiving circuit 10 corresponding to the four phase signals Er, Ef, Or, Of is completed, when the first counter 7012 outputs the first count result cnt[5] at the high level, the oscillation signal receiving unit 701 stops receiving the oscillation clock signal, i.e. stops the calibration.

[0110] It should be noted that the offset calibration circuit 40 is in a non-working state (DFEOFF) when calibrating the feedback equalization module 300 in the data receiving circuit 10.

[0111] The further embodiment of the present disclosure also provides a storage device, comprising: a plurality of data ports; and a plurality of data receiving systems 20 as provided by the another embodiment of the present disclosure, each of the data receiving systems 20 corresponding to one of the data ports.

[0112] Therefore, when it is required to reduce the influence of the inter-symbol interference on the storage device, each of the data ports in the storage device can flexibly adjust the received data signal DQ through the data receiving system, and improve the adjustment capability of the first output signal Vout and the second output signal VoutN, thereby improving the receiving performance of the storage device.

[0113] In some embodiments, the storage device can be a DDR memory, such as a DDR4 memory, a DDR5 memory, a DDR6 memory, a LPDDR4 memory, a LPDDR5 memory, or a LPDDR6 memory.

[0114] Those skilled in the art can understand that the above-mentioned embodiments are specific embodiments for implementing the present disclosure, and in actual applications, various changes can be made in form and details without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make various modifications and changes without departing from the spirit and scope of the embodiments of the present disclosure, and therefore the protection scope of the embodiments of the present disclosure should be subject to the scope defined by the claims.

Claims

1. A data receiving circuit, characterized by comprising: The application relates to a data receiving device, comprising: a data receiving module (100) configured to receive a data signal (DQ) and a reference signal (Vref), and charge a first node (n_stg1) and a second node (p_stg1) in response to a sampling clock signal (CLK) to output a first voltage signal and a second voltage signal, the first voltage signal and the second voltage signal having a first time difference (Delta t1); a data inversion module (200) connected between a power supply node (Vcc) and a ground terminal, configured to receive the first voltage signal and the second voltage signal and output a third voltage signal and a fourth voltage signal; a feedback equalization module (300) connected with the data inversion module (200), configured to perform decision feedback equalization based on an enable signal (DFE[0:2]) and a feedback signal (fdata / fdatan) to adjust the third voltage signal or the fourth voltage signal, so that the third voltage signal and the fourth voltage signal have a second time difference (Delta t2), wherein the feedback signal (fdata / fdatan) is obtained based on previously received data signal (DQ); a data decision module (400) configured to receive the third voltage signal and the fourth voltage signal in turn according to the time of arrival of the third node (net3) and the fourth node (net4), and output a first output signal (Vout) and a second output signal (VoutN) through a fifth node (net5) and a sixth node (net6) respectively.

2. The data receiving circuit of claim 1, wherein, When the previously received data signal (DQ) is low and the currently received data signal (DQ) is high, the first time difference (Delta t1) is smaller than the second time difference (Delta t2).

3. The data receiving circuit of claim 1, wherein, The data receiving module (100) comprises: a first current source (101) connected between a power supply node (Vcc) and a seventh node (net7), configured to provide a current to the seventh node (net7) in response to the sampling clock signal (CLK); a charging unit (102) connected with the seventh node (net7), the first node (n_stg1) and the second node (p_stg1), configured to receive the data signal (DQ) and the reference signal (Vref) when the first current source (101) provides the current to the seventh node (net7) in response to the sampling clock signal (CLK), and output the first voltage signal through the first node (n_stg1) and the second voltage signal through the second node (p_stg1).

4. The data receiving circuit of claim 3, wherein, The first current source (101) comprises: a first transistor group (1011) connected between the power supply node (Vcc) and the seventh node (net7), the first transistor group (1011) comprising a main transistor (1011a) and a plurality of sub-transistors (1011b) connected in parallel with the main transistor (1011a) and configured to provide current to the seventh node (net7) in response to a first control signal; a first switch unit (1012) connected with the first transistor group (1011) and configured to output the first control signal in response to the sampling clock signal (CLK) and a first logic signal to control switching of the main transistor (1011a) and / or the sub-transistors (1011b) in the first transistor group (1011); a regulating unit (1013) connected with the first switch unit (1012) and configured to output the first logic signal in response to a reference signal (Vref).

5. The data receiving circuit of claim 4, wherein, The first control signal comprises a main control signal (dr0) and a plurality of sub-control signals (dr1, dr2, dr3), and the first switch unit (1012) comprises: a first inverter (1012a) connected with the gate of the main transistor (1011a) and configured to output the main control signal (dr0) in response to the sampling clock signal (CLK); and a plurality of first NAND gates (1012b) connected in parallel with the first inverter (1012a), each of the first NAND gates (1012b) having an output connected with the gate of a corresponding sub-transistor (1011b) and being configured to output a sub-control signal (dr1, dr2, dr3) in response to the sampling clock signal (CLK) and the first logic signal, the sub-transistor (1011b) being configured to provide current to the seventh node (net7) in response to the sub-control signal (dr1, dr2, dr3) and according to the sub-control signal (dr1, dr2, dr3). The data inversion module (200) comprises:

6. The data receiving circuit of claim 1, wherein, a first inversion unit (201) connected between the first node (n_stg1) and an eighth node (net8) and configured to output a third voltage signal after receiving the first voltage signal; and a second inversion unit (202) connected between the second node (p_stg1) and a ninth node (net9) and configured to output a fourth voltage signal after receiving the second voltage signal. The feedback signal (fdata / fdatan) comprises a first feedback signal (fdata) and a second feedback signal (fdatan), and the feedback equalization module (300) comprises: a second current source (301) configured to be connected between the power supply node (Vcc) and a tenth node (net10) and to provide current to the tenth node (net10) in response to a second logic signal and the first feedback signal (fdata); and a second switch unit (302) connected with the second current source (301) and configured to output the second logic signal in response to the third voltage signal and the fourth voltage signal.

7. The data receiving circuit of claim 1, wherein, ​ ​ a first decision feedback unit (302) connected between the third node (net3) and the eighth node (net8) and configured to perform decision feedback equalization on the eighth node (net8) based on the second logic signal and the first feedback signal (fdata) to adjust a time for the third voltage signal to reach the third node (net3) when the second current source (301) provides a current to the tenth node (net10) in response to the second logic signal and the first feedback signal (fdata); a third current source (303) connected between the power supply node (Vcc) and an eleventh node (net11) and configured to provide a current to the eleventh node (net11) in response to the second logic signal and a second feedback signal (fdatan); a second decision feedback unit (304) connected between the fourth node (net4) and a ninth node (net9) and configured to perform decision feedback equalization on the ninth node (net9) based on the second logic signal and the second feedback signal (fdatan) to adjust a time for the fourth voltage signal to reach the fourth node (net4) when the third current source (303) provides a current to the eleventh node (net11) in response to the second logic signal and the second feedback signal (fdatan).

8. The data receiving circuit of claim 7, wherein, The second current source (301) comprises: a second transistor group (3011) connected between the power supply node (Vcc) and the tenth node (net10), the second transistor group (3011) comprising a plurality of first transistors (3011a) connected in parallel and configured to provide a current to the tenth node (net10) in response to a second control signal and according to the second control signal; a first control unit (3012) connected to gates of the plurality of first transistors (3011a) in the second transistor group (3011) and configured to output a second control signal in response to the second logic signal and the first feedback signal (fdata) to control switching of the plurality of first transistors (3011a) in the second transistor group (3011); The third current source (303) comprises: a third transistor group (3031) connected between the power supply node (Vcc) and the eleventh node (net11), the third transistor group (3031) comprising a plurality of second transistors (3031a) connected in parallel and configured to provide a current to the eleventh node (net11) in response to a third control signal and according to the third control signal; a second control unit (3032) connected to the gate of each of the plurality of the second transistors (3031a) in the third transistor group (3031) and configured to output a third control signal to control the switching of each of the plurality of the second transistors (3031a) in the third transistor group (3031) in response to the second feedback signal (fdatan) and the second logic signal.

9. The data receiving circuit of claim 7, wherein, The first control unit (3012) comprises: a plurality of second NAND gates (3012b) connected to the gate of each of the plurality of the first transistors (3011a) and configured to output the second control signal to control the switching of each of the plurality of the first transistors (3011a) in response to the first feedback signal (fdata) and the second logic signal. The second control unit (3032) comprises: a plurality of third NAND gates (3032b) connected to the gate of each of the plurality of the second transistors (3031a) and configured to output the third control signal to control the switching of each of the plurality of the second transistors (3031a) in response to the second feedback signal (fdatan) and the second logic signal.

10. The data receiving circuit of claim 7, wherein, The feedback equalization module (300) further comprises: an enabling unit (305) configured to receive the enabling signal (DFE[0:2]) and output the second logic signal, and connected to the first control unit (3012) and the second control unit (3032) respectively.

11. The data receiving circuit of claim 6, wherein, The first decision feedback unit (302) comprises: a first PMOS transistor (MP1) connected between the power supply node (Vcc) and the third node (net3); a first NMOS transistor (MN1) connected between the third node (net3) and the ground terminal; a second PMOS transistor (MP2) connected between the third node (net3) and the tenth node (net10), the gate of the first PMOS transistor (MP1), the first NMOS transistor (MN1) and the second PMOS transistor (MP2) receiving the third voltage signal simultaneously. The second decision feedback unit (304) comprises: a third PMOS transistor (MP3) connected between the power supply node (Vcc) and the fourth node (net4); a second NMOS transistor (MN2) connected between the fourth node (net4) and the ground terminal; 12. The data receiving circuit of claim 3, wherein, a fourth PMOS transistor (MP4) connected between the fourth node (net4) and the eleventh node (net11), the gate of the third PMOS transistor (MP3), the second NMOS transistor (MN2) and the fourth PMOS transistor (MP4) receiving the fourth voltage signal simultaneously. The charging unit (102) comprises: a first comparison unit (1021) connected between the seventh node (net7) and the first node (n_stg1), a gate of the first comparison unit (1021) configured to receive the data signal (DQ); a second comparison unit (1022) connected between the seventh node (net7) and the second node (p_stg1), a gate of the second comparison unit (1022) configured to receive the reference signal (Vref); a first reset unit (1023) connected between the first node (n_stg1) and the ground terminal, configured to reset the first node (n_stg1) in response to the sampling clock signal (CLK); a second reset unit (1024) connected between the second node (p_stg1) and the ground terminal, configured to reset the second node (p_stg1) in response to the sampling clock signal (CLK).

13. The data receiving circuit of claim 1, wherein, The data decision module (400) comprises: a decision unit (401) connected between the third node (net3) and the fourth node (net4), the decision unit (401) comprising: a third reset unit (4011) connected between a power supply node (Vcc) and a fifth node (net5), configured to reset the fifth node (net5) in response to the sampling clock signal (CLK); a fourth reset unit (4012) connected between the power supply node (Vcc) and a sixth node (net6), configured to reset the sixth node (net6) in response to the sampling clock signal (CLK); a first input unit (4013) connected between a twelfth node (net12) and the ground terminal, a gate of the first input unit (4013) configured to receive the third voltage signal adjusted by the feedback equalization module (300); a second input unit (4014) connected between a thirteenth node (net13) and the ground terminal, a gate of the second input unit (4014) configured to receive the fourth voltage signal adjusted by the feedback equalization module (300); a fifth PMOS tube (MP5) connected between the power supply node (Vcc) and the fifth node (net5), a gate of the fifth PMOS tube (MP5) configured to receive the second output signal (VoutN); a sixth PMOS tube (MP6) connected between the power supply node (Vcc) and the sixth node (net6), a gate of the sixth PMOS tube (MP6) configured to receive the first output signal (Vout); a third NMOS tube (MN3) connected between the fifth node (net5) and the twelfth node (net12), a gate of the third NMOS tube (MN3) configured to receive the second output signal (VoutN); a fourth NMOS transistor (MN4) connected between the sixth node (net6) and a thirteenth node (net13), a gate of the fourth NMOS transistor (MN4) configured to receive the first output signal (Vout).

14. The data receiving circuit of claim 1, wherein, The data receiving circuit further comprises: a calibration module (500) configured to calibrate the data receiving circuit in response to a calibration signal (offset[5:0]).

15. An offset calibration circuit, characterized by The offset calibration circuit is configured to output a calibration signal (offset[5:0]) in response to a phase signal and an oscillation clock signal (OSC), and the data receiving circuit as claimed in any one of claims 1-14 calibrates the data receiving circuit in response to the calibration signal (offset[5:0]).

16. A data receiving system, characterized by comprising: a plurality of cascaded data transmitting circuits, each of the data transmitting circuits comprising the data receiving circuit as claimed in any one of claims 1-14, each of the data receiving circuits connected to a data port to receive the data signal (DQ); a decision feedback equalization module (300) of a previous stage data transmitting circuit connected to a decision feedback equalization module (300) of a next stage data transmitting circuit, an output of the previous stage data transmitting circuit as the feedback signal (fdata / fdatan) of the decision feedback equalization module (300) of the next stage data transmitting circuit; a decision feedback equalization module (300) of a last stage data transmitting circuit connected to a decision feedback equalization module (300) of a first stage data transmitting circuit, an output of the last stage data transmitting circuit as the feedback signal (fdata / fdatan) of the decision feedback equalization module (300) of the first stage data transmitting circuit; the data receiving circuit receiving data in response to the sampling clock signal (CLK); and the data receiving system comprising four cascaded data transmitting circuits, a phase difference of the sampling clock signal (CLK) of adjacent stages of the data receiving circuits being 90°.

17. A memory device, comprising: comprising: a plurality of data ports; a plurality of data receiving systems as claimed in claim 16, each of the data receiving systems corresponding to one of the data ports.

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