Integrated circuit configuration selection device and integrated circuit configuration selection method

Abstract

An integrated circuit configuration selection device (300) selects circuit configurations for realizing a plurality of predefined interconnected functions by using an interconnected integrated circuit (200) obtained by interconnecting a plurality of juxtaposed integrated circuits (20, 30, 40) in which a plurality of FPGAs (10a-10i) for realizing functions are juxtaposed. Said configuration is either one or both of a plurality of interconnected paths and a plurality of function arrangements of the FPGAs (10a-10i). A configuration selection unit (52a) for selecting a circuit configuration in which the number of juxtaposed integrated circuits (20, 30, 40) is minimized from among the plurality of circuit configurations for realizing the plurality of interconnected functions is provided.

Description

Integrated circuit configuration selection device and integrated circuit configuration selection method

[0001] The present invention relates to an integrated circuit configuration selection device and an integrated circuit configuration selection method, and relates to, for example, a device for selecting the circuit configuration of a linked integrated circuit that links parallel integrated circuits (accelerators, servers) that each include a plurality of integrated circuits (e.g., FPGAs) whose functions can be changed.

[0002] A processing unit may be equipped with accelerators that realize a wide variety of functions to increase processing speed. Power efficiency can be improved by appropriately allocating functions to each accelerator. For example, Non-Patent Document 1 discloses a technology for allocating functions to maximize the operating time of service function chains operating within a system.

[0003] R. Kang, F. He, T. Sato and E. Oki, "Virtual Network Function Allocation to Maximize Continuous Available Time of Service Function Chains With Availability Schedule," in IEEE Transactions on Network and Service Management, vol. 18, no. 2, pp. 1556-1570, June 2021

[0004] The accelerator required varies from user to user. An accelerator may require a function chain with multiple functions. Multiple accelerators may also be connected. In these cases, accelerators or integrated circuits may be chained together so that only the required function chains are available. This eliminates the need for development for each chain, thereby reducing development costs. Furthermore, equipment costs can be reduced by sharing the integrated circuits (FPGAs or ASICs) that make up the accelerators across the chain. However, if a path (connection path) that chains multiple integrated circuits spans nodes connecting multiple accelerators, a node failure at any one of the nodes along the path will cause service to stop, reducing the fault tolerance of the connected integrated circuits.

[0005] The present invention has been made in consideration of the above background, and its objective is to provide an integrated circuit configuration selection device and an integrated circuit configuration selection method that can improve the fault tolerance of a linked integrated circuit in which multiple integrated circuits are linked.

[0006] In order to solve the above-mentioned problems, the present invention provides an integrated circuit configuration selection device that selects a circuit configuration that realizes a plurality of predefined connected functions using a connected integrated circuit in which a plurality of parallel integrated circuits that realize a plurality of integrated circuits that realize a function are connected, wherein the circuit configuration is either one or both of a plurality of functional arrangements and a plurality of connection paths of the integrated circuits, each of the integrated circuits has a functional unit that realizes the function and a first transfer unit that transfers output data of the functional unit to an input unit of another integrated circuit, each of the parallel integrated circuits has a second transfer unit that transfers data to another parallel integrated circuit when the destination of the transfer made by the first transfer unit is another parallel integrated circuit, and is characterized by comprising: a configuration selection unit that selects a circuit configuration that minimizes the number of parallel integrated circuits from among the plurality of circuit configurations that realize the plurality of connected functions.

[0007] According to the present invention, it is possible to improve the fault tolerance of a linked integrated circuit in which a plurality of integrated circuits are linked together.

[0008] FIG. 1 is a conceptual diagram showing the prerequisite operation of a linked integrated circuit according to an embodiment of the present invention. FIG. 2 is a configuration diagram of an integrated circuit configuration selection system according to a first embodiment of the present invention. FIG. 3 is a configuration diagram showing an example of an integrated circuit according to the first embodiment of the present invention. FIG. 4 is a configuration diagram of an integrated circuit configuration selection device according to the first embodiment of the present invention. FIG. 5 is a flowchart explaining the operation of the integrated circuit configuration selection device according to the first embodiment of the present invention. FIG. 6 is an explanatory diagram explaining a method for selecting a functional layout of a plurality of integrated circuits according to the first embodiment of the present invention. FIG. 7 is an explanatory diagram explaining a connection method for connecting a plurality of integrated circuits according to the first embodiment of the present invention. FIG. 8 is an explanatory diagram explaining a method for selecting connection paths for connecting a plurality of integrated circuits according to a second embodiment of the present invention. FIG. 9 is an explanatory diagram explaining a connection method for connecting a plurality of integrated circuits according to the second embodiment of the present invention. FIG. 10 is an explanatory diagram explaining a connection method for connecting a plurality of integrated circuits according to a third embodiment of the present invention. FIG. 11 is an explanatory diagram explaining a connection method for connecting a plurality of integrated circuits according to a fourth embodiment of the present invention. FIG. 12 is a configuration diagram of a linked integrated circuit according to a modified example of the present invention.

[0009] (Prerequisite Operation of the Integrated Circuit Configuration Selection Device) FIG. 1 is a conceptual diagram illustrating the prerequisite operation of a linked integrated circuit according to a first embodiment of the present invention. The linked integrated circuit 200 is formed by connecting parallel integrated circuits 20, 30, and 40, each of which includes a plurality of field programmable gate arrays (FPGAs) that are integrated circuits. The parallel integrated circuits 20, 30, and 40 are disposed, for example, inside a server and are connected to each other so that they can communicate with each other. The parallel integrated circuits 20, 30, and 40 are referred to as nodes. The parallel integrated circuit 20, which serves as a server, has multiple FPGAs 10a, 10b, and 10c arranged in parallel. Similarly, the parallel integrated circuit 30, which serves as a server, has multiple FPGAs 10d, 10e, and 10f arranged in parallel. The parallel integrated circuit 40, which serves as a server, has multiple FPGAs 10g, 10h, and 10i arranged in parallel.

[0010] Each of these FPGAs 10 (10a to 10i) has a function unit 1 (FIG. 3) whose functions can be set externally. For example, FPGA 10a is configured to implement a VPN (Virtual Private Network) function. FPGA 10b implements an encryption function, FPGA 10d implements data processing, FPGA 10g includes a GPU (Graphics Processing Unit) that performs AI inference, FPGA 10h includes a GPU that performs machine learning, and FPGA 10i includes a CPU (Central Processing Unit).

[0011] Meanwhile, a user may use the linked integrated circuit 200 to execute a plurality of different functions (connected functions obtained by connecting FPGAs 10). For example, in chain a, the VPN function realized by FPGA 10a, the data processing function realized by FPGA 10d, and the AI ​​inference function realized by FPGA 10g are executed consecutively. In chain b, the encryption function realized by FPGA 10b, the data processing function realized by FPGA 10d, and the AI ​​inference function realized by FPGA 10g are executed consecutively. In chain c, the data processing function realized by FPGA 10d and the machine learning function realized by FPGA 10h are executed consecutively without going through FPGAs 10a, 10b, and 10c.

[0012] In this case, in chains a and b, data passes through three servers, the parallel integrated circuits 20, 30, and 40, whereas in chain c, data passes through two servers, the parallel integrated circuits 30 and 40. In other words, chain c is less susceptible to failures than chains a and b.

[0013] In addition, when the CPU of FPGA 10i displays the AI ​​inference results or machine learning results on a display unit not shown, FPGAs 10a to 10h and parallel integrated circuits 20 and 30 function as accelerators that expand and speed up the functions of the CPU.

[0014] In the embodiments described below, it is assumed that the linked integrated circuit 200 executes each function (linking function) of multiple chains a, b, and c. In the first and second embodiments, the integrated circuit configuration selection devices 100 (FIGS. 2 and 5) and 101 (FIG. 8) select one or more functions (functions to be provided in the FPGAs 10a to 10i) and linking paths (chains) to be implemented by each of the FPGAs 10a to 10i, so as to reduce the occurrence of faults. In the third and fourth embodiments, an integrated circuit with fixed functions (an FPGA or an ASIC (Application Specific Integrated Circuit) with preset functions) is used. In the third and fourth embodiments, the integrated circuit configuration selection devices 102 (FIG. 10) and 103 (FIG. 11) select one or more function locations and linking paths for the integrated circuit, so as to reduce the occurrence of faults.

[0015] First Embodiment FIG. 2 is a configuration diagram of an integrated circuit configuration selection system according to a first embodiment of the present invention. The integrated circuit configuration selection system 300 includes a linked integrated circuit 200 and an integrated circuit configuration selection device 100. The linked integrated circuit 200 includes parallel integrated circuits 20, 30, and 40, which are servers. Each of the parallel integrated circuits 20, 30, and 40 includes multiple FPGAs, although the number is limited to three for example. Specifically, the parallel integrated circuit 20 includes multiple parallel-connected FPGAs 10a, 10b, and 10c and a communication unit 15 serving as a second transfer unit. Similarly, the parallel integrated circuit 30 includes multiple FPGAs 10d, 10e, and 10f and the communication unit 15. The parallel integrated circuit 40 includes multiple FPGAs 10g, 10h, and 10i and the communication unit 15. The integrated circuit configuration selection device 100 can communicate with each of the communication units 15 via a communication unit 60. The parallel integrated circuits 20, 30, and 40, which are the servers, are called nodes.

[0016] FIG. 3 is a block diagram showing an example of an integrated circuit according to the first embodiment of the present invention. Each FPGA 10 (10a to 10i) is an integrated circuit including a functional unit 1, a first transfer unit 2, an input unit 3, and a transfer setting unit 4. The functional unit 1 realizes its function based on external settings. The first transfer unit 2 transfers output data from the functional unit 1 to the input unit 3 of another FPGA 10. Based on data stored in the transfer setting unit 4, the first transfer unit 2 can transfer data not only to the FPGA 10 in its own parallel integrated circuit 20 but also to FPGAs 10 in other parallel integrated circuits 30 and 40 via communication units 15. The input unit 3 receives data from other FPGAs 10 and receives data via the communication unit 15. The transfer setting unit 4 is a storage unit (volatile or nonvolatile storage unit) that stores the destination of the other FPGA 10 to which the first transfer unit 2 transfers output data.

[0017] 4 is a configuration diagram of an integrated circuit configuration selection device according to a first embodiment of the present invention. The integrated circuit configuration selection device 100 is a PC (Personal Computer) equipped with a control unit 50, a communication unit 60, and a display / operation unit 70. The illustrated integrated circuit configuration selection device 101 will be described later in a second embodiment. The control unit 50 (50a, 50b) is a CPU that executes an integrated circuit configuration selection program to realize the functions of a priority determination unit 51, a configuration selection unit 52, and a display / operation control unit 55. The configuration narrowing-down unit 53, indicated by a dashed line, will be described in a fourth embodiment (FIG. 11).

[0018] The priority determination unit 51 is a functional unit that prioritizes a plurality of link functions (chain information) that a user intends to realize in the link integrated circuit 200. In this embodiment, the priority determination unit 51 prioritizes the plurality of link functions based on a service level agreement (SLA). For example, the priority determination unit 51 prioritizes configurations (particularly, link paths) that have a short recovery time without refund.

[0019] The configuration selection unit 52 selects one or more circuit configurations (either or both of the arrangement of functions (functional arrangement) that can be set in each of the FPGAs 10a to 10i and the connection path) from the multiple connection functions (chains) ranked by the priority determination unit 51, in descending order of priority, so as to minimize the number of parallel integrated circuits 20, 30, 40 to be passed through (the number of nodes to be passed through). Here, in the first and third embodiments, the configuration selection unit 52 selects the function arrangement, and in the second and fourth embodiments, the configuration selection unit 52 selects the connection path (chain).

[0020] The display operation control unit 55 controls the display operation unit 70. For example, if there are multiple configurations (functional layouts or connection paths) selected by the configuration selection unit 52, the display operation control unit 55 displays the multiple functional layouts and connection paths on the display operation unit 70 and allows the operator to select one of them. The display operation control unit 55 may also display input data and output data of the linked integrated circuit 200 on the display operation unit 70. In this case, the integrated circuit configuration selection device 100 also functions as an arithmetic processing unit, and each of the parallel integrated circuits 20, 30, and 40 functions as an accelerator for that arithmetic processing unit.

[0021] The communication unit 60 communicates with the parallel integrated circuits 20, 30, and 40 as servers via a network NW (FIG. 5). The network NW is a local area network (LAN) or may be a wide area network (WAN). The display operation unit 70 is a liquid crystal display (LCD) panel with a touch function.

[0022] 5 is a flowchart illustrating the operation of the integrated circuit configuration selection device according to the first embodiment of the present invention. This flow is initiated by updating chain information. Here, chain information is information about link functions that the user causes the linked integrated circuit 200 to execute. There are multiple link functions, and they are executed at different times. First, the control unit 50 (FIG. 4) determines priorities for the multiple link functions using the priority determination unit 51 (S1).

[0023] 6 is an explanatory diagram illustrating a method for allocating functions to a plurality of integrated circuits according to the first embodiment of the present invention. For example, the chain information that the user causes the linked integrated circuit 200 to execute is a plurality of linked functions, namely, Chain 1 = (Function 1 + Function 2 + Function 3), Chain 2 = (Function 4 + Function 5 + Function 3), and Chain 3 = (Function 4 + Function 6 + Function 7).

[0024] Furthermore, the SLA limits the non-refundable fault recovery time for Chain 1 = (Function 1 + Function 2 + Function 3) to "within one hour," the non-refundable fault recovery time for Chain 2 = (Function 4 + Function 5 + Function 3) to "within one day," and the non-refundable fault recovery time for Chain 3 = (Function 4 + Function 6 + Function 7) to "within seven days."

[0025] In such a case, the priority determination unit 51 (FIG. 4) prioritizes the connection path (chain) with the shortest recovery time without refund, by assigning the priority of "1st" to chain 1, "2nd" to chain 2, and "3rd" to chain 3. In this way, the priorities are determined (S1 (FIG. 5)).

[0026] Returning to the explanation of FIG. 5, the control unit 50 (FIG. 4) determines the location of the function from the chain with the highest priority by the configuration selection unit 52 (S2).

[0027] 7 is an explanatory diagram for explaining a method for connecting a plurality of integrated circuits according to the first embodiment of the present invention. The location of functions will be explained below with reference to FIGS.

[0028] The configuration selection unit 52 ( FIG. 4 ) first selects one or more function arrangements (function arrangements) that can be set in the FPGAs 10 a to 10 i so as to minimize the number of parallel integrated circuits 20, 30, and 40 ( FIG. 7 ) to be passed through (the number of nodes to be passed through) for the highest-priority chain 1 = (function 1 + function 2 + function 3). For example, if the configuration selection unit 52 accommodates (function 1 + function 2 + function 3) in one of the parallel integrated circuits 20, 30, and 40, the number of nodes to be passed through becomes the minimum, "1." For example, if (function 1 + function 2 + function 3) is accommodated in the parallel integrated circuit 20, the configuration selection unit 52 can allocate function 1 to any of the FPGAs 10 a, 10 b, and 10 c. Here, when function 1 is allocated to FPGA 10 a, the configuration selection unit 52 can allocate function 2 to any of FPGAs 10 b and 10 c. When function 2 is placed in FPGA 10b, the configuration selection unit 52 places function 3 in FPGA 10c. This causes the parallel integrated circuit 20 to become full. The same applies when (function 1 + function 2 + function 3) is accommodated in parallel integrated circuits 30 and 40. As a result, the configuration selection unit 52 selects multiple functional arrangements of FPGAs 10a to 10i for chain 1, which has one node to pass through.

[0029] Next, the configuration selection unit 52 selects one or more functional arrangements of FPGAs 10a to 10i for chain 2, which has the second highest priority, (function 4 + function 5 + function 3). Since the parallel integrated circuit 20 is full, the configuration selection unit 52 can set functions 4 and 5 to either of the parallel integrated circuits 30 and 40. For example, when functions 4 and 5 are to be arranged in the parallel integrated circuit 30, the configuration selection unit 52 can set function 4 to either of FPGAs 10d, 10e, and 10f. When the configuration selection unit 52 sets function 4 to FPGA 10d, it can set function 5 to either of FPGAs 10e and 10f. In the figure, function 5 is set to FPGA 10e. The configuration selection unit 52 may reuse function 3 set in FPGA 10c, or may set function 3 in either FPGA 10e or 10f. It is preferable to avoid arranging multiple FPGAs 10 that achieve the same function in the linked integrated circuit 200. For this reason, in the figure, function 3 set in FPGA 10c is reused.

[0030] Next, the configuration selection unit 52 selects one or more functional arrangements of the FPGAs 10a to 10i for the third highest priority chain 3 = (function 4 + function 6 + function 7). Since function 4 is set in the FPGA 10d, it is acceptable to use FPGA 10d, or to set it in either FPGA 10e or 10f, which does not have function 5 set therein.

[0031] Assuming that function 4 uses FPGA d set in chain 2, the configuration selection unit 52 can set function 6 to either FPGA 10 f or FPGA 10 g, 10 h, or 10 i of the parallel integrated circuit 40. If function 6 is set to FPGA 10 g, the configuration selection unit 52 can set function 7 to FPGA 10 h or FPGA 10 i.

[0032] 7, it is assumed that the configuration selection unit 52 has set function 1 to FPGA 10a, function 2 to FPGA 10b, and function 3 to FPGA 10c. It is also assumed that the configuration selection unit 52 has set function 4 to FPGA 10d and function 5 to FPGA 10e. It is also assumed that the configuration selection unit 52 has set function 6 to FPGA 10g and function 7 to FPGA 10i.

[0033] In chain 1 (function 1 → function 2 → function 3), the processing of the functions is completed only in the parallel integrated circuit 20. In chain 2 (function 4 → function 5 → function 3), the processing of functions 4 and 5 is performed in the parallel integrated circuit 30, and the processing of function 3 is performed in the parallel integrated circuit 20. In chain 3 (function 4 → function 6 → function 7), the processing of function 4 is performed in the parallel integrated circuit 30, and the processing of functions 6 and 7 is performed in the parallel integrated circuit 40. In chain 2, processing is performed in two different parallel integrated circuits 20 and 30, and in chain 3, processing is performed in two different parallel integrated circuits 30 and 40. In other words, chains 2 and 3 have lower fault tolerance than chain 1.

[0034] In this way, the placement destination is determined starting from the chain with the highest priority (S2 (FIG. 5)). After the placement destination is determined, the control unit 50 executes deployment (S3). Specifically, the control unit 50 instructs the placement of functions in the FPGAs 10a to 10i (FIG. 7) and sets the transfer setting unit 4 (FIG. 3) so that the connection paths (see FIG. 7) are Chain 1 = (Function 1 → Function 2 → Function 3), Chain 2 = (Function 4 → Function 5 → Function 3), and Chain 3 = (Function 4 → Function 6 → Function 7).

[0035] As described above, according to the integrated circuit configuration selection device 100 of this embodiment, the configuration selection unit 52a selects, from among multiple circuit configurations that realize multiple linking functions (chain information), a circuit layout that minimizes the number of parallel integrated circuits 20, 30, and 40 (number of nodes passed through). This minimizes the use of the second transfer unit (communication unit 15), which transfers output data from the integrated circuits 10a to 10i to other parallel integrated circuits (other servers). As a result, the number of failures occurring in the linked integrated circuit 200 is reduced.

[0036] In the first embodiment, one or more functional arrangements of the FPGAs 10a to 10i were selected so as to minimize the number of parallel integrated circuits 20, 30, and 40 (number of nodes passed through) for the chain with the highest priority. In this embodiment, the priority is selected so as to maximize the number of chains with a number of nodes passed through of "1."

[0037] Like the integrated circuit configuration selection system 300 of the first embodiment, the integrated circuit configuration selection system 301 (FIG. 9) of this embodiment includes a linked integrated circuit 200 and an integrated circuit configuration selection device 101. However, the integrated circuit configuration selection device 101 includes a control unit 50b (FIG. 4), which realizes the functions of the priority determination unit 51, the configuration selection unit 52b, and the display operation control unit 55.

[0038] 8 is an explanatory diagram illustrating a method for selecting a connection path for connecting a plurality of integrated circuits according to a second embodiment of the present invention. In this embodiment, Chain 1 = (Function 1 + Function 2 + Function 3), Chain 2 = (Function 4 + Function 5 + Function 3), and Chain 3 = (Function 4 + Function 6 + Function 7).

[0039] The priority determination unit 51 ( FIG. 4 ) determines the priority so that the number of paths (number of chains) with a passed node count of "1" is maximized. For example, the priority determination unit 51 accommodates Chain 1 = (Function 1 + Function 2 + Function 3) in the parallel integrated circuit 20, as in the above embodiment. In this case, Chain 2 = (Function 4 + Function 5 + Function 3) can be accommodated in the parallel integrated circuit 30, and Chain 3 = (Function 4 + Function 6 + Function 7) can be accommodated in the parallel integrated circuit 40 (not shown). In this case, the number of paths (number of chains) with a passed node count of "1" is the maximum value of "3," and this arrangement is prioritized. In this case, the number of functions used in multiple chains is zero.

[0040] However, in this embodiment, functions 4, 5, and 3 of chain 2 require large processing capabilities and should be placed in different parallel integrated circuits 20, 30, and 40. In other words, function 3 uses function 3 of chain 1. In this case, the number of nodes passed through in chain 2 is "3."

[0041] Chain 3 = (function 4 + function 6 + function 7) can be accommodated in either of the same parallel integrated circuits 30, 40 by using function 4 set in chain 2. In other words, the number of nodes passed through in chain 3 is "1". As a result, chains 1 and 3, which have the maximum number of paths (number of chains) of "2" with a passed node number of "1", are given priority. In other words, chains 1 and 3 are determined to have the "first" priority, and chain 2 is determined to have the "third" priority.

[0042] 9 is an explanatory diagram illustrating a connection method for connecting multiple integrated circuits according to the second embodiment of the present invention. For example, the configuration selection unit 52b (FIG. 9) assigns function 1 of chain 1, which has the "first" priority, to FPGA 10a, function 2 to FPGA 10b, and function 3 to FPGA 10c. The configuration selection unit 52b (FIG. 9) assigns function 4 of chain 3, which has the "first" priority, to FPGA 10g, function 6 to FPGA 10h, and function 7 to FPGA 10i. Next, the configuration selection unit 52b (FIG. 9) assigns function 4 of chain 2, which has the "third" priority, to FPGA 10g, function 5 to FPGA 10d, and uses function 3 assigned to FPGA 10c.

[0043] As described above, according to the integrated circuit configuration selection device 101 of this embodiment, the configuration selection unit 52b selects, from among multiple circuit configurations that realize multiple linking functions (chain information), a circuit configuration that maximizes the number of paths (number of chains) in which the number of parallel integrated circuits 20, 30, and 40 (number of nodes passed through) is 1. Accordingly, the configuration selection unit 52b selects, from among multiple circuit configurations that realize multiple linking functions, a circuit configuration that minimizes the use of the second transfer unit (e.g., communication unit 15). As a result, the occurrence of failures in the linked integrated circuit 200 is reduced.

[0044] In the first embodiment, a method for allocating functions to FPGAs 10a to 10i that do not have pre-defined functions so as to satisfy the connection function has been described. In this embodiment, a connection path is set for an integrated circuit such as an FPGA or an ASIC (Application Specific Integrated Circuit) that has pre-defined functions.

[0045] FIG. 10 is an explanatory diagram illustrating a connection method for connecting multiple integrated circuits according to a third embodiment of the present invention. The integrated circuit configuration selection system 302 includes a linked integrated circuit 201 and an integrated circuit configuration selection device 102. The linked integrated circuit 202 is composed of multiple parallel integrated circuits 21, 31, and 41, which are servers. Each of the parallel integrated circuits 21, 31, and 41 includes multiple integrated circuits. The integrated circuits are FPGAs with pre-configured functions, and differ from the previous embodiments in that they include an ASIC. The parallel integrated circuit 21 includes multiple parallel integrated circuits 11a, 11b, and 11c and a communication unit 15 (not shown) serving as a second transfer unit. Similarly, the parallel integrated circuit 31 includes multiple integrated circuits 11d, 11e, and 11f and a communication unit 15 (not shown). The parallel integrated circuit 41 includes multiple integrated circuits 11g, 11h, and 11i and a communication unit 15 (not shown).

[0046] Function 1 is set in advance in integrated circuit 11a, function 2 in integrated circuit 11b, and function 3 in integrated circuit 11c. Function 4 is set in integrated circuit 11d. Function 6 is set in integrated circuit 11g, and function 7 is set in integrated circuit 11h. Note that, although the description will be given assuming that no functions are set in integrated circuits 11i and 11f, functions may be set therein.

[0047] Next, referring to Figure 6, a method for selecting a connection path for an integrated circuit in this embodiment will be explained. As in the first embodiment, the SLA limits the non-refundable failure recovery time for Chain 1 = (Function 1 + Function 2 + Function 3) to within one hour, the non-refundable failure recovery time for Chain 2 = (Function 4 + Function 5 + Function 3) to within one day, and the non-refundable failure recovery time for Chain 3 = (Function 4 + Function 6 + Function 7) to within "7 days".

[0048] As in the first embodiment, the priority determination unit 51 prioritizes chain 1 as the first priority, chain 2 as the second priority, and chain 3 as the third priority, so as to prioritize the connection path (chain) with the shortest failure recovery time without refund.

[0049] The configuration selection unit 52a selects a connection path from the chain with the highest priority so that the number of nodes passed through is the smallest. The chain with the "first" priority is Chain 1 = (Function 1 + Function 2 + Function 3), and Chain 1 has the smallest number of nodes passed through, "1." Therefore, only the connection path (integrated circuit 11a → integrated circuit 11b → integrated circuit 11c) is selected for Chain 1. Since only one connection path is selected, the configuration selection unit 52a determines that it is (integrated circuit 11a → integrated circuit 11b → integrated circuit 11c).

[0050] The chain with the second highest priority is Chain 2 = (Function 4 + Function 5 + Function 3), and the number of nodes passed through in Chain 1 is "2." Since there are no other chains with the second highest priority, the number of nodes passed through in Chain 2 is the smallest. Therefore, the connection path for Chain 2 is selected and determined to be (integrated circuit 11d → integrated circuit 11e → integrated circuit 11c).

[0051] The chain with the "third" priority is Chain 3 = (Function 4 + Function 6 + Function 7), and the number of nodes passed through Chain 3 is "2." Since there are no other chains with the "third" priority, the number of nodes passed through Chain 3 is the smallest. Therefore, the connection path of Chain 3 is selected and determined to be (integrated circuit 11d → integrated circuit 11g → integrated circuit 11h).

[0052] Now, consider a case where the integrated circuit 11f has been set to function 3 in advance. In this case, a connection path with one passed node (integrated circuit 11d → integrated circuit 11e → integrated circuit 11f) is added to the chain with the second highest priority. The configuration selection unit 52a selects the connection path with the minimum number of passed nodes, one (integrated circuit 11d → integrated circuit 11e → integrated circuit 11f).

[0053] As described above, according to the integrated circuit configuration selection device 102 of this embodiment, the configuration selection unit 52a selects, from among multiple connection paths (chains) that realize multiple connection functions, a connection path that minimizes the number of parallel integrated circuits 20, 30, and 40 (number of nodes passed through). This minimizes the use of the second transfer unit (communication unit 15), which transfers output data from the integrated circuits 11a to 11i to other parallel integrated circuits (other servers). As a result, failures occurring in the linked integrated circuit 201 are reduced.

[0054] (Fourth embodiment) In the second embodiment, a method for setting functions for FPGAs 10a to 10i in which no functions have been set so as to satisfy the connection function has been described, but a connection path is set for an integrated circuit such as an FPGA or ASIC in which functions have been set.

[0055] 11 is an explanatory diagram illustrating a linking method for linking a plurality of integrated circuits according to a fourth embodiment of the present invention. The configuration of this embodiment is similar to that of the third embodiment. The integrated circuit configuration selection system 303 includes a linked integrated circuit 201 and an integrated circuit configuration selection device 103. As in the second embodiment, the integrated circuit configuration selection device 103 includes a control unit 50b, which not only realizes the functions of the priority determination unit 51, the configuration selection unit 52b, and the display operation control unit 55, but also realizes the function of the configuration narrowing down unit 53.

[0056] These functions 1 to 7 are different functions, but may include the same function.

[0057] The configuration selection unit 52b determines the priority order so that the number of chains with a passed node count of "1" is maximized. The number of passed nodes in chain 1 = (function 1 + function 2 + function 3) is "1", the number of passed nodes in chain 2 = (function 4 + function 5 + function 3) is "3", and the number of passed nodes in chain 3 = (function 4 + function 6 + function 7) is "1". The number of chains with a passed node count of "1" is "2", and the number of chains with a passed node count of "3" is "1". Chains 1 and 3, which have the largest number of chains of "2", are given priority. In other words, chains 1 and 3 have the "first" priority, and chain 2 has the "third" priority.

[0058] Next, the configuration narrowing unit 53 prioritizes the chains that use the fewest number of functions. The number of functions used in the multiple chains is "one" for chain 1, only function 3, "two" for chain 2, functions 3 and 4, and "one" for chain 3, only function 4. Chains 1 and 3, which use the fewest number of functions in the multiple chains, are prioritized.

[0059] Now, consider the case where function 2 = function 5. In this case, chain 1 can also be chain 1a = (function 1 + function 5 + function 3). In this case, the number of functions used in multiple chains is "2" for chain 1 and "3" for chain 1a. Chain 1, which has the fewest number of functions used in multiple chains, is given priority.

[0060] As described above, according to the integrated circuit configuration selection device 103 of this embodiment, the configuration selection unit 52b selects, from among multiple circuit configurations that realize multiple connection functions (chain information), a connection path that maximizes the number of paths (number of chains) in which the number of parallel integrated circuits 20, 30, and 40 (number of nodes passed through) is 1. Accordingly, the configuration selection unit 52b selects, from among multiple connection paths that realize multiple connection functions, a connection path that minimizes the use of the second transfer unit (e.g., the communication unit 15). Furthermore, the configuration narrowing-down unit 53 prioritizes a configuration that uses fewer functions in multiple chains. As a result, fewer failures occur in the linked integrated circuit 201.

[0061] (Modification) In each of the above-described embodiments, the parallel integrated circuits 20, 30, and 40 are arranged in different servers and are connected to each other so as to be able to communicate with each other via the communication unit 15 (see FIG. 2, etc.). Therefore, each of the FPGAs 10a to 10i (FIG. 2) and the integrated circuits 11a to 11i has a first transfer unit 2 (FIG. 3), which transfers output data to other FPGAs or integrated circuits. In this modification, the parallel integrated circuits 20, 30, and 40 are arranged in a single device. Also, the parallel integrated circuits have a plurality of switches which transfer output data to other FPGAs or integrated circuits.

[0062] 12 is a configuration diagram of a linked integrated circuit according to a modified example of the present invention. The linked integrated circuit 304 includes a plurality of parallel integrated circuits 22, 32, and 42, a plurality of second switch groups 25 and 26, and an integrated circuit configuration selection device (not shown). The parallel integrated circuit 22 includes a plurality of integrated circuits 11a, 11b, and 11c and a first switch group 19. The parallel integrated circuit 32 includes a plurality of integrated circuits 11d, 11e, and 11f and the first switch group 19. The parallel integrated circuit 42 includes a plurality of integrated circuits 11g, 11h, and 11i and the first switch group 19.

[0063] As in the above-described embodiments, the integrated circuits 11a to 11i may be FPGAs with no functions set, or may be FPGAs or ASICs with functions set. The first switch group 19 functions as a first transfer unit that transfers output data from the integrated circuits 11a to 11i to other integrated circuits in the parallel integrated circuit. The second switch groups 25 and 26 function as second transfer units that transfer output data from the integrated circuits 11a to 11i output via the first switch group 19 to other parallel integrated circuits. As in the above-described embodiments, the opening and closing of each switch that determines the transfer destination is determined by an integrated circuit configuration selection device (not shown).

[0064] (Effects) The following describes the effects of the integrated circuit configuration selection devices 100, 101, 102, and 103 according to the embodiments of the present invention.

[0065] (1) An integrated circuit configuration selection device (100, 101, 102, 103) that selects a circuit configuration that realizes a plurality of predefined connected functions using a linked integrated circuit (200, 201, 304) in which a plurality of integrated circuits (integrated circuits 11a to 11i, FPGAs 10a to 10i, ASICs) that realize functions are connected in parallel (20, 21, 22, 30, 31, 32, 40, 41, 42 or servers), the circuit configuration being either one or both of a plurality of functional arrangements of the integrated circuits and a plurality of connection paths (chains), and each of the integrated circuits realizes the function. an integrated circuit configuration selection device comprising: a functional unit (1); a first transfer unit (2) that transfers output data of the functional unit to an input unit (3) of another integrated circuit; each of the parallel integrated circuits having a second transfer unit (communication unit 15) that transfers data to the other parallel integrated circuit (another node, another server) when the destination of the transfer made by the first transfer unit is the other parallel integrated circuit; and a configuration selection unit (52, 52a, 52b) that selects a circuit configuration that minimizes the number of parallel integrated circuits (the number of nodes passed through) from among a plurality of circuit configurations that realize the plurality of linking functions (e.g., chain information).

[0066] According to this, the configuration selection unit selects a circuit configuration that minimizes the use of the second transfer unit (e.g., the communication unit 15) from among multiple circuit configurations that realize multiple connection functions, thereby reducing the occurrence of failures.

[0067] (2) The integrated circuit configuration selection device described in (1) is characterized in that, when the function of the integrated circuit is changeable, the configuration selection unit selects the functional layout and selects the connection path based on the selected functional layout, and when the functional layout of the integrated circuit is fixed in advance, the configuration selection unit selects the connection path.

[0068] When the integrated circuits are FPGAs with configurable functions, the configuration selection unit selects a functional layout that minimizes the number of parallel integrated circuits (the number of nodes passed through) from among multiple functional layouts that realize multiple link functions (e.g., chain information). The configuration selection unit can select a link path based on the selected functional layout. Furthermore, when the integrated circuits are FPGAs or ASICs with pre-fixed functional layouts, the configuration selection unit selects a link path that minimizes the number of parallel integrated circuits (the number of nodes passed through) from among multiple link paths that realize multiple link functions (e.g., chain information).

[0069] (3) An integrated circuit configuration selection device (100, 101, 102, 103) for selecting a circuit configuration for realizing a plurality of predefined linked functions using a linked integrated circuit (200, 201) in which a plurality of parallel integrated circuits (20, 21, 30, 31, 40, 41) are connected in parallel, each of which connects a plurality of integrated circuits (11a to 11i, FPGAs 10a to 10i, ASICs) that realize a function, wherein the circuit configuration is either one or both of a plurality of functional arrangements of the integrated circuits and a plurality of linking paths (chains), each of the integrated circuits has a functional unit (1) that realizes the function and a first transfer unit (2) that transfers output data of the functional unit to an input unit (3) of another integrated circuit, and each of the parallel integrated circuits has a second transfer unit (communication unit 15) that transfers data to the other parallel integrated circuit (another server) when the transfer destination of the first transfer unit is the other parallel integrated circuit, a configuration selection unit (52, 52a, 52b) that selects, from among the plurality of circuit configurations that realize the plurality of linking functions (chain information), a circuit configuration that maximizes the number of paths (number of chains) in which the number of parallel integrated circuits (number of nodes passed through) is 1.

[0070] Furthermore, the integrated circuit described in (3) above may further include a configuration narrowing-down unit (53) that, when there are multiple configurations selected by the configuration selection unit, narrows down the configurations to those with the fewest number (number of functions) of identical integrated circuits included in the multiple connection paths.

[0071] According to this, the configuration selection unit 52b selects a connection path that minimizes the use of the second transfer unit (e.g., the communication unit 15) from among multiple connection paths that realize multiple connection functions, thereby reducing the occurrence of failures.

[0072] 1 Functional unit 2 First transfer unit 10, 10a, 10b, 10c, 10d, 10e, 10f, 10g, 10h, 10i FPGA (integrated circuit) 11, 11a, 11b, 11c, 11d, 11e, 11f, 11g, 11h, 11i Integrated circuit 15 Communication unit (second transfer unit) 19 First switch group (first transfer unit) 20, 21, 22, 30, 31, 32, 40, 41, 42 Parallel integrated circuit (server) 25, 26 Second switch group (second transfer unit) 50, 50a, 50b Control unit 51 Priority determination unit 52, 52a Configuration selection unit 52b Configuration selection unit (transfer path selection unit) 53 Configuration narrowing unit 100, 101, 102, 103 Integrated circuit configuration selection device 200, 201, 304 Linked integrated circuits 300, 301, 302, 303 Integrated circuit configuration selection system

Claims

1. An integrated circuit configuration selection device that selects a circuit configuration that realizes a plurality of predefined linked functions using a linked integrated circuit in which a plurality of parallel integrated circuits that realize a plurality of integrated circuits that realize a function are connected, wherein the circuit configuration is either one or both of a plurality of functional layouts of the integrated circuits and a plurality of linking paths, each of the integrated circuits has a functional unit that realizes the function and a first transfer unit that transfers output data of the functional unit to an input unit of another integrated circuit, each of the parallel integrated circuits has a second transfer unit that transfers data to another parallel integrated circuit when the destination of the transfer made by the first transfer unit is another parallel integrated circuit, and the integrated circuit configuration selection device is equipped with a configuration selection unit that selects, from a plurality of circuit configurations that realize the plurality of linked functions, a circuit configuration that minimizes the number of parallel integrated circuits.

2. The integrated circuit configuration selection device described in claim 1, characterized in that, when the function of the integrated circuit is changeable, the configuration selection unit selects the functional layout and selects the connection path based on the selected functional layout, and when the functional layout of the integrated circuit is fixed in advance, the configuration selection unit selects the connection path.

3. An integrated circuit configuration selection device that selects a circuit configuration that realizes a plurality of predefined connected functions using a connected integrated circuit in which a plurality of parallel integrated circuits that realize a plurality of integrated circuits that are parallelly arranged to realize a function are connected, wherein the circuit configuration is one or both of a plurality of functional layouts of the integrated circuits and a plurality of connection paths, each of the integrated circuits has a functional unit that realizes the function and a first transfer unit that transfers output data of the functional unit to an input unit of another integrated circuit, and each of the parallel integrated circuits has a second transfer unit that transfers data to another parallel integrated circuit when the destination of the transfer from the first transfer unit is another parallel integrated circuit, the integrated circuit configuration selection device comprising: a configuration selection unit that selects, from a plurality of circuit configurations that realize the plurality of connected functions, a circuit configuration that maximizes the number of paths in which the number of parallel integrated circuits is 1; and a configuration narrowing down unit that, when there are a plurality of circuit configurations selected by the configuration selection unit, narrows down the selection to a circuit configuration in which the number of identical integrated circuits included in the plurality of connection paths is the smallest.

4. An integrated circuit configuration selection method executed by an integrated circuit configuration selection device that selects a circuit configuration that realizes a plurality of predefined connected functions using a connected integrated circuit in which a plurality of parallel integrated circuits that realize a plurality of integrated circuits that realize a function are connected in parallel, wherein the circuit configuration is either one or both of a plurality of functional layouts of the integrated circuits and a plurality of connection paths, each of the integrated circuits has a functional unit that realizes the function and a first transfer unit that transfers output data of the functional unit to an input unit of another integrated circuit, and each of the parallel integrated circuits has a second transfer unit that transfers data to another parallel integrated circuit when the transfer destination of the first transfer unit is another parallel integrated circuit, and the integrated circuit configuration selection device executes a configuration selection step that selects a circuit configuration that minimizes the number of parallel integrated circuits from among the plurality of circuit configurations that realize the plurality of connected functions.

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