Semiconductor light-emitting element, semiconductor light-emitting device, and method for manufacturing same

Abstract

[Problem] To make it possible to establish an electrical connection in an easy and stable manner. [Solution] A semiconductor light-emitting element comprises a layered body obtained by layering, in a prescribed layering direction, a plurality of light-emitting unit layers, each of which is obtained by layering a p-type layer, a light-emitting layer, and a n-type layer. The layered body constitutes a plurality of pixels that are partitioned by partition grooves and have a plurality of sub-pixels. The sub-pixels are divided, by a division groove that divides the light-emitting layer of a prescribed light-emitting unit layer, into a light-emitting portion and a non-light-emitting portion. Electrodes are provided on a mounting surface for the non-light-emitting portion and the light-emitting portion. The sub-pixels each have a conductive via that extends to a prescribed n-type layer adapted for constituting a circuit from the electrodes to the light-emitting layer of a prescribed light-emitting unit layer. The side surfaces of the conductive vias have a greater angle of inclination with respect to the layering direction than the side surfaces of the partition grooves. In a plurality of the sub-pixels, the electrodes on the light-emitting-portion side are formed on the same plane, and the electrodes on the non-light-emitting-portion side are formed on the same plane.

Description

Semiconductor light emitting element, semiconductor light emitting device, and method for manufacturing the same CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based on Japanese Patent Application No. 2024-152467 filed on September 4, 2024, Japanese Patent Application No. 2025-20968 filed on February 12, 2025, Japanese Patent Application No. 2025-58459 filed on March 31, 2025, Japanese Patent Application No. 2025-65874 filed on April 11, 2025, and Japanese Patent Application No. 2025-108850 filed on June 27, 2025, the contents of which are incorporated herein by reference.

[0002] The present disclosure relates to a semiconductor light emitting element, a semiconductor light emitting device, and a method for manufacturing the same.

[0003] As a high-resolution color display, a semiconductor light-emitting element is known in which several p-n junction LEDs are grown in the same epitaxial wafer and a multilevel mesa etching process is performed to form independent electrical contacts at each p-n junction, allowing for independent control of wavelength and radiance (e.g., Patent Document 1).

[0004] Special Publication No. 2021-508175

[0005] However, in the semiconductor light-emitting device described in Patent Document 1, the independent electrical contacts of the p-n junctions are formed at different heights. This poses a problem of proneness to poor electrical connection when mounted on a mounting substrate. Alternatively, to ensure good electrical connection, a mounting substrate with a complex structure is required to accommodate electrical contacts at different heights.

[0006] The present disclosure has been made in view of the above-described conventional circumstances, and aims to provide a semiconductor light emitting element and a semiconductor light emitting device that can be easily and stably electrically connected, and a method for manufacturing the same.

[0007] (1) A semiconductor light-emitting element according to a first aspect of the present disclosure includes a stack (30) in which a plurality of light-emitting unit layers (30R, 30G, 30B) each including a p-type layer (304, 308, 313), a light-emitting layer (303, 307, 312), and an n-type layer (302, 306, 310) are stacked in a predetermined stacking direction, and the stack (30) is partitioned by partitioning grooves (80) to form a plurality of pixels (70) each having a plurality of sub-pixels (71), and the sub-pixels are divided into light-emitting portions (72) and non-light-emitting portions (73) by partitioning grooves (801) that divide the light-emitting layer of a predetermined light-emitting unit layer, and electrodes (31) are provided on mounting surfaces of the light-emitting portions and the non-light-emitting portions, and the semiconductor light-emitting element has a conductive via (32) that leads from the electrode to a predetermined n-type layer for circuit configuration with the light-emitting layer of the predetermined light-emitting unit layer, and a side surface of the conductive via is inclined relative to the stacking direction relative to a side surface of the partitioning groove, The above problem is solved by forming, in the plurality of sub-pixels, the electrodes on the light-emitting portion side on the same surface, and the electrodes on the non-light-emitting portion side on the same surface.

[0008] (2) A semiconductor light-emitting element according to a second aspect of the present disclosure includes a stack (30) in which a plurality of light-emitting unit layers (30R, 30G, 30B) each including a p-type layer (304, 308, 313), a light-emitting layer (303, 307, 312), and an n-type layer (302, 306, 310) are stacked in a predetermined stacking direction, and the stack (30) is partitioned by partitioning grooves (80) to form a plurality of pixels (70) each including a plurality of sub-pixels (71), and the sub-pixels are divided into light-emitting portions (72) and non-light-emitting portions (73) by dividing grooves (801) that divide the light-emitting layer of a predetermined light-emitting unit layer, and electrodes (31) are provided on mounting surfaces of the light-emitting portions and the non-light-emitting portions, and a conductive via (32) is provided from the electrode to a predetermined n-type layer for forming a circuit from the electrode to the light-emitting layer of the predetermined light-emitting unit layer, The conductive vias include a plurality of conductive vias of different depths, and the conductive vias that are deeper than the other conductive vias have a continuous shape without any steps on the side of the portion corresponding to the depth of the other conductive vias, and in the plurality of sub-pixels, the electrodes on the light-emitting portion side are formed on the same surface, and the electrodes on the non-light-emitting portion side are formed on the same surface, thereby solving the above problem.

[0009] (3) In the semiconductor light emitting device of the present disclosure described above in (2), the side surface of the conductive via may be formed perpendicular to the mounting surface.

[0010] (4) In the semiconductor light emitting element of the present disclosure, in any one of (1) to (3) above, the electrode on the light emitting portion side and the electrode on the non-light emitting portion side may be formed on the same surface.

[0011] (5) In the semiconductor light-emitting element of the present disclosure, in any one of (1) to (3) above, the dividing groove of the subpixel may be a groove that has the same depth as the dividing groove to the n-type layer and is shallower than the conductive via of the light-emitting portion of a subpixel other than the subpixel.

[0012] (6) In the semiconductor light emitting element of the present disclosure, in any one of the above (1) to (3), the conductive via on the non-light emitting portion side of the subpixel may be a groove deeper than the dividing groove.

[0013] (7) In the semiconductor light-emitting element of the present disclosure, in any one of (1) to (3) above, the dividing groove may have a bottom (801x) having a flat surface (801y) and a recess (801z) deeper than the flat surface.

[0014] (8) The stacked body may have tunnel junction layers (305, 309) between the p-type layer and the n-type layer of the light-emitting unit layers adjacent to each other in the stacking direction.

[0015] (9) The plurality of sub-pixels may include a sub-pixel having a single light-emitting unit layer and a sub-pixel having two light-emitting unit layers.

[0016] (10) In the pixel, the number of the non-light-emitting portions may be smaller than the number of the light-emitting portions.

[0017] (11) In the pixel, the sub-pixel may not be sandwiched between other sub-pixels when viewed from the stacking direction of the stack.

[0018] (12) A semiconductor light emitting device according to another aspect of the present disclosure may be configured such that the semiconductor light emitting element (1) according to any one of (1) to (3) is mounted on a mounting substrate (90).

[0019] (13) A plurality of the semiconductor light-emitting elements (2) are mounted in the mounting region (90a) of the mounting substrate, and the semiconductor light-emitting elements may include an element substrate and a plurality of the pixels arranged on the element substrate.

[0020] (14) A method for manufacturing a semiconductor light-emitting element according to another aspect of the present disclosure includes: a laminate (30) in which a plurality of light-emitting unit layers (30R, 30G, 30B) each having a p-type layer (304, 308, 313), a light-emitting layer (303, 307, 312), and an n-type layer (302, 306, 310) are laminated on an element substrate (10) in a predetermined lamination direction; the laminate (30) is partitioned by partition grooves (80) to form a plurality of pixels (70) each having a plurality of sub-pixels (71); the sub-pixels are divided into light-emitting portions (72) and non-light-emitting portions (73) by partition grooves (801) that divide the light-emitting layer of a predetermined light-emitting unit layer; electrodes (31) are provided on mounting surfaces of the light-emitting portions and the non-light-emitting portions, and conductive vias (32) are provided from the electrodes to a predetermined n-type layer for configuring a circuit from the electrode to the light-emitting layer of the predetermined light-emitting unit layer; A method for manufacturing a semiconductor light-emitting element, in which the electrodes on the light-emitting portion side of the plurality of sub-pixels are formed on the same surface and the electrodes on the non-light-emitting portion side are formed on the same surface, can include: an epitaxial stacking process (S00) in which each layer of the stack is formed on the element substrate by epitaxial film formation; a pixel partition groove forming process (S01) in which the partition grooves are formed by etching in the stacking direction of the stack; a pixel shape processing process (S02) in which the dividing grooves and grooves of at least the conductive vias in the light-emitting portion among the conductive vias are formed by etching multiple times; and an electrode forming process (S05) in which the electrodes and the conductive vias are formed.

[0021] (15) In the method for manufacturing a semiconductor light-emitting element according to the present disclosure, in the above (13), the stack may include a tunnel junction layer (305, 309) between a p-type layer and an n-type layer of the light-emitting unit layers adjacent to each other in the stacking direction.

[0022] (16) In the manufacturing method of the semiconductor light-emitting element of the present disclosure, in the above (13), in the multiple etchings in the pixel shape processing step, the dividing groove and the conductive via groove are formed from shallower portions, and the difference in depth is additionally formed in deeper portions.

[0023] (17) In the method for manufacturing a semiconductor light-emitting element according to the present disclosure, in the above (13), the dividing grooves and the conductive via grooves may be formed as grooves of the same depth in the multiple etchings in the pixel shape processing step.

[0024] (18) The grooves for the conductive vias in the non-light-emitting portions may be formed in the pixel partition groove forming step (S01).

[0025] (19) A method for manufacturing a semiconductor light emitting device according to another aspect of the present disclosure may include mounting a semiconductor light emitting element manufactured by the manufacturing method described in (13) above on a mounting substrate (90).

[0026] (20) The method for manufacturing a semiconductor light emitting device according to the present disclosure in the above (18) may further include a lift-off step of lifting off the element substrate after the semiconductor light emitting element is mounted on the mounting substrate.

[0027] (21) In the method for manufacturing a semiconductor light emitting device according to the present disclosure as recited in (19), the pixel of the semiconductor light emitting element may be formed by integrating the plurality of sub-pixels.

[0028] According to the present disclosure, it is possible to provide a semiconductor light emitting element and a semiconductor light emitting device that can be easily and stably electrically connected, as well as a method for manufacturing the same.

[0029] 5 is a schematic diagram showing VR goggles as an example of a display device including a first embodiment of a semiconductor light emitting device according to the present disclosure; FIG. 6 is a schematic plan view showing a mounting substrate used in the first embodiment of the semiconductor light emitting device according to the present disclosure; FIG. 7 is a partial plan view showing an arrangement of pixels and the like in the first embodiment of the semiconductor light emitting device according to the present disclosure; FIG. 8 is a plan view showing a pixel in the first embodiment of the semiconductor light emitting device according to the present disclosure; FIG. 9 is a cross-sectional view showing a pixel in the first embodiment of the semiconductor light emitting device according to the present disclosure; FIG. 10 is a cross-sectional view in a direction intersecting FIG. 5; FIG. 11 is a schematic cross-sectional view for explaining the principle of current flow in the first embodiment of the semiconductor light emitting device according to the present disclosure; FIG. 12 is a cross-sectional view showing the bottom of a dividing groove in the first embodiment of the semiconductor light emitting device according to the present disclosure; FIG. 13 is a flowchart showing a first embodiment of a method for manufacturing a semiconductor light emitting element according to the present disclosure; FIG. 14 is an explanatory view of steps illustrating the first embodiment of the method for manufacturing a semiconductor light emitting element according to the present disclosure; FIG. 15 is an explanatory view of steps illustrating the first embodiment of the method for manufacturing a semiconductor light emitting element according to the present disclosure; FIG. 16 is an explanatory view of steps illustrating the first embodiment of the method for manufacturing a semiconductor light emitting element according to the present disclosure; FIG. 1 is an explanatory diagram of a process illustrating a third variation of the first embodiment of the method for manufacturing a semiconductor light emitting element according to the present disclosure. FIG. 2 is an explanatory diagram of a process illustrating a fourth variation of the first embodiment of the method for manufacturing a semiconductor light emitting element according to the present disclosure. FIG. 3 is an explanatory diagram of a process illustrating a fifth variation of the first embodiment of the method for manufacturing a semiconductor light emitting element according to the present disclosure. FIG. 4 is a cross-sectional view showing a first embodiment of the semiconductor light emitting device according to the present disclosure. FIG. 5 is a cross-sectional view showing a first embodiment of the semiconductor light emitting device according to the present disclosure. FIG. 6 is a schematic partial cross-sectional view showing a first variation of the first embodiment of the semiconductor light emitting device according to the present disclosure. FIG. 7 is a schematic partial cross-sectional view showing a second variation of the first embodiment of the semiconductor light emitting device according to the present disclosure. FIG. 8 is a cross-sectional view showing each pixel in a fourth variation of the first embodiment of the semiconductor light emitting element according to the present disclosure. FIG. 9 is a schematic partial cross-sectional view showing a third variation of the first embodiment of the semiconductor light emitting device according to the present disclosure.FIG. 1 is a schematic partial cross-sectional view showing a fourth modification of the first embodiment of the semiconductor light emitting device according to the present disclosure. FIG. 2 is a schematic partial cross-sectional view showing a fifth modification of the first embodiment of the semiconductor light emitting device according to the present disclosure. FIG. 3 is a schematic partial cross-sectional view showing a sixth modification of the first embodiment of the semiconductor light emitting device according to the present disclosure. FIG. 4 is a schematic partial cross-sectional view showing a sixth modification of the first embodiment of the semiconductor light emitting device according to the present disclosure. FIG. 5 is a schematic partial cross-sectional view showing a sixth modification of the first embodiment of the semiconductor light emitting device according to the present disclosure. FIG. 6 is a schematic partial cross-sectional view showing a sixth modification of the first embodiment of the semiconductor light emitting device according to the present disclosure. FIG. 7 is a schematic partial cross-sectional view showing a sixth modification of the first embodiment of the semiconductor light emitting device according to the present disclosure. FIG. 8 is a schematic partial cross-sectional view showing a sixth modification of the first embodiment of the semiconductor light emitting device according to the present disclosure.

[0030] First Embodiment A first embodiment of a semiconductor light emitting element, a semiconductor light emitting device, and a method for manufacturing the same according to the present disclosure will be described below with reference to the drawings.

[0031] 1 is a schematic diagram showing VR goggles, which is an example of a display device including a semiconductor light emitting device according to this embodiment. In the figure, reference numeral 100 denotes a semiconductor light emitting device.

[0032] The semiconductor light-emitting device 100 according to this embodiment is used in a display device such as a VR goggle. As shown in FIG. 1 , a VR (virtual reality) goggle 200 includes a plurality of semiconductor light-emitting devices 100. The semiconductor light-emitting devices 100 are disposed in front of a viewer's eyes 202, with lenses 201 sandwiched between them. The distance between the semiconductor light-emitting device 100 and the viewer's eyes 202 is approximately 5 cm. The semiconductor light-emitting device 100 is a self-luminous display having, for example, 320 × 180 pixels densely arranged in a dot matrix. The width of the pixels of the semiconductor light-emitting device 100 may be less than 100 μm. The width of the pixels of the semiconductor light-emitting device 100 is formed to a size of, for example, 60 μm, 12 μm, or 5 μm.

[0033] FIG. 2 is a schematic plan view showing a mounting substrate used in the semiconductor light emitting device of this embodiment.

[0034] The semiconductor light emitting device 100 includes a mounting substrate 90 shown in Fig. 2 and a semiconductor light emitting element 1 mounted in a mounting area of ​​the mounting substrate 90. The mounting substrate 90 is provided with metal bumps 94 serving as connection terminals with the semiconductor light emitting element 1 and a plurality of external terminals 90t in the mounting area of ​​the mounting substrate 90. The plurality of metal bumps 94 and the plurality of external terminals 90t are electrically connected by three-dimensional wiring such as wiring 91 and wiring 93. The mounting substrate 90 also includes a CMOS (Complementary Metal Oxide Semiconductor) and has a switching function.

[0035] The semiconductor light emitting element 1 has a plurality of pixels 70 (described later) arranged vertically and horizontally at positions corresponding to the metal bumps 94 in the mounting area of ​​the mounting substrate 90. The semiconductor light emitting element 1 is electrically connected to the external terminals 90t and is provided on the surface of the mounting substrate 90 facing the viewer's eye 202. The light emitted by the semiconductor light emitting element 1 reaches the viewer's eye 202.

[0036] In the following description, the direction of the semiconductor light-emitting device 100 relative to the viewer's eye 202 is referred to as the Z direction. The semiconductor light-emitting device 100 is primarily shown with the direction of the viewer's eye 202 as the upside, while the semiconductor light-emitting element 1 is shown with the direction opposite the viewer's eye 202 as the upside. The direction opposite the viewer's eye 202 is referred to as the positive Z direction. [Semiconductor Light-Emitting Element of First Embodiment] FIG. 3 is a partial plan view showing the arrangement of pixels and the like of a semiconductor light-emitting element of this embodiment. In FIG. 3, multiple pixels are arranged along an XY plane formed by the X direction and the Y direction. The Z direction is the normal direction to the XY plane. The X direction, the Y direction, and the Z direction are perpendicular to one another.

[0037] The semiconductor light emitting element 1 has a plurality of pixels 70 partitioned by partitioning grooves 80. The plurality of pixels 70 are arranged adjacent to one another in a matrix along the XY plane.

[0038] 4 is a plan view showing a pixel of the semiconductor light-emitting element according to this embodiment. The pixel 70 is formed in a substantially square shape. The pixel 70 includes sub-pixels 71, namely, a blue-emitting sub-pixel 71B, a green-emitting sub-pixel 71G, and a red-emitting sub-pixel 71R, which are partitioned by partitioning grooves 802.

[0039] Each sub-pixel 71 has a light-emitting portion 72 and a non-light-emitting portion 73 separated by a separating groove 801 .

[0040] That is, the blue-emitting subpixel 71B has a light-emitting portion 72B and a non-light-emitting portion 73B, the green-emitting subpixel 71G has a light-emitting portion 72G and a non-light-emitting portion 73G, and the red-emitting subpixel 71R has a light-emitting portion 72R and a non-light-emitting portion 73R.

[0041] An electrode 31p and an electrode 31n are formed in the light-emitting portion 72 and the non-light-emitting portion 73 of each sub-pixel 71, respectively. The electrode 31p is a positive electrode (anode electrode), and the electrode 31n is a negative electrode (cathode electrode). Furthermore, a conductive via 32 electrically connected to the respective electrode 31 is formed in the light-emitting portion 72 and the non-light-emitting portion 73 of each sub-pixel 71 (excluding the non-light-emitting portion 73R of the red sub-pixel 71R).

[0042] That is, the blue-emitting sub-pixel 71B has an electrode 31p and a conductive via 32p formed in the light-emitting portion 72, and an electrode 31n and a conductive via 32n formed in the non-light-emitting portion 73. The green-emitting sub-pixel 71G has an electrode 31Gp and a conductive via 32Gp formed in the light-emitting portion 72G, and an electrode 31Gn and a conductive via 32Gn formed in the non-light-emitting portion 73G. The red-emitting sub-pixel 71R has an electrode 31Rp and a conductive via 32Rp formed in the light-emitting portion 72R, and an electrode 31Rn and a conductive via 32Rn formed in the non-light-emitting portion 73R.

[0043] The electrodes 31p and 31n are formed on substantially the entire upper surfaces of the light-emitting portion 72 and non-light-emitting portion 73 of each sub-pixel 71. The conductive via 32 is formed in the shape of a slit extending in the X direction near the center of the electrode 31. As will be described later, the conductive via 32 is formed in a concave shape facing downward in the Z direction from the upper surface of the stack 30.

[0044] 5 and 6 are cross-sectional views of pixels of the semiconductor light-emitting element according to this embodiment. Fig. 5 shows a cross section of each sub-pixel in the X direction. From the left, these are cross sections A-A, B-B, and C-C of the plan view shown in Fig. 4. Fig. 6 is a cross-sectional view taken along the line D-D in a direction intersecting Fig. 5.

[0045] As shown in FIGS. 5 and 6, the subpixel 71 of the semiconductor light emitting element 1 includes a sapphire substrate 10 as an element substrate, a laminated body 30, an electrode 31, a conductive via 32, and a dividing groove 801.

[0046] The sapphire substrate (element substrate) 10 is a plate-shaped sapphire substrate having both surfaces polished to flat surfaces, and has a thickness of, for example, 300 μm.

[0047] The laminate 30 is stacked on the upper surface of the sapphire substrate 10. The layers of the laminate 30 are stacked in a predetermined stacking direction. The vertical direction in FIGS. 5 and 6 is the stacking direction of the laminate 30. The stacking direction of the laminate 30 is a direction perpendicular to the plate surface of the sapphire substrate 10. As shown in FIGS. 5 and 6, the laminate 30 has layers stacked on the upper surface of the sapphire substrate 10 in the following order:

[0048] First buffer layer 301, first n-type layer 302, first light-emitting layer 303 (blue light-emitting layer), first p-type layer 304, first tunnel junction layer 305, second n-type layer 306, second light-emitting layer 307 (green light-emitting layer), second p-type layer 308, second tunnel junction layer 309, third n-type layer 310, second buffer layer 311, third light-emitting layer 312 (red light-emitting layer), third p-type layer 313, third tunnel junction layer 314, fourth n-type layer 315. The first buffer layer 301 is stacked on the upper surface of the sapphire substrate 10. The thickness of the first buffer layer 301 is, for example, 2000 nm. The first buffer layer 301 may be made of AlN, GaN, or the like grown at a low temperature. The first buffer layer 301 is located at the bottom of the stack 30. The first buffer layer 301 reduces the lattice mismatch between at least the sapphire substrate 10 and the first n-type layer 302 .

[0049] The first n-type layer 302 is stacked on the upper surface of the first buffer layer 301. The thickness of the first n-type layer 302 is, for example, 2000 nm. The first n-type layer 302 is formed of, for example, GaN doped with n-type impurities such as Si (n-GaN).

[0050] The first light-emitting layer 303 is laminated on the upper surface of the first n-type layer 302. The first light-emitting layer 303 is formed, for example, as a multiple quantum well. The thickness of the first light-emitting layer 303 is, for example, 50 nm. The first light-emitting layer 303 is configured to be able to emit light with an emission wavelength corresponding to blue (for example, 450 to 470 nm).

[0051] The first p-type layer 304 is stacked on the upper surface of the first light-emitting layer 303. The thickness of the first p-type layer 304 is, for example, 180 nm. The first p-type layer 304 is formed of, for example, GaN doped with p-type impurities such as Mg (p-GaN).

[0052] The first tunnel junction layer 305 is stacked on the top surface of the first p-type layer 304. The thickness of the first tunnel junction layer 305 is, for example, 25 nm. The first tunnel junction layer 305 is formed by stacking an n++ GaN layer doped with a high concentration of Si and a p++ GaN layer doped with a high concentration of Mg. Here, n++ means a state where n-type impurities are doped with a high concentration, and p++ means a state where p-type impurities are doped with a high concentration. The tunnel junction layer is a layer that allows current to flow from an n-type semiconductor to a p-type semiconductor.

[0053] The second n-type layer 306 is stacked on the upper surface of the first tunnel junction layer 305. The second n-type layer 306 has a thickness of, for example, 400 nm. The second n-type layer 306 is formed of, for example, GaN doped with n-type impurities such as Si (n-GaN).

[0054] The second light-emitting layer 307 is laminated on the upper surface of the second n-type layer 306. The second light-emitting layer 307 is formed, for example, as a multiple quantum well. The thickness of the second light-emitting layer 307 is, for example, 50 nm. The second light-emitting layer 307 is configured to be able to emit light having an emission wavelength corresponding to green (for example, 500 to 570 nm).

[0055] The second p-type layer 308 is laminated on the upper surface of the second light-emitting layer 307. The thickness of the second p-type layer 308 is, for example, 180 nm. The second p-type layer 308 is formed of, for example, GaN doped with p-type impurities such as Mg (p-GaN).

[0056] The second tunnel junction layer 309 is stacked on the upper surface of the second p-type layer 308. The thickness of the second tunnel junction layer 309 is, for example, 25 nm. The second tunnel junction layer 309 is formed by stacking an n++ GaN layer doped with a high concentration of Si and a p++ GaN layer doped with a high concentration of Mg.

[0057] The third n-type layer 310 is stacked on the upper surface of the second tunnel junction layer 309. The third n-type layer 310 has a thickness of, for example, 400 nm. The third n-type layer 310 is formed of, for example, GaN doped with n-type impurities such as Si.

[0058] The second buffer layer 311 is stacked on the upper surface of the third n-type layer 310. The thickness of the second buffer layer 311 is, for example, 600 nm. The second buffer layer 311 reduces the lattice mismatch between the third light-emitting layer 312 and the third n-type layer 310. The second buffer layer 311 is made of GaInN.

[0059] The third light-emitting layer 312 is laminated on the upper surface of the second buffer layer 311. The third light-emitting layer 312 is formed, for example, as a multiple quantum well. The thickness of the third light-emitting layer 312 is, for example, 50 nm. The third light-emitting layer 312 is configured to be able to generate light with an emission wavelength corresponding to red (for example, 600 to 650 nm).

[0060] The third p-type layer 313 is stacked on the upper surface of the third light-emitting layer 312. The thickness of the third p-type layer 313 is, for example, 180 nm. The third p-type layer 313 is formed of, for example, GaN doped with p-type impurities such as Mg.

[0061] The third tunnel junction layer 314 is stacked on the top surface of the third p-type layer 313. The thickness of the third tunnel junction layer 314 is, for example, 25 nm. The third tunnel junction layer 314 is formed by stacking an n++ GaN layer doped with a high concentration of Si and a p++ GaN layer doped with a high concentration of Mg.

[0062] The fourth n-type layer 315 is stacked on the upper surface of the third tunnel junction layer 314. The fourth n-type layer 315 has a thickness of, for example, 300 nm. The fourth n-type layer 315 is formed of, for example, GaN doped with n-type impurities such as Si.

[0063] Of the above layers, the first n-type layer 302, the first light-emitting layer 303 (blue light-emitting layer), and the first p-type layer 304 form a blue light-emitting unit layer 30B. The second n-type layer 306, the second light-emitting layer 307 (green light-emitting layer), and the second p-type layer 308 form a green light-emitting unit layer 30G. The third n-type layer 310, the second buffer layer 311, the third light-emitting layer 312 (red light-emitting layer), and the third p-type layer 313 form a red light-emitting unit layer 30R. The light-emitting unit layers 30 of each color include at least a light-emitting layer of the corresponding color and an n-type layer and a p-type layer on either side of the light-emitting layer, and are the basic unit of a light-emitting diode.

[0064] Tunnel junction layers 305 and 309 are provided between the p-type layers 304, 308 and 313 and the n-type layers 302, 306 and 310 of the adjacent light-emitting unit layers 30R, 30G and 30B.

[0065] A first tunnel junction layer 305 is provided between the blue light-emitting unit layer 30B and the green light-emitting unit layer 30G. A second tunnel junction layer 309 is provided between the green light-emitting unit layer 30G and the red light-emitting unit layer 30R.

[0066] Furthermore, a third tunnel junction layer 314 and a fourth n-type layer 315 are provided on the upper surface of the red light-emitting unit layer 30R.

[0067] 6 , the partitioning grooves 80 that partition the pixels 70 and the partitioning grooves 802 that partition the sub-pixels 71 are grooves that extend from the upper surface of the stacked body 30 to the sapphire substrate 10. Therefore, the pixels 70 and the sub-pixels 71 are formed in an island shape on the sapphire substrate 10. The partitioning grooves 80 are formed perpendicular to the sapphire substrate 10.

[0068] In the thick laminate 30 in which a plurality of light-emitting unit layers 30R, 30G, and 30B are stacked, the partition grooves 80 are formed vertically, thereby narrowing the width of the partition grooves 80 and increasing the effective area of ​​the pixels 70 and sub-pixels 71. This also makes it possible to advantageously form fine pixels.

[0069] 5 , the electrodes 31 of the sub-pixels 71 of each luminescent color are all formed on the fourth n-type layer 315, which is the uppermost layer of the laminate 30. The surface of the laminate 30 on which the electrodes 31 are formed becomes the mounting surface that is connected to the mounting substrate 90.

[0070] On the other hand, the dividing grooves 801 and conductive vias 32 of the sub-pixels 71 of each luminescent color are formed to a predetermined depth up to the layer necessary for the circuit configuration to the luminescent layers of the light-emitting unit layers 30R, 30G, and 30B corresponding to each luminescent color. Note that in this specification, "depth" means the depth from the mounting surface of the laminate 30.

[0071] That is, in the blue-emitting subpixel 71B, the dividing groove 801B is deep enough to reach the first n-type layer 302, the conductive via 32Bp of the light-emitting portion 72B is deep enough to reach the second n-type layer 306, and the conductive via 32Bn of the non-light-emitting portion 73B is deep enough to reach the first n-type layer 302.

[0072] In the green-emitting subpixel 71G, the dividing groove 801G is deep enough to reach the second n-type layer 306, the conductive via 32Gp of the light-emitting portion 72G is deep enough to reach the third n-type layer 310, and the conductive via 32Gn of the non-light-emitting portion 73G is deep enough to reach the second n-type layer 306.

[0073] In the red-emitting sub-pixel 71R, the dividing groove 801R and the conductive via 32Rn in the non-light-emitting portion 73R are set to a depth reaching the third n-type layer 310.

[0074] As shown in Fig. 4, the conductive via 32 has a slit-like outline with a longitudinal side and a lateral side when viewed in the Z direction. As shown in Fig. 5 and Fig. 6, the conductive via 32 has a shape including an inclined surface that tapers downward in the Z direction.

[0075] The principle of current flow in the circuit configuration of the semiconductor light emitting device of this embodiment is shown in Fig. 7. Here, the green light emitting sub-pixel 71G will be described as an example.

[0076] A current flows from the positive electrode 31Gp through the conductive via 32Gp to the third n-type layer 310. Here, the conductive via 32Gp has a lower electrical resistance than the laminate 30, and the third light-emitting layer 312 has a band gap. Therefore, no current flows through the third light-emitting layer 312, and the third light-emitting layer 312 does not emit light.

[0077] The current diffuses in the direction along the XY plane in the third n-type layer 310. The current diffused in the direction along the XY plane is injected from the second tunnel junction layer 309 into the second p-type layer 308, passes through the second light-emitting layer 307, and reaches the second n-type layer 306. Then, the entire surface of the second light-emitting layer 307 of the light-emitting unit 72G emits light.

[0078] Current diffusion in the direction along the XY plane in the third n-type layer 310 is facilitated because the n-type layer has a significantly lower resistivity and a larger thickness than the p-type layer. In addition, the tunnel junction layer enables current to flow from the n-type semiconductor to the p-type semiconductor.

[0079] If the second tunnel junction layer 309 is not provided and the conductive via 32Gp directly reaches the second p-type layer 308, only a part of the second light-emitting layer 307 emits light. That is, since the second p-type layer 308 has high resistance, diffusion does not occur in the surface direction. Therefore, current flows only in the part of the second light-emitting layer 307 directly below the conductive via 32Gp. Therefore, only the part directly below the conductive via 32Gp emits light.

[0080] Furthermore, the current that has reached the second n-type layer 306 flows to the second n-type layer 306 on the non-light-emitting portion 73 side, and reaches the negative electrode 31Gn through the conductive via 32Gn.

[0081] As described above, the conductive vias 32n on the dividing groove 801 and non-light-emitting portion 73 side are deep enough to reach the n-type layers of the light-emitting unit layers 30R, 30G, and 30B corresponding to the emitted light colors. The conductive vias 32p on the light-emitting portion 72 side are deep enough to reach the n-type layers via the upper tunnel junction layers of the light-emitting unit layers 30R, 30G, and 30B corresponding to the emitted light colors. This completes the circuit configuration for the light-emitting layers of the light-emitting unit layers 30R, 30G, and 30B corresponding to the respective emitted light colors. Note that the light-emitting portion 72B of the uppermost red-emitting sub-pixel 71R does not require a conductive via 32 because the electrode 31Rp is formed in the n-type layer 315 via the upper tunnel junction layer 314 of the light-emitting unit layer 30R corresponding to the emitted light color.

[0082] As configured above, in the semiconductor light emitting device 1, an independent circuit is formed in each of the light emitting unit layers 30R, 30G, and 30B corresponding to the emitted light color, and the emitted light color and light intensity can be controlled independently.

[0083] The plurality of electrodes 31 of the semiconductor light emitting element 1, which serve as electrical terminals of the circuits to the light emitting layers of the light emitting unit layers 30R, 30G, and 30B corresponding to the respective light emission colors, are formed on the same surface of the laminate 30. The same surface on which the electrodes 31 are formed serves as the mounting surface, and can easily be electrically connected stably to the mounting substrate 90.

[0084] The material of the conductive vias 32 is not particularly limited as long as it is a conductive material that has sufficient conductivity to form the above-mentioned current-carrying circuit, and examples thereof include gold, aluminum, and copper.

[0085] In this embodiment, the opening of the conductive via 32 is slit-shaped. The width of this opening in the Y direction is approximately 2.5 μm. The shape of the opening in the Z direction is a cone shape including an inclined surface that tapers from the electrode 31 toward the n-type layer.

[0086] The taper angle of the inclined surface of this groove is preferably an angle that does not make the electrode-side opening of the conductive via 32 excessively large for small-sized LEDs, and that allows a conductive material to be stably placed on the side surface of the inclined groove, as described below. Therefore, for example, the taper angle of the inclined surface of this groove is preferably 10° to 45°, and more preferably 20° to 40°. The side surface of the conductive via 32 is inclined at a greater angle with respect to the stacking direction of the laminate 30 than the side surface of the partitioning groove 80.

[0087] The opening of the conductive via 32 is not limited to a slit shape, and may be other shapes such as a circle (cone). However, a slit shape makes it easier to form a narrow shape. A resist mask with a smaller dimension can be formed when the width of the shorter side of the slit shape is smaller than the diameter of the circle. Furthermore, for a rectangular light-emitting portion 72, a slit shape that is long in the long side direction is advantageous for current diffusion to the light-emitting layer. The conductive via 32 may be formed on the outer periphery of the electrode rather than inside it.

[0088] Fig. 8 is an enlarged cross-sectional view of a bottom 801x of a dividing groove 801. The dividing groove 801 shown in Fig. 8 includes a dividing groove 801B formed in the blue-emitting subpixel 71B, a dividing groove 801G formed in the green-emitting subpixel 71G, and a dividing groove 801R formed in the red-emitting subpixel 71R. In the red-light-emitting unit layer 30R, a second buffer layer 311 is present between the third light-emitting layer 312 and the third n-type layer 310, but is not shown in Fig. 8 for ease of explanation.

[0089] 8 , the dividing grooves 801 are formed to a depth that reaches the n-type layers 302, 306, and 310 of the light-emitting unit layers 30R, 30G, and 30B, and bottoms 801x of the dividing grooves 801 are formed in the n-type layers 302, 306, and 310. The bottoms 801x of the dividing grooves 801 have flat surfaces 801y with a predetermined area.

[0090] A recess 801z is formed in part of the bottom 801x of the dividing groove 801. In other words, the bottom 801x does not have a uniform depth all over, but a recess 801z that is deeper than the flat surface 801y is formed in the peripheral portion along the side surface of the dividing groove 801. The recess 801z can also be called a cutout or notch. The recess 801z is formed in part of the bottom 801x when plasma gathers in the peripheral portion along the side surface of the dividing groove 801 when the dividing groove 801 is formed by etching.

[0091] The recesses 801z have a significant depth, for example, 50 nm or more, relative to the flat portion of the bottom 801x. The dividing grooves 801 can divide the light-emitting layers 303, 307, and 312 of the light-emitting unit layers 30R, 30G, and 30B by the recesses 801z of the bottom 801x. Furthermore, in the shallow flat portion of the bottom 801x other than the recesses 801z, the thickness of the n-type layers 302, 306, and 310 can be left large, thereby keeping the resistance value of the n-type layers 302, 306, and 310 between the light-emitting portion 72 and the non-light-emitting portion 73 low. The maximum depth of the dividing grooves 801, including the recesses 801z, is set within a range that does not divide the n-type layers 302, 306, and 310.

[0092] (First Embodiment of Method for Manufacturing Semiconductor Light Emitting Device) Next, a method for manufacturing a semiconductor light emitting device according to this embodiment will be described.

[0093] Fig. 9 is a flowchart showing a method for manufacturing a semiconductor light-emitting element according to this embodiment. Fig. 10 is an explanatory diagram of step S00 showing the method for manufacturing a semiconductor light-emitting element according to this embodiment. Fig. 11 is an explanatory diagram of step S01 showing the method for manufacturing a semiconductor light-emitting element according to this embodiment. Figs. 12 to 16 are explanatory diagrams of step S02 showing the method for manufacturing a semiconductor light-emitting element according to this embodiment.

[0094] As shown in FIG. 9, the method for manufacturing a semiconductor light-emitting element in this embodiment includes an epitaxial layer stacking step S00, a pixel partition groove forming step S01, a pixel shape processing step S02, a p-active annealing step S03, an insulating film forming step S04, and an electrode forming step S05.

[0095] The method for manufacturing the semiconductor light-emitting element 1 first performs an epitaxial layering step S00 in which each layer of the laminate 30 is formed on the sapphire substrate 10 by epitaxial film formation. In the epitaxial layering step S00, as shown in Fig. 10, each layer constituting the laminate 30 shown in Fig. 5 is deposited by crystal growth on the upper surface side of the sapphire substrate 10 using a metal-organic vapor phase epitaxy (MOVPE) method. This results in a layer configuration corresponding to the laminate 30. Note that Fig. 10 schematically shows the sapphire substrate 10 and the laminate 30.

[0096] Next, in a pixel partition groove forming step S01, partition grooves 80 and 802 are formed in the laminate 30, as shown in Fig. 11. This process of forming partition grooves includes a laminate mask forming step for forming vertical grooves, an etching step, and a laminate mask removing step. (Laminate Mask Forming Step) In the laminate mask forming step, as shown in Fig. 12(a), a thin-film base film 53, a thin-film metal bonding layer 54, and a lower layer film 51 are laminated in this order in contact with the entire surface of the top layer of the laminate 30.

[0097] The thin underlayer film 53 is, for example, ITO (indium tin oxide) having a thickness of 5 nm. The thin metal bonding layer 54 is, for example, Ti (titanium) having a thickness of 5 nm. The underlayer film 51 is, for example, SiO ２ (silicon oxide). These can be deposited using a sputtering device, for example.

[0098] Next, as shown in FIG. 12B , an upper layer film 52 is laminated on the lower layer film 51 in areas other than where the partitioning grooves 80 and 802 are to be formed. First, a resist material is applied to the upper surface of the lower layer film 51 to form a resist film. Next, a resist mask is formed using lithography only in areas where the partitioning grooves 80 and 802 are to be formed. Then, the upper layer film 52 is deposited by vapor deposition on the upper surface of the lower layer film 51 exposed from the resist mask and on the upper surface of the resist mask. Thereafter, the resist mask is removed, allowing the upper layer film 52 to be laminated on areas other than where the partitioning grooves 80 and 802 are to be formed. The upper layer film 52 is, for example, Ni (nickel) with a thickness of 100 nm. The upper layer film 52 can be formed using, for example, a vapor deposition apparatus.

[0099] Next, as shown in FIG. 12(c), fluoride gas CF ４ 12(d), the lower layer 51, the metal bonding layer 54, and the base film 53 are removed from the regions where the partitioning grooves 80 and 802 are to be formed, which are not covered by the upper layer 52. In this embodiment, the etching rate of the lower layer 51 with respect to the fluoride gas is sufficiently higher than that of the upper layer 52. Therefore, the side surfaces of the upper layer 52 and the lower layer 51 that form the layered mask 50 are formed so as to have an extremely small taper angle and are sheer vertically. In this way, the layered mask 50 is formed. (Etching Process) In the etching process, as shown in FIG. 12(d), Cl ２ The laminate 30 in the exposed regions not covered by the laminate mask 50 is removed by dry etching using chlorine gas (chlorine gas). The etching is performed to a depth reaching the top surface of the sapphire substrate 10 and is stopped when the etching reaches the top surface of the sapphire substrate 10. As a result, as shown in FIG. 11( b), partition grooves 80 and partition grooves 802 are formed around the periphery of the pixel 70, reaching the top surface of the sapphire substrate 10, and a plurality of island-shaped pixels 70 are formed on the sapphire substrate 10. At this time, the Cl of the laminate 30 made of GaN is removed from the laminate mask 50. ２ 11( b), the etching rate is sufficiently high, and the partitioning grooves 80 and 802 are deep and have a vertically sheer shape with an extremely small taper angle. (Stack Mask Removal Step) In the stack mask removal step, the stack mask 50 provided on the top surface of the stack 30 is removed using hydrofluoric acid, which is an aqueous solution containing hydrogen fluoride at a predetermined concentration. This exposes the entire top surface of the top layer of the stack 30.

[0100] In experiments conducted by the inventors, the angle formed by the wall surfaces of the partition grooves 80 and 802 with respect to the upper surface of the sapphire substrate 10 was 89 degrees or more, and it was confirmed that the partition grooves 80 and 802 were formed to be almost vertical.

[0101] Furthermore, it has been confirmed that, when the thickness of the ITO of the thin-film base film 53 is set to 20 nm and other conditions are the same, partition grooves 80 and 802 with a wall angle of 87 degrees can be formed. When the partition grooves 80 and 802 with wall angles of 89 and 87 degrees are set to a depth of 6 μm, the inclined surface effect (6 μm × tan (taper angle)) of the partition grooves 80 and 802 can be suppressed to 0.1 μm and 0.3 μm, respectively. Theoretically, partition grooves 80 and 802 with widths of 0.3 μm or 0.7 μm can be formed. Alternatively, with a margin, partition grooves 80 and 802 with widths of 0.5 μm or 1 μm can be formed. This allows for increased pixel density and / or a wider light-emitting area.

[0102] In the layer mask forming process of the partition groove forming process, the material of the lower layer film 51 is SiO ２ Instead of Al ２ O ３ oxides such as Al ２ O ３ As the material of the upper layer 52, Pt, Cr, etc. can be used instead of Ni.

[0103] The materials of the lower layer 51 and the upper layer 52 are combined so that the etching selectivity of the material of the lower layer 51 to the material of the upper layer 52 is 40 or more in the process of etching the layered mask 50. By using such a combination, the etching rate of the lower layer 51 relative to the upper layer 52 becomes sufficiently large. For example, when the upper layer 52 is made of Ni and the upper layer 52 is made of SiO ２ The etching selectivity of the lower layer 51 is about 50.

[0104] The material of the thin undercoat film 53 is In instead of ITO. ２ O ３ -SnO ２ (90-10wt%), AZO[ZnO:Al]-IZO[In ２ O ３Conductive oxides such as Ti—ZnO (90-10 wt %) can be used. Ni, Cr, etc. can be used as the material for the thin-film metal bonding layer 54 instead of Ti. The metal bonding layer 54 may be formed as needed, or may not be formed at all.

[0105] The thickness of the base film 53 and the metal bonding layer 54 may be within a range that allows the desired perpendicular partitioning grooves 80 and 802 to be formed, but the total thickness of the thin films is preferably 40 nm or less. In order to further suppress the influence of the base film 53 and the metal bonding layer 54, the thickness may be 25 nm or less, or 10 nm or less.

[0106] In the etching process of the partition groove forming process, the material of the fluoride gas used to remove the lower layer film 51, the metal bonding layer 54, and the base film 53 is CF ４ Instead of SF ６ , CHF ３ etc. can be used.

[0107] As shown in FIG. 11B, by forming the partitioning grooves 80 and 802, the sub-pixels 71B, 71G, and 71R of the pixel 70 are formed, and the pixel partitioning groove forming step S01 is completed.

[0108] By using this laminate mask, even when the laminate 30 does not include the third tunnel junction layer 314 and the fourth n-type layer 315 and the surface of the laminate 30 is the third p-type layer 313, it is possible to avoid adverse effects on electrical characteristics, such as high resistance, caused by damage to the third p-type layer 313. In cases such as when the laminate 30 includes the third tunnel junction layer 314 and the fourth n-type layer 315, the laminate mask may be configured to include only the lower film 51 and the upper film 52, omitting the thin-film base film 53 and the thin-film metal junction layer 54.

[0109] Next, in the pixel shape processing step S02, the dividing grooves 801 and the grooves for the conductive vias 32 are formed by multiple etchings. In the first example of the pixel shape processing step, the dividing grooves 801 and the grooves for the conductive vias 32 are formed sequentially in multiple steps by forming the shallower portions first and then additionally forming the difference in depth in the deeper portions. Dry etching using a mask is used to form the grooves.

[0110] 13 is an explanatory diagram of the first pixel shape processing step, which illustrates the AA cross section, the BB cross section, and the CC cross section of FIG. 4 shown in FIG.

[0111] For the sub-pixels 71B, 71G, and 71R shown in Figure 13(a), first, as a first depth etching process, grooves of the shallowest first depth are formed as shown in Figure 13(b), and grooves of deeper second and third depths are also formed up to the first depth.

[0112] That is, a mask patterned to form grooves corresponding to the first depth, second depth, and third depth is used to form the dividing groove 801R, the conductive via 32Rn, and the conductive via 32Gp, as well as grooves up to the first depth for the dividing groove 801G, the conductive via 32Gn, the conductive via 32Bp, the dividing groove 801B, and the conductive via 32Bn.

[0113] Next, as a second depth etching step, as shown in FIG. 13C, an additional depth equal to the difference between the first depth and the second depth is formed.

[0114] That is, using a mask patterned to add a depth that is the difference between the first depth and the second depth, the dividing groove 801G and the grooves for the conductive via 32Gn and the conductive via 32Bp are each added with a depth that is the difference between the first depth and the second depth of the dividing groove 801B and the conductive via 32Bn.

[0115] Next, as a third depth etching step, as shown in FIG. 13D, an additional depth equal to the difference between the second depth and the third depth is formed.

[0116] That is, a mask patterned to form additional grooves having a depth equal to the difference between the second depth and the third depth is used to form additional grooves having a depth equal to the difference between the second depth and the third depth of the dividing groove 801B and the conductive via 32Bn.

[0117] In this way, by additionally forming the differential depth, groove formation can be performed in a time-efficient manner. In other words, the etching time required to form all grooves in the pixel 70 is the same as the etching time required to form the groove of the third depth. Note that the order of the multi-stage process is not limited to forming the shallower portions first and then additionally forming the differential portions in the deeper portions. The differential portions in the deeper portions may be formed first, and then the shallower portions may be formed.

[0118] The mask used in the etching process may be made of a resin resist material, or may be made of a metal material such as Ni (nickel). For example, by using a 100 nm thick Ni (nickel) mask formed by sputtering, the mask is less likely to be damaged even when forming relatively deep grooves. Furthermore, after forming the grooves, the groove shape is measured, and if the depth is insufficient, additional grooves may be formed. When measuring this groove shape, the processed shape is measured with the mask still attached. Since the thickness of the mask is stable, the accuracy of reading the groove depth can be increased. A mask made of a metal material can be a mask that is the inverse of a mask made of a resin resist material.

[0119] In the etching process, Cl ２ The laminate 30 in the exposed region not covered by the mask layer is removed by dry etching using chlorine gas. At this time, the side surfaces of the dividing grooves 801 and the conductive vias 32 formed are inclined surfaces having a taper angle of about 10° to 30°.

[0120] Next, as a p-type activation annealing step S03, an RTA (Rapid Thermal Annealing) process is performed in a N ２ The annealing temperature is 725° C. and the annealing time is 30 minutes.

[0121] Next, in the insulating film forming step S04, a SiO 2 film is formed on the entire surface of the laminated body 30 on which the pixel partition grooves and pixel shape processing have been performed, except for the openings where the electrodes 31 and conductive vias 32 are to be formed. ２ The insulating film (passivation film) is formed by plasma CVD or sputtering to a thickness of about 250 nm.

[0122] Next, in the electrode formation step S05, electrodes 31 are formed on the upper surfaces of the light-emitting portions 72 and non-light-emitting portions 73 of the subpixels 71. The electrodes 31 are formed by laminating metal thin films by sputtering or vapor deposition. For example, the electrodes 31 may be laminated with Cr / Ni / Au layers having respective thicknesses of 10 nm / 20 nm / 170 nm. The positive electrode 31p and negative electrode 31n are formed simultaneously on the fourth n-type layer 315 using the same material and to the same thickness.

[0123] When forming this electrode 31, the conductive via 32 is formed at the same time. The conductive via 32 is formed by laminating the metal thin film of the electrode 31 in the groove of the conductive via 32 formed in the pixel shape processing step S02. The groove of the conductive via 32 has a tapered inclined surface that opens upward, so that a stable electrical connection can be easily achieved from the electrode 31 to the bottom surface of the conductive via 32.

[0124] The conductive vias 32 do not have to be formed simultaneously with the electrodes 31. They may be formed separately by plating or the like. In this case, the grooves of the conductive vias 32 may be completely filled with a conductive material.

[0125] In the method for manufacturing a semiconductor light-emitting device in this embodiment, pixels 70 each consisting of a large number of sub-pixels 71 can be manufactured in a batch on a sapphire substrate 10, which is an element substrate, in a state where the pixels 70 are arranged at intervals as in a display device.

[0126] Furthermore, in the semiconductor light emitting element of this embodiment, the width of the partitioning groove 80 can be narrowed to increase the effective area of ​​the pixels 70 and the sub-pixels 71. Meanwhile, the grooves forming the conductive vias 32 are formed such that the sides of the partitioning grooves are inclined relative to the stacking direction of the stack 30, thereby making it possible to easily and stably form the conductive vias 32.

[0127] The above-mentioned film thicknesses, processing conditions, etc. are not limited to the above values.

[0128] (Variation 1 of First Embodiment of Semiconductor Light-Emitting Device) Next, Variation 1 of the manufacturing method for the semiconductor light-emitting device of this embodiment will be described. In this example, the main difference from the semiconductor light-emitting device described above is the pixel shape processing step S02. In the pixel shape processing step S02 of the first embodiment, the dividing grooves 801 and the grooves of the conductive vias 32 are formed sequentially by starting with shallower portions and then additionally forming the difference in depth at deeper portions. In contrast, in the pixel shape processing step S02 of Variation 1, the dividing grooves 801 and the grooves of the conductive vias 32 are consistently formed, one groove at a time, with the same depth. As a result, for example, the groove of the deepest conductive via 32Bn has a continuous, smooth shape. Other components corresponding to those in the manufacturing method described above are assigned the same reference numerals, and their description will be omitted.

[0129] 14A and 14B are explanatory diagrams of the pixel shape processing step of Modification 1. First, in the first depth etching step, a mask having a pattern for forming a groove of the first depth is used to form a dividing groove 801R of the first depth, and grooves for the conductive vias 32Rn and 32Gp, as shown in FIG.

[0130] Next, as a second depth etching process, a mask patterned to form a groove of the second depth is used to form a dividing groove 801G of the second depth and grooves for the conductive vias 32Gn and 32Bp, as shown in FIG. 14(c).

[0131] Next, as a third depth etching process, a mask patterned to form a groove of the third depth is used to form a dividing groove 801B of the third depth and a groove for the conductive via 32Bn, as shown in FIG. 14(d).

[0132] The pixel shape processing step S02 of the first modification requires approximately twice the etching time compared to the pixel shape processing step S02 shown in Fig. 13. That is, the etching time required to form all the grooves in the pixel 70 includes the etching time required to form the grooves of the second depth and the etching time required to form the grooves of the first depth, in addition to the etching time required to form the grooves of the third depth.

[0133] However, when forming a fine shape by sequentially forming the difference as shown in Fig. 13, the positional deviation of the mask relative to the width of the groove may not be negligible. That is, there is a concern that the masks for forming grooves of each depth may be formed with significant positional deviation. This may result in a distorted groove shape or an inability to form a groove of the required depth.

[0134] For example, when forming a groove of the third depth by sequential formation, a step shape may occur on the side surface of the groove at the height of the first depth or the second depth. Alternatively, the depth of the groove may not reach the third depth. In contrast, the pixel shape processing step S02 of Modification 1 can form a groove without a step on the side surface at the portion corresponding to the first depth or the second depth. That is, in Modification 1, among multiple grooves of different depths, a groove deeper than the other grooves can have a continuous shape without a step on the side surface at the portion corresponding to the other depths. Specifically, for a groove of the second depth, the side surface at the portion corresponding to the first depth can have a continuous shape without a step in the depth direction, and for a groove of the third depth, the side surfaces at the portions corresponding to the first and second depths can have a continuous shape without a step in the depth direction.

[0135] The pixel shape processing step S02 of Modification 1 allows for the formation of grooves without steps to a predetermined depth, even when forming fine groove shapes. Furthermore, in the electrode formation step S05, conductive vias 32 that stably electrically connect the electrodes 31 to a predetermined n-GaN layer can be easily formed. The predetermined n-GaN layer refers to the n-type layer of the light-emitting unit layer 30R, 30G, or 30B corresponding to the emitted color, and the n-type layer via a tunnel junction layer above the light-emitting unit layer 30R, 30G, or 30B corresponding to the emitted color.

[0136] (Variation 2 of First Embodiment of Semiconductor Light-Emitting Device) Next, Variation 2 of the semiconductor light-emitting device of this embodiment will be described. In this example, the difference from the semiconductor light-emitting device described above is mainly in the pixel shape processing step S02. In the pixel shape processing step S02 of the first embodiment and Variation 1 thereof, the dividing groove 801 and the groove for the conductive via 32 were completed when the grooves reaching the predetermined n-type layer were simultaneously formed. In contrast, in the pixel shape processing step S02 of Variation 2, additional etching is performed only on the groove for the conductive via 32. As a result, in the same sub-pixel 71, the groove for the conductive via 32n in the non-light-emitting portion 73 is formed deeper than the dividing groove 801. Other configurations corresponding to those in the manufacturing method described above are assigned the same reference numerals, and descriptions thereof will be omitted.

[0137] 15A and 15B are explanatory diagrams of the pixel shape processing step S02 of Modification 2. Fig. 15A shows the state after the pixel shape processing step S02 of Modification 1 has been performed and before additional etching. Fig. 15B shows the state after additional etching has been performed only on the grooves of the conductive vias 32.

[0138] In the pixel shape processing step S02 of the second modification, as shown in Fig. 15(a), the simultaneous formation of grooves reaching a predetermined n-type layer is limited to the upper part of the predetermined n-type layer. Then, as shown in Fig. 15(b), only the grooves of the conductive vias 32 are slightly etched to the height of the center of the predetermined n-type layer. As a result, the dividing grooves 801 of the subpixels 71 are shallower than the conductive vias 32p of the light-emitting portions 72 of other subpixels 71, which have the same depth to the n-type layer as the dividing grooves 801.

[0139] That is, in the dividing groove 801G of the green-emitting subpixel 71G and the conductive via 32Bp of the light-emitting portion 72B of the blue-emitting subpixel 71B, which is a groove that reaches into the second n-type layer 306, the dividing groove 801G is a groove shallower than the conductive via 32Bp.

[0140] Furthermore, in the dividing groove 801R of the red-emitting subpixel 71R and the conductive via 32Gp of the light-emitting portion 72G of the green-emitting subpixel 71G, which are grooves that reach into the third n-type layer 310, the dividing groove 801R is shallower than the conductive via 32Gp.

[0141] In the pixel shape processing step S02 of the second modification, the dividing grooves 801 are shallow grooves that remain in the upper part of the n-type layer, thereby leaving the n-type layer thick. This suppresses an increase in resistance of the n-type layer that conducts current from the light-emitting portion 72 to the non-light-emitting portion 73. In addition, the grooves of the conductive vias 32 that reach the same n-type layer are made deeper than the dividing grooves 801, so that the conductive vias 32 can stably reach the n-type layer.

[0142] In this step, grooves of the same depth for another sub-pixel are simultaneously formed, so that grooves are formed to the same depth as the dividing grooves, down to the n-type layer, but shallower than the conductive vias in the light-emitting portions of the sub-pixels other than the sub-pixels. (Variation 3 of the First Embodiment of the Semiconductor Light-Emitting Device) Next, Variation 3 of the semiconductor light-emitting device of this embodiment will be described. What differs from the semiconductor light-emitting device and Variation 1 described above in this example is that the conductive vias on the non-light-emitting portion sides of the green-emitting and red-emitting sub-pixels are deepened so that they are deeper than the dividing grooves within the sub-pixels, and in the pixel shape processing step S02 in the manufacturing method.

[0143] 16A and 16B are explanatory diagrams of the pixel shape processing step of Modification Example 3. As shown in Fig. 16D, the conductive via 32Rn in the non-light-emitting portion 73R of the red-emitting sub-pixel 71R has a second depth. The conductive via 32Gn in the non-light-emitting portion 73G of the green-emitting sub-pixel 71G has a third depth.

[0144] First, in the first depth etching step, as shown in FIG. 16B, dividing grooves 801R of the first depth and grooves for the conductive vias 32Gp are formed.

[0145] Next, as a second depth etching step, as shown in FIG. 16C, dividing grooves 801G of the second depth and grooves for the conductive vias 32Rn and 32Bp are formed.

[0146] Next, in a third depth etching step, as shown in FIG. 16D, dividing grooves 801B of a third depth and grooves for the conductive vias 32Gn and 32Bn are formed.

[0147] The conductive vias 32n in the non-light-emitting portion 73 only need to reach the n-type layer of the specified light-emitting unit; deeper depths do not pose any problems. Therefore, the conductive vias 32n may reach the n-type layer of the light-emitting unit below the specified light-emitting unit. The thickness of the first n-type layer 302 is, for example, 2000 nm. Therefore, the grooves of the conductive vias 32Bn may be formed deep from the boundary between the first n-type layer 302 and the first light-emitting layer 303. (Variation 4 of the First Embodiment of the Semiconductor Light-Emitting Device) Next, Variation 4 of the semiconductor light-emitting device of this embodiment will be described. FIG. 17 is an explanatory diagram showing steps of a manufacturing method for Variation 4. Variation 4 differs from the first embodiment and the other variations described above in that, as shown in FIG. 17(a), the grooves of the conductive vias 32n (32Rn, 32Gn, 32Bn) in the non-light-emitting portion 73 are formed in the pixel partition groove forming step S01. In the pixel partition groove forming step S01, etching is performed using a stacked mask with vertical side surfaces. The grooves of the conductive vias 32 n are formed perpendicular to the mounting surface of the laminate 30 in the same manner as the partitioning grooves 80 , and have a depth that reaches the sapphire substrate 10 .

[0148] In the fourth modification, by forming a vertical groove, it is possible to form a groove with little influence of the groove taper, for example, with a taper angle of less than 10 degrees. This allows the groove of the deep conductive via 32n up to the third depth to be formed with a smaller diameter. Furthermore, since the grooves of the non-light-emitting portion 73 of the subpixel 71 and the conductive via 32n are formed using the same mask pattern, it is possible to obtain a semiconductor light-emitting element 1 in which the position of the conductive via 32n in the non-light-emitting portion 73 is stable. These are advantageous for forming grooves of small-sized conductive vias 32n that can fit into the non-light-emitting portion 73 of a limited size, for example, a width of 10 μm or less, in a high-definition micro LED.

[0149] 17 , in Modification 4, the groove of the conductive via 32n on the non-light-emitting portion side of the subpixel 71 is formed deep enough to reach the sapphire substrate 10. In the independent circuits of each light-emitting unit layer 30R, 30G, 30B, the path connecting the light-emitting portion side and non-light-emitting portion side of the subpixel 71 is the n-type layer 302, 306, 310 on the sapphire substrate 10 side of the light-emitting layer 303, 307, 312 of a predetermined light-emitting color. Even if the groove of the conductive via 32n is formed deeper than the n-type layer 302, 306, 310, the resulting change in the path can be ignored. Furthermore, the fact that the groove of the conductive via 32n on the non-light-emitting portion side of the subpixel 71 is formed deep enough to reach the sapphire substrate 10 does not lead to the emission of other light-emitting colors from the other light-emitting unit layers 30R, 30G, 30B. Furthermore, in the fourth modification, the grooves of the conductive vias 32n are formed simultaneously with the partitioning grooves 80 and 802 in the pixel partitioning groove forming step S01, so that no effort is required to form the grooves of the conductive vias 32n.

[0150] In the electrode formation step S05, in order to easily form the electrode 31 by stacking a metal thin film in the groove of the vertical conductive via 32n, it is desirable that the sapphire substrate 10 is positioned at a slight inclination from a vertical position with respect to the supply direction of the metal serving as the evaporation source. That is, the electrode material from the evaporation source is deposited on the opening at an angle greater than 0°. －１ By positioning the beam at an angle of incidence within a range of (2·r / d3) or less, a metal thin film can be deposited in the groove of the vertical conductive via 32n. Furthermore, the above conditions can be more easily achieved by using a deposition machine equipped with a substrate rotation mechanism that rotates the substrate on which the semiconductor light emitting device is mounted. Alternatively, by using sputtering instead of deposition, a metal thin film can be more easily deposited in the groove of the vertical conductive via 32n. As a result, even if the groove of the conductive via 32n has a surface perpendicular to the sapphire substrate 10, as in Modification 4, a stable electrical connection can be achieved, as if it had a tapered inclined surface that widens upward.

[0151] The grooves of the conductive vias 32n may be formed perpendicular to the mounting surface of the laminate 30 in a separate process from the pixel partition groove forming process S01. Even in this case, the grooves of the conductive vias 32n may be formed using the same laminate mask as that used in the pixel partition groove forming process S01. When the perpendicular grooves of the conductive vias 32n are formed in a separate process from the pixel partition groove forming process S01, the depth of the grooves of the conductive vias 32n may be shallower than the depth to which the grooves reach the sapphire substrate 10. (Variation 5 of the First Embodiment of the Semiconductor Light-Emitting Device) Next, Variation 5 of the semiconductor light-emitting device of this embodiment will be described. FIG. 18 is an explanatory diagram showing steps of a manufacturing method for Variation 5. Variation 5 differs from the manufacturing methods of the first embodiment and each of the variations described above in that the side surfaces of the dividing grooves 801 of the sub-pixels 71 and the grooves of the conductive vias 32p are formed perpendicular to the mounting surface of the laminate 30 in the pixel shape processing process S02.

[0152] In Modification 5, as shown in FIG. 18( a), similar to Modification 4 described above, grooves for conductive vias 32n (32Rn, 32Gn, 32Bn) in the non-light-emitting portion 73 are formed in the pixel partition groove forming step S01. In Modification 5, in the stacked body 30 in which the conductive vias 32n are formed, a dividing groove 801R of a first depth and grooves for conductive vias 32Gp are formed as shown in FIG. 18( b), a dividing groove 801G of a second depth and grooves for conductive vias 32Bp are formed as shown in FIG. 18( c), and a dividing groove 801B of a third depth is formed as shown in FIG. 18( d). As a result, the dividing grooves 801R and the grooves for conductive vias 32p are consistently formed for each groove of the same depth.

[0153] In the pixel shape processing step S02 of the fifth modification, the dividing grooves 801 and the grooves of the conductive vias 32p are formed using a laminate mask similar to that in the pixel partition groove forming step S01. This laminate mask is composed of a lower layer film and an upper layer film, and is combined so that the etching selectivity ratio of the material of the lower layer film to the material of the upper layer film is 40 or more. In the pixel shape processing step S02 of the fifth modification, the dividing grooves 801 and the grooves of the conductive vias 32p of various depths are formed by repeating the laminate mask forming step, etching step, and laminate mask removing step similar to those in the pixel partition groove forming step S01. As a result, the dividing grooves 801 and the grooves of the conductive vias 32p are formed as grooves perpendicular to the sapphire substrate 10, similar to the partition grooves 80.

[0154] In the fifth modification, all the dividing grooves 801 and the grooves of the conductive vias 32 have vertical sides with no inclination angle, so that even fine grooves with small inner diameters can be easily formed deep. That is, when r is the radius of the opening, d3 is the depth of the third depth, and θ is the inclination angle of the groove, tan －１ With a small diameter where (r / d3)≦θ, it is not possible to form a groove with a depth of the third depth, or the shape of the bottom surface becomes unstable. For example, in the configuration of the laminate 30 of this embodiment, if the radius of the opening is 1 μm, it is difficult to stably form a groove with a third depth of about 3 μm on an inclined surface with a taper angle of about 20°. In contrast, by setting θ≦10°, preferably θ≦5°, it is possible to form a third depth of 3 μm. In Modification 5, θ≦2° can be realized. In other words, θ≦(tan －１ (r / d3)) / 2, preferably θ≦(tan －１ By setting the ratio to (r / d3) / 4, it is possible to form deep grooves even if they are minute grooves with small inner diameters.

[0155] When forming grooves with small inner diameters reaching the second or third depth, it is preferable to combine this with a method of consistently forming grooves of the same depth in the pixel shape processing step S02, which is not affected by mask misalignment. In Modification 5, grooves of different depths may also be formed sequentially by additional etching. However, this may be affected by mask misalignment. [Semiconductor Light-Emitting Device of the First Embodiment] FIGS. 19 and 20 are cross-sectional views showing a semiconductor light-emitting device 100 according to this embodiment. FIGS. 19 and 20 correspond to the cross section of the partially enlarged front view of the mounting substrate 90 in FIG. 2. The semiconductor light-emitting element 1 in FIG. 19 corresponds to the A-A cross-section, B-B cross-section, and C-C cross-section in FIG. 5, and the semiconductor light-emitting element 1 in FIG. 20 corresponds to the D-D cross-section in FIG. 6.

[0156] In the semiconductor light-emitting device 100, as shown in Figures 19 and 20, the semiconductor light-emitting element 1 is mounted on the mounting substrate 90 with the electrodes 31 facing the mounting substrate 90. The mounting substrate 90 has an anode-side wiring 91 and a cathode-side wiring 93, which are at the same height on the mounting surface side, formed on a mounting substrate base 90A, and metal bumps 94 of the same thickness formed on each of them. The mounting substrate 90 is a CMOS (Complementary Metal Oxide Semiconductor) substrate whose base material is silicon. The mounting substrate 90 has functions such as switch control and current control.

[0157] The wiring 91 on the anode side and the wiring 93 on the cathode side of the mounting substrate 90 intersect while being electrically insulated from each other via an insulating layer 92. A protrusion 91a is formed on the wiring 91 on the anode side, and the heights of the surfaces on which the metal bumps 94 are formed on the anode side and the cathode side are aligned. The wiring 91, the protrusion 91a, and the wiring 93 are made of highly electrically conductive materials such as Cu (copper) or Au (gold). The metal bumps 94 are made of, for example, Au (gold).

[0158] The semiconductor light emitting element 1 is mounted on the mounting substrate 90 by thermocompression bonding at, for example, 300° C. At this time, the electrodes 31 of the semiconductor light emitting element 1 are the same height, the wiring 91 and wiring 93 of the mounting substrate 90 are the same height, and the metal bumps 94 have the same thickness. This makes it easy to apply a uniform force to each metal bump 94, and the multiple metal bumps 94 can be uniformly crushed, resulting in stable electrical connection.

[0159] The metal bumps 94 may be made of a bonding material such as a eutectic material, such as AuSn (gold-tin alloy), which is melted and bonded. In this case, it is necessary not only to electrically connect the electrode 31 of a given semiconductor light-emitting element 1 to the wiring 91 or wiring 93 of the mounting substrate 90, but also to control the bonding material to prevent overflow and prevent unintended electrical connections. The semiconductor light-emitting element 1 and semiconductor light-emitting device 100 of the present disclosure can easily apply a controlled, uniform force to each metal bump 94, making them suitable for such bonding.

[0160] When a bonding material that melts and bonds is used, the self-alignment effect due to the surface tension when the bonding material melts can be utilized by approximating the shapes of the electrode 31 of the semiconductor light emitting element 1 and the corresponding wiring 91 or wiring 93 of the mounting substrate 90. Furthermore, it is easy to bring the entire surface of the electrode into contact with the bonding material, and the physical bond can also be made strong.

[0161] In the semiconductor light emitting device of this embodiment, a semiconductor light emitting element having a plurality of electrodes formed on a mounting surface at the same height is mounted on a mounting substrate having a mounting surface at the same height. Therefore, a semiconductor light emitting device in which a semiconductor light emitting element is stably mounted can be obtained by using a mounting substrate having a stable mounting surface without using a mounting substrate with a complex configuration that is time-consuming to manufacture.

[0162] (First Modification of the First Embodiment of the Semiconductor Light-Emitting Device) FIG. 21 is a schematic partial cross-sectional view of a first modification of the semiconductor light-emitting device of this embodiment.

[0163] The semiconductor light emitting device 100A of Modification 1 does not have the sapphire substrate 10 of the semiconductor light emitting device 100 shown in Fig. 19. That is, the semiconductor light emitting device 100A of Modification 1 is manufactured by mounting the semiconductor light emitting element 1 on a mounting substrate 90 and then performing a lift-off process of lifting off the sapphire substrate 10 from the semiconductor light emitting element 1. As a result, the semiconductor light emitting device 100A has the sub-pixels 71 of each color arranged on the mounting substrate 90 in a completely separated and independent state.

[0164] When removing the sapphire substrate 10 of the semiconductor light-emitting element 1, the semiconductor light-emitting element 1 is mounted on the mounting substrate 90, and then the sapphire substrate 10 is peeled off, for example, by laser irradiation. The sub-pixels 71 of each color are several μm thick, and in order to prevent damage to the sub-pixels 71 of each color when the sapphire substrate 10 is removed, sufficient support for the semiconductor light-emitting element 1 is required. The semiconductor light-emitting element 1 of the present disclosure is suitable for this purpose.

[0165] In particular, by using a bonding material that melts and bonds, and by bringing the entire surface of the electrode into contact with the bonding material, and then removing the sapphire substrate 10, damage to the sub-pixels 71 can be suppressed.

[0166] The semiconductor light emitting device 100A can suppress interference of light with other pixels 70 via the sapphire substrate 10. This can suppress spurious lighting.

[0167] (Modification 2 of Semiconductor Light-Emitting Device of First Embodiment) FIG. 22 is a schematic partial cross-sectional view of Modification 2 of the semiconductor light-emitting device of this embodiment.

[0168] The semiconductor light emitting device 100B of the second modification includes a light absorbing member 40 between each of the sub-pixels 71 of the semiconductor light emitting device 100 shown in FIG. 19, and further includes no sapphire substrate 10.

[0169] In the semiconductor light emitting device 100B of the second modification, the sapphire substrate 10 is peeled off in a state in which the semiconductor light emitting element 1 is supported not only by the mounting substrate 90 but also by the light absorbing member 40. Therefore, damage to the sub-pixels 71 can be suppressed.

[0170] The light absorbing member 40 may be made of a material that absorbs the light emitted by the semiconductor light emitting element 1, such as a metal complex dye, black silicone resin, black epoxy resin, or black paint, thereby suppressing optical interference with other pixels 70 and preventing spurious lighting.

[0171] (Variation 6 of the first embodiment of the semiconductor light-emitting element, Variation 3 of the first embodiment of the semiconductor light-emitting device) Figure 23 is a cross-sectional view in the Y direction of each pixel of Variation 6 of the semiconductor light-emitting element of this embodiment, and Figure 24 is a schematic partial cross-sectional view of Variation 3 of the semiconductor light-emitting device of this embodiment.

[0172] 6 , the partition grooves 802 of the sub-pixels 71 reach the sapphire substrate 10, whereas the partition grooves 802 of the sub-pixels 71 do not reach the sapphire substrate 10. In the semiconductor light-emitting device 100C of Modification 3, the semiconductor light-emitting element 1 of Modification 6 is mounted on a mounting substrate 90, and the sapphire substrate 10 is removed.

[0173] In the semiconductor light-emitting element 1 of Modification 4, when the sapphire substrate 10 is removed, the pixels 70 are independent, but the sub-pixels 71, i.e., the red-emitting sub-pixel 71R, the green-emitting sub-pixel 71G, and the blue-emitting sub-pixel 71B, maintain an integral structure with the first buffer layer 301 and the like being continuous. Therefore, the semiconductor light-emitting element 1 of Modification 4 is less susceptible to damage when the sapphire substrate 10 is peeled off.

[0174] Furthermore, when the sapphire substrate 10 is peeled off, the pixels 70 become independent in the medium of the laminate 30 having a refractive index of 2 or more. Meanwhile, the sub-pixels 71 of each color within the pixel 70 maintain an integral structure. Therefore, the color mixing of the light of multiple colors emitted from the sub-pixels 71 of each color within the pixel 70 is enhanced.

[0175] 25, the partitioning groove 80 may be provided with a light absorbing member 40 that absorbs light generated from the light emitting layer. This configuration improves support and prevents light from reaching adjacent pixels, thereby suppressing false lighting. Note that, in order to improve color mixing, it is possible to not dispose a light absorbing member in the partitioning groove 802.

[0176] Furthermore, the material, installation method, and effects of the light absorbing member 40 are not limited to this configuration.

[0177] (Fourth Modification of the First Embodiment of the Semiconductor Light-Emitting Device) As shown in FIG. 26 , a semiconductor light-emitting device 100 of the fourth modification includes a mounting substrate 90 and twelve semiconductor light-emitting elements 2. The semiconductor light-emitting device 100 is an intermediate structure for an LED-equipped display product. The semiconductor light-emitting elements 2 are mounted on the mounting substrate 90. The mounting substrate 90 includes a circuit for driving pixels 70 (described later) of the semiconductor light-emitting elements 2. The mounting substrate 90 is a CMOS substrate using silicon as a base material. The mounting substrate 90 includes a mounting region 90a on which twelve semiconductor light-emitting elements 2 are mounted. A plurality of pixels 70 are arranged in the mounting region 90a. The plurality of pixels 70 are regularly arranged at equal intervals in each of the X direction and the Y direction. The X direction and the Y direction are each parallel to the main surface of the mounting substrate 90. The X direction is perpendicular to the Y direction. The number of the plurality of pixels 70 arranged in the mounting region 90a is, for example, 320 pixels in the X direction and 240 pixels in the Y direction.

[0178] 26 , the mounting area 90a is partitioned into multiple mounting sections 90b. One semiconductor light emitting element 2 has the same number of pixels as one mounting section 90b. For example, the mounting area 90a has 320 pixels in the X direction and 240 pixels in the Y direction, whereas the semiconductor light emitting element 2 has 80 pixels in the X direction, which is obtained by dividing the 320 pixels into four, and 80 pixels in the Y direction, which is obtained by dividing the 240 pixels into thirds.

[0179] In Modification 4, the semiconductor light emitting device 100 does not include the element substrate 10. In Modification 4, the semiconductor light emitting device 100 is manufactured as follows: After mounting the semiconductor light emitting element 2 on the mounting substrate 90, the element substrate 10 is removed from this semiconductor light emitting element 2. Thereafter, the next semiconductor light emitting element 2 is mounted in the adjacent mounting section 90b, and the element substrate 10 is removed from this semiconductor light emitting element 2.

[0180] Next, we will explain the mounting of the semiconductor light emitting element 2 in Modification 4. In Modification 4, one semiconductor light emitting element 2 is mounted in each of the 12 mounting sections 90b of the mounting substrate 90 shown in Fig. 26. Before mounting, the electrical and optical characteristics of the semiconductor light emitting elements 2 are measured, and semiconductor light emitting elements 2 with a high yield rate are selected.

[0181] 27A, one semiconductor light-emitting element 2 is mounted in a first mounting section 90b_1, which is one of the mounting sections 90b. The orientation of the semiconductor light-emitting element 2 is such that the multiple pixels 70 face the mounting substrate 90. In plan view, the pixel formation region 2A fits within and substantially overlaps the first mounting section 90b_1. In plan view, the non-pixel formation region 2B extends outside the first mounting section 90b_1.

[0182] A positive electrode 92p and a negative electrode 92n are formed on the mounting substrate 90 corresponding to each pixel 70. When the semiconductor light-emitting element 2 is mounted, the positive electrode 92p is connected to the positive electrode 31p via a metal bump, and the negative electrode 92n is connected to the negative electrode 31n via a metal bump. Note that in Figure 27, the number of pixels is omitted and the semiconductor light-emitting element 2 is shown as having five pixels. Furthermore, the number of mounting sections 90b is omitted and the mounting substrate 90 is shown as having two mounting sections 90b.

[0183] (ii) Next, as shown in Fig. 27(b), the element substrate 10 is removed from the semiconductor light-emitting element 2 mounted in (i) above. Methods for removing the element substrate 10 include laser lift-off and immersing the semiconductor light-emitting element 2 in water. When the semiconductor light-emitting element 2 is immersed in water, the buffer layer 301 dissolves, and the element substrate 10 is separated from the pixels 70. When the element substrate 10 is removed, part or all of the buffer layer 301 is also separated from the pixels 70.

[0184] (iii) Next, as shown in Fig. 27(c), another semiconductor light-emitting element 2 is newly mounted in a second mounting section 90b_2, which is one of the mounting sections 90b. The second mounting section 90b_2 is the mounting section 90b adjacent to the first mounting section 90b_1. The method for mounting the other semiconductor light-emitting element 2 is the same as the method for mounting the semiconductor light-emitting element 2 in (i) above.

[0185] In plan view, the non-pixel formation region 2B of the semiconductor light emitting element 2 mounted in (iii) fits within and nearly overlaps the first mounting section 90b_1. However, in (ii) above, the element substrate 10 is removed from the semiconductor light emitting element 2 mounted in (i) above. Therefore, even if the non-pixel formation region 2B extends into the adjacent mounting section 90b, the element substrate 10 of the semiconductor light emitting element 2 mounted in (i) above does not interfere with the element substrate 10 of the semiconductor light emitting element 2 mounted in (iii) above.

[0186] (iv) Next, as shown in FIG. 27(d), the element substrate 10 is removed from the semiconductor light emitting element 2 mounted in (iii) above.

[0187] Similarly, from step (v) onwards, new semiconductor light emitting elements 2 are mounted in other mounting sections 90b adjacent to the mounting section 90b in which the semiconductor light emitting elements 2 have already been mounted, and the process of removing the element substrate 10 from the new semiconductor light emitting elements 2 is repeated. Eventually, pixels 70 are mounted in all of the mounting sections 90b. Through the above steps, the semiconductor light emitting device 100 is completed.

[0188] According to the fourth modification, the following effects can be obtained.

[0189] In the present disclosure, a plurality of semiconductor light emitting elements 2 are mounted corresponding to a plurality of mounting sections 90b obtained by partitioning the mounting area 90a. The mounted semiconductor light emitting elements 2 have been selected through prior characteristic confirmation and have a high yield rate. Furthermore, the mounted semiconductor light emitting elements 2 have sizes corresponding to each of the plurality of mounting sections 90b obtained by partitioning the mounting area 90a. Therefore, the yield rate of pixels 70 in the semiconductor light emitting device 100 can be increased compared to when a single semiconductor light emitting element 1 is mounted to cover the entire mounting area 90a.

[0190] That is, it is not easy to consistently produce good pixels 70 in one semiconductor light-emitting element 2 corresponding to the entire mounting area 90a, and there are often partially defective pixels 70. To address this, semiconductor light-emitting elements 2 with a high yield rate are selected to correspond to the partitioned mounting area 90b. Then, using the selected plurality of semiconductor light-emitting elements 2, the entire mounting area 90a can be configured with pixels 70 with a high yield rate.

[0191] Furthermore, in the present disclosure, a semiconductor light emitting element 2 is mounted in each of the multiple mounting sections 90b included in the mounting area 90a. Therefore, the dimensions of each semiconductor light emitting element 2 are smaller than when a single semiconductor light emitting element 2 is mounted over the entire mounting area 90a. This reduces the degree of warping of the semiconductor light emitting element 2. Furthermore, the influence of the difference in thermal expansion between the mounting substrate 90 and the semiconductor light emitting element 2 is also reduced. As a result, when the semiconductor light emitting element 2 is mounted, the physical bonding and electrical connection between the pixel 70 and the mounting substrate 90 can be stabilized. This allows for an increased yield rate of the pixels 70 in the semiconductor light emitting device 100.

[0192] Furthermore, in the present disclosure, after a semiconductor light emitting element 2 is mounted in the first mounting section 90b_1, the element substrate 10 is removed from the semiconductor light emitting element 2. Thereafter, another semiconductor light emitting element 2 is mounted in the second mounting section 90b_2 adjacent to the first mounting section 90b_1. Therefore, in the adjacent mounting sections 90b, there is no interference between the semiconductor light emitting elements 2 due to the element substrate 10 when they are mounted, making it easy to densely mount multiple semiconductor light emitting elements 2. This allows for efficient manufacture of semiconductor light emitting devices 100 with a high yield rate of pixels 70.

[0193] Furthermore, in the present disclosure, the non-pixel formation region 2B of the semiconductor light emitting element 2 can be made larger than the arrangement interval of the pixels 70. This makes it possible to manufacture the semiconductor light emitting device 100 by mounting a plurality of semiconductor light emitting elements 2, even if the arrangement interval of the pixels 70 is narrower than the dimensional accuracy of the shape processing when the semiconductor light emitting element 2 is divided into high-definition semiconductor light emitting devices 100.

[0194] Furthermore, since the heights of the electrodes of the plurality of pixels 70 are the same and the heights of the plurality of electrodes of the mounting substrate 90 are the same, stable mounting is possible. This allows the element substrate 10 to be removed stably.

[0195] (Variation 5 of First Embodiment of Semiconductor Light Emitting Device) In the above-described variation 4, as shown in FIG. 27(d), the mounting section 90b is continuous and in contact with other adjacent mounting sections 90b.

[0196] In contrast, in Modification 5, as shown in Figures 28(a) and 28(b), a non-mounting section 90c is provided between two adjacent mounting sections 90b. No pixels 70 are mounted in the non-mounting section 90c. In a plan view, the non-mounting section 90c is provided so as to surround the periphery of each mounting section 90b.

[0197] When one semiconductor light emitting element 2 is mounted in one mounting section 90b, in a plan view, the semiconductor light emitting element 2 overlaps the non-mounting section 90c but does not overlap other adjacent mounting sections 90b.

[0198] In addition, in variant example 4, after mounting a semiconductor light-emitting element 2 in one mounting section 90b, the element substrate 10 is removed from that semiconductor light-emitting element 2, and then another semiconductor light-emitting element 2 is mounted in another adjacent mounting section 90b.

[0199] In contrast, in Modification 5, there is no limitation on the timing for removing the element substrate 10 from the semiconductor light emitting element 2. For example, after the semiconductor light emitting elements 2 are mounted in all of the mounting sections 90b, the element substrate 10 can be removed from each of the semiconductor light emitting elements 2. Note that the element substrate 10 does not necessarily have to be removed.

[0200] As described above, the semiconductor light-emitting element 2 that has been previously mounted does not overlap with other adjacent mounting sections 90b in a planar view, so that other semiconductor light-emitting elements 2 can be mounted in other adjacent mounting sections 90b without removing the element substrate 10 from the semiconductor light-emitting element 2 that has been previously mounted.

[0201] 28B, in a plan view, an optical element 95 is mounted on the mounted pixels 70 in an area spanning the non-mounting section 90c and the adjacent mounting section 90b. The optical element 95 is a lens or a prism that generates a virtual image of a plurality of pixels regularly arranged at equal intervals.

[0202] The optical element 95 refracts the light 97 emitted by the pixel 70. As a result, the path of the light 97 emitted from the optical element 95 becomes the same as the path of the light 97 when all the pixels 70 are arranged at equal intervals on the mounting substrate 90.

[0203] The fifth modification described above in detail provides the same effects as the fourth modification described above, and further provides the following effects.

[0204] In the manufacturing method of Modification 5, there is no limitation on the timing for removing the element substrate 10 from the semiconductor light emitting element 2. Therefore, there is a high degree of freedom in the process for manufacturing the LED device 1. Even if the non-mounting portion 90c exists, by providing the optical element 95, the path of the light 97 emitted from the optical element 95 can be made the same as the path of the light 97 when all the pixels 70 are mounted at equal intervals on the mounting substrate 90.

[0205] (Seventh Modification of the First Embodiment of the Semiconductor Light Emitting Device, and Sixth Modification of the First Embodiment of the Semiconductor Light Emitting Device) Figures 29 and 30 show a seventh modification of the semiconductor light emitting device, and Figure 31 shows a sixth modification of the semiconductor light emitting device. Figure 29 corresponds to the A-A cross section, the B-B cross section, and the C-C cross section of Figure 4, and illustrates electrodes 31p and 31n facing downward.

[0206] 29 , the semiconductor light-emitting element 3 of Variation 7 differs in that the multiple sub-pixels 71 emitting different colors of light are composed of a sub-pixel 71R formed of a single light-emitting unit layer and sub-pixels 71B and 71G formed of two light-emitting unit layers. In Variation 7 of the semiconductor light-emitting element 3, the blue sub-pixel 71B and the green sub-pixel 71G are formed of two light-emitting unit layers, and the red sub-pixel 71R is formed of a single light-emitting unit layer. The blue and green sub-pixels 71B and 71G are formed in different semiconductor light-emitting elements 3BG and 3R, respectively. The blue and green sub-pixels 71B and 71G are formed in the semiconductor light-emitting element 3BG, and the red sub-pixel 71R is formed in the semiconductor light-emitting element 3R.

[0207] 29 , the blue subpixel 71B includes a stacked body 30. The stacked body 30 includes a buffer layer 301, an emitting unit layer 30B, a tunnel junction layer 305, an emitting unit layer 30G, a tunnel junction layer 314, and an n-type layer 315.

[0208] The dividing groove 801B that separates the light-emitting portion 72B and the non-light-emitting portion 73B has a depth that reaches the first n-type layer 302 of the light-emitting unit layer 30B, and divides the first light-emitting layer 303 of the light-emitting unit layer 30B. The conductive via 32Bn of the non-light-emitting portion 73B has a depth that reaches the first n-type layer 302.

[0209] A conductive via 32Bp is also formed in the light emitting portion 72B. The conductive via 32Bp of the light emitting portion 72B is formed in a slit shape having a longitudinal side and a lateral side. The conductive via 32Bp of the light emitting portion 72B has a depth reaching the second n-type layer 306. The conductive via 32Bp has a tapered shape that narrows as it approaches the bottom of the conductive via 32Bn.

[0210] The configuration of this blue subpixel 71B forms an electrical circuit that causes the first light-emitting layer 303 of the light-emitting unit layer 30B to emit light. That is, an electrical circuit is formed that runs from the positive electrode 31p to the negative electrode 31n via the conductive via 32Bp, the second n-type layer 306, the tunnel junction layer 305, the first p-type layer 304, the first light-emitting layer 303, the first n-type layer 302, and the conductive via 32Bn. The blue subpixel 71B corresponds to the subpixel 71 that has two light-emitting unit layers.

[0211] 29 , the green subpixel 71G has a stack 30 with the same configuration as the blue subpixel 71B. The dividing groove 801G, which separates the light-emitting portion 72G and the non-light-emitting portion 73G, has a depth that reaches the second n-type layer 306 of the light-emitting unit layer 30G and divides the second light-emitting layer 307 of the light-emitting unit layer 30G. The conductive via 32Gn of the non-light-emitting portion 73G has a depth that reaches the second n-type layer 306.

[0212] This configuration of the green sub-pixel 71G forms an electrical circuit that causes the second light-emitting layer 307 of the light-emitting unit layer 30G to emit light. That is, an electrical circuit is formed that runs from the positive electrode 31p to the negative electrode 31n via the n-type layer 315, the tunnel junction layer 314, the second p-type layer 308, the second light-emitting layer 307, the second n-type layer 306, and the conductive via 32Gp. The green sub-pixel 71G corresponds to the sub-pixel 71 that has two light-emitting unit layers.

[0213] 29, the red subpixel 71R includes a stacked body 30. The stacked body 30 includes a buffer layer 301, an emitting unit layer 30R, a tunnel junction layer 314, and an n-type layer 315.

[0214] The dividing groove 801R, which separates the light-emitting portion 72R and the non-light-emitting portion 73R, has a depth reaching the third n-type layer 310 and divides the third light-emitting layer 312 of the light-emitting unit layer 30R. A conductive via 32Rn is formed in the non-light-emitting portion 73R. The conductive via 32Rn has a depth reaching the third n-type layer 310.

[0215] This configuration of the light-emitting unit layer 30R forms an electrical circuit that causes the third light-emitting layer 312 to emit light. That is, an electrical circuit is formed that extends from the positive electrode 31p to the negative electrode 31n via the n-type layer 315, the tunnel junction layer 314, the third p-type layer 313, the third light-emitting layer 312, the second buffer layer 311, the third n-type layer 310, and the conductive via 32Rn. The red sub-pixel 71R corresponds to the sub-pixel 71 that has a single light-emitting unit layer.

[0216] 30 , the semiconductor light emitting element 3BG includes an element substrate 10, a plurality of blue sub-pixels 71B, and a plurality of green sub-pixels 71G. The plurality of blue sub-pixels 71B and the plurality of green sub-pixels 71G are arranged on one surface of the element substrate 10. The orientation of the blue sub-pixels 71B and the green sub-pixels 71G relative to the element substrate 10 is such that the buffer layer 301 is in contact with the element substrate 10. The arrangement of the plurality of blue sub-pixels 71B and the plurality of green sub-pixels 71G on the element substrate 10 is the same as the arrangement on the mounting substrate 90.

[0217] In the semiconductor light emitting element 3BG, the blue sub-pixels 71B are arranged in a row along the Y direction. The rows of the blue sub-pixels 71B are arranged periodically and repeatedly at intervals in the X direction. The intervals between the blue sub-pixels 71B in the X and Y directions are the same as the intervals on the mounting substrate 90.

[0218] In the semiconductor light emitting element 3BG, the green sub-pixels 71G are arranged in a row along the Y direction. The rows of the green sub-pixels 71G are arranged periodically and repeatedly at intervals in the X direction. The intervals between the green sub-pixels 71G in the X and Y directions are the same as the intervals on the mounting substrate 90.

[0219] In the semiconductor light emitting element 3BG, the relative position of the green sub-pixel 71G with respect to the blue sub-pixel 71B is the same as that in the semiconductor light emitting element 1.

[0220] Although not shown in the figure, the semiconductor light emitting element 3R includes an element substrate 10 and a plurality of red sub-pixels 71R. The plurality of red sub-pixels 71R are arranged on one surface of the element substrate 10. The orientation of the red sub-pixels 71R relative to the element substrate 10 is such that the buffer layer 301 is in contact with the element substrate 10. The arrangement of the plurality of red sub-pixels 71R on the element substrate 10 is the same as the arrangement on the mounting substrate 90.

[0221] In the semiconductor light-emitting element 3R, the red sub-pixels 71R are arranged in a row along the Y direction. The rows of the red sub-pixels 71R are arranged periodically and repeatedly at intervals in the X direction. The intervals between the red sub-pixels 71R in the X and Y directions are the same as the intervals on the mounting substrate 90.

[0222] Here, the mounting of the semiconductor light emitting elements 3BG and 3R will be described.

[0223] First, the electrical and optical characteristics of the semiconductor light emitting elements 3BG and 3R are measured to confirm whether the semiconductor light emitting elements 3BG and 3R are non-defective.

[0224] 31A, the semiconductor light emitting element 3R that has been confirmed to be a non-defective is placed in a mounting area 90a of a mounting substrate 90. The multiple red sub-pixels 71R of the semiconductor light emitting element 3R are oriented in an array on the mounting substrate 90. The multiple red sub-pixels 71R are also placed at positions of the positive electrodes 92p, negative electrodes, and metal bumps on the mounting substrate 90 that correspond to each of the red sub-pixels 71R. The reason for mounting the semiconductor light emitting element 3R first is that the thickness of the stack 30 of the semiconductor light emitting element 3R is thinner than the thickness of the stack 30 of the semiconductor light emitting element 3BG.

[0225] Next, the arranged semiconductor light emitting element 3R is pressurized and heated, thereby bonding the positive electrode 31p and negative electrode 31n of each red sub-pixel 71R to the positive electrode 92p and negative electrode 92n of the mounting substrate 90 via the metal bumps. In this manner, the semiconductor light emitting element 3R is mounted on the mounting substrate 90.

[0226] 31(b), the element substrate 10 is removed from the semiconductor light-emitting element 3R. Methods for removing the element substrate 10 include laser lift-off and immersing the semiconductor light-emitting element 3R in water. When the semiconductor light-emitting element 3R is immersed in water, the buffer layer 301 dissolves, causing the element substrate 10 to separate from the red sub-pixel 71R. When the element substrate 10 is removed, part or all of the buffer layer 301 is also separated from the red sub-pixel 71R.

[0227] 31(c), the semiconductor light-emitting element 3BG that has been confirmed to be a non-defective product is placed in the mounting area 90a of the mounting substrate 90. At this time, the positions at which the blue sub-pixel 71B and the green sub-pixel 71G are mounted are shifted in the X direction compared to the previously mounted red sub-pixel 71R.

[0228] Since the heights of the blue sub-pixel 71B and the green sub-pixel 71G are greater than the height of the red sub-pixel 71R, the element substrate 10 of the semiconductor light emitting element 3BG is unlikely to come into contact with the red sub-pixel 71R.

[0229] Next, the arranged semiconductor light emitting element 3BG is pressurized and heated, thereby bonding the positive electrode 31p and negative electrode 31n of each blue sub-pixel 71B and each green sub-pixel 71G to the positive electrode 92p and negative electrode 92n of the mounting substrate 90 via the metal bumps. In this manner, the semiconductor light emitting element 3BG is mounted on the mounting substrate 90.

[0230] 31(d), the element substrate 10 is removed from the semiconductor light emitting element 3BG by the same method as that for the semiconductor light emitting element 3R. Through the above steps, the red sub-pixel 71R, the blue sub-pixel 71B, and the green sub-pixel 71G are mounted on the mounting substrate 90, and the semiconductor light emitting device 100 is completed.

[0231] The manufacturing method of the semiconductor light-emitting device 100 described above involves mounting a semiconductor light-emitting element 3 having one or two of the blue sub-pixel 71B, green sub-pixel 71G, and red sub-pixel 71R in the mounting region 90a, and then removing the element substrate 10, and repeating this process multiple times until the blue sub-pixel 71B, green sub-pixel 71G, and red sub-pixel 71R are mounted on the mounting substrate 90. The emitted color of the sub-pixels 71 of the semiconductor light-emitting element 3 used varies with each process.

[0232] Next, the effects of the semiconductor light-emitting element variation 7 and the semiconductor light-emitting device variation 6 will be described. When light-emitting unit layers emitting different light colors are stacked, stress effects due to differences in lattice spacing may occur. In particular, since the difference in lattice spacing between the blue light-emitting unit layer 30B and the red light-emitting unit layer 30R is large, when the blue light-emitting unit layer 30B and the red light-emitting unit layer 30R are stacked, stress effects due to the difference in lattice spacing are more likely to occur.

[0233] According to the semiconductor light-emitting device 100 of the present disclosure, the plurality of subpixels emitting different colors of light include a subpixel 71 formed of a single light-emitting unit layer and a subpixel 71 formed of two light-emitting unit layers. The subpixel 71 formed of two light-emitting unit layers is a combination of a blue light-emitting unit layer 30B and a green light-emitting unit layer 30G. Therefore, the blue light-emitting unit layer 30B and the red light-emitting unit layer 30R, which have a large difference in lattice spacing between the light-emitting layers, are not stacked. As a result, there is no effect from the difference in lattice spacing between the blue light-emitting unit layer 30B and the red light-emitting unit layer 30R. This allows the electrical and optical characteristics to be maintained at a good level.

[0234] These features enable the semiconductor light emitting device 100 to maintain good electrical and optical characteristics, thereby reducing the technical difficulty of forming sub-pixels 71 of multiple emitted colors.

[0235] Furthermore, according to the semiconductor light emitting device 100 of the present disclosure, many pixels 70 can be formed and mounted collectively by mounting the semiconductor light emitting element 3, on which multiple sub-pixels 71 are formed, on the mounting substrate 90, thereby enabling efficient manufacturing. Therefore, the semiconductor light emitting device 100 of the present disclosure can reduce the technical difficulty of forming sub-pixels 71 of multiple emitted colors.

[0236] 29 illustrates an example in which the blue sub-pixel 71B and the green sub-pixel 71G are formed with two light-emitting unit layers, and the red sub-pixel 71R is formed with a single light-emitting unit layer. However, a configuration in which the green sub-pixel 71G and the red sub-pixel 71R are formed with two light-emitting unit layers, and the blue sub-pixel 71B is formed with a single light-emitting unit layer, may also be used. Forming light-emitting unit layers with approximately the same generation temperature in separate sub-pixels makes it easier to maintain good electrical and optical characteristics. [Second Embodiment] Hereinafter, a second embodiment of a semiconductor light-emitting element and a semiconductor light-emitting device, as well as a manufacturing method thereof, according to the present disclosure will be described with reference to the drawings. The semiconductor light-emitting element of the second embodiment differs from the semiconductor light-emitting element of the first embodiment mainly in that the electrodes on the light-emitting portion side and the electrodes on the non-light-emitting portion side are formed on surfaces at different heights.

[0237] In the semiconductor light emitting device of the first embodiment, the electrode on the light emitting portion side and the electrode on the non-light emitting portion side are formed on the same surface, whereas in the semiconductor light emitting device of the second embodiment, the non-light emitting portion of the subpixel is etched to a height of a first depth, and the electrode on the non-light emitting portion side is formed there.

[0238] Accordingly, the corresponding mounting substrates are different, and the configuration of the semiconductor light emitting device is also different.

[0239] 32 and 33 are explanatory views of the pixel shape processing step S02 of the semiconductor light emitting element in this embodiment. Fig. 34 is a cross-sectional view showing the semiconductor light emitting device in this embodiment. In this embodiment, components corresponding to those in the first embodiment described above are assigned the same reference numerals, and descriptions thereof will be omitted.

[0240] First, as a first-depth etching step, as shown in FIG. 32(b), a portion corresponding to the non-light-emitting portion 73 of the sub-pixel 71 is etched to a height of a first depth to form a mesa structure. As a result, cathode recesses 77R, 77G, and 77B, which are cutouts in the electrode surface, are formed in the sub-pixel 71. Next, as a first-depth etching step, as shown in FIG. 32(c), grooves for the conductive vias 32Gp are formed. Note that the mesa structure and the grooves for the conductive vias 32Gp may be formed simultaneously in a single step.

[0241] Next, as a second depth etching step, a dividing groove 801G and a groove for the conductive via 32Gn are formed as shown in Fig. 33(d). Next, as a second depth etching step, a groove for the conductive via 32Bp is formed as shown in Fig. 33(e).

[0242] Next, as a third deep etching step, as shown in FIG. 33(f), dividing grooves 801B and grooves for conductive vias 32Bn are formed.

[0243] In the semiconductor light-emitting element 1 fabricated in this manner, the electrodes 31p on the light-emitting portion 72 side of the sub-pixels 71 of each color are formed to the same height. Also, the electrodes 31n on the non-light-emitting portion 73 side of the sub-pixels 71 of each color are formed to the same height. However, the light-emitting portions 72 have a convex shape by the height of the first depth relative to the non-light-emitting portions 73. Therefore, the electrodes 31p on the light-emitting portion 72 side and the electrodes 31n on the non-light-emitting portions 73 side are formed to have different heights by the height of the first depth.

[0244] As shown in FIGS. 32 and 33, in the semiconductor light emitting device 100 of this embodiment, the semiconductor light emitting element 1 is mounted on a mounting substrate 90 so that the electrodes 31 face the mounting substrate.

[0245] 34 , in the semiconductor light emitting device 100, the semiconductor light emitting element 1 is mounted on the mounting substrate 90 with the electrodes 31 facing the mounting substrate 90. The mounting substrate 90 is formed with an anode-side wiring 91 and a cathode-side wiring 93 whose height on the mounting surface side is higher than that of the anode-side wiring 91 by the height of the first depth. Metal bumps 94 of the same thickness are formed on the anode-side wiring 91 and the cathode-side wiring 93, respectively.

[0246] The wiring 91 on the anode side and the wiring 93 on the cathode side of the mounting substrate 90 are electrically insulated from each other and cross each other via an insulating layer 92 having a thickness corresponding to the height of the first depth. Note that the protrusion 91 a formed on the mounting substrate 90 of the semiconductor light emitting device 100 of the first embodiment is omitted in this embodiment.

[0247] In this way, also in the semiconductor light-emitting element and semiconductor light-emitting device of the second embodiment, the multiple electrodes of the semiconductor light-emitting element 1 form independent circuits in each light-emitting unit layer 30R, 30G, 30B corresponding to the emitted light color, and the emitted light color and light amount can be controlled independently.

[0248] The plurality of electrodes on the light-emitting portion side of the semiconductor light-emitting element 1, which serve as electrical terminals of the circuits to the light-emitting layers of the light-emitting unit layers 30R, 30G, and 30B corresponding to the respective emitted colors, are formed on the same surface. The plurality of electrodes on the non-light-emitting portion side are also formed on the same surface. This same surface on which the plurality of electrodes are formed serves as the mounting surface, allowing for easy and stable electrical connection with the mounting substrate 90.

[0249] Furthermore, a semiconductor light emitting device can be obtained in which a semiconductor light emitting element is stably mounted using a mounting substrate on which a stable mounting surface is easily formed, without using a mounting substrate with a complex configuration that is time-consuming to manufacture. [Third Embodiment] A third embodiment of a semiconductor light emitting element and a semiconductor light emitting device according to the present disclosure will now be described with reference to the drawings. Fig. 35 is a plan view of a semiconductor light emitting element of the third embodiment. Fig. 36 shows the E-E, F-F, and G-G cross sections of Fig. 35. Fig. 37 shows the H-H and I-I cross sections of Fig. 35.

[0250] In the first and second embodiments, the subpixel 71 was divided into an emissive portion 72 and a non-emissive portion 73 by a dividing groove 801 that divided the emissive layer of a predetermined emissive unit layer. Each subpixel 71 had an emissive portion 72 and a non-emissive portion 73. The dividing groove 801 of the subpixel 71 divided the emissive layers of all of the emissive unit layers 30R, 30G, and 30B. In contrast, in the third embodiment, similar to the first and second embodiments, the subpixel 71 is divided into an emissive portion and a non-emissive portion 73 by a dividing groove that divided the emissive layer of a predetermined emissive unit layer. However, in the third embodiment, multiple subpixels 71 share the non-emissive portion 73. Therefore, in the pixel 70, the number of non-emissive portions is smaller than the number of emissive portions. The dividing groove of the subpixel 71 divided the emissive layer of at least a predetermined emissive unit layer, but did not necessarily divide the emissive layer of all of the emissive unit layers.

[0251] In the third embodiment, if a sub-pixel 71 is composed of a light-emitting portion and a non-light-emitting portion, overlapping areas will occur in each sub-pixel 71, and therefore only the light-emitting portion will be described as the sub-pixel 71. Also, dividing grooves that divide the light-emitting layer of the sub-pixel 71 will be described as partitioning grooves 802a, 802b, and 802c. These partitioning grooves 802a, 802b, and 802c are grooves that partition the sub-pixels 71, including grooves that divide the light-emitting layer of a predetermined light-emitting unit layer into a light-emitting portion and a non-light-emitting portion 73.

[0252] 35 , a pixel 70 includes two or more subpixels 71B, 71G, and 71R and one or more non-emissive portions 73. In the third embodiment, the subpixels 71B, 71G, and 71R are each composed of only an emissive portion and do not include a non-emissive portion 73. The number of non-emissive portions 73 included in a pixel 70 is fewer than the number of subpixels 71B, 71G, and 71R included in the pixel 70. In the third embodiment, one pixel 70 includes three subpixels 71B, 71G, and 71R and one non-emissive portion 73. In the third embodiment, the first subpixel 71B is a blue subpixel, the second subpixel 71G is a green subpixel, and the third subpixel 71R is a red subpixel.

[0253] The pixel 70 is partitioned by two partitioning grooves 802a and 802b into three regions: a blue subpixel 71B, a red subpixel 71R and a non-emitting portion 73, and a green subpixel 71G. The first partitioning groove 802a and the second partitioning groove 802b are arranged parallel to each other. Therefore, the subpixels 71B, 71G, and 71R are arranged side by side with their longitudinal directions aligned. The red subpixel 71R and the non-emitting portion 73 are sandwiched between the blue subpixel 71B and the green subpixel 71G.

[0254] The blue subpixel 71B is separated from the red subpixel 71R and non-light-emitting portion 73 by a first partition groove 802a. The green subpixel 71G is separated from the red subpixel 71R and non-light-emitting portion 73 by a second partition groove 802b. The red subpixel 71R is separated from the non-light-emitting portion 73 by a third partition groove 802c.

[0255] In the third embodiment, the subpixels 71B, 71G, and 71R include a subpixel 71R in which the area of ​​the surface on which the anode electrode 31p is provided is different from that of the other subpixels 71B, 71G, and 71R. In the example shown in Figure 35, the short sides of the three subpixels 71B, 71G, and 71R are the same, and the long side of the red subpixel 71R is shorter than those of the other subpixels 71B and 71G. Therefore, the area of ​​the red subpixel 71R is smaller than that of the blue subpixel 71B and the green subpixel 71G.

[0256] In the third embodiment, each of the multiple sub-pixels 71B, 71G, and 71R is adjacent to the non-light-emitting portion 73. In other words, the sub-pixels 71B, 71G, and 71R are in contact with the non-light-emitting portion 73 via the partitioning grooves 802a to 802c, and no other sub-pixels 71B, 71G, or 71R are present between the sub-pixels 71B, 71G, or 71R and the non-light-emitting portion 73.

[0257] An anode electrode 31p is provided in each of the plurality of sub-pixels 71B, 71G, and 71R. A cathode electrode 31n is provided in the non-light-emitting portion 73. The anode electrode 31p and the cathode electrode 31n are provided on the surface of the laminate 30. The number of cathode electrodes 31n in the non-light-emitting portion 73 is smaller than the number of anode electrodes 31p in the sub-pixels 71B, 71G, and 71R. In the third embodiment, three anode electrodes 31p and one cathode electrode 31n are provided.

[0258] The first anode electrode 31Bp is provided in the blue sub-pixel 71B, the second anode electrode 31Gp is ​​provided in the green sub-pixel 71G, and the third anode electrode 31Rp is provided in the red sub-pixel 71R. Each of the anode electrodes 31Bp, 31Gp, and 31Rp is formed on almost the entire upper surface of the corresponding sub-pixel 71B, 71G, or 71R. The cathode electrode 31n is formed on almost the entire upper surface of the non-light-emitting portion 73.

[0259] Conductive vias 32 are provided in the sub-pixels 71B and 71G and the non-light-emitting portion 73. The conductive vias 32 include a first anode via 32Bp, a second anode via 32Gp, and a cathode via 32n. The first anode via 32Bp is provided in the blue sub-pixel 71B. The second anode via 32Gp is ​​provided in the green sub-pixel 71G. The cathode via 32n is provided in the non-light-emitting portion 73.

[0260] 36 and 37 , the cathode via 32n in the non-light-emitting portion 73 is formed from the top layer of the laminate 30 to the first n-type layer 302 in order to form current paths between the anode electrodes 31Bp, 31Gp, and 31Rp and the light-emitting layers 303, 307, and 312 of each color. The cathode via 32n penetrates all of the light-emitting layers 303, 307, and 312.

[0261] A current path including the first light-emitting layer 303 is formed between the first anode via 32Bp connected to the first anode electrode 31Bp and the cathode via 32n connected to the cathode electrode 31n. A current path including the second light-emitting layer 307 is formed between the second anode via 32Gp connected to the second anode electrode 31Gp and the cathode via 32n connected to the cathode electrode 31n. A current path including the third light-emitting layer 312 is formed between the third anode electrode 31Rp and the cathode via 32n connected to the cathode electrode 31n.

[0262] In this way, a current path is formed in each of the sub-pixels 71B, 71G, and 71R, including the light-emitting layers 303, 307, and 312 corresponding to the emitted light color, and therefore, each of the sub-pixels 71B, 71G, and 71R can independently control the emitted light color and amount of light emitted by the light-emitting layers 303, 307, and 312 included in the respective current paths.

[0263] In the third embodiment described above, in the semiconductor light-emitting device 1 having a plurality of pixels 70, the pixels 70 include sub-pixels 71B, 71G, 71R each having an anode electrode 31p and a non-light-emitting portion 73 each having a cathode electrode 31n, and the number of cathode electrodes 31n is smaller than the number of anode electrodes 31p.

[0264] Therefore, compared to a configuration in which the same number of cathode electrodes as anode electrodes are provided, the proportion of sub-pixels 71 in the pixel 70 can be increased, and the light-emitting area of ​​the pixel 70 can be increased. This increases the amount of light emitted by each pixel 70, improving the brightness of the pixel 70. Alternatively, it is possible to improve the light-emitting efficiency of the entire semiconductor light-emitting element 1 including multiple pixels 70.

[0265] Furthermore, according to the third embodiment, it is possible to reduce the number of cathode electrodes 31n of the semiconductor light emitting element 1 and the corresponding bumps 94 on the mounting substrate 90. This simplifies the configuration of the semiconductor light emitting element 1, and improves the yield when the semiconductor light emitting element 1 is mounted on the mounting substrate 90.

[0266] Furthermore, according to the third embodiment, the non-light-emitting portion 73 includes a plurality of light-emitting unit layers 30B, 30G, and 30R stacked thereon, and the cathode via 32n is formed up to the first n-type layer 302 of the light-emitting unit layer 30B, which is the farthest from the cathode electrode 31n. This allows electrical connection between all of the light-emitting unit layers 30B, 30G, and 30R and the cathode via 32n, and allows a current path including the target light-emitting layers 303, 307, and 312 to be formed between one cathode electrode 31n and multiple anode electrodes 31Bp, 31Gp, and 31Rp. As a result, the cathode electrode 31n can be used as a common electrode, and the number of cathode electrodes 31n can be made smaller than the number of anode electrodes 31p.

[0267] Furthermore, in the third embodiment, each of the multiple sub-pixels 71B, 71G, and 71R is arranged adjacent to the non-light-emitting portion 73. This allows the anode electrodes 31Bp, 31Gp, and 31Rp provided in the multiple sub-pixels 71B, 71G, and 71R to be connected over the shortest distance to the cathode electrode 31n provided in the non-light-emitting portion 73. This also allows the resistance between the sub-pixels 71B, 71G, and 71R and the non-light-emitting portion 73 to be reduced.

[0268] Furthermore, according to the third embodiment, by forming the anode vias 32Bp, 32Gp and the cathode vias 32n that reach predetermined semiconductor layers from the top layer of the stack 30, it is possible to form a current path that includes the target light-emitting layer without removing the semiconductor layer that is located closer to the electrode than the target light-emitting layer. This makes it possible to make the multiple electrodes 31Bp, 31Gp, 31Rp, and 31n of the semiconductor light-emitting element 1 the same height.

[0269] In the blue subpixel 71B, by forming the first anode via 32Bp deeper than the second light-emitting layer 307 and the third light-emitting layer 312, a current path including the first light-emitting layer 303 can be formed without removing the light-emitting layers 307 and 312 provided closer to the first anode electrode 31Bp than the first light-emitting layer 303. In the green subpixel 71G, by forming the second anode via 32Gp deeper than the third light-emitting layer 312, a current path including the second light-emitting layer 307 can be formed without removing the third light-emitting layer 312 provided closer to the second anode electrode 31Gp than the second light-emitting layer 307. In the non-light-emitting portion 73, by forming the cathode via 32n deeper than all of the light-emitting layers 303, 307, 312, a current path including the target light-emitting layers 303, 307, 312 can be formed between multiple anode electrodes 31Bp, 31Gp, 31Rp and one cathode electrode 31n.

[0270] (Modification of the Third Embodiment of the Semiconductor Light Emitting Device) Next, a modification of the third embodiment of the present disclosure will be described.

[0271] Fig. 38 is a plan view of a pixel 70 according to a modification of the third embodiment, and corresponds to Fig. 35 described above. As shown in Fig. 38, in this modification, multiple subpixels 71B, 71G, and 71R are not arranged in parallel, but are arranged so that each subpixel 71B, 71G, and 71R is not sandwiched between two other subpixels 71B, 71G, and 71R. When viewed from the stacking direction of the stacked body 30, the subpixels 71B, 71G, and 71R are formed in a region that includes at least one corner of the rectangular pixel 70. The stacking direction of the stacked body 30 is perpendicular to the plane of the paper in Fig. 38.

[0272] The blue sub-pixel 71B is provided in a region including the upper right corner of the pixel 70 in the drawing, and has a substantially square planar shape. The green sub-pixel 71G is provided in a region including the lower right corner of the pixel 70 in the drawing, and has a substantially square planar shape. The red sub-pixel 71R is provided in a region including the upper left corner and the upper left corner of the pixel 70 in the drawing, and has a substantially rectangular planar shape.

[0273] The non-light-emitting portion 73 is provided near the center of the pixel 70 and has a substantially circular planar shape. The plurality of sub-pixels 71B, 71G, and 71R are arranged adjacent to the non-light-emitting portion 73, respectively.

[0274] In this modification, a first partition groove 802a is provided between the green subpixel 71G and the red subpixel 71R around the blue subpixel 71B and the non-light-emitting portion 73. A second partition groove 802b is provided between the red subpixel 71R around the green subpixel 71G and the non-light-emitting portion 73. A third partition groove 802c is provided between the red subpixel 71R and the non-light-emitting portion 73.

[0275] The anode electrodes 31Bp, 31Gp, and 31Rp provided in the sub-pixels 71B, 71G, and 71R, and the cathode electrode 31n provided in the non-light-emitting portion 73, are generally circular. The cathode electrode 31n is provided near the center of the three anode electrodes 31Bp, 31Gp, and 31Rp. Therefore, the distances between the three anode electrodes 31Bp, 31Gp, and 31Rp and one cathode electrode 31n are all the same.

[0276] The three anode electrodes 31Bp, 31Gp, and 31Rp are arranged at different positions in the Y direction. Therefore, the anode wirings 91 corresponding to the three anode electrodes 31Bp, 31Gp, and 31Rp do not overlap each other when viewed from a direction perpendicular to the surface of the mounting substrate 90. This allows the anode wirings 91 and cathode wirings 93 to be configured as two-layer three-dimensional wiring, as in the above-described embodiments.

[0277] According to this modification, the sum of the areas of the partitioning grooves 802a to 802c in the pixel 70 can be reduced, and the light-emitting areas of the sub-pixels 71B, 71G, and 71R can be increased. Furthermore, reducing the number of sub-pixels 71 arranged side by side makes it possible to form a higher-resolution pixel 70. In other words, there is a limit to the size of the sub-pixels 71 that can be processed, and by reducing the number of arrangements of the sub-pixels 71 and the number of dividing grooves, it becomes possible to form a pixel 70 with smaller dimensions.

[0278] Furthermore, in this modification, the sides of the sub-pixels 71B, 71G, and 71R can be made longer, which allows for a larger installation space for the anode electrodes 31Bp, 31Gp, and 31Rp.

[0279] The various aspects of the semiconductor light emitting element and semiconductor light emitting device of the present disclosure have been described above, and all of them can be suitably used in VR goggles and AR glasses that employ dot matrix displays with pixel widths of less than 100 μm. Furthermore, they can also be applied to various display devices other than VR goggles and AR glasses.

[0280] Furthermore, in the present disclosure, it is also possible to individually select and combine the individual configurations in the above-described embodiments and modifications.

[0281] DESCRIPTION OF SYMBOLS 1, 2, 3... Semiconductor light-emitting element 10... Sapphire substrate (element substrate) 30... Laminated body 30R... Red light-emitting unit layer (light-emitting unit layer) 30G... Green light-emitting unit layer (light-emitting unit layer) 30B... Blue light-emitting unit layer (light-emitting unit layer) 31... Electrode 31n, 31Rn, 31Gn, 31Bn... Negative electrode 31p, 31Rp, 31Gp, 31Bp... Positive electrode 32, 32Rn, 32Gn, 32Bn, 32Gp, 32Bp... Conductive via 70... Pixel 71... Sub-pixel 71R... Red sub-pixel 71G... Green sub-pixel 71B... Blue sub-pixel 72, 72R, 72G, 72B... Light-emitting portion 73, 73R, 73G, 73B... Non-light-emitting portion DESCRIPTION OF SYMBOLS 77, 77R, 77G, 77B... Cathode recess (electrode surface cutout) 80, 802... Partition groove 100... Semiconductor light emitting device 301... First buffer layer 302... First n-type layer (power supply layer) 303... First light emitting layer (blue light emitting layer) 304... First p-type layer 305... First tunnel junction layer 306... Second n-type layer (power supply layer) 307... Second light emitting layer (green light emitting layer) 308... Second p-type layer 309... Second tunnel junction layer 310... Third n-type layer (power supply layer) 311... Second buffer layer 312... Third light emitting layer (red light emitting layer) 313... Third p-type layer 314... Third tunnel junction layer 315... Fourth n-type layer (power supply layer) 801, 801R, 801G, 801B...Division grooves 801x...Bottom 801y...Flat surface 801z...Recess

Claims

1. A laminate (30) in which a plurality of light-emitting unit layers (30R, 30G, 30B) each having a p-type layer (304, 308, 313), a light-emitting layer (303, 307, 312), and an n-type layer (302, 306, 310) are stacked in a predetermined stacking direction is partitioned by partitioning grooves (80) to form a plurality of pixels (70) each having a plurality of sub-pixels (71), the sub-pixels are divided into light-emitting sections (72) and non-light-emitting sections (73) by partitioning grooves (801) that divide the light-emitting layer of a predetermined light-emitting unit layer, electrodes (31) are provided on the mounting surfaces of the light-emitting sections and the non-light-emitting sections, and conductive vias (32) are provided from the electrodes to a predetermined n-type layer for circuit configuration to the light-emitting layer of the predetermined light-emitting unit layer, and the side surfaces of the conductive vias are inclined relative to the stacking direction relative to the side surfaces of the partitioning grooves, In the plurality of sub-pixels, the electrodes on the light-emitting portion side are formed on the same surface, and the electrodes on the non-light-emitting portion side are formed on the same surface.

2. A laminate (30) in which a plurality of light-emitting unit layers (30R, 30G, 30B) each having a p-type layer (304, 308, 313), a light-emitting layer (303, 307, 312), and an n-type layer (302, 306, 310) stacked in a predetermined stacking direction is partitioned by partitioning grooves (80) to form a plurality of pixels (70) each having a plurality of sub-pixels (71), the sub-pixels being divided into light-emitting sections (72) and non-light-emitting sections (73) by dividing grooves (801) that divide the light-emitting layer of a predetermined light-emitting unit layer, electrodes (31) are provided on the mounting surfaces of the light-emitting sections and the non-light-emitting sections, and conductive vias (32) are provided from the electrodes to a predetermined n-type layer for circuit configuration to the light-emitting layer of the predetermined light-emitting unit layer, the conductive vias include a plurality of conductive vias with different depths, and a conductive via deeper than other conductive vias has a continuous shape without steps on the side surface at a portion corresponding to the depth of the other conductive vias, In the plurality of sub-pixels, the electrodes on the light-emitting portion side are formed on the same surface, and the electrodes on the non-light-emitting portion side are formed on the same surface.

3. The semiconductor light emitting element according to claim 2, wherein the side surface of the conductive via is formed perpendicular to the mounting surface.

4. The semiconductor light-emitting element according to any one of claims 1 to 3, wherein the electrode on the light-emitting portion side and the electrode on the non-light-emitting portion side are formed on the same surface.

5. The semiconductor light-emitting element according to any one of claims 1 to 3, wherein the dividing groove of the subpixel is a groove that has the same depth as the dividing groove to the n-type layer, but is shallower than the conductive via of the light-emitting portion of a subpixel other than the subpixel.

6. The semiconductor light-emitting element according to claim 1, wherein in the subpixel, the conductive via on the non-light-emitting portion side is a groove deeper than the dividing groove.

7. The semiconductor light-emitting element according to any one of claims 1 to 3, wherein the dividing groove has a bottom (801x) having a flat surface (801y) and a recess (801z) deeper than the flat surface.

8. The semiconductor light-emitting device according to any one of claims 1 to 3, wherein the stacked body has tunnel junction layers (305, 309) between the p-type layer and the n-type layer of the light-emitting unit layers adjacent to each other in the stacking direction.

9. The semiconductor light-emitting element according to any one of claims 1 to 3, wherein the plurality of sub-pixels include a sub-pixel having a single light-emitting unit layer and a sub-pixel having two light-emitting unit layers.

10. The semiconductor light-emitting element according to any one of claims 1 to 3, wherein the number of non-light-emitting portions in the pixel is smaller than the number of light-emitting portions.

11. The semiconductor light-emitting element according to any one of claims 1 to 3, wherein in the pixel, the sub-pixel is not sandwiched between other sub-pixels when viewed from the stacking direction of the stack.

12. A semiconductor light emitting device in which the semiconductor light emitting element according to any one of claims 1 to 3 is mounted on a mounting substrate (90).

13. The semiconductor light emitting device according to claim 12, wherein a plurality of the semiconductor light emitting elements (2) are mounted in the mounting region (90a) of the mounting substrate, and the semiconductor light emitting elements comprise an element substrate and a plurality of the pixels arranged on the element substrate.

14. A laminate (30) in which a plurality of light-emitting unit layers (30R, 30G, 30B) each having a p-type layer (304, 308, 313), a light-emitting layer (303, 307, 312), and an n-type layer (302, 306, 310) are stacked in a predetermined stacking direction on an element substrate (10), is partitioned by partitioning grooves (80) to form a plurality of pixels (70) each having a plurality of sub-pixels (71), the sub-pixels are divided into light-emitting sections (72) and non-light-emitting sections (73) by dividing grooves (801) that divide the light-emitting layer of a predetermined light-emitting unit layer, electrodes (31) are provided on the mounting surfaces of the light-emitting sections and the non-light-emitting sections, and conductive vias (32) are provided from the electrodes to a predetermined n-type layer for circuit configuration to the light-emitting layer of the predetermined light-emitting unit layer, a pixel dividing groove forming step (S01) in which the dividing grooves and the grooves of at least the conductive vias of the light-emitting portion of the plurality of sub-pixels are formed by etching a pixel shape processing step (S02) in which the dividing grooves and the grooves of the conductive vias of at least the light-emitting portion of the plurality of sub-pixels are formed by etching a plurality of times; and an electrode forming step (S05) in which the electrodes and the conductive vias are formed.

15. The method for manufacturing a semiconductor light-emitting element according to claim 14, wherein the stacked body has tunnel junction layers (305, 309) between the p-type layer and the n-type layer of the light-emitting unit layers adjacent in the stacking direction.

16. The method for manufacturing a semiconductor light-emitting element according to claim 14, wherein, in the multiple etchings in the pixel shape processing step, the dividing grooves and the conductive via grooves are formed starting from shallower depths, and the difference in depth is additionally formed in deeper portions.

17. The method for manufacturing a semiconductor light-emitting element according to claim 14, wherein, in the multiple etching steps in the pixel shape processing step, the dividing grooves and the grooves for the conductive vias are formed in grooves of the same depth.

18. The method for manufacturing a semiconductor light-emitting element according to claim 14, wherein the grooves for the conductive vias in the non-light-emitting portions are formed in the pixel partition groove forming step (S01).

19. A method for manufacturing a semiconductor light emitting device, comprising mounting a semiconductor light emitting element manufactured by the manufacturing method according to claim 14 on a mounting substrate (90).

20. The method for manufacturing a semiconductor light emitting device according to claim 19, further comprising a lift-off step of lifting off the element substrate after the semiconductor light emitting element has been mounted on the mounting substrate.

21. The method for manufacturing a semiconductor light emitting device according to claim 20, wherein the pixel of the semiconductor light emitting element is formed by integrating the plurality of sub-pixels.

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