Semiconductor device

Abstract

This semiconductor device comprises: a first semiconductor chip including a carrier transistor; and a second semiconductor chip including a peak transistor. The first semiconductor chip includes a first active region and a first inactive region in which 2DEG is less likely to occur than in the first active region. The second semiconductor chip includes a second active region and a second inactive region in which 2DEG is less likely to occur than in the second active region. The dimension in the Y direction of the first semiconductor chip is equal to the dimension in the Y direction of the second semiconductor chip. The sum of the dimensions in the Y direction of the first inactive regions arranged on both sides of the first active region in the Y direction is larger than the sum of dimensions in the Y direction of the second inactive regions arranged on both sides of the second active region in the Y direction.

Description

Semiconductor Devices

[0001] The present disclosure relates to a semiconductor device used in a Doherty amplifier.

[0002] Patent Document 1 discloses a Doherty amplifier including a carrier amplifier configured with a first FET and a peak amplifier configured with a second FET.

[0003] JP 2012-28880 A

[0004] [Summary] In semiconductor devices used in Doherty amplifiers, improvements in heat dissipation performance are desired.

[0005] A semiconductor device according to one aspect of the present disclosure includes a first semiconductor chip including a carrier transistor constituting a part of a carrier amplifier, and a second semiconductor chip including a peak transistor constituting a part of a peak amplifier, wherein the first semiconductor chip includes a first electron transit layer, a first electron supply layer provided on the first electron transit layer and having a band gap larger than that of the first electron transit layer, a first active region in which two-dimensional electron gas is generated, extending in a first direction and a second direction orthogonal to the first direction in a plan view, a first inactive region surrounding the first active region in a plan view and in which two-dimensional electron gas is less likely to be generated than in the first active region, and a first source electrode, a first gate electrode, and a first drain electrode provided above the first electron supply layer in the first active region, extending in the first direction and spaced apart from each other in the second direction; and the second semiconductor chip includes a second electron transit layer and a first inactive region provided on the second electron transit layer. a second active region that is a region in which two-dimensional electron gas is generated and that extends in the first direction and the second direction; a second inactive region that surrounds the second active region in a planar view and in which the two-dimensional electron gas is less likely to be generated in the peak transistor than in the second active region; and a second source electrode, a second gate electrode, and a second drain electrode that are provided above the second electron supply layer in the second active region, extend in the first direction, and are spaced apart from each other in the second direction, wherein, in a planar view, a dimension of the first semiconductor chip in the first direction is equal to a dimension of the second semiconductor chip in the first direction, and a sum of the dimensions in the first direction of the first inactive regions that are disposed on both sides of the first active region in the first direction is greater than a sum of the dimensions in the first direction of the second inactive regions that are disposed on both sides of the second active region in the first direction.

[0006] FIG. 1 is a schematic circuit diagram of an exemplary Doherty amplifier according to a first embodiment. FIG. 2 is a graph showing the relationship between output power and drain efficiency in the Doherty amplifier of FIG. 1. FIG. 3 is a schematic plan view of a semiconductor device constituting a part of the Doherty amplifier of FIG. 1. FIG. 4 is a schematic cross-sectional view of the semiconductor device taken along line F4-F4 in FIG. 3. FIG. 5 is a schematic plan view of a first semiconductor chip of the semiconductor device of FIG. 3. FIG. 6 is a schematic cross-sectional view of the first semiconductor chip taken along line F6-F6 in FIG. 5. FIG. 7 is a schematic cross-sectional view of the first semiconductor chip taken along line F7-F7 in FIG. 5. FIG. 8 is a schematic plan view of a second semiconductor chip of the semiconductor device of FIG. 3. FIG. 9 is a schematic cross-sectional view of the second semiconductor chip taken along line F9-F9 in FIG. 8. FIG. 10 is a schematic cross-sectional view of the second semiconductor chip taken along line F10-F10 in FIG. 8. FIG. 11 is a schematic plan view showing active regions and inactive regions in the first semiconductor chip and the second semiconductor chip. FIG. 12 is a schematic plan view illustrating a manufacturing process of the method for manufacturing a semiconductor device according to the first embodiment. FIG. 13 is a schematic cross-sectional view of a semiconductor wafer cut along line FA-FA in FIG. 12. FIG. 14 is a schematic plan view illustrating a manufacturing process of a semiconductor device subsequent to that shown in FIG. 13. FIG. 15 is a schematic cross-sectional view illustrating a manufacturing process of a semiconductor device subsequent to that shown in FIG. 14. FIG. 16 is a schematic cross-sectional view illustrating a manufacturing process of a semiconductor device subsequent to that shown in FIG. 15. FIG. 17 is a schematic cross-sectional view illustrating a manufacturing process of a semiconductor device subsequent to that shown in FIG. 16. FIG. 18 is a schematic cross-sectional view illustrating a manufacturing process of a semiconductor device subsequent to that shown in FIG. 17. FIG. 19 is a schematic cross-sectional view illustrating a manufacturing process of a semiconductor device subsequent to that shown in FIG. 18. FIG. 20 is a schematic cross-sectional view illustrating a manufacturing process of a semiconductor device subsequent to that shown in FIG. 19. FIG. 21 is a schematic plan view illustrating a manufacturing process of the semiconductor device shown in FIG. 20. FIG. 22 is a schematic plan view of a semiconductor chip in a semiconductor device according to a second embodiment. FIG. 23 is a schematic cross-sectional view of the semiconductor device cut along line F23-F23 in FIG. 22. FIG. 24 is a schematic plan view illustrating active regions and inactive regions in a semiconductor chip. Fig. 25 is a schematic plan view for explaining the manufacturing process of the semiconductor device manufacturing method according to the second embodiment. Fig. 26 is a schematic plan view of a semiconductor device according to a modified example. Fig. 27 is a schematic plan view of a first semiconductor chip in the semiconductor device according to the modified example.Fig. 28 is a schematic plan view of a first semiconductor chip in a semiconductor device of a modified example. Fig. 29 is a schematic plan view of a first semiconductor chip in a semiconductor device of a modified example. Fig. 30 is a schematic plan view of a semiconductor chip in a semiconductor device of a modified example. Fig. 31 is a schematic plan view of a second semiconductor chip in a semiconductor device of a modified example. Fig. 32 is a schematic plan view showing active regions and inactive regions of the first semiconductor chip and the second semiconductor chip in a semiconductor device of a modified example. Fig. 33 is a schematic plan view showing active regions and inactive regions of the first semiconductor chip and the second semiconductor chip in a semiconductor device of a modified example. Fig. 34 is a schematic plan view showing active regions and inactive regions of the first semiconductor chip and the second semiconductor chip in a semiconductor device of a modified example.

[0007] DETAILED DESCRIPTION Hereinafter, several embodiments of semiconductor devices used in the Doherty amplifier of the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of explanation, components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered to limit the present disclosure.

[0008] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0009] The terms "first," "second," "third," etc. used in this disclosure are merely used to label and are not necessarily intended to assign any order to their objects. The phrase "at least one" used in this disclosure means "one or more" of the desired options. As an example, the phrase "at least one" used in this disclosure means "only one option" or "both of two options" if the number of options is two. As another example, the phrase "at least one" used in this disclosure means "only one option" or "any combination of two or more options" if the number of options is three or more.

[0010] As used in this disclosure, "the dimensions (width, length) of A are equal to the dimensions (width, length) of B" or "the dimensions (width, length) of A and the dimensions (width, length) of B are equal to each other" also includes a relationship in which the difference between the dimensions (width, length) of A and the dimensions (width, length) of B is, for example, within 10% of the dimensions (width, length) of A.

[0011] First Embodiment [Schematic Configuration of Doherty Amplifier] A schematic configuration of a Doherty amplifier 10 according to a first embodiment will be described with reference to Fig. 1. Fig. 1 schematically shows the circuit configuration of the Doherty amplifier 10.

[0012] 1 , the Doherty amplifier 10 includes an input terminal 11, an output terminal 12, a carrier amplifier 13, a peak amplifier 14, a distribution circuit 15, and a combining circuit 16. The Doherty amplifier 10 may be used, for example, as an amplifier for wireless communications. In one example, the Doherty amplifier 10 may be used as a wireless communications base station amplifier (base station amplifier).

[0013] The distribution circuit 15 is electrically connected to the input terminal 11. The distribution circuit 15 is configured to distribute an input signal input to the input terminal 11 into two signals. In one example, the distribution circuit 15 may be configured to distribute the input signal into a first distribution signal and a second distribution signal, which are two signals having equal power. The distribution circuit 15 may be configured to output the first distribution signal to the carrier amplifier 13, and may be configured to output the second distribution signal to the peak amplifier 14.

[0014] The carrier amplifier 13 is electrically connected to the distribution circuit 15 and the combining circuit 16. The carrier amplifier 13 is configured to amplify the input first distribution signal. The carrier amplifier 13 is configured to output the amplified first distribution signal as a first output signal to the combining circuit 16. The carrier amplifier 13 is, for example, a class A or class AB amplifier. The carrier amplifier 13 is configured to constantly amplify the input first distribution signal.

[0015] The distribution circuit 15 and the peak amplifier 14 are connected by a quarter-wave phase line 17. The peak amplifier 14 is electrically connected to the combining circuit 16. The peak amplifier 14 is configured to amplify the peak of the input second distribution signal. The peak amplifier 14 is configured to output the second distribution signal, whose peak has been amplified, as a second output signal to the combining circuit 16. The peak amplifier 14 is, for example, a class C amplifier. The peak amplifier 14 is configured to amplify the peak of the input second distribution signal when it is equal to or greater than a predetermined power.

[0016] The combining circuit 16 is electrically connected to the output terminal 12. The combining circuit 16 is configured to combine the first output signal of the carrier amplifier 13 and the second output signal of the peak amplifier 14. More specifically, the combining circuit 16 adjusts the impedances of the first output signal and the second output signal, and then combines the first output signal and the second output signal. The combining circuit 16 is configured to output the combined output signal to the output terminal 12.

[0017] The combining circuit 16 includes a node N1 that combines the first output signal and the second output signal, a quarter-wave phase line 18 that connects the node N1 to the carrier amplifier 13, and a quarter-wave phase line 19 that connects the node N1 to the output terminal 12. The quarter-wave phase lines 17 to 19 are transmission lines having an electrical length of a quarter wavelength at the frequency of the input signals (first distribution signal and second distribution signal). The quarter-wave phase line 17 is a line that compensates for the phase difference between the carrier amplifier 13 and the peak amplifier 14 that is caused by the quarter-wave phase line 18.

[0018] [Operation of Doherty Amplifier] The operation of the Doherty amplifier 10 will be described with reference to Fig. 2. Fig. 2 shows a graph of the drain efficiency of the Doherty amplifier 10 versus the output power.

[0019] Since the carrier amplifier 13 is a class A or class AB amplifier, the bias point is set between class A and class AB. Since the peak amplifier 14 is a class C amplifier, the bias point is set to class C. Due to these differences in bias point, the carrier amplifier 13 amplifies the first distribution signal regardless of the input power, while the peak amplifier 14 amplifies the peak of the second distribution signal only when the input power exceeds a predetermined power. In other words, the carrier amplifier 13 always operates, while the peak amplifier 14 operates only when the input power exceeds the predetermined power.

[0020] As shown in FIG. 2 , when the output power of the Doherty amplifier 10 is a saturated output P1, both the carrier amplifier 13 and the peak amplifier 14 are saturated, resulting in maximum drain efficiency. On the other hand, at an output P2 where the output power is backed off by 6 dB from the saturated output P1, only the carrier amplifier 13 is saturated, and the peak amplifier 14 is not amplifying. Even in this case, the drain efficiency is maximized. As described above, since there are two output powers where the drain efficiency is maximized, the range of output powers where the drain efficiency is high can be widened. For example, in a power amplifier for digitally modulated signals, the power amplifier is often operated at an output power (output P2) backed off by 5 dB to 8 dB from the saturated output P1 in order to maintain linearity.

[0021] Assuming that the carrier amplifier 13 and the peak amplifier 14 are the same size, when only the carrier amplifier 13 is operating, the load is doubled compared to when both the carrier amplifier 13 and the peak amplifier 14 are operating. As a result, when only the carrier amplifier 13 is operating, the amplifier size is halved, the current is halved, and the output power is ¼ of when both the carrier amplifier 13 and the peak amplifier 14 are operating. Therefore, as shown in FIG. 2 , when only the carrier amplifier 13 is operating, the output power is backed off by 6 dB compared to when both the carrier amplifier 13 and the peak amplifier 14 are operating. Note that by changing the size relationship between the carrier amplifier 13 and the peak amplifier 14 from 1:1, the peak drain efficiency can be changed from the relationship of being backed off by 6 dB.

[0022] [Configuration of Semiconductor Device] The configuration of a semiconductor device 20 that constitutes a part of the Doherty amplifier 10 will be described with reference to Figures 3 and 4. Figure 3 schematically shows the internal planar structure of the semiconductor device 20. Figure 4 schematically shows the cross-sectional structure of the semiconductor device 20 taken along line F4-F4 in Figure 3. Note that in Figure 3, internal components of the semiconductor device 20 are shown with solid lines to make the drawing easier to understand.

[0023] As shown in FIG. 3 , the semiconductor device 20 includes a first semiconductor chip 30, a second semiconductor chip 50, a die pad 70, external terminals 80, and a sealing resin 90. The die pad 70 is flat and has a thickness in the Z direction. In the following description, two mutually orthogonal directions perpendicular to the Z direction are referred to as the "X direction" and the "Y direction." As shown in FIG. 3 , the die pad 70 has a rectangular shape in a plan view, with the long side extending in the X direction and the short side extending in the Y direction. The die pad 70 is made of, for example, a metal material. Examples of metal materials that have excellent heat dissipation properties include aluminum (Al) and copper (Cu). The die pad 70 includes a first surface 71 and a second surface 72 (see FIG. 4 ) opposite the first surface 71. In this disclosure, the X direction is an example of a "second direction," and the Y direction is an example of a "first direction."

[0024] A first semiconductor chip 30 and a second semiconductor chip 50 are mounted on a first surface 71 of the die pad 70. The first semiconductor chip 30 and the second semiconductor chip 50 are arranged at the same position in the Y direction and spaced apart from each other in the X direction. Therefore, the long side direction of the die pad 70 can also be said to be the arrangement direction of the first semiconductor chip 30 and the second semiconductor chip 50. As shown in FIG. 4 , both the first semiconductor chip 30 and the second semiconductor chip 50 are bonded to the first surface 71 of the die pad 70 by a conductive bonding material SD. A second surface 72 of the die pad 70 may be exposed from the sealing resin 90.

[0025] As shown in FIG. 3 , the first semiconductor chip 30 is a semiconductor chip including a carrier transistor TC (see FIG. 6 ) that constitutes part of the carrier amplifier 13 (see FIG. 1 ). The first semiconductor chip 30 is flat and has a thickness in the Z direction. The dimension LY1 of the first semiconductor chip 30 in the Y direction is larger than the dimension PX1 of the first semiconductor chip 30 in the X direction. Therefore, the first semiconductor chip 30 has a rectangular shape with its short side extending in the X direction and its long side extending in the Y direction in a planar view. In other words, the long side direction of the first semiconductor chip 30 is perpendicular to the long side direction of the die pad 70 in a planar view.

[0026] The first semiconductor chip 30 includes a first input pad 30A and a first output pad 30B. Both the first input pad 30A and the first output pad 30B are exposed from the surface of the first semiconductor chip 30. The first input pad 30A and the first output pad 30B are arranged at the same position in the X direction and spaced apart from each other in the Y direction. In other words, the first input pad 30A and the first output pad 30B can be said to be arranged in the direction of the long side of the first semiconductor chip 30. Both the first input pad 30A and the first output pad 30B are strip-shaped extending in the X direction in a plan view.

[0027] The second semiconductor chip 50 is a semiconductor chip including a peak transistor TP (see FIG. 9) that constitutes part of the peak amplifier 14 (see FIG. 1). The second semiconductor chip 50 is flat and has a thickness in the Z direction. The second semiconductor chip 50 is rectangular in shape, with its long sides in the X direction and its short sides in the Y direction in a plan view. That is, the long side direction of the second semiconductor chip 50 coincides with the long side direction of the die pad 70 in a plan view. In other words, the long side direction of the second semiconductor chip 50 coincides with the arrangement direction of the first semiconductor chip 30 and the second semiconductor chip 50. The dimension LX2 in the X direction of the second semiconductor chip 50 is larger than the dimension LX1 in the X direction of the first semiconductor chip 30. The dimension LY2 in the Y direction of the second semiconductor chip 50 is equal to the dimension LY1 in the Y direction of the first semiconductor chip 30.

[0028] The second semiconductor chip 50 includes a second input pad 50A and a second output pad 50B. Both the second input pad 50A and the second output pad 50B are exposed from the surface of the second semiconductor chip 50. The second input pad 50A and the second output pad 50B are arranged at the same position in the X direction and spaced apart from each other in the Y direction. In other words, the second input pad 50A and the second output pad 50B can be said to be arranged in the direction of the short side of the second semiconductor chip 50. Both the second input pad 50A and the second output pad 50B are strip-shaped extending in the X direction in a plan view. The X-direction dimensions of the second input pad 50A and the second output pad 50B are larger than the X-direction dimensions of the first input pad 30A and the first output pad 30B. The Y-direction dimension (width dimension) of the second input pad 50A and the Y-direction dimension (width dimension) of the second output pad 50B may be equal to the Y-direction dimension (width dimension) of the first input pad 30A and the Y-direction dimension (width dimension) of the first output pad 30B.

[0029] The external terminals 80 are arranged at a distance from the die pad 70 in a plan view. The external terminals 80 are individually and electrically connected to the carrier transistor TC and the peak transistor TP. The external terminals 80 include first to fourth terminals 81 to 84. The first terminal 81 and the second terminal 82 and the third terminal 83 and the fourth terminal 84 are arranged at a distance from each other in the Y direction. The die pad 70 is arranged between the first terminals 81 and the second terminals 82 and the third terminals 83 and the fourth terminals 84 in the Y direction. The first terminal 81 and the second terminal 82 are arranged at the same position as each other in the Y direction and at a distance from each other in the X direction. The third terminal 83 and the fourth terminal 84 are arranged at the same position as each other in the Y direction and at a distance from each other in the X direction. The first terminal 81 is arranged at the same position as the third terminal 83 in the X direction. The second terminal 82 is arranged at the same position as the fourth terminal 84 in the X direction.

[0030] The first terminals 81 and the second terminals 82 are arranged closer to the first input pads 30A of the first semiconductor chip 30 and the second input pads 50A of the second semiconductor chip 50. The first terminals 81 are arranged corresponding to the first semiconductor chip 30 in the Y direction. The second terminals 82 are arranged corresponding to the second semiconductor chip 50 in the Y direction.

[0031] The third terminal 83 and the fourth terminal 84 are arranged closer to the first output pad 30B of the first semiconductor chip 30 and the second output pad 50B of the second semiconductor chip 50. The third terminal 83 is arranged corresponding to the first semiconductor chip 30 in the Y direction. The fourth terminal 84 is arranged corresponding to the second semiconductor chip 50 in the Y direction.

[0032] The first terminal 81 and the first input pad 30A are connected by a wire W1. That is, the first input pad 30A and the first terminal 81 are electrically connected by the wire W1. Therefore, it can be said that the first terminal 81 constitutes an input terminal of the first semiconductor chip 30.

[0033] The second terminal 82 and the second input pad 50A are connected by a wire W2. In other words, the second input pad 50A and the second terminal 82 are electrically connected by the wire W2. For this reason, it can be said that the second terminal 82 constitutes an input terminal of the second semiconductor chip 50.

[0034] The third terminal 83 and the first output pad 30B are connected by a wire W3. In other words, the first output pad 30B and the third terminal 83 are electrically connected by the wire W3. For this reason, it can be said that the third terminal 83 constitutes an output terminal of the first semiconductor chip 30.

[0035] The fourth terminal 84 and the second output pad 50B are connected by a wire W4. In other words, the second output pad 50B and the fourth terminal 84 are electrically connected by the wire W4. For this reason, it can be said that the fourth terminal 84 constitutes an output terminal of the second semiconductor chip 50.

[0036] Both the first terminal 81 and the second terminal 82 are electrically connected to the distribution circuit 15 of Fig. 1 . Both the third terminal 83 and the fourth terminal 84 are electrically connected to the composite circuit 16 of Fig. 1 . Therefore, the first input pad 30A of the first semiconductor chip 30 and the second input pad 50A of the second semiconductor chip 50 are electrically connected to the distribution circuit 15. The first output pad 30B of the first semiconductor chip 30 and the second output pad 50B of the second semiconductor chip 50 are electrically connected to the composite circuit 16.

[0037] The sealing resin 90 covers the first semiconductor chip 30, the second semiconductor chip 50, and the wires W1 to W4, and also partially covers the die pad 70 and the external terminals 80. The sealing resin 90 is made of, for example, an insulating material. For example, a black epoxy resin may be used as the insulating material. Although not shown, the lower surfaces of the first to fourth terminals 81 to 84 of the external terminal 80 may be exposed from the lower surface of the sealing resin 90. The first to fourth terminals 81 to 84 may include protrusions 81A to 84A that protrude from the side surfaces of the sealing resin 90 in the Y direction.

[0038] [Structure of First Semiconductor Chip] The detailed configuration of the first semiconductor chip 30 will be described with reference to FIGS. 5 to 7. FIG. 5 schematically shows the planar structure of the first semiconductor chip 30. FIG. 6 schematically shows the cross-sectional structure of the first semiconductor chip 30 taken along line F6-F6 in FIG. 5. FIG. 7 schematically shows the cross-sectional structure of the first semiconductor chip 30 taken along line F7-F7 in FIG. 5. Note that the first input pads 30A and the first output pads 30B (both of which are shown in FIG. 3) are omitted in FIGS. 4 and 5.

[0039] (Planar structure of first semiconductor chip) As shown in FIG. 5, the first semiconductor chip 30 may include an insulating layer 40, and a first source wiring 43, a first drain wiring 44, and a first gate wiring 45 provided on the insulating layer 40.

[0040] The insulating layer 40 can be made of any insulating material that can insulate the first source wiring 43, the first drain wiring 44, and the first gate wiring 45 from one another. For example, the insulating layer 40 can be made of silicon oxide (SiO ２ ), silicon nitride (SiN), silicon oxynitride (SiON), aluminum oxide (Al ２ O ３ ), aluminum nitride (AlN), aluminum oxynitride (AlON), hafnium oxide (HfO), hafnium nitride (HfN), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), or any combination thereof.

[0041] The first source wiring 43, the first drain wiring 44, and the first gate wiring 45 can be made of one or more conductive materials. For example, the first source wiring 43, the first drain wiring 44, and the first gate wiring 45 can each include gold (Au), titanium (Ti), titanium nitride (TiN), platinum (Pt), nickel (Ni), copper (Cu), aluminum (Al), aluminum silicon copper (AlSiCu), aluminum copper (AlCu), or any combination thereof. In one example, the first source wiring 43, the first drain wiring 44, and the first gate wiring 45 can be made of gold. Each of the first source wiring 43, the first drain wiring 44, and the first gate wiring 45 can have a thickness of approximately 3 μm.

[0042] The first source wiring 43 may include a first base portion 43A, a plurality of first source fingers 43B connected to the first base portion 43A, and a plurality of first pad portions 43C connected to the first base portion 43A. In the illustrated example, the first base portion 43A extends in the X direction, and the plurality of first source fingers 43B extend in the Y direction. The plurality of first source fingers 43B are arranged spaced apart from each other in the X direction. The plurality of first pad portions 43C are arranged on the opposite side of the first base portion 43A from the plurality of first source fingers 43B in the Y direction. The plurality of first pad portions 43C are arranged spaced apart from each other in the X direction. In the example shown in FIG. 5 , the plurality of first pad portions 43C are connected to both ends of the first base portion 43A in the X direction.

[0043] The first drain wiring 44 may include a first base portion 44A and a plurality of first drain fingers 44B connected to the first base portion 44A. In the illustrated example, the first base portion 44A extends in the X direction, and the plurality of first drain fingers 44B extend in the Y direction. The plurality of first drain fingers 44B are arranged spaced apart from one another in the X direction. The first base portion 44A is arranged spaced apart from the first base portion 43A of the first source wiring 43 in the Y direction. The first base portion 44A faces the first base portion 43A of the first source wiring 43 in the Y direction. The plurality of first drain fingers 44B and the plurality of first source fingers 43B may be arranged alternately one by one in the X direction.

[0044] The first gate wiring 45 is disposed between the first pad portions 43C of the first source wiring 43 in the X direction. The first gate wiring 45 has a rectangular shape with its long side extending in the X direction and its short side extending in the Y direction in plan view.

[0045] (Cross-sectional structure of first semiconductor chip) As shown in Figures 6 and 7, the first semiconductor chip 30 may include a first semiconductor substrate 31, a first buffer layer 32 provided on the first semiconductor substrate 31, a first electron transit layer 33 provided on the first buffer layer 32, a first electron supply layer 34 provided on the first electron transit layer 33, and a first cap layer 35 provided on the first electron supply layer 34.

[0046] The first semiconductor substrate 31 includes a first substrate front surface 31S and a first substrate back surface 31R opposite to the first substrate front surface 31S. The first semiconductor substrate 31 may be a hexagonal silicon carbide (SiC) substrate.

[0047] The first semiconductor substrate 31 may be a 4H semi-insulating SiC substrate. Here, "4H" represents the polytype of SiC crystal. The resistivity of the first semiconductor substrate 31 is, for example, 1×10 ５The resistivity may be Ω·cm or more. In one example, the first semiconductor substrate 31 may not have an off-angle. The thickness of the first semiconductor substrate 31 may be, for example, 30 μm or more and 300 μm or less. The thickness of the first semiconductor substrate 31 is, for example, 50 μm or more. The thickness of the first semiconductor substrate 31 is, for example, 200 μm or less. In the first embodiment, the first semiconductor substrate 31 may have a thickness of 150 μm. Here, the thickness of the first semiconductor substrate 31 can be defined as the distance in the Z direction between the first substrate front surface 31S and the first substrate back surface 31R.

[0048] In the first embodiment, a SiC substrate is used as the first semiconductor substrate 31, but this is not limiting. For example, a Si substrate may be used as the first semiconductor substrate 31, or a semiconductor substrate other than a substrate containing Si, such as a GaN substrate or a sapphire substrate, may be used.

[0049] The first buffer layer 32, the first electron transit layer 33, the first electron supply layer 34, and the first cap layer 35 constitute a nitride semiconductor layer formed by epitaxial growth on the first substrate surface 31S of the first semiconductor substrate 31.

[0050] The first buffer layer 32 may be made of any material that can suppress warping, cracking, and the like of the first semiconductor substrate 31 due to, for example, a mismatch in thermal expansion coefficients between the first semiconductor substrate 31 and the first electron transit layer 33. The first buffer layer 32 may include, for example, at least one of an aluminum nitride (AlN) layer, an aluminum gallium nitride (AlGaN) layer, an aluminum indium gallium nitride (AlInGaN), and a graded AlGaN layer containing different aluminum compositions. The first buffer layer 32 may also be made of a single AlN layer, a single AlGaN layer, a layer having an AlGaN / GaN superlattice structure, a layer having an AlN / AlGaN superlattice structure, or a layer having an AlN / GaN superlattice structure. In the first embodiment, the first buffer layer 32 may include a substrate-side buffer layer that is an AlN layer provided on the first substrate surface 31S of the first semiconductor substrate 31, and a stacked buffer layer that is an AlGaN layer provided on the AlN layer. The thickness of the first buffer layer 32 can be set to 5 nm or more and 2 μm or less.

[0051] The first buffer layer 32 may include a GaN layer doped with an impurity. This GaN layer may be provided to suppress leakage current. The impurity may be, for example, carbon (C) or iron (Fe). Alternatively, the impurity may be both carbon and iron.

[0052] The first electron transit layer 33 may be made of GaN. In the first embodiment, the first electron transit layer 33 may be an n-type GaN layer doped with donor impurities. In another example, the first electron transit layer 33 may be an undoped GaN layer. The thickness of the first electron transit layer 33 may be 0.05 μm or more and 1 μm or less. In the first embodiment, the first electron transit layer 33 may have a thickness of approximately 0.5 μm. The first electron transit layer 33 may also contain aluminum gallium nitride or aluminum indium gallium nitride.

[0053] The first electron supply layer 34 has a larger band gap than the first electron transit layer 33. The first electron supply layer 34 is made of, for example, a nitride semiconductor. In the first embodiment, the first electron supply layer 34 is made of Al ｘ Ga １－ｘ The first electron supply layer 34 may be composed of N. Here, 0<x≦1, and more preferably 0.1<x<0.3. The band gap of AlGaN increases as the aluminum composition increases. In the first embodiment, x=0.2. The thickness of the first electron supply layer 34 may be 1 nm or more and 100 nm or less. In the first embodiment, the first electron supply layer 34 may have a thickness of approximately 20 nm. The first electron supply layer 34 may contain aluminum nitride or aluminum indium gallium nitride. Furthermore, the first electron supply layer 34 may be partially or entirely doped with silicon.

[0054] The first electron transit layer 33 and the first electron supply layer 34 are composed of nitride semiconductors having different lattice constants. Therefore, the nitride semiconductor (e.g., GaN) constituting the first electron transit layer 33 and the nitride semiconductor (e.g., AlGaN) constituting the first electron supply layer 34 form a lattice-mismatched heterojunction. Due to spontaneous polarization in the first electron transit layer 33 and the first electron supply layer 34 and piezoelectric polarization caused by crystal strain near the heterojunction interface, the energy level of the conduction band of the first electron transit layer 33 near the heterojunction interface is lower than the Fermi level. As a result, a two-dimensional electron gas (2DEG) 36 is formed in the first electron transit layer 33 near the heterojunction interface between the first electron transit layer 33 and the first electron supply layer 34 (e.g., within a few nanometers from the interface). The 2DEG 36 in the first electron transit layer 33 functions as a channel for the first semiconductor chip 30. The sheet carrier density of the 2DEG 36 generated in the first electron transit layer 33 can be increased by increasing at least one of the aluminum composition and the thickness of the first electron supply layer 34 .

[0055] The first cap layer 35 may be made of GaN. In the first embodiment, the first cap layer 35 may be an n-type GaN layer doped with a donor-type impurity. Silicon (Si) may be used as the impurity. The impurity concentration of the first cap layer 35 may be, for example, 2×10 １８ cm －３ In another example, the first cap layer 35 may be an undoped GaN layer. In the first embodiment, the thickness of the first cap layer 35 may be about 2 nm.

[0056] The insulating layer 40 includes a first insulating layer 41 provided to cover the first cap layer 35. The first insulating layer 41 has a first source contact opening 41A, a first drain contact opening 41B, and a first gate contact opening 41C that expose the surface of the first cap layer 35. The first source contact opening 41A and the first drain contact opening 41B are spaced apart in the X direction. The first gate contact opening 41C is provided between the first source contact opening 41A and the first drain contact opening 41B in the X direction. In the first embodiment, the first insulating layer 41 may be made of silicon nitride. The thickness of the first insulating layer 41 may be, for example, not less than 10 nm and not more than 200 nm. In the first embodiment, the first insulating layer 41 may have a thickness of approximately 50 nm.

[0057] The first semiconductor chip 30 includes a first source electrode 46 and a first drain electrode 47 disposed on the first cap layer 35. The first semiconductor chip 30 also includes a first gate electrode 48 disposed on the first insulating layer 41. As such, the first source electrode 46, the first drain electrode 47, and the first gate electrode 48 are disposed above the first electron supply layer 34. The first source electrode 46 and the first drain electrode 47 are disposed spaced apart in the X direction. The first gate electrode 48 is disposed between the first source electrode 46 and the first drain electrode 47 in the X direction in a plan view. In other words, the first source electrode 46, the first drain electrode 47, and the first gate electrode 48 are disposed spaced apart from each other in the X direction. The first source electrode 46, the first drain electrode 47, and the first gate electrode 48 are disposed so as to allow electrons to travel in the X direction via the 2DEG 36. The first source electrode 46 and the first drain electrode 47 are covered by the first insulating layer 41. On the other hand, the first source electrode 46 is partially exposed through the first source contact opening 41 A. The first drain electrode 47 is partially exposed through the first drain contact opening 41 B. The first gate electrode 48 is in contact with the first cap layer 35 through the first gate contact opening 41 C.

[0058] Both the first source electrode 46 and the first drain electrode 47 may be made of any material capable of forming an ohmic contact with the first cap layer 35. In the first embodiment, both the first source electrode 46 and the first drain electrode 47 may include a titanium layer and an aluminum layer. In this case, the titanium layer may be disposed between the first insulating layer 41 and the aluminum layer. In one example, the titanium layer may have a thickness of approximately 20 nm. The aluminum layer may have a thickness of approximately 300 nm. In another example, both the first source electrode 46 and the first drain electrode 47 may include a tantalum (Ta) layer and an aluminum layer. In yet another example, both the first source electrode 46 and the first drain electrode 47 may include a titanium layer, an aluminum layer, a nickel (Ni) layer, and a gold layer, in this order from the bottom.

[0059] The first gate electrode 48 may be made of any material capable of forming a Schottky junction with the first cap layer 35. In the first embodiment, the first gate electrode 48 may include a nickel layer and a gold layer. In this case, the nickel layer may be disposed between the first insulating layer 41 and the gold layer. In one example, the nickel layer may have a thickness of 100 Å. The gold layer may have a thickness of 3000 Å.

[0060] The first gate electrode 48 extends in the Y direction in plan view (see FIG. 5 ). Although not shown, both the first source electrode 46 and the first drain electrode 47 also extend in the Y direction in plan view. That is, the first source electrode 46, the first gate electrode 48, and the first drain electrode 47, which extend in the Y direction, are aligned in this order in the X direction. Therefore, electrons can travel in the X direction between the first source electrode 46 and the first drain electrode 47 via the 2DEG 36 in the first electron transit layer 33.

[0061] The insulating layer 40 may further include a second insulating layer 42 provided on the first insulating layer 41. The second insulating layer 42 covers the first gate electrode 48. Therefore, it can be said that the insulating layer 40 covers the first source electrode 46, the first drain electrode 47, and the first gate electrode 48.

[0062] The second insulating layer 42 has a second source contact opening 42A, a second drain contact opening 42B, and a second gate contact opening 42C (see FIG. 6 ). The second source contact opening 42A exposes a portion of the first source electrode 46. The second drain contact opening 42B exposes a portion of the first drain electrode 47. The second gate contact opening 42C exposes a portion of the first gate electrode 48. The second source contact opening 42A and the second drain contact opening 42B are spaced apart in the X direction. In the first embodiment, the second insulating layer 42 may be made of silicon oxide. The second insulating layer 42 may have a thickness of, for example, 200 nm.

[0063] The first source wiring 43, the first drain wiring 44, and the first gate wiring 45 (see FIG. 6) are provided on the second insulating layer 42. The first source finger 43B of the first source wiring 43 is connected to the first source electrode 46 through the second source contact opening 42A. This electrically connects the first source wiring 43 to the first source electrode 46. The first drain finger 44B of the first drain wiring 44 is connected to the first drain electrode 47 through the second drain contact opening 42B. This electrically connects the first drain wiring 44 to the first drain electrode 47. The first gate wiring 45 is connected to the first gate electrode 48 through the second gate contact opening 42C. This electrically connects the first gate wiring 45 to the first gate electrode 48.

[0064] Although not shown, the first source electrode 46 may be electrically connected to the first semiconductor substrate 31. The first semiconductor substrate 31 is electrically connected to the die pad 70 through the conductive bonding material SD shown in Fig. 4. Therefore, the first source wiring 43 is electrically connected to the die pad 70 through the first source electrode 46 and the first semiconductor substrate 31.

[0065] Although not shown, the first gate wiring 45 is electrically connected to the first input pad 30A (see FIG. 3) of the first semiconductor chip 30. The first drain wiring 44 is electrically connected to the first output pad 30B (see FIG. 3) of the first semiconductor chip 30.

[0066] [Structure of Second Semiconductor Chip] The detailed configuration of the second semiconductor chip 50 will be described with reference to Figures 8 to 10. Figure 8 schematically shows the planar structure of the second semiconductor chip 50. Figure 9 schematically shows the cross-sectional structure of the second semiconductor chip 50 taken along line F9-F9 in Figure 8. Figure 10 schematically shows the cross-sectional structure of the second semiconductor chip 50 taken along line F10-F10 in Figure 8. Note that the second input pads 50A and the second output pads 50B (both see Figure 3) are omitted from Figures 8 to 10.

[0067] 8 to 10 , the configuration of the second semiconductor chip 50 is generally similar to the configuration of the first semiconductor chip 30. As shown in Fig. 8 , the second semiconductor chip 50 includes an insulating layer 60, and a second source wiring 63, a second drain wiring 64, and a second gate wiring 65 provided on the insulating layer 60. The configuration of the insulating layer 60 is the same as the configuration of the insulating layer 40 of the first semiconductor chip 30.

[0068] The second source wiring 63 may include a second base portion 63A, a plurality of second source fingers 63B, and a plurality of second pad portions 63C, similar to the first source wiring 43 of the first semiconductor chip 30 (see FIG. 5).

[0069] The X-direction dimension of the second base portion 63A is larger than the X-direction dimension of the first base portion 43A (see FIG. 5 ) of the first source wiring 43. In the first embodiment, the X-direction dimension of the second base portion 63A is approximately twice the X-direction dimension of the first base portion 43A. The Y-direction dimension of the second base portion 63A may be equal to the Y-direction dimension of the first base portion 43A.

[0070] The number of the second source fingers 63B is greater than the number of the first source fingers 43B of the first source wiring 43. In the example shown in FIG. 8 , the X-direction dimension (width dimension) of the second source finger 63B arranged at the center in the X-direction among the second source fingers 63B is larger than the X-direction dimensions (width dimensions) of the other second source fingers 63B. The X-direction dimension of the other second source fingers 63B may be equal to the X-direction dimension (width dimension) of the first source finger 43B. The Y-direction length of the second source finger 63B may be equal to the Y-direction length of the first source finger 43B. The arrangement pitch of the second source fingers 63B may be equal to the arrangement pitch of the first source fingers 43B.

[0071] The number of second pad portions 63C is greater than the number of first pad portions 43C (see FIG. 5) of the first source wiring 43. The second pad portions 63C are connected to both ends of the second base portion 63A in the X direction and to the center of the second base portion 63A in the X direction. The arrangement pitch of the second pad portions 63C may be equal to the arrangement pitch of the first pad portions 43C.

[0072] The second drain wiring 64 may include a second base portion 64A and a plurality of second drain fingers 64B, similar to the first drain wiring 44 of the first semiconductor chip 30 (see FIG. 5).

[0073] The X-direction dimension of the second base portion 64A is larger than the X-direction dimension of the first base portion 44A of the first drain wiring 44. In the first embodiment, the X-direction dimension of the second base portion 64A is approximately twice the X-direction dimension of the first base portion 44A. The Y-direction dimension of the second base portion 64A may be equal to the Y-direction dimension of the first base portion 44A.

[0074] The number of the second drain fingers 64B is greater than the number of the first drain fingers 44B of the first drain wiring 44. The dimension in the Y direction of the second drain fingers 64B may be equal to the dimension in the Y direction of the first drain fingers 44B. The dimension in the X direction of the second drain fingers 64B may be equal to the dimension in the X direction of the first drain fingers 44B. The arrangement pitch of the second drain fingers 64B may be equal to the arrangement pitch of the first drain fingers 44B.

[0075] A plurality of second gate wirings 65 are provided spaced apart in the X direction. The dimensions of each second gate wiring 65 in the X direction and the Y direction are equal to the dimensions of the first gate wiring 45 in the X direction and the Y direction.

[0076] 9 and 10 , the second semiconductor chip 50 includes a second semiconductor substrate 51, a second buffer layer 52, a second electron transit layer 53, a second electron supply layer 54, and a second cap layer 55. The second semiconductor substrate 51 includes a second substrate front surface 51S and a second substrate back surface 51R opposite the second substrate front surface 51S. The second buffer layer 52 is provided on the second substrate front surface 51S. The second electron supply layer 54 is provided on the second electron transit layer 53. The second electron supply layer 54 has a larger band gap than the second electron transit layer 53.

[0077] The second semiconductor substrate 51, second buffer layer 52, second electron transit layer 53, second electron supply layer 54, and second cap layer 55 have the same configurations as the first semiconductor substrate 31, first buffer layer 32, first electron transit layer 33, first electron supply layer 34, and first cap layer 35 (all of which are shown in FIG. 7 ) of the first semiconductor chip 30. Therefore, detailed descriptions of the second semiconductor substrate 51, second buffer layer 52, second electron transit layer 53, second electron supply layer 54, and second cap layer 55 will be omitted.

[0078] Due to spontaneous polarization in the second electron transit layer 53 and the second electron supply layer 54 and piezoelectric polarization due to crystal distortion near the heterojunction interface, the energy level of the conduction band of the second electron transit layer 53 near the heterojunction interface becomes lower than the Fermi level. As a result, a two-dimensional electron gas (2DEG) 56 is formed in the second electron transit layer 53 near the heterojunction interface between the second electron transit layer 53 and the second electron supply layer 54 (e.g., within a range of about several nanometers from the interface). The 2DEG 56 in the second electron transit layer 53 functions as a channel for the second semiconductor chip 50. The sheet carrier density of the 2DEG 56 generated in the second electron transit layer 53 can be increased by increasing at least one of the aluminum composition and thickness of the second electron supply layer 54.

[0079] The second semiconductor chip 50 includes a second source electrode 66 and a second drain electrode 67 provided on the second cap layer 55. The second semiconductor chip 50 also includes a second gate electrode 68 provided on the first insulating layer 61 (described later). The configurations of the second source electrode 66, the second drain electrode 67, and the second gate electrode 68 are the same as the configurations of the first source electrode 46, the first drain electrode 47, and the first gate electrode 48 of the first semiconductor chip 30. However, the number of the second source electrodes 66, the second drain electrodes 67, and the second gate electrodes 68 is greater than the number of the first source electrodes 46, the first drain electrodes 47, and the first gate electrodes 48. The multiple second source electrodes 66 and the multiple second drain electrodes 67 are alternately arranged one by one in the X direction. As shown in FIG. 8 , the second gate electrode 68 is arranged between the second source electrode 66 and the second drain electrode 67 adjacent to each other in the X direction. A plurality of second gate electrodes 68 (four in the example shown in FIG. 8 ) are connected to one second gate wiring 65. The second source electrode 66, the second drain electrode 67, and the second gate electrode 68 are arranged spaced apart from each other in the X direction. Each of the second source electrode 66, the second drain electrode 67, and the second gate electrode 68 extends in the Y direction.

[0080] Similar to the insulating layer 40, the insulating layer 60 includes a first insulating layer 61 and a second insulating layer 62. Similar to the first insulating layer 41 of the insulating layer 40, the first insulating layer 61 covers the second source electrode 66 and the second drain electrode 67. Meanwhile, the second gate electrode 68 provided on the first insulating layer 61 includes a portion that penetrates the first insulating layer 61 in the Z direction and contacts the second cap layer 55. The second insulating layer 62 covers the second gate electrode 68. In this manner, it can be said that the insulating layer 60 covers the second source electrode 66, the second drain electrode 67, and the second gate electrode 68. The second source electrode 66 and the second drain electrode 67 can be made of any material that can form an ohmic contact with the second cap layer 55. In one example, the second source electrode 66 and the second drain electrode 67 may be made of the same material as the first source electrode 46 and the first drain electrode 47. The second gate electrode 68 may be made of any material that can form a Schottky junction with the second cap layer 55. In one example, the second gate electrode 68 may be made of the same material as the first gate electrode 48.

[0081] Similar to the connection structure between the first source wiring 43, the first drain wiring 44, and the first gate wiring 45 of the first semiconductor chip 30 and the first source electrode 46, the first drain electrode 47, and the first gate electrode 48, the second source wiring 63 is electrically connected to the second source electrode 66, the second drain wiring 64 is electrically connected to the second drain electrode 67, and the second gate wiring 65 is electrically connected to the second gate electrode 68.

[0082] Although not shown, the second source electrode 66 may be electrically connected to the second semiconductor substrate 51. The second semiconductor substrate 51 is electrically connected to the die pad 70 through the conductive bonding material SD shown in Fig. 4. Therefore, the second source wiring 63 is electrically connected to the die pad 70 through the second source electrode 66 and the second semiconductor substrate 51.

[0083] Although not shown, the second gate wiring 65 is electrically connected to a second input pad 50A (see FIG. 3) of the second semiconductor chip 50. The second drain wiring 64 is electrically connected to a second output pad 50B (see FIG. 3) of the second semiconductor chip 50.

[0084] [Active Region and Inactive Region of Semiconductor Chip] As shown in FIG. 7 , the first semiconductor chip 30 includes a first active region 37 where 2DEG 36 is generated and a first inactive region 38 where the generation of 2DEG 36 is reduced or inhibited. The first inactive region 38 is provided in a region including the first electron supply layer 34 and the first electron transit layer 33. The first inactive region 38 is doped with an impurity that reduces or inhibits the generation of 2DEG 36. This impurity may include, for example, at least one of helium (He), boron (B), nitrogen (N), oxygen (O), fluorine (F), and argon (Ar). The first inactive region 38 may have a higher resistance than the first active region 37.

[0085] As a result, in the first active region 37, 2DEG 36 is generated in the first electron transit layer 33. On the other hand, in the first inactive region 38, the generation of 2DEG 36 in the first electron transit layer 33 is reduced or prevented. In other words, the first inactive region 38 can be said to be a region where 2DEG 36 is less likely to be generated. At least a portion of the 2DEG 36 in the first electron transit layer 33 in the first active region 37 can function as a channel of the first semiconductor chip 30.

[0086] As shown in FIG. 5 , the first active region 37 is a region extending in the X and Y directions in a plan view. In the example shown in FIG. 5 , the first active region 37 is rectangular with its long side extending in the X direction and its short side extending in the Y direction. That is, the long side direction of the first active region 37 coincides with the long side direction of the first semiconductor chip 30. Furthermore, the long side direction of the first active region 37 coincides with the arrangement direction of the multiple first source fingers 43B of the first source wiring 43 and the multiple first drain fingers 44B of the first drain wiring 44. Furthermore, the long side direction of the first active region 37 coincides with the arrangement direction of the multiple first gate electrodes 48.

[0087] In the first embodiment, the first active region 37 is arranged at the center of the first semiconductor chip 30 in the Y direction. The first active region 37 is arranged at the center of the first semiconductor chip 30 in the X direction. The Y-direction dimension RY1 of the first active region 37 is smaller than the Y-direction dimension SF1 of the first source finger 43B of the first source wiring 43. The Y-direction dimension RY1 of the first active region 37 is smaller than the Y-direction dimension DF1 of the first drain finger 44B of the first drain wiring 44. In the first embodiment, the X-direction dimension RX1 of the first active region 37 is smaller than the X-direction dimension BX1 of the first base portion 44A. Each of the multiple first drain fingers 44B includes a portion that is arranged within the first active region 37 in a plan view. Each of the multiple first source fingers 43B includes a portion that is arranged within the first active region 37 in a plan view.

[0088] The first inactive region 38 is a region that surrounds the first active region 37 in a plan view. The first inactive region 38 is provided from the first active region 37 to the periphery of the first semiconductor chip 30 in a plan view.

[0089] The first inactive region 38 includes a first region 38A and a second region 38B adjacent to the first active region 37 in the Y direction, and a third region 38C and a fourth region 38D adjacent to the first active region 37 in the X direction.

[0090] The first region 38A is a region that is provided closer to one side in the Y direction than the first active region 37 in a plan view. The first region 38A includes a region that overlaps with the first base portion 44A of the first drain wiring 44 in a plan view.

[0091] The second region 38B is a region that is provided closer to the other side in the Y direction than the first active region 37 in a plan view. It can also be said that the first active region 37 is provided between the first region 38A and the second region 38B in the Y direction. The second region 38B includes a region that overlaps with both the first base portion 43A of the first source wiring 43 and the first gate wiring 45 in a plan view.

[0092] The third region 38C is a region that is provided closer to one side in the X direction than the first active region 37 in a plan view. It can also be said that the third region 38C is a region that is provided closer to one side in the X direction than the multiple first source fingers 43B of the first source wiring 43, the multiple first drain fingers 44B of the first drain wiring 44, and the multiple first gate electrodes 48 in a plan view.

[0093] The fourth region 38D is a region that is provided closer to the other side in the X direction than the first active region 37 in a plan view. It can also be said that the first active region 37 is provided between the third region 38C and the fourth region 38D in the Y direction. It can also be said that the fourth region 38D is a region that is provided closer to the other side in the X direction than the multiple first source fingers 43B of the first source wiring 43, the multiple first drain fingers 44B of the first drain wiring 44, and the multiple first gate electrodes 48 in a plan view.

[0094] 10 , the second semiconductor chip 50 includes a second active region 57 where 2DEG 56 is generated and a second inactive region 58 where the generation of 2DEG 56 is reduced or inhibited. The second inactive region 58 is provided in a region including the second cap layer 55, the second electron supply layer 54, and the second electron transit layer 53. The second inactive region 58 is doped with an impurity that reduces or inhibits the generation of 2DEG 56. The impurity may include, for example, at least one of helium, boron, nitrogen, oxygen, fluorine, and argon. The second inactive region 58 may have a higher resistance than the second active region 57.

[0095] As a result, in the second active region 57, 2DEG 56 is generated in the second electron transit layer 53. On the other hand, in the second inactive region 58, the generation of 2DEG 56 in the second electron transit layer 53 is reduced or prevented. In other words, the second inactive region 58 can be said to be a region where 2DEG 56 is less likely to be generated. At least a portion of the 2DEG 56 in the second electron transit layer 53 in the second active region 57 can function as a channel of the second semiconductor chip 50.

[0096] As shown in FIG. 8 , the second active region 57 is a region extending in the X and Y directions in a plan view. In the example shown in FIG. 8 , the second active region 57 is rectangular with its long side extending in the X direction and its short side extending in the Y direction. That is, the long side direction of the second active region 57 coincides with the long side direction of the second semiconductor chip 50. Furthermore, the long side direction of the second active region 57 coincides with the arrangement direction of the multiple second source fingers 63B of the second source wiring 63 and the multiple second drain fingers 64B of the second drain wiring 64. Furthermore, the long side direction of the second active region 57 coincides with the arrangement direction of the multiple second gate electrodes 68.

[0097] In the first embodiment, the second active region 57 is disposed at the center of the second semiconductor chip 50 in the Y direction. The second active region 57 is disposed at the center of the second semiconductor chip 50 in the X direction. In one example, the second active region 57 is disposed at a position adjacent to the second base portion 63A of the second source wiring 63 in a plan view. In this way, the first active region 37 is provided so that its center in the Y direction is at the same position as the center in the Y direction of the second active region 57.

[0098] The Y-direction dimension RY2 of the second active region 57 is smaller than the Y-direction dimension SF2 of the second source finger 63B of the second source wiring 63. The Y-direction dimension RY2 of the second active region 57 is smaller than the Y-direction dimension DF2 of the second drain finger 64B of the second drain wiring 64. In the first embodiment, the X-direction dimension RX2 of the second active region 57 is smaller than the X-direction dimension BX2 of the second base portion 64A of the second drain wiring 64. Each of the multiple second drain fingers 64B includes a portion that is arranged within the second active region 57 in a plan view. Each of the multiple second source fingers 63B includes a portion that is arranged within the second active region 57 in a plan view.

[0099] The second inactive region 58 is a region that surrounds the second active region 57 in a plan view. The second inactive region 58 is provided from the second active region 57 to the periphery of the second semiconductor chip 50 in a plan view.

[0100] The second inactive region 58 includes a fifth region 58A and a sixth region 58B adjacent to the second active region 57 in the Y direction, and a seventh region 58C and an eighth region 58D adjacent to the second active region 57 in the X direction.

[0101] The fifth region 58A is a region that is provided closer to one side in the Y direction than the second active region 57 in a plan view. The fifth region 58A includes a region that overlaps with the second base portion 64A of the second drain wiring 64 in a plan view.

[0102] The sixth region 58B is a region that is provided closer to the other side in the Y direction than the second active region 57 in a plan view. In other words, the second active region 57 is provided between the fifth region 58A and the sixth region 58B in the Y direction. The sixth region 58B includes a region that overlaps with both the second base portion 63A of the second source wiring 63 and the second gate wiring 65 in a plan view.

[0103] The seventh region 58C is a region that is provided closer to one side in the X direction than the second active region 57 in a plan view. It can also be said that the seventh region 58C is a region that is provided closer to one side in the X direction than the second source fingers 63B of the second source wiring 63, the second drain fingers 64B of the second drain wiring 64, and the second gate electrodes 68 in a plan view.

[0104] The eighth region 58D is a region that is provided closer to the other side in the X direction than the second active region 57 in a plan view. It can also be said that the second active region 57 is provided between the seventh region 58C and the eighth region 58D in the Y direction. It can also be said that the eighth region 58D is a region that is provided closer to the other side in the X direction than the multiple second source fingers 63B of the second source wiring 63, the multiple second drain fingers 64B of the second drain wiring 64, and the multiple second gate electrodes 68 in a plan view.

[0105] 11, an example of the dimensions of the first active region 37, the first inactive region 38, the second active region 57, and the second inactive region 58. In FIG. 11, the boundaries between the first to fourth regions 38A to 38D of the first inactive region 38 are indicated by dashed dotted lines, and the boundaries between the fifth to eighth regions 58A to 58D of the second inactive region 58 are indicated by dashed dotted lines.

[0106] The X-direction dimension RX1 of the first active region 37 is larger than the Y-direction dimension RY1 of the first active region 37. The X-direction dimension RX1 of the first active region 37 is smaller than the X-direction dimension RX2 of the second active region 57. The Y-direction dimension RY1 of the first active region 37 is smaller than the Y-direction dimension RY2 of the second active region 57.

[0107] The X-direction dimension PX1 of the first region 38A in the first inactive region 38 is larger than the Y-direction dimension PY1 of the first region 38A. The X-direction dimension PX2 of the second region 38B is larger than the Y-direction dimension PY2 of the second region 38B. The dimension PX1 is equal to the dimension PX2. The dimension PY1 is equal to the dimension PY2. Therefore, in a plan view, the area of ​​the first region 38A is equal to the area of ​​the second region 38B.

[0108] The X-direction dimension PX1 of the first region 38A is larger than the X-direction dimension RX1 of the first active region 37. The Y-direction dimension PY1 of the first region 38A is larger than the Y-direction dimension RY1 of the first active region 37. The X-direction dimension PX2 of the second region 38B is larger than the X-direction dimension RX1 of the first active region 37. The Y-direction dimension PY2 of the second region 38B is larger than the Y-direction dimension RY1 of the first active region 37. Therefore, the area of ​​the first region 38A and the area of ​​the second region 38B are each larger than the area of ​​the first active region 37 in a plan view.

[0109] The dimension PY1 in the Y direction of the first region 38A is larger than the dimension PX3 in the X direction of the third region 38C. The dimension PY1 is larger than the dimension PY3 in the Y direction of the third region 38C. The dimension PY1 is larger than the dimension PX4 in the X direction of the fourth region 38D. The dimension PY1 is larger than the dimension PY4 in the Y direction of the fourth region 38D.

[0110] The dimension PY2 in the Y direction of the second region 38B is larger than the dimension PX3 in the X direction of the third region 38C. The dimension PY2 is larger than the dimension PY3 in the Y direction of the third region 38C. The dimension PY2 is larger than the dimension PX4 in the X direction of the fourth region 38D. The dimension PY2 is larger than the dimension PY4 in the Y direction of the fourth region 38D.

[0111] The X-direction dimension PX3 of the third region 38C is smaller than the X-direction dimension RX1 of the first active region 37. The X-direction dimension PX4 of the fourth region 38D is smaller than the X-direction dimension RX1 of the first active region 37. The sum of the dimensions PX3 and PX4 is smaller than the dimension RX1. The Y-direction dimension PY3 of the third region 38C and the Y-direction dimension PY4 of the fourth region 38D are equal to each other. Therefore, in a plan view, the area of ​​the third region 38C is equal to the area of ​​the fourth region 38D. Furthermore, the dimensions PY3 and PY4 are equal to the Y-direction dimension RY1 of the first active region 37. Therefore, the sum of the areas of the third region 38C and the fourth region 38D is smaller than the area of ​​the first active region 37.

[0112] The X-direction dimension PX5 of the fifth region 58A in the second inactive region 58 is larger than the Y-direction dimension PY5 of the fifth region 58A. The X-direction dimension PX6 of the sixth region 58B is larger than the Y-direction dimension PY6 of the sixth region 58B. The dimension PX5 is equal to the dimension PX6. The dimension PY5 is equal to the dimension PY6. Therefore, in a plan view, the area of ​​the fifth region 58A is equal to the area of ​​the sixth region 58B.

[0113] The X-direction dimension PX7 of the seventh region 58C in the second inactive region 58 is equal to the X-direction dimension PX8 of the eighth region 58D. The Y-direction dimension PY7 of the seventh region 58C is equal to the Y-direction dimension PY8 of the eighth region 58D. Therefore, in a plan view, the area of ​​the seventh region 58C is equal to the area of ​​the eighth region 58D. In one example, the dimension PX7 is equal to the X-direction dimension PX3 of the third region 38C in the first inactive region 38. In one example, the dimension PX8 is equal to the dimension PX3. In one example, the dimension PX7 is equal to the X-direction dimension PX4 of the fourth region 38D in the first inactive region 38. In one example, the dimension PX8 is equal to the dimension PX4.

[0114] The X-direction dimension PX7 of the seventh region 58C is smaller than the X-direction dimension RX2 of the second active region 57. The X-direction dimension PX8 of the eighth region 58D is smaller than the X-direction dimension RX2 of the second active region 57. The sum of the dimensions PX7 and PX8 is smaller than the dimension RX2. The Y-direction dimension PY7 of the seventh region 58C and the Y-direction dimension PY8 of the eighth region 58D are equal to each other. Therefore, in a plan view, the area of ​​the seventh region 58C is equal to the area of ​​the eighth region 58D. Furthermore, the dimensions PY7 and PY8 are equal to the Y-direction dimension RY2 of the second active region 57. Therefore, the sum of the areas of the seventh region 58C and the eighth region 58D is smaller than the area of ​​the second active region 57.

[0115] The X-direction dimension PX5 of the fifth region 58A is larger than the X-direction dimension PX1 of the first region 38A. The Y-direction dimension PY1 of the first region 38A is larger than the Y-direction dimension PY5 of the fifth region 58A. The X-direction dimension PX6 of the sixth region 58B is larger than the X-direction dimension PX2 of the second region 38B. The Y-direction dimension PY2 of the second region 38B is larger than the Y-direction dimension PY6 of the sixth region 58B. Therefore, the sum of the Y-direction dimension PY1 of the first region 38A and the Y-direction dimension PY2 of the second region 38B is larger than the sum of the Y-direction dimension PY5 of the fifth region 58A and the Y-direction dimension PY6 of the sixth region 58B. In other words, the sum of the Y-direction dimensions of the first inactive regions 38 arranged on both sides of the first active region 37 in the Y direction (first direction) is greater than the sum of the Y-direction dimensions of the second inactive regions 58 arranged on both sides of the second active region 57 in the Y direction.

[0116] 11 , a first ratio of the area of ​​the first inactive region 38 to the area of ​​the first active region 37 in a plan view is greater than a second ratio of the area of ​​the second inactive region 58 to the area of ​​the second active region 57 in a plan view. In one example, the first ratio may be 1.5 times or more the second ratio. In one example, the first ratio may be approximately twice the second ratio.

[0117] In a plan view, the ratio of the Y-direction dimension RY1 of the first active region 37 to the Y-direction dimension LY1 of the first semiconductor chip 30 is smaller than the ratio of the Y-direction dimension PY1 of the second active region 57 to the Y-direction dimension LY2 of the second semiconductor chip 50. In addition, in a plan view, the ratio of the X-direction dimension RX1 of the first active region 37 to the X-direction dimension LX1 of the first semiconductor chip 30 is smaller than the ratio of the X-direction dimension PX2 of the second active region 57 to the X-direction dimension LX2 of the second semiconductor chip 50. Therefore, it can be said that the ratio of the area of ​​the first active region 37 to the area of ​​the first semiconductor chip 30 (LY1 × LX1) in a plan view is smaller than the ratio of the area of ​​the second active region 57 to the area of ​​the second semiconductor chip 50 (LY2 × LX2) in a plan view.

[0118] In a plan view, the multiple first gate electrodes 48 extend through the first active region 37 in the Y direction. The multiple second gate electrodes 68 extend through the second active region 57 in the Y direction. In the first embodiment, the Y direction dimension of each first gate electrode 48 is equal to the Y direction dimension of each second gate electrode 68. As described above, in a plan view, the number of the multiple second gate electrodes 68 arranged in the second active region 57 is greater than the number of the multiple first gate electrodes 48 arranged in the first active region 37. The sum of the Y direction dimensions of the multiple second gate electrodes 68 in the second active region 57 is 1.5 times or more the sum of the Y direction dimensions of the multiple first gate electrodes 48 in the first active region 37.

[0119] Here, the Y-direction dimension of the first gate electrode 48 in the first active region 37 is the sum of the Y-direction dimensions of the multiple first gate electrodes 48 arranged in the first active region 37 in a plan view. The Y-direction dimension of each first gate electrode 48 in the first active region 37 is equal to the Y-direction dimension RY1 of the first active region 37. Furthermore, the Y-direction dimension of the second gate electrode 68 in the second active region 57 is the sum of the Y-direction dimensions of the multiple second gate electrodes 68 arranged in the second active region 57 in a plan view. The Y-direction dimension of each second gate electrode 68 is equal to the Y-direction dimension RY2 of the second active region 57.

[0120] Furthermore, the areas of the first active region 37 and the second active region 57, and the numbers and Y-direction dimensions of the first gate electrodes 48 and the second gate electrodes 68 may be set so that the maximum output of the semiconductor device 20 divided by the sum of the Y-direction dimensions of the plurality of first gate electrodes 48 in the first active region 37 and the sum of the Y-direction dimensions of the plurality of second gate electrodes 68 in the second active region 57 is 5 W / mm or more.

[0121] [Manufacturing Method of Semiconductor Device] An example of a manufacturing method of the semiconductor device 20 will be described with reference to FIGS. 12 to 21. FIGS. 13 to 20 schematically show a cross-sectional structure taken along line FA-FA in FIG. 12 in an exemplary manufacturing process of the semiconductor device 20. FIG. 21 schematically shows an enlarged planar structure of a portion of a semiconductor wafer 800, which will be described later. For ease of understanding, components in FIGS. 12 to 20 that are common to FIGS. 6, 7, 9, and 10 are designated by the same reference numerals. As shown in FIG. 12, the manufacturing method of the semiconductor device 20 described below will be described mainly using the cross-sectional structure of a portion of the semiconductor wafer 800.

[0122] As shown in FIG. 12 , the manufacturing method of the semiconductor device 20 includes preparing a semiconductor wafer 800. The semiconductor wafer 800 constitutes the first semiconductor substrate 31 of the first semiconductor chip 30 and the second semiconductor substrate 51 of the second semiconductor chip 50. The semiconductor wafer 800 includes a plurality of first semiconductor substrates 31 and a plurality of second semiconductor substrates 51. For example, a silicon carbide wafer (SiC wafer) may be used as the semiconductor wafer 800. The semiconductor wafer 800 includes a first surface 801 and a second surface 802 (see FIG. 13 ) opposite the first surface 801. The enlarged view of a portion of the semiconductor wafer 800 in FIG. 12 shows a plurality of first chip regions C1 where the first semiconductor chips 30 (see FIG. 3 ) are formed and a plurality of second chip regions C2 where the second semiconductor chips 50 (see FIG. 5 ) are formed. The areas of the semiconductor wafer 800 between adjacent first chip areas C1 and second chip areas C2, the areas between adjacent first chip areas C1, and the areas between adjacent second chip areas C2 are cutting areas C3 where the semiconductor wafer 800 is cut.

[0123] The multiple first chip regions C1 are arranged spaced apart from one another in the Y direction. The multiple second chip regions C2 are arranged spaced apart from one another in the Y direction. The first chip regions C1 and the second chip regions C2 are arranged alternately one by one in the X direction. In this manner, the multiple first chip regions C1 and the multiple second chip regions C2 are arranged in a matrix in plan view. In the following description of the manufacturing method for semiconductor device 20, the cross-sectional structures of a portion of one first chip region C1 and a portion of one second chip region C2 will be described.

[0124] 13 , the method for manufacturing the semiconductor device 20 includes sequentially forming a buffer layer 812, an electron transit layer 813, an electron supply layer 814, and a cap layer 815 on a first surface 801 of a semiconductor wafer 800. Each of the buffer layer 812, the electron transit layer 813, the electron supply layer 814, and the cap layer 815 is formed by epitaxial growth on the first surface 801 of the semiconductor wafer 800 using, for example, a metal organic chemical vapor deposition (MOCVD) method.

[0125] The buffer layer 812 may include a first buffer layer that is an aluminum nitride layer (AlN layer) formed on the first side 801 of the semiconductor wafer 800, and a second buffer layer that is an aluminum gallium nitride layer (AlGaN layer) formed on the aluminum nitride layer. The buffer layer 812 may have a thickness of approximately 0.5 μm. More specifically, the first buffer layer may have a thickness of approximately 0.3 μm. The second buffer layer may have a thickness of approximately 0.2 μm.

[0126] The electron transit layer 813 formed on the buffer layer 812 may be a gallium nitride layer (n-type GaN layer) doped with donor impurities and may have a thickness of about 0.2 μm.

[0127] The electron supply layer 814 formed on the electron transit layer 813 is made of Al ｘ Ga １－ｘN, where x=0.2. The electron transit layer 813 may have a thickness of approximately 20 nm. By forming a heterojunction between the electron transit layer 813 and the electron supply layer 814, a two-dimensional electron gas (2DEG) 816 is formed in the electron transit layer 813 near the interface between the electron transit layer 813 and the electron supply layer 814.

[0128] The cap layer 815 formed on the electron supply layer 814 may be a gallium nitride layer (n-type GaN layer) doped with donor impurities and may have a thickness of about 2 nm.

[0129] 14 , the manufacturing method for semiconductor device 20 includes forming inactive region 818. Inactive region 818 is a region that includes first inactive region 38 of first semiconductor chip 30 (see FIG. 5 ) and second inactive region 58 of second semiconductor chip 50 (see FIG. 8 ). Therefore, in a plan view, a region of first surface 801 of semiconductor wafer 800 that is different from inactive region 818 becomes active region 817. Active region 817 is a region that includes first active region 37 of first semiconductor chip 30 (see FIG. 5 ) and second active region 57 of second semiconductor chip 50 (see FIG. 8 ).

[0130] A plurality of active regions 817 are formed corresponding to the first chip region C1 and the second chip region C2. In the example shown in FIG. 14 , the plurality of active regions 817 include a first active region 817A and a second active region 817B spaced apart in the X direction. The first active region 817A is formed in the first chip region C1. The second active region 817B is formed in the second chip region C2. The inactive region 818 is formed across the first chip region C1, the second chip region C2, and the cutting region C3. The inactive region 818 is formed to surround each of the plurality of active regions 817.

[0131] This process includes, for example, forming a resist mask as a mask only in regions of the cap layer 815 (see FIG. 13 ) corresponding to the first active region 817A and the second active region 817B, and ion-implanting impurities into both the first active region 817A, the second active region 817B, and the inactive region 818 to reduce or inhibit the generation of 2DEG 816 (see FIG. 13 ). As a result, the impurities are introduced into the inactive region 818 where the resist mask is not formed. The impurities are introduced into the cap layer 815, the electron supply layer 814, and the electron transit layer 813 (all see FIG. 13 ). Meanwhile, the impurities are not introduced into the cap layer 815, the electron supply layer 814, and the electron transit layer 813 in the active region 817 where the resist mask is formed. The impurities may include at least one of helium, boron, nitrogen, oxygen, fluorine, and argon.

[0132] As shown in FIG. 15 , the manufacturing method of the semiconductor device 20 includes forming a first source electrode 46, a first drain electrode 47, a second source electrode 66, and a second drain electrode 67. In this process, a first metal layer (not shown) is formed on the cap layer 815 by, for example, electron beam evaporation. The first source electrode 46, the first drain electrode 47, the second source electrode 66, and the second drain electrode 67 shown in FIGS. 7 and 10 are formed by part of the first metal layer. The first metal layer may have a stacked structure of a titanium layer, an aluminum layer, a nickel layer, and a gold layer. The titanium layer is in contact with the cap layer 815. Subsequently, an ohmic contact is formed between the first metal layer and the cap layer 815 by annealing. Subsequently, the first metal layer is selectively removed by etching. As a result, the first source electrode 46, the first drain electrode 47, the second source electrode 66, and the second drain electrode 67 are formed on the cap layer 815.

[0133] As shown in FIG. 16 , the method for manufacturing the semiconductor device 20 includes forming a first insulating layer 820. In this step, the first insulating layer 820 is formed by, for example, plasma-enhanced vapor deposition (PECVD). The first insulating layer 820 is formed to cover the cap layer 815, the first source electrode 46, the first drain electrode 47, the second source electrode 66, and the second drain electrode 67. The first insulating layer 820 may be made of, for example, silicon nitride. The first insulating layer 820 may have a thickness of approximately 100 nm. In another example, the first insulating layer 820 may be formed by low-pressure chemical vapor deposition (LPCVD) or molecular beam epitaxy (MBE).

[0134] As shown in FIG. 17 , the method for manufacturing the semiconductor device 20 includes forming the first gate electrode 48 and the second gate electrode 68. In this process, the first insulating layer 820 is first selectively removed by etching, thereby forming a gate contact opening 821 in the first insulating layer 820. Next, a second metal layer (not shown) is formed on the first insulating layer 820. The second metal layer is embedded in the gate contact opening 821. The second metal layer may have a stacked structure of a nickel layer and a gold layer. The nickel layer is in contact with the surface of the cap layer 815 exposed by the gate contact opening 821. A Schottky junction is formed between the second metal layer and the cap layer 815. Next, the second metal layer is selectively removed by etching, thereby forming the first gate electrode 48 and the second gate electrode 68.

[0135] 18 , the method for manufacturing the semiconductor device 20 includes forming a second insulating layer 830. In this step, the second insulating layer 830 is formed by, for example, a PECVD method. The second insulating layer 830 is formed to cover the first insulating layer 820, the first gate electrode 48, and the second gate electrode 68. The second insulating layer 830 is made of silicon oxide. The second insulating layer 830 may have a thickness of approximately 500 nm. In another example, the second insulating layer 830 may be formed by an LPCVD method, a sputtering method, an atomic layer deposition (ALD) method, or an MBE method.

[0136] As shown in FIG. 19, the method for manufacturing semiconductor device 20 includes forming a first source wiring 43, a first drain wiring 44, a first gate wiring 45, a second source wiring 63, a second drain wiring 64, and a second gate wiring 65.

[0137] In this process, the second insulating layer 830 and the first insulating layer 820 are first selectively removed by etching. This forms a source contact opening 831, a drain contact opening 832, and a gate contact opening (not shown). The source contact opening 831 exposes the first source electrode 46 and the second source electrode 66, respectively. The drain contact opening 832 exposes the first drain electrode 47 and the second drain electrode 67, respectively. The gate contact opening exposes the first gate electrode 48 and the second gate electrode 68, respectively.

[0138] Next, a third metal layer (not shown) is formed on the second insulating layer 830. The third metal layer is embedded in the source contact opening 831, the drain contact opening 832, and the gate contact opening. The first source wiring 43, the first drain wiring 44, the first gate wiring 45 (see FIG. 5), the second source wiring 63, the second drain wiring 64, and the second gate wiring 65 (see FIG. 8) are formed from part of the third metal layer. The third metal layer may have a stacked structure of a platinum layer and a gold layer. Next, the third metal layer is patterned. As a result, the first source wiring 43, the first drain wiring 44, the first gate wiring 45, the second source wiring 63, the second drain wiring 64, and the second gate wiring 65 are formed.

[0139] 20 and 21 , the manufacturing method of the semiconductor device 20 includes dividing the semiconductor wafer 800 into individual pieces. In this step, the semiconductor wafer 800 is cut by, for example, dicing along cutting lines CL shown by dashed lines in FIGS. 20 and 21 . This forms a plurality of first semiconductor chips 30 and a plurality of second semiconductor chips 50. The cutting lines CL are straight lines extending in the X and Y directions in the cutting region C3.

[0140] After that, although not shown, the manufacturing method of semiconductor device 20 includes mounting each of first semiconductor chip 30 and second semiconductor chip 50 on die pad 70 (see FIG. 3), forming wires W1 to W4 (see FIG. 3), and forming sealing resin 90 (see FIG. 4). Through the above steps, semiconductor device 20 is manufactured.

[0141] [Operation of First Embodiment] The operation of the semiconductor device 20 of the first embodiment will be described. In the Doherty amplifier 10, the carrier amplifier 13 always operates, while the peak amplifier 14 operates only when the output is above a certain level. For this reason, the carrier transistor TC of the carrier amplifier 13 is more likely to generate heat than the peak transistor TP of the peak amplifier 14. In other words, the first semiconductor chip 30 is more likely to generate heat than the second semiconductor chip 50.

[0142] Incidentally, the region of the first semiconductor chip 30 that is likely to generate heat is the first active region 37. On the other hand, the first inactive region 38 is less likely to generate heat. For this reason, heat from the first active region 37 of the first semiconductor chip 30 moves to the first inactive region 38. In view of this, if the area of ​​the first active region 37 is reduced and the area of ​​the first inactive region 38 is increased, heat from the first active region 37 moves more easily to the first inactive region 38.

[0143] Furthermore, in order to suppress variations in the electrical characteristics (e.g., gate threshold voltage) of the carrier transistors TC and the peak transistors TP, it is desirable that the first semiconductor chip 30 and the second semiconductor chip 50 be manufactured so that they include carrier transistors TC and peak transistors TP in regions close to each other on the same semiconductor wafer 800. Therefore, the semiconductor wafer 800 is manufactured so that the region where the carrier transistors TC are formed and the region where the peak transistors TP are formed are adjacent to each other. Since this semiconductor wafer 800 is diced into a grid pattern, the sides of the regions where the carrier transistors TC are formed and the regions where the peak transistors TP are formed in a common direction (e.g., the Y direction) have the same length. In other words, the Y direction dimension of the first semiconductor chip 30 and the Y direction dimension of the second semiconductor chip 50 are the same length.

[0144] Based on this premise, in the semiconductor device 20 of the first embodiment, the sum of the Y-direction dimensions PY1 and PY2 of the first inactive regions 38 arranged on both sides of the first active region 37 in the first semiconductor chip 30 in the Y direction is made larger than the sum of the Y-direction dimensions PY5 and PY6 of the second inactive regions 58 arranged on both sides of the second active region 57 in the second semiconductor chip 50 in the Y direction. This reduces the area of ​​the first active region 37 and increases the area of ​​the first inactive region 38, making it easier for heat from the first active region 37 to move to the first inactive region 38. This makes it possible to improve the heat dissipation performance of the first semiconductor chip 30.

[0145] Effects of the First Embodiment The semiconductor device 20 of the first embodiment has the following effects: (1-1) The semiconductor device 20 includes a first semiconductor chip 30 including a carrier transistor TC that constitutes a part of the carrier amplifier 13, and a second semiconductor chip 50 including a peak transistor TP that constitutes a part of the peak amplifier 14. The first semiconductor chip 30 includes a first electron transit layer 33, a first electron supply layer 34 provided on the first electron transit layer 33 and having a band gap larger than that of the first electron transit layer 33, a first active region 37 extending in the X and Y directions in a planar view as a region where two-dimensional electron gas (2DEG) 36 is generated, a first inactive region 38 surrounding the first active region 37 in a planar view as a region where 2DEG 36 is less likely to be generated than in the first active region 37, and a first source electrode 46, a first gate electrode 48, and a first drain electrode 47 provided above the first electron supply layer 34 in the first active region 37, extending in the Y direction, and spaced apart from each other in the X direction. The second semiconductor chip 50 includes a second electron transit layer 53, a second electron supply layer 54 provided on the second electron transit layer 53 and having a larger bandgap than the second electron transit layer 53, a second active region 57 extending in the X and Y directions and in which two-dimensional electron gas (2DEG) 56 is generated, a second inactive region 58 surrounding the second active region 57 in plan view and in which 2DEG 56 is less likely to be generated in the peak transistor TP than in the second active region 57, and a second source electrode 66, a second gate electrode 68, and a second drain electrode 67 provided in the second active region 57 above the second electron supply layer 54, extending in the Y direction, and spaced apart from each other in the X direction. In plan view, a dimension LY1 in the Y direction of the first semiconductor chip 30 is equal to a dimension LY2 in the Y direction of the second semiconductor chip 50. The sum of the Y-direction dimensions PY1 and PY2 of the first inactive regions 38 arranged on both sides of the first active region 37 in the Y direction is greater than the sum of the Y-direction dimensions PY5 and PY6 of the second inactive regions 58 arranged on both sides of the second active region 57 in the Y direction.

[0146] This configuration makes it possible to reduce the area of ​​the first active region 37, which is prone to heat generation, while increasing the area of ​​the first inactive region 38, which is difficult to heat generation. This makes it easier for heat from the first active region 37 to move to the first inactive region 38, thereby improving the heat dissipation performance of the first semiconductor chip 30. Therefore, the heat dissipation performance of the semiconductor device 20 can be improved.

[0147] (1-2) The first inactive region 38 includes a first region 38A and a second region 38B adjacent to the first active region 37 in the Y direction, and a third region 38C and a fourth region 38D adjacent to the first active region 37 in the X direction. The second inactive region 58 includes a fifth region 58A and a sixth region 58B adjacent to the second active region 57 in the Y direction, and a seventh region 58C and an eighth region 58D adjacent to the second active region 57 in the X direction. The Y-direction dimensions PY1 and PY2 of both the first region 38A and the second region 38B are larger than the Y-direction dimensions PY5 and PY6 of both the fifth region 58A and the sixth region 58B.

[0148] According to this configuration, the areas of the first inactive regions 38 on both sides of the first active region 37 in the Y direction can be increased. This makes it easier for heat from the first active region 37 to move to the first inactive regions 38 on both sides in the Y direction. In other words, heat from the first active region 37 moves more easily to both sides in the Y direction. This makes it possible to improve the heat dissipation performance of the first semiconductor chip 30.

[0149] (1-3) The Y-direction dimensions PY1, PY2 of the first region 38A and the second region 38B are larger than the X-direction dimensions PX3, PX4 of the third region 38C and the fourth region 38D. With this configuration, the Y-direction dimensions of the first region 38A and the second region 38B, which are regions that contact the first active region 37 with a large area, are large, and therefore heat from the first active region 37 is more likely to move to the first inactive region 38. This improves the heat dissipation performance of the first semiconductor chip 30.

[0150] (1-4) The dimension LY1 in the Y direction of the first semiconductor chip 30 is larger than the dimension LX1 in the X direction of the first semiconductor chip 30. With this configuration, the dimensions PY1, PY2 in the Y direction of the first region 38A and the second region 38B can be increased. This increases the areas of the first region 38A and the second region 38B, thereby increasing the heat capacity of the first region 38A and the second region 38B. Because heat from the first active region 37 can more easily move to the first region 38A and the second region 38B, the heat dissipation performance of the first semiconductor chip 30 can be improved.

[0151] (1-5) The Y-direction dimension RY1 of the first active region 37 is smaller than the Y-direction dimension RY2 of the second active region 57. With this configuration, the Y-direction dimensions PY1, PY2 of the first region 38A and the second region 38B can be increased. In other words, the heat capacities of the first region 38A and the second region 38B can be increased. Therefore, heat from the first active region 37 can be more easily transferred to the first region 38A and the second region 38B, thereby improving the heat dissipation performance of the first semiconductor chip 30.

[0152] (1-6) The total length in the Y direction of the second gate electrodes 68 in the second active region 57 is 1.5 times or more the total length in the Y direction of the first gate electrodes 48 in the first active region 37. This configuration can widen the range of output power that is backed off in the Doherty amplifier 10.

[0153] (1-7) The first semiconductor chip 30 includes an insulating layer 40 covering the first source electrode 46, the first drain electrode 47, and the first gate electrode 48, a first source wiring 43 provided on the insulating layer 40 and electrically connected to the first source electrode 46, and a first drain wiring 44 provided on the insulating layer 40 and electrically connected to the first drain electrode 47. The second semiconductor chip 50 includes an insulating layer 60 covering the second source electrode 66, the second drain electrode 67, and the second gate electrode 68, a second source wiring 63 provided on the insulating layer 60 and electrically connected to the second source electrode 66, and a second drain wiring 64 provided on the insulating layer 60 and electrically connected to the second drain electrode 67. The Y-direction dimension SF1 of the first source wiring 43 is equal to the Y-direction dimension SF2 of the second source wiring 63. The Y-direction dimension DF1 of the first drain wiring 44 is equal to the Y-direction dimension DF2 of the second drain wiring 64.

[0154] According to this configuration, in the manufacturing process of the semiconductor device 20, masks of the same shape can be used for the first source wiring 43 and the second source wiring 63, and masks of the same shape can be used for the first drain wiring 44 and the second drain wiring 64. Therefore, the first source wiring 43, the second source wiring 63, the first drain wiring 44, and the second drain wiring 64 can be formed more easily than in a case where the first source wiring 43 and the second source wiring 63 have different dimensions and the first drain wiring 44 and the second drain wiring 64 have different dimensions.

[0155] (1-8) The value obtained by dividing the maximum output of the semiconductor device 20 by the sum of the Y-direction dimensions of the first gate electrodes 48 in the first active region 37 and the Y-direction dimensions of the second gate electrodes 68 in the second active region 57 is 5 W / mm or more. This configuration allows the Doherty amplifier 10 to have a wide back-off output power range.

[0156] (1-9) A first ratio of the area of ​​the first inactive region 38 to the area of ​​the first active region 37 in a plan view is greater than a second ratio of the area of ​​the second inactive region 58 to the area of ​​the second active region 57 in a plan view.

[0157] According to this configuration, the first semiconductor chip 30 can be structured to dissipate heat from the active region to the outside of the chip more easily than the second semiconductor chip 50. In other words, the heat dissipation performance of the first semiconductor chip 30, which is always operating, is higher than the heat dissipation performance of the second semiconductor chip 50, which operates only under predetermined conditions, and therefore the heat dissipation performance of the semiconductor device 20 can be improved.

[0158] (1-10) The first ratio is 1.5 times or more the second ratio. With this configuration, the first semiconductor chip 30 can be structured to dissipate heat from the active region to the outside of the chip more easily than the second semiconductor chip 50. In other words, the heat dissipation performance of the first semiconductor chip 30, which is always operating, is even higher than the heat dissipation performance of the second semiconductor chip 50, which operates only under specified conditions, and therefore the heat dissipation performance of the semiconductor device 20 can be further improved.

[0159] (1-11) In a planar view, the ratio (RY1 / LY1) of the Y-direction dimension RY1 of the first active region 37 to the Y-direction dimension LY1 of the first semiconductor chip 30 is smaller than the ratio (RY2 / LY2) of the Y-direction dimension RY2 of the second active region 57 to the Y-direction dimension LY2 of the second semiconductor chip 50.

[0160] This configuration makes it possible to reduce the area of ​​the first active region 37, which is prone to heat generation, while increasing the area of ​​the first inactive region 38, which is difficult to heat generation. This makes it easier for heat from the first active region 37 to move to the first inactive region 38, thereby improving the heat dissipation performance of the first semiconductor chip 30. Therefore, the heat dissipation performance of the carrier amplifier 13 can be improved.

[0161] (1-12) The first active region 37 is disposed in the center of the first semiconductor chip 30 in the Y direction. With this configuration, heat from the first active region 37 is transferred in a balanced manner to both the first region 38A and the second region 38B. This improves the heat dissipation performance of the first semiconductor chip 30.

[0162] 22 to 25, a semiconductor device 20 according to a second embodiment will be described. The semiconductor device 20 according to the second embodiment differs from the semiconductor device 20 according to the first embodiment mainly in that the carrier amplifier 13 and the peak amplifier 14 are provided on the same chip.

[0163] [General Structure of Semiconductor Device] The configuration of the semiconductor device 20 of the second embodiment will be described with reference to Figures 22 to 24. Figure 22 schematically shows the planar structure of a semiconductor chip 100, described later, in the semiconductor device 20 of the second embodiment. Figure 23 schematically shows the cross-sectional structure of the semiconductor chip 100 taken along line F23-F23 in Figure 22. Figure 24, like Figure 22, schematically shows the planar structure of the semiconductor chip 100. In Figure 24, inactive regions 143, described later, are dotted to make the drawing easier to understand.

[0164] 22 , the semiconductor device 20 includes a semiconductor chip 100. The semiconductor chip 100 is flat and has a thickness in the Z direction. The semiconductor chip 100 has a quadrangular shape extending in the X and Y directions in a plan view. In one example, the semiconductor chip 100 may have a rectangular shape with its long sides extending in the X direction and its short sides extending in the Y direction in a plan view.

[0165] The semiconductor chip 100 is provided with a carrier transistor TC that constitutes part of the carrier amplifier 13 (see FIG. 1 ) and a peak transistor TP that constitutes part of the peak amplifier 14 (see FIG. 1 ). More specifically, in a plan view, the semiconductor chip 100 can be divided into a carrier region RC in which the carrier transistor TC is formed and a peak region RP in which the peak transistor TP is formed. The carrier region RC and the peak region RP are aligned in the X direction. In other words, the carrier region RC and the peak region RP are aligned in the direction of the longer sides of the semiconductor chip 100. The dimension of the carrier region RC in the X direction is smaller than the dimension of the peak region RP in the X direction.

[0166] The semiconductor chip 100 may include an insulating layer 110, and a first source wiring 121, a first drain wiring 122, a first gate wiring 123, a second source wiring 124, a second drain wiring 125, and a second gate wiring 126 provided on the insulating layer 110.

[0167] The first source wiring 121, the first drain wiring 122, and the first gate wiring 123 are provided in the carrier region RC. The configurations of the first source wiring 121, the first drain wiring 122, and the first gate wiring 123 may be the same as those of the first source wiring 43, the first drain wiring 44, and the first gate wiring 45 of the first embodiment (see FIG. 5 ). Therefore, the first source wiring 121 includes a first base portion 121A, a plurality of first source fingers 121B, and a plurality of first pad portions 121C. The size of the first base portion 121A may be the same as that of the first base portion 43A of the first source wiring 43 of the first embodiment (see FIG. 5 ). The size and arrangement pitch of the plurality of first source fingers 121B may be the same as those of the plurality of first source fingers 43B of the first source wiring 43 of the first embodiment (see FIG. 5 ). The size and arrangement pitch of the multiple first pad portions 121C may be the same as those of the first pad portions 43C of the first source wiring 43 of the first embodiment (see FIG. 5 ). The first drain wiring 122 includes a first base portion 122A and multiple first drain fingers 122B. The size of the first base portion 122A may be the same as those of the first base portion 44A of the first drain wiring 44 of the first embodiment. The size and arrangement pitch of the multiple first drain fingers 122B may be the same as those of the multiple first drain fingers 44B of the first drain wiring 44 of the first embodiment.

[0168] The second source wiring 124, the second drain wiring 125, and the second gate wiring 126 are provided in the peak region RP. The configurations of the second source wiring 124, the second drain wiring 125, and the second gate wiring 126 may be the same as those of the second source wiring 63, the second drain wiring 64, and the second gate wiring 65 of the first embodiment (see FIG. 8 ). Therefore, the second source wiring 124 includes a second base portion 124A, a plurality of second source fingers 124B, and a plurality of second pad portions 124C. The size of the second base portion 124A may be the same as that of the second base portion 63A of the second source wiring 63 of the first embodiment (see FIG. 8 ). The size and arrangement pitch of the plurality of second source fingers 124B may be the same as those of the plurality of second source fingers 63B of the second source wiring 63 of the first embodiment (see FIG. 8 ). The size and arrangement pitch of the multiple second pad portions 124C may be the same as those of the second pad portions 63C of the second source wiring 63 of the first embodiment (see FIG. 8 ). The second drain wiring 125 also includes a second base portion 125A and multiple second drain fingers 125B. The size of the second base portion 125A may be the same as those of the second base portion 64A of the second drain wiring 64 of the first embodiment. The size and arrangement pitch of the multiple second drain fingers 125B may be the same as those of the multiple second drain fingers 64B of the second drain wiring 64 of the first embodiment.

[0169] 22 , similar to the first semiconductor chip 30 and the second semiconductor chip 50 of the first embodiment (see FIGS. 7 and 10 ), the semiconductor chip 100 includes a semiconductor substrate 101, a buffer layer 102, an electron transit layer 103, an electron supply layer 104, and a cap layer 105. The semiconductor substrate 101 includes a substrate front surface 101S and a substrate back surface 101R opposite to the substrate front surface 101S. The buffer layer 102 is provided on the substrate front surface 101S. The electron supply layer 104 is provided on the electron transit layer 103. The electron supply layer 104 has a larger band gap than the electron transit layer 103.

[0170] The semiconductor substrate 101, buffer layer 102, electron transit layer 103, electron supply layer 104, and cap layer 105 have the same configurations as the first semiconductor substrate 31, first buffer layer 32, first electron transit layer 33, first electron supply layer 34, and first cap layer 35 of the first semiconductor chip 30. It can also be said that the semiconductor substrate 101, buffer layer 102, electron transit layer 103, electron supply layer 104, and cap layer 105 have the same configurations as the second semiconductor substrate 51, second buffer layer 52, second electron transit layer 53, second electron supply layer 54, and second cap layer 55 of the second semiconductor chip 50.

[0171] Due to spontaneous polarization in the electron transit layer 103 and the electron supply layer 104 and piezoelectric polarization due to crystal distortion near the heterojunction interface, the energy level of the conduction band of the electron transit layer 103 near the heterojunction interface becomes lower than the Fermi level. As a result, a two-dimensional electron gas (2DEG) 106 is formed in the electron transit layer 103 near the heterojunction interface between the electron transit layer 103 and the electron supply layer 104 (e.g., within a range of about several nanometers from the interface). The 2DEG 106 in the electron transit layer 103 functions as a channel for the semiconductor chip 100. The sheet carrier density of the 2DEG 106 generated in the electron transit layer 103 can be increased by increasing at least one of the aluminum composition and thickness of the electron supply layer 104.

[0172] The insulating layer 110 includes a first insulating layer 111 and a second insulating layer 112, similar to the insulating layers 40 and 60 of the first embodiment. The first insulating layer 111 covers the first source electrode 131, the first drain electrode 132, the second source electrode 134, and the second drain electrode 135, similar to the first insulating layers 41 and 61 of the insulating layers 40 and 60. The first gate electrode 133 and the second gate electrode 136 are each provided on the first insulating layer 111. Meanwhile, the first gate electrode 133 and the second gate electrode 136 each include a portion that penetrates the first insulating layer 111 in the Z direction and is in contact with the cap layer 105. The second insulating layer 112 covers the first gate electrode 133 and the second gate electrode 136. In this manner, the insulating layer 110 can be said to cover the first source electrode 131, the first drain electrode 132, the first gate electrode 133, the second source electrode 134, the second drain electrode 135, and the second gate electrode 136. The first source electrode 131, the first drain electrode 132, the second source electrode 134, and the second drain electrode 135 can be made of any material that can form an ohmic contact with the cap layer 105. In one example, the first source electrode 131, the first drain electrode 132, the second source electrode 134, and the second drain electrode 135 can be made of the same material. The first gate electrode 133 and the second gate electrode 136 can be made of any material that can form a Schottky junction with the cap layer 105. In one example, the first gate electrode 133 and the second gate electrode 136 can be made of the same material.

[0173] The semiconductor device 20 includes a first source electrode 131, a first drain electrode 132, a second source electrode 134, and a second drain electrode 135 provided on the cap layer 105. The semiconductor device 20 also includes a first gate electrode 133 and a second gate electrode 136 provided on a first insulating layer 111 (described later).

[0174] The first source electrode 131, the first drain electrode 132, and the first gate electrode 133 are provided in the carrier region RC. The configurations and arrangements of the first source electrode 131, the first drain electrode 132, and the first gate electrode 133 are the same as those of the first source electrode 46, the first drain electrode 47, and the first gate electrode 48 in the first embodiment. As in the first embodiment, the first source electrode 131 is electrically connected to the first source wiring 121, the first drain electrode 132 is electrically connected to the first drain wiring 122, and the first gate electrode 133 is electrically connected to the first gate wiring 123. As shown in FIG. 22 , the first gate electrode 133 is disposed in the X direction between the first source electrode 131 and the first drain electrode 132 adjacent to each other in the X direction. The first source electrode 131, the first drain electrode 132, and the first gate electrode 133 are disposed spaced apart from each other in the X direction. The first source electrode 131, the first drain electrode 132, and the first gate electrode 133 each extend in the Y direction.

[0175] The second source electrode 134, the second drain electrode 135, and the second gate electrode 136 are provided in the peak region RP. The configurations and arrangements of the second source electrode 134, the second drain electrode 135, and the second gate electrode 136 are the same as those of the second source electrode 66, the second drain electrode 67, and the second gate electrode 68 in the first embodiment. As in the first embodiment, the second source electrode 134 is electrically connected to the second source wiring 124, the second drain electrode 135 is electrically connected to the second drain wiring 125, and the second gate electrode 136 is electrically connected to the second gate wiring 126. The second gate electrode 136 is disposed in the X direction between the second source electrode 134 and the second drain electrode 135 that are adjacent in the X direction. The second source electrode 134, the second drain electrode 135, and the second gate electrode 136 are disposed spaced apart from each other in the X direction. The second source electrode 134, the second drain electrode 135, and the second gate electrode 136 each extend in the Y direction.

[0176] 24 , the semiconductor chip 100 includes a first active region 141, a second active region 142, and an inactive region 143. The first active region 141 is provided in the carrier region RC, and the second active region 142 is provided in the peak region RP. The first active region 141 and the second active region 142 are provided spaced apart from each other in the X direction. The inactive region 143 is provided across both the carrier region RC and the peak region RP. The inactive region 143 is provided so as to surround both the first active region 141 and the second active region 142 in a plan view.

[0177] The first active region 141 is a region in the carrier region RC where the 2DEG 106 (see FIG. 23 ) is generated. The first active region 141 is a region extending in the X and Y directions in a plan view. In the example shown in FIG. 24 , the first active region 141 has a rectangular shape with its long side in the X direction and its short side in the Y direction. That is, the long side direction of the first active region 141 coincides with the long side direction of the semiconductor chip 100. Furthermore, the long side direction of the first active region 141 coincides with the arrangement direction of the multiple first source fingers 121B of the first source wiring 121 and the multiple first drain fingers 122B of the first drain wiring 122 (both see FIG. 22 ). Furthermore, the long side direction of the first active region 141 coincides with the arrangement direction of the multiple first gate electrodes 133 (see FIG. 22 ).

[0178] In the second embodiment, the first active region 141 is disposed at the center of the semiconductor chip 100 in the Y direction. The first active region 141 is disposed offset to one side of the center of the semiconductor chip 100 in the X direction. The dimension QY1 in the Y direction of the first active region 141 is equal to the dimension RY1 in the Y direction of the first active region 37 in the first embodiment (see FIG. 11 ). The dimension QX1 in the X direction of the first active region 141 is equal to the dimension RX1 in the X direction of the first active region 37 in the first embodiment (see FIG. 11 ).

[0179] The second active region 142 is a region where the 2DEG 106 is generated in the peak region RP. The second active region 142 is a region extending in the X and Y directions in a plan view. In the example shown in FIG. 24 , the second active region 142 is rectangular with its long side in the X direction and its short side in the Y direction. That is, the long side direction of the second active region 142 coincides with the long side direction of the semiconductor chip 100. Furthermore, the long side direction of the second active region 142 coincides with the arrangement direction of the multiple second source fingers 124B of the second source wiring 124 and the multiple second drain fingers 125B of the second drain wiring 125 (both see FIG. 22 ). Furthermore, the long side direction of the second active region 142 coincides with the arrangement direction of the multiple second gate electrodes 136 (see FIG. 22 ).

[0180] In the second embodiment, the second active region 142 is disposed at the center of the semiconductor chip 100 in the Y direction. In one example, the second active region 142 is disposed adjacent to the second base portion 124A of the second source wiring 124 (see FIG. 22 ) in a plan view. The second active region 142 is disposed offset to the other side of the center of the semiconductor chip 100 in the X direction. The dimension QY2 in the Y direction of the second active region 142 is equal to the dimension RY2 in the Y direction of the second active region 57 in the first embodiment (see FIG. 11 ). The dimension QX2 in the X direction of the second active region 142 is equal to the dimension RX2 in the X direction of the second active region 57 in the first embodiment (see FIG. 11 ).

[0181] The inactive region 143 is a region that reduces or inhibits the generation of 2DEG 106. The inactive region 143 can also be considered a region where 2DEG 106 is unlikely to be generated. The inactive region 143 is provided in a region that includes the cap layer 105, the electron supply layer 104, and the electron transit layer 103. Impurities that reduce or inhibit the generation of 2DEG 106 are introduced into the inactive region 143. The impurities may include, for example, at least one of helium, boron, nitrogen, oxygen, fluorine, and argon. The inactive region 143 may have a resistance value greater than both the first active region 141 and the second active region 142. Thus, the inactive region 143 can also be considered a region where 2DEG 106 is unlikely to be generated.

[0182] The inactive region 143 can be divided into first to seventh regions 143A to 143G. Note that in FIG. 24 , the boundaries between the first to seventh regions 143A to 143G are indicated by dashed lines. The first region 143A and the second region 143B are adjacent to the first active region 141 in the Y direction. The third region 143C is adjacent to the first active region 141 on the opposite side of the first active region 141 from the second active region 142 in the X direction. The fourth region 143D and the fifth region 143E are adjacent to the second active region 142 in the Y direction. The sixth region 143F is adjacent to the second active region 142 on the opposite side of the second active region 142 from the first active region 141 in the X direction. The seventh region 143G is between the first active region 141 and the second active region 142 in the X direction.

[0183] The X-direction dimension QX1 of the first active region 141 is smaller than the X-direction dimension QX2 of the second active region 142. The Y-direction dimension QY1 of the first active region 141 is smaller than the Y-direction dimension QY2 of the second active region 142. Therefore, the area of ​​the first active region 141 is smaller than the area of ​​the second active region 142.

[0184] The X-direction dimension TX1 of the first region 143A in the inactive region 143 is larger than the Y-direction dimension TY1 of the first region 143A. The X-direction dimension TX2 of the second region 143B is larger than the Y-direction dimension TY2 of the second region 143B. The dimension TX1 is equal to the dimension TX2. The dimension TX1 is equal to the X-direction dimension QX1 of the first active region 141. The dimension TY1 is equal to the dimension TY2. Therefore, in a planar view, the area of ​​the first region 143A is equal to the area of ​​the second region 143B. The X-direction dimension TX3 of the third region 143C is smaller than the X-direction dimension QX1 of the first active region 141. In the second embodiment, the dimension TX3 is equal to the X-direction dimension TX6 of the sixth region 143F.

[0185] The Y-direction dimension TY1 of the first region 143A is larger than the Y-direction dimension QY1 of the first active region 141. The Y-direction dimension PY2 of the second region 38B is larger than the Y-direction dimension RY1 of the first active region 37. The X-direction dimension TX3 of the third region 143C is smaller than the X-direction dimension QX1 of the first active region 141.

[0186] The X-direction dimension TX4 of the fourth region 143D is larger than the Y-direction dimension TY4 of the fourth region 143D. The X-direction dimension TX5 of the fifth region 143E is larger than the Y-direction dimension TY5 of the fifth region 143E. The dimension TX4 is equal to the dimension TX5. The dimension TY4 is equal to the dimension TY5. Therefore, in a plan view, the area of ​​the fourth region 143D is equal to the area of ​​the fifth region 143E. The X-direction dimension TX6 of the sixth region 143F is smaller than the X-direction dimension QX2 of the second active region 142.

[0187] The X-direction dimension TX7 of the seventh region 143G is smaller than the X-direction dimension QX2 of the second active region 142. The dimension TX7 is smaller than the X-direction dimension QX1 of the first active region 141. The dimension TX7 may be smaller than the X-direction dimension of the cutting region C3 of the first embodiment. On the other hand, the dimension TX7 is larger than the X-direction dimension TX3 of the third region 143C. The dimension TX7 is larger than the X-direction dimension TX6 of the sixth region 143F.

[0188] The Y-direction dimension TY1 of the first region 143A is larger than the Y-direction dimension TY4 of the fourth region 143D. The Y-direction dimension TY2 of the second region 143B is larger than the Y-direction dimension TY5 of the fifth region 143E. Therefore, the sum of the Y-direction dimension TY1 of the first region 143A and the Y-direction dimension TY2 of the second region 143B is larger than the sum of the Y-direction dimension TY4 of the fourth region 143D and the Y-direction dimension TY5 of the fifth region 143E. In other words, the sum of the Y-direction dimensions of the inactive regions 143 arranged on both sides of the first active region 141 in the Y direction (first direction) is larger than the sum of the Y-direction dimensions of the inactive regions 143 arranged on both sides of the second active region 142 in the Y direction.

[0189] The X-direction dimension TX7 of the seventh region 143G may be smaller than the Y-direction dimension TY1 of the first region 143A. The dimension TX7 may be smaller than the Y-direction dimension TY2 of the second region 143B. The dimension TX7 may be smaller than the Y-direction dimension TY4 of the fourth region 143D. The dimension TX7 may be smaller than the Y-direction dimension TY5 of the fifth region 143E.

[0190] Although not shown, the semiconductor chip 100 may include a first input pad, a first output pad, a second input pad, and a second output pad. These pads are the same as the first input pad 30A, the first output pad 30B, the second input pad 50A, and the second output pad 50B of the first embodiment (see FIG. 3). The first input pad is electrically connected to the first gate wiring 123. The first output pad is electrically connected to the first drain wiring 122. The second input pad is electrically connected to the second gate wiring 126. The second output pad is electrically connected to the second drain wiring 125.

[0191] The semiconductor chip 100 is mounted on a die pad 70 (see FIG. 3). The first input pad is electrically connected to a first terminal 81 by a wire W1. The first output pad is electrically connected to a third terminal 83 by a wire W3. The second input pad is electrically connected to a second terminal 82 by a wire W2. The second output pad is electrically connected to a fourth terminal 84 by a wire W4.

[0192] Although not shown, the first source electrode 131 and the second source electrode 134 may be electrically connected to the semiconductor substrate 101. The semiconductor substrate 101 is electrically connected to the die pad 70 (see FIG. 3 ) through a conductive bonding material. Therefore, the first source wiring 121 is electrically connected to the die pad 70 through the first source electrode 131 and the semiconductor substrate 101. The second source wiring 124 is electrically connected to the die pad 70 through the second source electrode 134 and the semiconductor substrate 101.

[0193] [Manufacturing Method of Semiconductor Device] An example of a manufacturing method of the semiconductor device 20 will be described with reference to Fig. 25. Fig. 25 schematically shows an enlarged planar structure of a part of the semiconductor wafer 800 for illustrating the process of dividing the semiconductor wafer 800 into individual pieces.

[0194] The manufacturing method of the semiconductor device 20 of the second embodiment differs from the manufacturing method of the semiconductor device 20 of the first embodiment mainly in the step of singulating the semiconductor wafer 800. As shown in Fig. 25 , in the singulation step, the semiconductor wafer 800 is cut by dicing, as in the first embodiment. On the other hand, in the second embodiment, unlike the first embodiment, the semiconductor wafer 800 is cut so that the carrier transistors TC and the peak transistors TP adjacent to each other in the X direction are provided on one semiconductor chip.

[0195] [Effects of Second Embodiment] The semiconductor device 20 of the second embodiment has the following effects. (2-1) The semiconductor device 20 includes a semiconductor chip 100 provided with a carrier transistor TC constituting a part of the carrier amplifier 13 and a peak transistor TP constituting a part of the peak amplifier 14. The semiconductor chip 100 has a rectangular shape extending in the X and Y directions. The semiconductor chip 100 includes an electron transit layer 103, an electron supply layer 104 provided on the electron transit layer 103 and having a band gap larger than that of the electron transit layer 103, a first active region 141 extending in the X and Y directions and being a region in which the 2DEG 106 is generated within the region in which the carrier transistor TC is provided, a second active region 142 extending in the X and Y directions and being a region in which the 2DEG 106 is generated within the region in which the peak transistor TP is provided, and a region surrounding the first active region 141 and the second active region 142 in a plan view, The second active region 142 includes an inactive region 143 in which 2DEG 106 is less likely to occur than in both the first active region 141 and the second active region 142, a first source electrode 131, a first gate electrode 133, and a first drain electrode 132 provided on the electron supply layer 104 in the first active region 141, extending in the Y direction and spaced apart from each other in the X direction, and a second source electrode 134, a second gate electrode 136, and a second drain electrode 135 provided on the electron supply layer 104 in the second active region 142, extending in the Y direction and spaced apart from each other in the X direction. The sum of the Y-direction dimensions of the inactive regions 143 located on both sides of the first active region 141 in the Y direction is greater than the sum of the Y-direction dimensions of regions adjacent to the inactive regions 143 located on both sides of the second active region 142 in the Y direction.

[0196] This configuration makes it possible to reduce the area of ​​the first active region 37, which is prone to heat generation, while increasing the area of ​​the first inactive region 38, which is difficult to heat generation. This makes it easier for heat from the first active region 37 to move to the first inactive region 38, thereby improving the heat dissipation performance of the first semiconductor chip 30. Therefore, the heat dissipation performance of the carrier amplifier 13 can be improved.

[0197] In addition, the distance between the carrier transistor TC and the peak transistor TP in the X direction can be made shorter than when a semiconductor chip including the carrier transistor TC and a semiconductor chip including the peak transistor TP are provided separately, thereby enabling the semiconductor device 20 to be made smaller.

[0198] (2-2) The carrier transistors TC and the peak transistors TP adjacent to each other in the X direction in the semiconductor wafer 800 are provided as one semiconductor chip 100. This reduces variations in the electrical characteristics of the carrier transistors TC and the peak transistors TP.

[0199] <Modifications> The above-described embodiments can be modified as follows: Furthermore, the above-described embodiments and the following modifications can be combined with each other to the extent that no technical contradiction occurs.

[0200] In each embodiment, the shape of the first semiconductor chip 30 in a plan view can be changed as desired. In one example, the dimension LY1 of the first semiconductor chip 30 in the Y direction may be equal to the dimension LX1 of the first semiconductor chip 30 in the X direction. That is, the first semiconductor chip 30 may be square in a plan view. In another example, the dimension LY1 of the first semiconductor chip 30 in the Y direction may be smaller than the dimension LX1 of the first semiconductor chip 30 in the X direction. That is, the first semiconductor chip 30 may be rectangular in a plan view with its long sides extending in the X direction and its short sides extending in the Y direction.

[0201] In each embodiment, the shape of the second semiconductor chip 50 in a plan view can be changed as desired. In one example, the dimension LX2 of the second semiconductor chip 50 in the X direction may be equal to the dimension LY2 of the second semiconductor chip 50 in the Y direction. In other words, the second semiconductor chip 50 may be square in a plan view. In another example, the dimension LX2 of the second semiconductor chip 50 in the X direction may be smaller than the dimension LY2 of the second semiconductor chip 50 in the Y direction. In other words, the second semiconductor chip 50 may be rectangular in a plan view with its long sides extending in the Y direction and its short sides extending in the X direction.

[0202] In the first embodiment, the first ratio of the area of ​​the first inactive region 38 to the area of ​​the first active region 37 may be less than 1.5 times the second ratio of the area of ​​the second inactive region 58 to the area of ​​the second active region 57. Alternatively, the first ratio may be equal to or less than the second ratio.

[0203] In each embodiment, the value obtained by dividing the maximum output of the semiconductor device 20 by the sum of the Y-direction dimensions of the plurality of first gate electrodes 48 in the first active region 37 and the Y-direction dimensions of the plurality of second gate electrodes 68 in the second active region 57 may be less than 5 W / mm.

[0204] In the first embodiment, the X-direction dimension PX3 of the third region 38C and the X-direction dimension PX4 of the fourth region 38D can each be changed arbitrarily. In one example, as shown in FIG. 26 , both the X-direction dimension PX3 of the third region 38C and the X-direction dimension PX4 of the fourth region 38D may be larger than both the X-direction dimension PX7 of the seventh region 58C and the X-direction dimension PX8 of the eighth region 58D. The sum of the X-direction dimensions of the first inactive regions 38 arranged on both sides of the first active region 37 in the X direction may be larger than the sum of the X-direction dimensions of the second inactive regions 58 arranged on both sides of the second active region 57 in the X direction. In other words, the sum of the X-direction dimension PX3 of the third region 38C and the X-direction dimension PX4 of the fourth region 38D may be larger than the sum of the X-direction dimension PX7 of the seventh region 58C and the X-direction dimension PX8 of the eighth region 58D. In this case, either the X-direction dimension PX3 of the third region 38C or the X-direction dimension PX4 of the fourth region 38D may be equal to or smaller than the X-direction dimension PX7 of the seventh region 58C or the dimension PX8 of the eighth region 58D. In this way, the ratio of the X-direction dimension RX1 of the first active region 37 to the X-direction dimension LX1 of the first semiconductor chip 30 in a plan view may be smaller than the ratio of the X-direction dimension RX2 of the second active region 57 to the X-direction dimension LX2 of the second semiconductor chip 50 in a plan view.

[0205] In each embodiment, the dimension PY1 of the first region 38A in the Y direction can be changed as desired. For example, the dimension PY1 of the first region 38A in the Y direction may be equal to or smaller than the dimension RY1 of the first active region 37 in the Y direction.

[0206] In each embodiment, the dimension PY2 of the second region 38B in the Y direction can be changed as desired. For example, the dimension PY2 of the second region 38B in the Y direction may be equal to or smaller than the dimension RY1 of the first active region 37 in the Y direction.

[0207] 27 , in the first embodiment, the X-direction dimension PX3 of the third region 38C and the X-direction dimension PX4 of the fourth region 38D may be equal to or greater than the Y-direction dimension PY1 of the first region 38A and the Y-direction dimension PY2 of the second region 38B. Also, either the X-direction dimension PX3 of the third region 38C or the X-direction dimension PX4 of the fourth region 38D may be equal to or greater than the Y-direction dimension PY1 of the first region 38A and the Y-direction dimension PY2 of the second region 38B.

[0208] In the first embodiment, the configuration of the first inactive region 38 can be changed as desired. For example, at least one of the third region 38C and the fourth region 38D may be omitted from the first inactive region 38.

[0209] In the first embodiment, the ratio of the X-direction dimension RX1 of the first active region 37 to the X-direction dimension LX1 of the first semiconductor chip 30 may be equal to or greater than the ratio of the X-direction dimension PX2 of the second active region 57 to the X-direction dimension LX2 of the second semiconductor chip 50 in a planar view.

[0210] In each embodiment, the dimension of the first gate electrode 48 in the Y direction may be smaller than the dimension of the second gate electrode 68 in the Y direction. In one example, as shown in FIG. 28 , the tip of the first gate electrode 48 may be provided in a position adjacent to the first active region 37 in the Y direction. With this configuration, the dimension of the first gate electrode 48 in the Y direction is reduced, thereby reducing the gate resistance. Therefore, the gain of the carrier amplifier 13 can be improved.

[0211] In each embodiment, the position of the first active region 37 (141) in the Y direction can be changed as desired. As an example, as shown in FIG. 29 , the first active region 37 may be provided so that the Y direction dimension PY1 of the first region 38A is larger than the Y direction dimension PY2 of the second region 38B. As another example, the first active region 37 may be provided so that the Y direction dimension PY2 of the second region 38B is larger than the Y direction dimension PY1 of the first region 38A.

[0212] In each embodiment, the positional relationship between the first active region 37 (141) and the second active region 57 (142) can be changed as desired. In one example, as shown in FIG. 30 , the center of the first active region 141 in the Y direction may be shifted in the Y direction from the center of the second active region 142 in the Y direction. Here, the center of the first active region 141 in the Y direction is indicated by a dashed-dotted line LC1. The center of the second active region 142 in the Y direction is indicated by a dashed-dotted line LC2.

[0213] In the second embodiment, the X-direction dimension TX7 of the seventh region 143G, which is between the first active region 141 and the second active region 142 in the X-direction, of the inactive region 143 can be changed as desired. For example, the X-direction dimension TX7 of the seventh region 143G may be equal to or greater than the Y-direction dimension TY4 of the fourth region 143D. For example, the dimension TX7 may be equal to or greater than the Y-direction dimension TY5 of the fifth region 143E. For example, the dimension TX7 may be equal to or greater than the Y-direction dimension TY1 of the first region 143A. For example, the dimension TX7 may be equal to or greater than the Y-direction dimension TY2 of the second region 143B. For example, the dimension TX7 may be equal to or less than the X-direction dimension TX6 of the sixth region 143F. For example, the dimension TX7 may be equal to or less than the X-direction dimension TX3 of the third region 143C.

[0214] In the second embodiment, the X-direction dimension TX3 of the third region 143C in the inactive region 143 may be larger than the X-direction dimension TX6 of the sixth region 143F. This configuration increases the area of ​​the inactive region 143 in the carrier region RC, thereby improving the heat dissipation performance of the carrier transistor TC. Note that the dimension TX3 may be smaller than the dimension TX6.

[0215] In each embodiment, the configuration of the second source wiring 63 can be changed as desired. For example, as shown in Fig. 31 , the second pad portion 63C arranged at the center in the X direction among the multiple second pad portions 63C of the second source wiring 63 may be omitted. In this case, the second gate wiring 65 may be provided as a single second gate wiring 65 extending in the X direction.

[0216] In each embodiment, the formation range of the first active region 37 and the second active region 57 can be changed as desired. In one example, as shown in FIG. 32 , the first semiconductor chip 30 may include a plurality of first active regions 37 (four in the example shown in FIG. 32 ). The plurality of first active regions 37 may be located at the same positions in the Y direction and spaced apart from each other in the X direction. A first inactive region 38 is provided in the region between adjacent first active regions 37 in the X direction.

[0217] The first active regions 37 are provided at positions overlapping the first gate electrodes 48 in plan view. The X-direction dimension SX1 of each first active region 37 is larger than the width dimension (X-direction dimension) of the first gate electrodes 48. Therefore, each first active region 37 is provided across the entire X-direction of the corresponding first gate electrode 48. Furthermore, each first active region 37 may be provided so as to partially overlap the first source finger 43B in the X-direction in plan view. Each first active region 37 may be provided so as to partially overlap the first drain finger 44B in the X-direction in plan view. In the example shown in FIG. 32 , the X-direction dimensions SX1 of the multiple first active regions 37 are equal to each other, and the Y-direction dimensions SY1 of the multiple first active regions 37 are equal to each other.

[0218] 32, the second semiconductor chip 50 may include a plurality of (eight in the example shown in FIG. 32) second active regions 57. The second active regions 57 may be located at the same positions as each other in the Y direction and spaced apart from each other in the X direction. Second inactive regions 58 are provided in the regions between the second active regions 57 adjacent to each other in the X direction.

[0219] The second active regions 57 are provided at positions overlapping the second gate electrodes 68 in plan view 43b. The X-direction dimension SX2 of each second active region 57 is larger than the width dimension (X-direction dimension) of the second gate electrodes 68. Therefore, each second active region 57 is provided across the entire X-direction of the corresponding second gate electrode 68. Furthermore, each second active region 57 may be provided so as to partially overlap with the second source finger 63B in the X-direction in plan view. Each second active region 57 may be provided so as to partially overlap with the second drain finger 64B in the X-direction in plan view. In the example shown in FIG. 32 , the X-direction dimensions SX2 of the multiple second active regions 57 are equal to each other, and the Y-direction dimensions SY2 of the multiple second active regions 57 are equal to each other. Furthermore, the X-direction dimension SX2 of the second active regions 57 may be equal to the X-direction dimension SX1 of the first active region 37. The dimension SY2 of the second active region 57 in the Y direction may be larger than the dimension SY1 of the first active region 37 in the Y direction.

[0220] 33 , each of the plurality of first active regions 37 (two in the example shown in FIG. 33 ) may be provided so as to straddle first gate electrodes 48 adjacent to each other in the X direction in plan view. The plurality of first active regions 37 may be provided at the same positions as each other in the Y direction and spaced apart from each other in the X direction. A first inactive region 38 is provided in a region between the first active regions 37 adjacent to each other in the X direction.

[0221] The first active region 37 may be provided so as to overlap, in plan view, two first gate electrodes 48 and the first drain finger 44B arranged between the first gate electrodes 48 in the X direction. The first active region 37 may be provided so as to partially overlap, in plan view, each of two first source fingers 43B adjacent to each other in the X direction. In the example shown in FIG. 33 , the multiple first active regions 37 have the same dimension SX1 in the X direction, and the multiple first active regions 37 have the same dimension SY1 in the Y direction.

[0222] 33 , each of the plurality of second active regions 57 (two in the example shown in FIG. 33 ) may be provided so as to straddle adjacent second gate electrodes 68 in the X direction in plan view. The plurality of second active regions 57 may be provided at the same positions as each other in the Y direction and spaced apart from each other in the X direction. Second inactive regions 58 are provided in the regions between the second active regions 57 adjacent to each other in the X direction.

[0223] The second active region 57 may be provided to overlap two second gate electrodes 68 and the second drain finger 64B arranged between the second gate electrodes 68 in the X direction in a plan view. The second active region 57 may be provided to partially overlap two second source fingers 63B adjacent to each other in the X direction in a plan view. In the example shown in FIG. 33 , the X-direction dimensions SX2 of the multiple second active regions 57 are equal to each other, and the Y-direction dimensions SY2 of the multiple second active regions 57 are equal to each other. Furthermore, the X-direction dimension SX2 of the second active region 57 may be equal to the X-direction dimension SX1 of the first active region 37. The Y-direction dimension SY2 of the second active region 57 may be greater than the Y-direction dimension SY1 of the first active region 37.

[0224] The X-direction dimension SX1 of the multiple first active regions 37 can be arbitrarily changed. For example, the X-direction dimension SX1 of at least one first active region 37 among the multiple first active regions 37 may be different from the X-direction dimension SX1 of the other first active regions 37. Furthermore, the Y-direction dimension SY1 of the multiple first active regions 37 can be arbitrarily changed. For example, the Y-direction dimension SY1 of at least one first active region 37 among the multiple first active regions 37 may be different from the Y-direction dimension SY1 of the other first active regions 37. Furthermore, the arrangement of the multiple first active regions 37 can be arbitrarily changed. For example, at least one first active region 37 among the multiple first active regions 37 may be arranged at least partially offset in the Y direction with respect to the other first active regions 37.

[0225] The X-direction dimension SX2 of the multiple second active regions 57 can be arbitrarily changed. For example, the X-direction dimension SX2 of at least one second active region 57 among the multiple second active regions 57 may be different from the X-direction dimension SX2 of the other second active regions 57. The Y-direction dimension SY2 of the multiple second active regions 57 can be arbitrarily changed. For example, the Y-direction dimension SY2 of at least one second active region 57 among the multiple second active regions 57 may be different from the Y-direction dimension SY2 of the other second active regions 57. The arrangement of the multiple second active regions 57 can be arbitrarily changed. For example, at least one second active region 57 among the multiple second active regions 57 may be arranged at least partially offset in the Y direction with respect to the other second active regions 57.

[0226] The number of second active regions 57 can be changed arbitrarily. In one example, there may be two second active regions 57. In this case, each second active region 57 is provided so as to overlap with four second gate electrodes 68 adjacent to each other in the X direction in plan view. The two second active regions 57 include a second active region 57 closer to one side of the center of the second semiconductor chip 50 in the X direction, and a second active region 57 closer to the other side of the center.

[0227] In each embodiment, the formation ranges of the first inactive region 38 and the second inactive region 58 can be changed as desired. For example, as shown in FIG. 34 , the first inactive region 38 may include a first isolation region 38P and a second isolation region 38Q provided in both a region overlapping with the first source finger 43B and a region overlapping with the first drain finger 44B in a plan view. The first isolation region 38P and the second isolation region 38Q are provided spaced apart from the first to fourth regions 38A to 38D of the first inactive region 38. A plurality of first isolation regions 38P (three in the example shown in FIG. 34 ) are provided corresponding to the plurality of first source fingers 43B. The first isolation region 38P is provided at a position overlapping with the first source finger 43B in a plan view. A plurality of second isolation regions 38Q (two in the example shown in FIG. 34 ) are provided corresponding to the plurality of first drain fingers 44B. The second isolation region 38Q is provided at a position overlapping the first drain finger 44B in a plan view.

[0228] Each first isolated region 38P and each second isolated region 38Q has a rectangular shape with its long side extending in the Y direction and its short side extending in the X direction in a plan view. The X-direction dimensions of the multiple first isolated regions 38P are equal to each other. The X-direction dimensions of the multiple second isolated regions 38Q are equal to each other. The X-direction dimensions of each first isolated region 38P are larger than the X-direction dimensions of each second isolated region 38Q. The Y-direction dimensions of the multiple first isolated regions 38P are equal to each other. The Y-direction dimensions of the multiple second isolated regions 38Q are equal to each other. The Y-direction dimensions of each first isolated region 38P are equal to the Y-direction dimensions of each second isolated region 38Q.

[0229] The Y-direction dimensions of the multiple first isolation regions 38P are equal to one another. The Y-direction dimensions of the multiple second isolation regions 38Q are equal to one another. The Y-direction dimensions of each first isolation region 38P are equal to the Y-direction dimensions of each second isolation region 38Q. The Y-direction dimensions of each first isolation region 38P and each second isolation region 38Q are smaller than the Y-direction dimension RY1 of the first active region 37.

[0230] 34 , the second inactive region 58 may include a first isolation region 58P and a second isolation region 58Q provided in both a region overlapping with the second source finger 63B and a region overlapping with the second drain finger 64B in a plan view. The first isolation region 58P and the second isolation region 58Q are provided spaced apart from the fifth to ninth regions 58A to 58D of the second inactive region 58. A plurality of first isolation regions 58P (five in the example shown in FIG. 34 ) are provided corresponding to the plurality of second source fingers 63B. The first isolation region 58P is provided at a position overlapping with the second source finger 63B in a plan view. A plurality of second isolation regions 58Q (four in the example shown in FIG. 34 ) are provided corresponding to the plurality of second drain fingers 64B. The second isolation region 58Q is provided at a position overlapping with the second drain finger 64B in a plan view.

[0231] Each first isolated region 58P and each second isolated region 58Q has a rectangular shape with its long side extending in the Y direction and its short side extending in the X direction in a plan view. The X-direction dimensions of the multiple second isolated regions 58Q are equal to each other. The X-direction dimensions of the multiple first isolated regions 58P are larger than the X-direction dimensions of the multiple second isolated regions 58Q. The X-direction dimension of the central first isolated region 58P among the multiple first isolated regions 58P in the X direction is larger than the X-direction dimensions of the other first isolated regions 58P. The Y-direction dimensions of the multiple first isolated regions 58P are equal to each other. The Y-direction dimensions of the multiple second isolated regions 58Q are equal to each other. The Y-direction dimension of each first isolated region 58P is equal to the Y-direction dimension of each second isolated region 58Q. The dimension in the Y direction of each of the first isolation regions 58P and each of the second isolation regions 58Q is smaller than the dimension RY2 in the Y direction of the second active region 57.

[0232] The X-direction dimension of at least one of the multiple first isolated regions 38P may be different from the X-direction dimension of the other first isolated regions 38P. The X-direction dimension of at least one of the multiple second isolated regions 38Q may be different from the X-direction dimension of the other second isolated regions 38Q. The X-direction dimension of the first isolated region 38P may be equal to the X-direction dimension of the second isolated region 38Q.

[0233] Furthermore, the Y-direction dimension of at least one of the multiple first isolated regions 38P may be different from the Y-direction dimension of the other first isolated regions 38P. The Y-direction dimension of at least one of the multiple second isolated regions 38Q may be different from the Y-direction dimension of the other second isolated regions 38Q. The Y-direction dimension of the first isolated region 38P may be different from the Y-direction dimension of the second isolated region 38Q.

[0234] Furthermore, the X-direction dimension of at least one of the multiple first isolated regions 58P other than the first isolated region 58P located at the center in the X direction may be different from the X-direction dimension of the other first isolated regions 58P. The X-direction dimension of at least one of the multiple second isolated regions 58Q may be different from the X-direction dimension of the other second isolated regions 58Q. The X-direction dimension of the first isolated regions 58P other than the first isolated region 58P located at the center in the X direction may be equal to the X-direction dimension of the second isolated region 58Q. The X-direction dimension of the first isolated region 58P located at the center in the X direction may be equal to the X-direction dimension of the other first isolated regions 58P.

[0235] Furthermore, the Y-direction dimension of at least one of the multiple first isolated regions 58P may be different from the Y-direction dimension of the other first isolated regions 58P. The Y-direction dimension of at least one of the multiple second isolated regions 58Q may be different from the Y-direction dimension of the other second isolated regions 58Q. The Y-direction dimension of the first isolated region 58P may be different from the Y-direction dimension of the second isolated region 58Q. In one example, the Y-direction dimension of the first isolated region 58P may be larger than the Y-direction dimension of the first isolated region 38P. In one example, the Y-direction dimension of the first isolated region 58P may be larger than the Y-direction dimension of the second isolated region 38Q. In one example, the Y-direction dimension of the second isolated region 58Q may be larger than the Y-direction dimension of the first isolated region 38P. In one example, the dimension in the Y direction of the second isolated region 58Q may be larger than the dimension in the Y direction of the second isolated region 38Q.

[0236] Furthermore, the first isolated region 38P may be provided so as to be connected to at least one of the first region 38A and the second region 38B. The second isolated region 38Q may be provided so as to be connected to at least one of the first region 38A and the second region 38B.

[0237] Furthermore, the first isolated region 58P may be provided so as to be connected to at least one of the fifth region 58A and the sixth region 58B. The second isolated region 58Q may be provided so as to be connected to at least one of the fifth region 58A and the sixth region 58B.

[0238] Although not shown, the inactive region 143 of the second embodiment may include the first isolated region 38P and the second isolated region 38Q. The inactive region 143 may also include the first isolated region 58P and the second isolated region 58Q.

[0239] In the first embodiment, the configurations of the first semiconductor chip 30 and the second semiconductor chip 50 can be changed as desired. For example, the first cap layer 35 may be omitted from the first semiconductor chip 30. For example, the second cap layer 55 may be omitted from the second semiconductor chip 50.

[0240] In the first embodiment, the first input pad 30A and the first output pad 30B may be omitted from the first semiconductor chip 30. In this case, the first source wiring 43, the first drain wiring 44, and the first gate wiring 45 are exposed from the first semiconductor chip 30. The wire W1 is connected to the first gate wiring 45. The wire W2 is connected to the first drain wiring 44. The second embodiment may also be modified in a similar manner.

[0241] In the first embodiment, the second input pad 50A and the second output pad 50B may be omitted from the second semiconductor chip 50. In this case, the second source wiring 63, the second drain wiring 64, and the second gate wiring 65 are exposed from the second semiconductor chip 50. The wire W3 is connected to the second gate wiring 65. The wire W4 is connected to the second drain wiring 64. The second embodiment may also be modified in a similar manner.

[0242] In the first embodiment, the first electron transit layer 33 and the second electron transit layer 53 may be made of a semiconductor other than a nitride semiconductor. Also, the second electron transit layer 53 and the second electron supply layer 54 may be made of a semiconductor other than a nitride semiconductor.

[0243] In each embodiment, the method for forming the inactive region 818 is not limited to ion implantation and can be changed as desired. For example, the inactive region 818 may be formed by removing the electron supply layer 814 using dry etching. In each embodiment, dry etching may be performed using, for example, chlorine (Cl ２ ), boron trichloride (BCl ３ ), and silicon tetrachloride (SiCl ４ ) may be used as an etching gas.

[0244] One or more of the various examples described in this disclosure can be combined to the extent that they are not technically inconsistent. The term "on" used in this disclosure includes the meanings of "on" and "above," unless the context clearly indicates otherwise. Thus, for example, the expression "a first element is disposed on a second element" means that in some embodiments, the first element may be in contact with the second element and disposed directly on the second element, but in other embodiments, the first element may be disposed above the second element without contacting the second element. In other words, the term "on" does not exclude a structure in which another element is formed between the first element and the second element.

[0245] The Z direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" in the Z axis direction described in this disclosure being "up" and "down" in the vertical direction. For example, the X direction may be the vertical direction, or the Y direction may be the vertical direction.

[0246] <Supplementary Notes> The technical ideas that can be understood from this disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the supplementary notes are given the reference numerals of the corresponding components in the above embodiment. The reference numerals are shown as examples to aid understanding, and the components described in each supplementary note should not be limited to the components indicated by the reference numerals.

[0247] [Supplementary Note 1] A semiconductor device (20) including: a first semiconductor chip (30) including a carrier transistor (TC) constituting a part of a carrier amplifier (13); and a second semiconductor chip (50) including a peak transistor (TP) constituting a part of a peak amplifier (14), wherein the first semiconductor chip (30) includes: a first electron transit layer (33); a first electron supply layer (34) provided on the first electron transit layer (33) and having a band gap larger than that of the first electron transit layer (33); a first active region (37) in which a two-dimensional electron gas (36) is generated, the first active region (37) extending in a first direction (Y) and a second direction (X) perpendicular to the first direction (Y) in a planar view; and a first inactive region (38) in which the two-dimensional electron gas (36) is less likely to be generated than in the first active region (37) in a planar view surrounding the first active region (37). a first source electrode (46), a first gate electrode (48), and a first drain electrode (47) that are provided above the first electron supply layer (34) in the first active region (37), extend in the first direction (Y), and are spaced apart from each other in the second direction (X); the second semiconductor chip (50) includes: a second electron transit layer (53); a second electron supply layer (54) that is provided on the second electron transit layer (53) and has a band gap larger than that of the second electron transit layer (53); a second active region (57) that is a region in which two-dimensional electron gas (56) is generated, and extends in the first direction (Y) and the second direction (X); and a second inactive region (58) that is a region that surrounds the second active region (57) in a planar view, and in which the two-dimensional electron gas (56) is less likely to be generated in the peak transistor (TP) than in the second active region (57). a second source electrode (66), a second gate electrode (68), and a second drain electrode (67) provided above the second electron supply layer (54) in the second active region (57), extending in the first direction (Y) and spaced apart from each other in the second direction (X), wherein, in a plan view, a dimension (LY1) of the first semiconductor chip (30) in the first direction (Y) is equal to a dimension (LY2) of the second semiconductor chip (50) in the first direction (Y);A semiconductor device (20) in which the sum of the dimensions (PY1, PY2) in the first direction (Y) of the first inactive regions (38, 38A, 38B) arranged on both sides of the first active region (37) in the first direction (Y) is greater than the sum of the dimensions (PY5, PY6) in the first direction (Y) of the second inactive regions (58, 58A, 58B) arranged on both sides of the second active region (57) in the first direction (Y).

[0248] [Supplementary Note 2] The first inactive region (38) includes a first region (38A) and a second region (38B) adjacent to the first active region (37) in the first direction (Y), and a third region (38C) and a fourth region (38D) adjacent to the first active region (37) in the second direction (X), and the second inactive region (58) includes a fifth region (58A) and a sixth region (58B) adjacent to the second active region (57) in the first direction (Y), and a seventh region (58C) and an eighth region (58D) adjacent to the second active region (57) in the second direction (X), A semiconductor device as described in Appendix 1, wherein the dimensions (PY1, PY2) in the first direction (Y) of both the first region (38A) and the second region (38B) are greater than the dimensions (PY5, PY6) in the first direction (Y) of both the fifth region (58A) and the sixth region (58B).

[0249] [Supplementary Note 3] The semiconductor device according to Supplementary Note 2, wherein a dimension (PY1, PY2) in the first direction (Y) of at least one of the first region (38A) and the second region (38B) is larger than a dimension (PX3, PX4) in the second direction (X) of both the third region (38C) and the fourth region (38D).

[0250] [Appendix 4] The semiconductor device according to appendix 2 or 3, wherein the dimensions (PX3, PX4) in the second direction (X) of both the third region (38C) and the fourth region (38D) are greater than the dimensions (PX7, PX8) in the second direction (X) of both the seventh region (58C) and the eighth region (58D).

[0251] [Supplementary Note 5] The semiconductor device according to Supplementary Note 1, wherein a sum of dimensions (PX3, PX4) in the second direction (X) of the first inactive regions (38, 38C, 38D) arranged on both sides of the first active region (37) in the second direction (X) is greater than a sum of dimensions (PX7, PX8) in the second direction (X) of the second inactive regions (58, 58C, 58D) arranged on both sides of the second active region (57) in the second direction (X).

[0252] [Appendix 6] The semiconductor device according to any one of Appendices 1 to 5, wherein a dimension (LX2) of the second semiconductor chip (50) in the second direction (X) is larger than a dimension (LX1) of the first semiconductor chip (30) in the second direction (X).

[0253] [Appendix 7] The semiconductor device according to Appendix 6, wherein a dimension (LY1) of the first semiconductor chip (30) in the first direction (Y) is greater than a dimension (LX1) of the first semiconductor chip (30) in the second direction (X).

[0254] [Appendix 8] The semiconductor device according to any one of appendices 1 to 7, wherein a dimension (RY1) of the first active region (37) in the first direction (Y) is smaller than a dimension (RY2) of the second active region (57) in the first direction (Y).

[0255] [Supplementary Note 9] The semiconductor device according to Supplementary Note 8, wherein a total dimension in the first direction (Y) of the second gate electrode (68) in the second active region (57) is 1.5 times or more a total dimension in the first direction (Y) of the first gate electrode (48) in the first active region (37).

[0256] [Supplementary Note 10] The first semiconductor chip (30) includes an insulating layer (40) covering the first source electrode (46), the first drain electrode (47), and the first gate electrode (48), a first source wiring (43) provided on the insulating layer (40) and electrically connected to the first source electrode (46), and a first drain wiring (44) provided on the insulating layer (40) and electrically connected to the first drain electrode (47), and the second semiconductor chip (50) includes an insulating layer (60) covering the second source electrode (66), the second drain electrode (67), and the second gate electrode (68), a second source wiring (63) provided on the insulating layer (60) and electrically connected to the second source electrode (66), and a second drain wiring (64) provided on the insulating layer (60) and electrically connected to the second drain electrode (67), The semiconductor device according to appendix 8 or 9, wherein a dimension (SF1) of the first source wiring (43) in the first direction (Y) is equal to a dimension (SF2) of the second source wiring (63) in the first direction (Y), and a dimension (DF1) of the first drain wiring (44) in the first direction (Y) is equal to a dimension (DF2) of the second drain wiring (64) in the first direction (Y).

[0257] [Supplementary Note 11] The semiconductor device according to Supplementary Note 8 or 9, wherein the dimension of the first gate electrode (48) in the first direction (Y) is smaller than the dimension of the second gate electrode (68) in the first direction (Y).

[0258] [Supplementary Note 12] The semiconductor device according to any one of Supplementary Notes 1 to 11, wherein a value obtained by dividing the maximum output of the semiconductor device (20) by the sum of the sum of the dimensions in the first direction (Y) of the first gate electrode (48) in the first active region (37) and the sum of the dimensions in the first direction (Y) of the second gate electrode (68) in the second active region (57) is 5 W / mm or more.

[0259] [Supplementary Note 13] The semiconductor device according to any one of Supplementary Notes 1 to 12, wherein a first ratio of an area of ​​the first inactive region (38) to an area of ​​the first active region (37) in a planar view is greater than a second ratio of an area of ​​the second inactive region (58) to an area of ​​the second active region (57) in a planar view.

[0260] [Supplementary Note 14] The semiconductor device according to Supplementary Note 13, wherein the first ratio is 1.5 times or more the second ratio.

[0261] [Appendix 15] The semiconductor device according to any one of Appendices 1 to 14, wherein each of the first electron transit layer (33), the first electron supply layer (34), the second electron transit layer (53), and the second electron supply layer (54) is made of a nitride semiconductor.

[0262] [Appendix 16] The semiconductor device according to any one of Appendices 1 to 15, wherein each of the first semiconductor chip (30) and the second semiconductor chip (50) includes a semiconductor substrate (31 / 51), and the semiconductor substrate (31 / 51) is made of a material containing SiC.

[0263] [Supplementary Note 17] The semiconductor device according to any one of Supplementary Notes 1 to 16, wherein the first semiconductor chip (30) and the second semiconductor chip (50) are at the same position as each other in the first direction (Y) and are spaced apart from each other in the second direction (X), and the first active region (37) is provided such that its center in the first direction (Y) is offset in the first direction (Y) with respect to the center of the second active region (57) in the first direction (Y).

[0264] [Appendix 18] The semiconductor device according to any one of Appendices 1 to 16, wherein the first semiconductor chip (30) and the second semiconductor chip (50) are arranged at the same position as each other in the first direction (Y) and spaced apart from each other in the second direction (X), and the first active region (37) is provided so that its center in the first direction (Y) is at the same position as the center of the second active region (57) in the first direction (Y).

[0265] [Supplementary Note 19] A semiconductor device (20) including a semiconductor chip (100) provided with a carrier transistor (TC) constituting a part of a carrier amplifier (13) and a peak transistor (TP) constituting a part of a peak amplifier (14), wherein the semiconductor chip (100) has a rectangular shape extending in a first direction (Y) and in a second direction (X) perpendicular to the first direction (Y) in a plan view, and the semiconductor chip (100) includes: an electron transit layer (103); an electron supply layer (104) provided on the electron transit layer (103) and having a band gap larger than that of the electron transit layer (103); a first active region (141) extending in the first direction (Y) and the second direction (X) in a region where the carrier transistor (TC) is provided and where two-dimensional electron gas (106) is generated; a second active region (142) that is a region in which the two-dimensional electron gas (106) is generated within the region in which the peak transistor (TP) is provided, the second active region (142) extending in the first direction (Y) and the second direction (X) and having a dimension in the first direction (Y) larger than that of the first active region (141); an inactive region (143) that is a region surrounding the first active region (141) and the second active region (142) in a planar view and in which the two-dimensional electron gas (106) is less likely to be generated than in both the first active region (141) and the second active region (142); a first source electrode (131), a first gate electrode (133), and a first drain electrode (132) that are provided above the electron supply layer (104) in the first active region (141), extending in the first direction (Y), and spaced apart from each other in the second direction (X); a second source electrode (134), a second gate electrode (136), and a second drain electrode (135) that are provided above the electron supply layer (104) in the second active region (142), extend in the first direction (Y), and are spaced apart from each other in the second direction (X), and a sum of the dimensions (TY1, TY2) in the first direction (Y) of the inactive regions (143, 143A, 143B) that are disposed on both sides of the first active region (141) in the first direction (Y) is greater than or equal to the sum of the dimensions (TY1, TY2) in the first direction (Y) of the inactive regions (143, 143D, 143E) that are disposed on both sides of the second active region (142) in the first direction (Y).143E) in the first direction (Y) of the semiconductor device (20).

[0266] [Supplementary Note 20] The semiconductor device according to Supplementary Note 19, wherein a dimension (TX7) in the second direction (X) of a region (143G) of the inactive region (143) between the first active region (141) and the second active region (142) in the second direction (X) is smaller than dimensions (TY1, TY2) in the first direction (Y) of regions (143A, 143B) of the inactive region (143) adjacent to the first active region (141) in the first direction (Y).

[0267] [Supplementary Note 21] The semiconductor device according to Supplementary Note 19 or 20, wherein a dimension (TX7) in the second direction (X) of a region (143G) of the inactive region (143) between the first active region (141) and the second active region (142) in the second direction (X) is smaller than dimensions (TY4, TY5) in the first direction (Y) of regions (143D, 143E) of the inactive region (143) adjacent to the second active region (142) in the first direction (Y).

[0268] [Supplementary Note 22] The semiconductor device according to any one of Supplementary Notes 19 to 21, wherein the carrier transistor (TC) and the peak transistor (TP) are arranged apart from each other in the second direction (X), and a dimension (TX3) in the second direction (X) of a region (143C) of the inactive region (143) adjacent to the first active region (141) on a side opposite to the peak transistor (TP) in the second direction (X) is larger than a dimension (TX6) in the second direction (X) of a region (143F) adjacent to the second active region (142) on a side opposite to the carrier transistor (TC) in the second direction (X).

[0269] [Supplementary Note 23] The semiconductor device according to any one of Supplementary Notes 1 to 7, wherein the dimension of the first gate electrode (48) in the first direction (Y) is equal to the dimension of the second gate electrode (68) in the first direction (Y).

[0270] [Appendix 24] The semiconductor device according to any one of Appendices 1 to 18, wherein a ratio of a dimension (RY1) in the first direction (Y) of the first active region (37) to a dimension (LY1) in the first direction (Y) of the first semiconductor chip (30) in a planar view is smaller than a ratio of a dimension (RY2) in the first direction (Y) of the second active region (57) to a dimension (LY2) in the first direction (Y) of the second semiconductor chip (50) in a planar view.

[0271] [Appendix 25] The semiconductor device according to Appendix 24, wherein a ratio of a dimension (RX1) in the second direction (X) of the first active region (37) to a dimension (LX1) in the second direction (X) of the first semiconductor chip (30) in a planar view is smaller than a ratio of a dimension (RX2) in the second direction (X) of the second active region (57) to a dimension (LX2) in the second direction (X) of the second semiconductor chip (50) in a planar view.

[0272] [Appendix 26] The semiconductor device according to any one of Appendices 2 to 4, wherein a dimension (PY1) of the first region (38A) in the first direction (Y) is greater than a dimension (RY1) of the first active region (37) in the first direction (Y).

[0273] [Appendix 27] The semiconductor device according to any one of Appendices 2 to 4, wherein a dimension (PY2) of the second region (38B) in the first direction (Y) is greater than a dimension (RY1) of the first active region (37) in the first direction (Y).

[0274] [Appendix 28] The semiconductor device according to any one of Appendices 2 to 4, wherein a dimension (PY1) in the first direction (Y) of the first region (38A) and a dimension (PY2) in the first direction (Y) of the second region (38B) are each larger than a dimension (RY1) in the first direction (Y) of the first active region (37).

[0275] [Supplementary Note 29] The semiconductor device according to any one of Supplementary Notes 1 to 28, wherein the first active region (37) is provided in plurality and spaced apart from one another in the second direction (X).

[0276] [Supplementary Note 30] The semiconductor device according to any one of Supplementary Notes 1 to 29, wherein the second active region (57) is provided in plurality and spaced apart from one another in the second direction (X).

[0277] [Supplementary Note 31] The semiconductor device according to any one of Supplementary Notes 1 to 18, wherein the first source wiring (43) includes a first source finger (43B) extending in the first direction (Y), the first drain wiring (44) includes a first drain finger (44B) extending in the first direction (Y), both of the first source finger (43B) and the first drain finger (44B) penetrate the first active region (37) in the first direction (Y) in the planar view, and the first inactive region (38) includes: a first isolation region (38P) provided in a region of the first source finger (43B) that overlaps with the first active region (37) in the first direction (Y) in the planar view, and a second isolation region (38Q) provided in a region of the first drain finger (44B) that overlaps with the first active region (37) in the first direction (Y) in the planar view.

[0278] [Supplementary Note 32] The second source wiring (63) includes a second source finger (63B) extending in the first direction (Y), The second drain wiring (64) includes a second drain finger (64B) extending in the first direction (Y), Both the second source finger (63B) and the second drain finger (64B) penetrate the second active region (57) in the first direction (Y) in the plan view, The second inactive region (58) includes: A first isolation region (58P) provided in a region of the second source finger (63B) that overlaps with the second active region (57) in the first direction (Y) in the plan view, A second isolation region (58Q) provided in a region of the second drain finger (64B) that overlaps with the second active region (57) in the first direction (Y) in the plan view, 32. The semiconductor device according to any one of appendices 1 to 18 and 31, comprising:

[0279] [Supplementary Note 33] The first source wiring (121) includes a first source finger (121B) extending in the first direction (Y), The first drain wiring (122) includes a first drain finger (122B) extending in the first direction (Y), Both the first source finger (121B) and the first drain finger (122B) penetrate the first active region (141) in the first direction (Y) in the plan view, The inactive region (143) includes: A first isolation region (38P) provided in a region of the first source finger (121B) that overlaps with the first active region (141) in the first direction (Y) in the plan view, A second isolation region (38Q) provided in a region of the first drain finger (122B) that overlaps with the first active region (141) in the first direction (Y) in the plan view, 23. The semiconductor device according to any one of appendices 19 to 22, comprising:

[0280] [Supplementary Note 34] The second source wiring (124) includes a second source finger (124B) extending in the first direction (Y), The second drain wiring (125) includes a second drain finger (125B) extending in the first direction (Y), Both the second source finger (124B) and the second drain finger (125B) penetrate the second active region (142) in the first direction (Y) in the plan view, The inactive region (143) includes: A first isolation region (58P) provided in a region of the second source finger (124B) that overlaps with the second active region (142) in the first direction (Y) in the plan view, A second isolation region (58Q) provided in a region of the second drain finger (125B) that overlaps with the second active region (142) in the first direction (Y) in the plan view, 34. The semiconductor device according to any one of appendices 19 to 22 and 33, comprising:

[0281] [Appendix 35] The semiconductor device according to any one of appendices 1 to 18, including: a die pad (70) on which the first semiconductor chip (30) and the second semiconductor chip (50) are mounted; a sealing resin (90) that seals at least the first semiconductor chip (30) and the second semiconductor chip (50); and external terminals (80) that are individually electrically connected to the carrier transistor (TC) and the peak transistor (TP) and are at least partially exposed from the sealing resin (90).

[0282] [Appendix 36] The semiconductor device according to any one of Appendices 19 to 22, including: a die pad (70) on which the semiconductor chip (100) is mounted; a sealing resin (90) that seals at least the semiconductor chip (100); and external terminals (80) that are individually electrically connected to the carrier transistor (TC) and the peak transistor (TP) and are at least partially exposed from the sealing resin (90).

[0283] [Supplementary Note 37] A Doherty amplifier (10) comprising: the semiconductor device (20) according to Supplementary Note 35 or 36; and a distribution circuit (15) and a combining circuit (16) electrically connected to the semiconductor device (20), wherein the external terminal (80) comprises: a first terminal (81) electrically connected to the first gate electrode (48) of the carrier transistor (TC); a second terminal (82) electrically connected to the second gate electrode (68) of the peak transistor (TP); a third terminal (83) electrically connected to the first drain electrode (47) of the carrier transistor (TC); and a fourth terminal (84) electrically connected to the second drain electrode (67) of the peak transistor (TP), wherein the distribution circuit (15) is electrically connected to the first terminal (81) and the second terminal (82), and the combining circuit (16) is electrically connected to the third terminal (83) and the fourth terminal (84).

[0284] [Supplementary Note 38] A method for manufacturing a semiconductor device (20) including a first semiconductor chip (30) including a carrier transistor (TC) constituting a part of a carrier amplifier (13), and a second semiconductor chip (50) including a peak transistor (TP) constituting a part of a peak amplifier (14), the method comprising the steps of: forming an electron transit layer (813) on a semiconductor wafer (800); forming an electron supply layer (814) on the electron transit layer (813) having a band gap larger than that of the electron transit layer (813); forming a first active region (817A) in which a two-dimensional electron gas (816) is generated; and forming a second active region (817B) spaced apart from the first active region (817A) in which the two-dimensional electron gas (816) is generated. forming an inactive region (818) in a plan view surrounding each of the first active region (817A) and the second active region (817B) in which the two-dimensional electron gas (816) is less likely to be generated than in both the first active region (817A) and the second active region (817B); forming a first source electrode (46) and a first drain electrode (47) spaced apart from each other above the electron supply layer (814) in the first active region (817A); forming a second source electrode (66) and a second drain electrode (67) spaced apart from each other above the electron supply layer (814) in the second active region (817B); and forming a first insulating layer (820) covering the first source electrode (46), the first drain electrode (47), the second source electrode (66), and the second drain electrode (67); forming a first gate electrode (48) on the first insulating layer (820) in the first active region (817A); forming a second gate electrode (68) on the first insulating layer (820) in the second active region (817B); and forming the first semiconductor chip (30) and the second semiconductor chip (50) by cutting the semiconductor wafer (800) in a plan view, wherein a dimension (LY1) of the first semiconductor chip (30) in a first direction (Y) is equal to a dimension (LY2) of the second semiconductor chip (50) in the first direction (Y),A method for manufacturing a semiconductor device, wherein the sum of the dimensions in the first direction (Y) of the inactive regions (818) arranged on both sides of the first active region (817A) in the first direction (Y) is greater than the sum of the dimensions in the first direction (Y) of the inactive regions (818) arranged on both sides of the second active region (817B) in the first direction (Y).

[0285] [Supplementary Note 39] The method for manufacturing a semiconductor device according to Supplementary Note 38, wherein the first source electrode (46), the first drain electrode (47), the second source electrode (66), and the second drain electrode (67) are formed in the same process, and the first gate electrode (48) and the second gate electrode (68) are formed in the same process.

[0286] [Supplementary Note 40] A method for manufacturing a semiconductor device (20) including a semiconductor chip (100) including a carrier transistor (TC) constituting a part of a carrier amplifier (13) and a peak transistor (TP) constituting a part of a peak amplifier (14), the method comprising: forming an electron transit layer (813) on a semiconductor wafer (800); forming an electron supply layer (814) on the electron transit layer (813) having a band gap larger than that of the electron transit layer (813); forming a first active region (817A) in which a two-dimensional electron gas (816) is generated; and forming a second active region (817B) spaced apart from the first active region (817A) in which the two-dimensional electron gas (816) is generated. forming an inactive region (818) in a plan view surrounding each of the first active region (817A) and the second active region (817B) in which the two-dimensional electron gas (816) is less likely to be generated than in both the first active region (817A) and the second active region (817B); forming a first source electrode (46) and a first drain electrode (47) spaced apart from each other above the electron supply layer (814) in the first active region (817A); forming a second source electrode (66) and a second drain electrode (67) spaced apart from each other above the electron supply layer (814) in the second active region (817B); and forming a first insulating layer (820) covering the first source electrode (46), the first drain electrode (47), the second source electrode (66), and the second drain electrode (67); forming a first gate electrode (48) on the first insulating layer (820) in the first active region (817A); forming a second gate electrode (68) on the first insulating layer (820) in the second active region (817B); and forming the semiconductor chip (100) by cutting the semiconductor wafer (800) in a plan view,A method for manufacturing a semiconductor device, wherein the sum of the dimensions in the first direction (Y) of the inactive regions (818) arranged on both sides of the first active region (817A) in the first direction (Y) is greater than the sum of the dimensions in the first direction (Y) of the inactive regions (818) arranged on both sides of the second active region (817B) in the first direction (Y).

[0287] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims.

[0288] 10...Doherty amplifier, 11...input terminal, 12...output terminal, 13...carrier amplifier, 14...peak amplifier, 15...distribution circuit, 16...combining circuit, 17-19...quarter wavelength phase line, 20...semiconductor device, 30...first semiconductor chip, 30A...first input pad, 30B...first output pad, 31...first semiconductor substrate, 31S...first substrate surface, 31R...first substrate back surface, 32...first buffer layer, 33...first electron transit layer, 34...first electron supply layer, 35...first cap layer, 36...two-dimensional electron gas (2DEG), 37...first active region, 38...first inactive region, 38A...first region, 38B...second region, 38C...third region, 38D...fourth region, 38P...first isolation region, 38Q...second isolation region, 40...insulating layer, 41...first insulating layer, 41A...first source contact opening, 41B...first drain contact opening, 41C...first gate contact opening, 42...second insulating layer, 42A...second source contact opening, 42B...second drain contact opening, 42C...second gate contact opening, 43...first source wiring, 43A...first base portion, 43B...first source finger, 43C...first pad portion, 44...first drain wiring, 44A...first base portion, 44B...first drain finger, 45...first gate wiring, 46...first source electrode, 47...first drain electrode, 48...first gate electrode, 50...second semiconductor chip, 50A...second input pad, 50B...second output pad, 51...second semiconductor substrate, 52...second buffer layer, 53...second electron transit layer, 54...second electron supply layer, 55...second cap layer, 56...two-dimensional electron gas (2DEG), 57...second active region, 58...second inactive region, 58A...fifth region, 58B...sixth region, 58C...seventh region, 58D...eighth region, 58P...first isolated region, 58Q...second isolated region, 6 0...insulating layer, 61...first insulating layer, 61A...first source contact opening, 61B...first drain contact opening, 61C...first gate contact opening, 62...second insulating layer, 62A...second source contact opening, 62B...second drain contact opening, 62C...second gate contact opening, 63...second source wiring, 63A...second base portion, 63B...second source finger, 63C...second pad portion, 64...second drain wiring, 64A...second base portion, 64B...second drain finger, 65...second gate wiring, 66...second source electrode, 67...second drain electrode,68...second gate electrode, 70...die pad, 71...first surface, 72...second surface, 80...external terminal, 81 to 84...first to fourth terminals, 81A to 84A...protruding portion, 90...sealing resin, 100...semiconductor chip, 101...semiconductor substrate, 101S...substrate front surface, 101R...substrate rear surface, 102...buffer layer, 103...electron transit layer, 104...electron supply layer, 105...cap layer, 106...two-dimensional electron gas (2DEG), 110...insulating layer, 111...first insulating layer, 112...second insulating layer, 121...first source wiring, 121A...first base portion, 121B...first source finger, 1 21C...first pad portion, 122...first drain wiring, 122A...first base portion, 122B...first drain finger, 123...first gate wiring, 124...second source wiring, 124A...second base portion, 124B...second source finger, 124C...second pad portion, 125...second drain wiring, 125A...second base portion, 125B...second drain finger, 126...second gate wiring, 131...first source electrode, 132...first drain electrode, 133...first gate electrode, 134...second source electrode, 135...second drain electrode, 136...second gate electrode, 141...first active region, 142...second active region, 143...inactive region, 143A to 143G...first to seventh regions, 800...semiconductor wafer, 801...first surface, 802...second surface, 812...buffer layer, 813...electron transit layer, 814...electron supply layer, 815...cap layer, 816...two-dimensional electron gas (2DEG), 817...active region, 817A...first active region, 817B...second active region, 818...inactive region, 820...first insulating layer, 821...gate contact opening, 830...second insulating layer, 831...source contact opening, 832...drain contact opening, W 1 to W4...wire, SD...conductive bonding material, TC...carrier transistor, TP...peak transistor, RC...carrier region, RP...peak region, C1...first chip region, C2...second chip region, LX1...X-direction dimension of first semiconductor chip, LX2...X-direction dimension of second semiconductor chip, LY1...Y-direction dimension of first semiconductor chip, LY2...Y-direction dimension of second semiconductor chip, RY1, QY1, SY1...Y-direction dimension of first active region, RX1, QX1, SX1...X-direction dimension of first active region, RY2, QY2, SY2...Y-direction dimension of second active region,RX2, QX2, SX2... X-direction dimension of the second active region, DF1... Y-direction dimension of the first drain finger of the first drain wiring, DF2... Y-direction dimension of the second drain finger of the second drain wiring, SF1... Y-direction dimension of the first source finger of the first source wiring, SF2... Y-direction dimension of the second source finger of the second source wiring, BX1... X-direction dimension of the first base portion of the first drain wiring, BX2... X-direction dimension of the second base portion of the second drain wiring, PX1, TX1... X-direction dimension of the first region, PX2, TX2... X-direction dimension of the second region, PX3, TX3... third region X-direction dimensions of the fourth region, PX4, TX4...X-direction dimensions of the fourth region, PX5, TX5...X-direction dimensions of the fifth region, PX6, TX6...X-direction dimensions of the sixth region, PX7, TX7...X-direction dimensions of the seventh region, PX8...X-direction dimensions of the eighth region, PY1, TY1...Y-direction dimensions of the first region, PY2, TY2...Y-direction dimensions of the second region, PY3, TY3...Y-direction dimensions of the third region, PY4, TY4...Y-direction dimensions of the fourth region, PY5, TY5...Y-direction dimensions of the fifth region, PY6, TY6...Y-direction dimensions of the sixth region, PY7...Y-direction dimensions of the seventh region, PY8...Y-direction dimensions of the eighth region.

Claims

1. A semiconductor device comprising: a first semiconductor chip including a carrier transistor constituting part of a carrier amplifier; and a second semiconductor chip including a peak transistor constituting part of a peak amplifier, wherein the first semiconductor chip includes: a first electron transit layer; a first electron supply layer provided on the first electron transit layer and having a larger band gap than the first electron transit layer; a first active region in which two-dimensional electron gas is generated, extending in a first direction and a second direction perpendicular to the first direction in a planar view; and a first inactive region surrounding the first active region in a planar view and in which two-dimensional electron gas is less likely to be generated than in the first active region; and a first source electrode, a first gate electrode, and a first drain electrode provided in the first active region above the first electron supply layer, extending in the first direction and spaced apart from each other in the second direction; and the second semiconductor chip includes: a second electron transit layer; and a second electron supply layer provided on the second electron transit layer and having a larger band gap than the second electron transit layer. a second active region in which two-dimensional electron gas is generated, the second active region extending in the first direction and the second direction; a second inactive region in which two-dimensional electron gas is less likely to be generated in the peak transistor than in the second active region in a planar view; and a second source electrode, a second gate electrode, and a second drain electrode provided above the second electron supply layer in the second active region, the second source electrode, the second gate electrode, and the second drain electrode extending in the first direction and spaced apart from each other in the second direction, wherein, in a planar view, a dimension of the first semiconductor chip in the first direction is equal to a dimension of the second semiconductor chip in the first direction, and a sum of the dimensions in the first direction of the first inactive regions disposed on both sides of the first active region in the first direction is greater than a sum of the dimensions in the first direction of the second inactive regions disposed on both sides of the second active region in the first direction.

2. The semiconductor device described in claim 1, wherein the first inactive region includes a first region and a second region adjacent to the first active region in the first direction, and a third region and a fourth region adjacent to the first active region in the second direction; the second inactive region includes a fifth region and a sixth region adjacent to the second active region in the first direction, and a seventh region and an eighth region adjacent to the second active region in the second direction; and the dimensions of both the first region and the second region in the first direction are larger than the dimensions of both the fifth region and the sixth region in the first direction.

3. The semiconductor device according to claim 2, wherein the dimension in the first direction of at least one of the first region and the second region is greater than the dimension in the second direction of both the third region and the fourth region.

4. The semiconductor device according to claim 2 or 3, wherein the dimensions in the second direction of both the third region and the fourth region are greater than the dimensions in the second direction of both the seventh region and the eighth region.

5. A semiconductor device as described in claim 1, wherein the sum of the dimensions in the second direction of the first inactive regions arranged on both sides of the first active region in the second direction is greater than the sum of the dimensions in the second direction of the second inactive regions arranged on both sides of the second active region in the second direction.

6. The semiconductor device according to any one of claims 1 to 5, wherein the dimension of the second semiconductor chip in the second direction is larger than the dimension of the first semiconductor chip in the second direction.

7. The semiconductor device according to claim 6, wherein the dimension of said first semiconductor chip in said first direction is larger than the dimension of said first semiconductor chip in said second direction.

8. The semiconductor device according to any one of claims 1 to 7, wherein the dimension of the first active region in the first direction is smaller than the dimension of the second active region in the first direction.

9. The semiconductor device according to claim 8, wherein the sum of the dimensions in the first direction of the second gate electrodes in the second active region is 1.5 times or more the sum of the dimensions in the first direction of the first gate electrodes in the first active region.

10. The semiconductor device described in claim 8 or 9, wherein the first semiconductor chip includes: an insulating layer covering the first source electrode, the first drain electrode, and the first gate electrode; a first source wiring provided on the insulating layer and electrically connected to the first source electrode; and a first drain wiring provided on the insulating layer and electrically connected to the first drain electrode; and the second semiconductor chip includes: an insulating layer covering the second source electrode, the second drain electrode, and the second gate electrode; a second source wiring provided on the insulating layer and electrically connected to the second source electrode; and a second drain wiring provided on the insulating layer and electrically connected to the second drain electrode; and the dimension in the first direction of the first source wiring is equal to the dimension in the first direction of the second source wiring, and the dimension in the first direction of the first drain wiring is equal to the dimension in the first direction of the second drain wiring.

11. The semiconductor device according to claim 8 or 9, wherein the dimension of the first gate electrode in the first direction is smaller than the dimension of the second gate electrode in the first direction.

12. A semiconductor device according to any one of claims 1 to 11, wherein the value obtained by dividing the maximum output of the semiconductor device by the sum of the sum of the dimensions in the first direction of the first gate electrode in the first active region and the sum of the dimensions in the first direction of the second gate electrode in the second active region is 5 W / mm or more.

13. A semiconductor device according to any one of claims 1 to 12, wherein a first ratio of the area of ​​the first inactive region to the area of ​​the first active region in a planar view is greater than a second ratio of the area of ​​the second inactive region to the area of ​​the second active region in a planar view.

14. The semiconductor device according to claim 13, wherein the first ratio is 1.5 times or more the second ratio.

15. The semiconductor device according to any one of claims 1 to 14, wherein the first electron transit layer, the first electron supply layer, the second electron transit layer, and the second electron supply layer are each made of a nitride semiconductor.

16. The semiconductor device according to any one of claims 1 to 15, wherein each of the first semiconductor chip and the second semiconductor chip includes a semiconductor substrate, and the semiconductor substrate is made of a material containing SiC.

17. A semiconductor device according to any one of claims 1 to 16, wherein the first semiconductor chip and the second semiconductor chip are arranged at the same position in the first direction and spaced apart from each other in the second direction, and the first active region is arranged such that its center in the first direction is offset in the first direction from the center in the first direction of the second active region.

18. A semiconductor device according to any one of claims 1 to 16, wherein the first semiconductor chip and the second semiconductor chip are arranged at the same position in the first direction and spaced apart from each other in the second direction, and the first active region is provided so that its center in the first direction is at the same position as the center in the first direction of the second active region.

19. A semiconductor device including a semiconductor chip provided with a carrier transistor constituting a part of a carrier amplifier and a peak transistor constituting a part of a peak amplifier, wherein the semiconductor chip has a rectangular shape extending in a first direction and in a second direction perpendicular to the first direction in a plan view, the semiconductor chip comprising: an electron transit layer; an electron supply layer provided on the electron transit layer and having a band gap larger than that of the electron transit layer; a first active region extending in the first direction and the second direction, the first active region being a region in which two-dimensional electron gas is generated within the region in which the carrier transistor is provided; a second active region extending in the first direction and the second direction and having a dimension in the first direction larger than that of the first active region, the second active region being a region in which the two-dimensional electron gas is generated within the region in which the peak transistor is provided; and an inactive region surrounding the first active region and the second active region in a plan view, the inactive region in which two-dimensional electron gas is less likely to be generated than in both the first active region and the second active region. a first source electrode, a first gate electrode, and a first drain electrode provided above the electron supply layer in the first active region, extending in the first direction and spaced apart from each other in the second direction; and a second source electrode, a second gate electrode, and a second drain electrode provided above the electron supply layer in the second active region, extending in the first direction and spaced apart from each other in the second direction, wherein a sum of dimensions in the first direction of the inactive regions provided on both sides of the first active region in the first direction is greater than a sum of dimensions in the first direction of regions adjacent to the inactive regions provided on both sides of the second active region in the first direction.

20. A semiconductor device as described in claim 19, wherein the dimension in the second direction of a region of the inactive region between the first active region and the second active region is smaller than the dimension in the first direction of a region of the inactive region adjacent to the first active region in the first direction.

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