Liquid cooling systems and methods of manufacturing thereof

Abstract

Disclosed herein is a liquid cooling system which may be adapted for cooling computing systems. In certain embodiments, a liquid-cooled computing system is provided including: a first plurality of semiconductor chips supported by a first ceramic substrate, where the first ceramic substrate includes microchannels, each microchannel includes an inlet, an outlet, and a path, where each microchannel is configured to support the flow of liquid through the inlet, through the path, and then out the outlet such that heat is pulled from the plurality of semiconductor chips by the liquid.

Description

LIQUID COOLING SYSTEMS AND METHODS OF MANUFACTURING THEREOFCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The current application claims the benefit of and priority under 35 U.S.C. §119(e) to U.S. Provisional Patent Application No. 63 / 689,865, entitled “Ceramic Substrate with Microchannels for Liquid Cooling”, filed September 3, 2024, and to U.S. Provisional Patent Application No. 63 / 720,010, entitled “Liquid Cooling Systems and Methods of Manufacturing Thereof’, filed November 13, 2024, the disclosures of which are incorporated herein by reference in their entireties for all purposes.FIELD OF THE INVENTION

[0002] The present invention generally relates to liquid cooling systems. More specifically, the present invention relates to liquid cooling systems which may be utilized to cool computing systems including semiconductor chips.BACKGROUND

[0003] For over 40 years Moore’s Law has propelled computing, but in recent years growth has reached a plateau. Clock frequency speeds are flat over the last decade while the number of cores has increased. This is due to thermal limits which limit operating frequency. It is simply not possible to remove the heat load from the chip.

[0004] While growth in the clock speed exponential is slowing, a new computing explosion has begun. Artificial Intelligence (Al) is pushing the boundaries of computing systems with ever expanding models and training sets. The next phase of cloud computing growth is being driven by AL One study shows Al models with 300,000 times increase in compute resources over the last 7 years.

[0005] The current state of the art in data center cooling is forced air cooling. The fundamental problem with this approach is that HVAC systems and chilled water systems are used at the facilities level but fan based air cooling is used in the building and the rack. Fan cooling can consume up to 25% extra parasitic power. Air is inherently a good insulator and impedes the flow of heat. However, liquid (e.g. water) may be 4000 times more efficient than air in transferring heat. Direct liquid cooling at the chip level maysignificantly improves performance and energy efficiency. With the ultimate goal of computing systems to reach and exceed human brain level performance, liquid cooling may be the only possible approach in the foreseeable future. While, liquid cooling has been utilized in the past, advanced liquid cooling with innovative packaging may be beneficial to aid in the growth of high-performance computing systems.SUMMARY OF THE INVENTION

[0006] In some aspects, the techniques described herein relate to a liquid-cooled computing system including: a first plurality of semiconductor chips supported by a first ceramic substrate, wherein the first ceramic substrate includes microchannels, each microchannel includes an inlet, an outlet, and a path, wherein each microchannel is configured to support the flow of liquid through the inlet, through the path, and then out the outlet such that heat is pulled from the plurality of semiconductor chips by the liquid.

[0007] In some aspects, the techniques described herein relate to a liquid-cooled computing system, where the microchannels are positioned directly below at least one of the plurality of chips.

[0008] In some aspects, the techniques described herein relate to a liquid-cooled computing system, wherein the path winds laterally in one direction and then the opposite direction while traveling vertically up the ceramic substrate.

[0009] In some aspects, the techniques described herein relate to a liquid-cooled computing system, wherein the ceramic substrate further includes electrical interconnects.

[0010] In some aspects, the techniques described herein relate to a liquid-cooled computing system, wherein the electrical interconnects include an interconnect that go completely through the ceramic substrate from a surface supporting the ceramic substrate to an opposite surface.

[0011] In some aspects, the techniques described herein relate to a liquid-cooled computing system, wherein the interconnect connects to one of the plurality of chips.

[0012] In some aspects, the techniques described herein relate to a liquid-cooled computing system, wherein the interconnect connects to a power source on the opposite side of the ceramic substrate.

[0013] In some aspects, the techniques described herein relate to a liquid-cooled computing system, wherein the interconnect connects to another chip or component configured to provide signals to or receive signals from at least one of the plurality of chips.

[0014] In some aspects, the techniques described herein relate to a liquid-cooled computing system, wherein the electrical interconnects include an interconnect that travels within the ceramic substrate.

[0015] In some aspects, the techniques described herein relate to a liquid-cooled computing system, wherein the interconnect connects a first chip to a second chip of the one or more chips.

[0016] In some aspects, the techniques described herein relate to a liquid-cooled computing system, wherein the electrical interconnects include metal.

[0017] In some aspects, the techniques described herein relate to a liquid-cooled computing system, wherein the metal includes copper.

[0018] In some aspects, the techniques described herein relate to a liquid-cooled computing system, wherein the ceramic substrate further includes one or more thermal vias including high thermal conductivity material.

[0019] In some aspects, the techniques described herein relate to a liquid-cooled computing system, wherein the high thermal conductivity material includes metal.

[0020] In some aspects, the techniques described herein relate to a liquid-cooled computing system, wherein the metal includes copper.

[0021] In some aspects, the techniques described herein relate to a liquid-cooled computing system, wherein the ceramic substrate includes silicon carbide (SiC), silicon nitride (Si3N4), and / or aluminum oxide (AI2O3).

[0022] In some aspects, the techniques described herein relate to a liquid-cooled computing system, wherein the one or more chips include silicon (Si).

[0023] In some aspects, the techniques described herein relate to a liquid-cooled computing system, wherein the ceramic substrate further supports a power converter, wherein the one or more silicon chips includes a first chip connected to the power converter through an interconnect supported by the ceramic substrate such that the power converter powers the first chip.

[0024] In some aspects, the techniques described herein relate to a liquid-cooled computing system, wherein the first chip is connected to an interposer or substrate.

[0025] In some aspects, the techniques described herein relate to a liquid-cooled computing system, further including a second chip supported on an opposite surface of the ceramic substrate from the one or more chips.

[0026] In some aspects, the techniques described herein relate to a liquid-cooled computer system, wherein the interconnect passes through the ceramic substrate and electrically connects to the other chip such that the power converter powers both the first chip and the second chip.

[0027] In some aspects, the techniques described herein relate to a liquid-cooled computer system, further including layers of interconnects which are layered between the ceramic substrate and the plurality of chips which allow the plurality of chips to communicate.

[0028] In some aspects, the techniques described herein relate to a liquid-cooled computer system, further including: a second plurality of semiconductor chips supported by a second ceramic substrate, wherein the second ceramic substrate includes microchannels, each microchannel includes an inlet, an outlet, and a path, wherein each microchannel is configured to support the flow of liquid through the inlet, through the path, and then out the outlet such that heat is pulled from the second plurality of semiconductor chips by the liquid, wherein a backside of the second ceramic substrate faces a backside of the first ceramic substrate.

[0029] In some aspects, the techniques described herein relate to a liquid-cooled computer system, wherein a low thermal conductivity layer is positioned between the first ceramic substrate and the second ceramic substrate.

[0030] In some aspects, the techniques described herein relate to a liquid-cooled computer system, further including: a second plurality of semiconductor chips supported on an opposite side of the first ceramic substrate than the first plurality of semiconductor chips.

[0031] In some aspects, the techniques described herein relate to a liquid-cooled computer system, wherein the first ceramic substrate includes an interconnect whichelectrically connects a chip of the second plurality of semiconductor chips with a chip of the first plurality of semiconductor chips.

[0032] In some aspects, the techniques described herein relate to a liquid-cooled computer system, wherein the first plurality of semiconductor chips are positioned on a center part of the first ceramic substrate and the inlet and outlet of the microchannels are located on the outside part of the first ceramic substrate.

[0033] In some aspects, the techniques described herein relate to a liquid-cooled thermophotovoltaic power generator including: a thermophotovoltaic power generator including an array of semiconductor chips supported by a ceramic substrate; and a heat source configured to emit energy towards the thermophotovoltaic power generator such that a fraction of the energy is converted to electricity and the rest remains as heat, wherein the ceramic substrate includes microchannels, each microchannel includes an inlet, an outlet, and a path, wherein each microchannel is configured to support the flow of liquid through the inlet, through the path, and then out the outlet such that heat is pulled from the array of semiconductor chips by the liquid.

[0034] In some aspects, the techniques described herein relate to a manufacturing method for a liquid-cooling device, the method including: providing a first green ceramic layer; patterning the first green ceramic layer to include an inlet and an outlet for microchannels; providing a second green ceramic layer; patterning the second green ceramic layer to include a channel for the microchannels; providing a third green ceramic layer; stacking the second green ceramic layer on the first green ceramic layer such that the inlet and the outlet are at opposite ends of the channel; stacking the third green ceramic layer on the second green ceramic layer such that the third green ceramic layer provides a top surface to the channel; and firing the stack of the first green ceramic layer, the second green ceramic layer, and the third green ceramic layer which merges the first green ceramic layer, the second green ceramic layer, and the third green ceramic layer into a single ceramic structure.

[0035] In some aspects, the techniques described herein relate to a method, wherein patterning the first green ceramic layer further includes patterning a first hole corresponding to the inlet and a second hole corresponding to the outlet.

[0036] In some aspects, the techniques described herein relate to a method, wherein patterning the first green ceramic layer includes cutting the first green ceramic layer.

[0037] In some aspects, the techniques described herein relate to a method, wherein patterning the second green ceramic layer further includes patterning a slot corresponding to the channel.

[0038] In some aspects, the techniques described herein relate to a method, further including patterning the third green ceramic layer to include vias and / or interconnect channels.

[0039] In some aspects, the techniques described herein relate to a manufacturing method for a liquid-cooling device, the method including: providing a first green ceramic layer; patterning the first green ceramic layer to include an inlet and an outlet for microchannels; providing a second green ceramic layer; patterning the second green ceramic layer to include a first channel for the microchannels and an outlet; providing a third green ceramic layer; patterning the third green ceramic layer to include an intermediate passageway and an outlet; providing a fourth green ceramic layer; patterning the fourth green ceramic layer to include a second channel for the microchannels; providing a fifth green ceramic layer; stacking the second green ceramic layer on the first green ceramic layer such that the inlet is at an end of the first channel; stacking the third green ceramic layer on the second green ceramic layer such that the intermediate passageway is at an end of the first channel opposite to the inlet; stacking the fourth green ceramic layer on the third green ceramic layer such that the intermediate passageway is at one end of the second channel and the outlet of the third green ceramic layer is at an other end of the second channel, wherein the outlet of the third green ceramic layer, the second green ceramic layer and the first green ceramic layer communicate to form a single outlet; stacking the fifth green ceramic layer on top of the fourth green ceramic layer; and firing the stack of the first green ceramic layer, the second green ceramic layer, the third green ceramic layer, the fourth green ceramic layer, and the fifth green ceramic layer which merges the first green ceramic layer, the second green ceramic layer, the third green ceramic layer, the fourth green ceramic layer, and the fifth green ceramic layer into a single ceramic structure.BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The description will be more fully understood with reference to the following figures and data graphs, which are presented as various embodiment of the disclosure and should not be construed as a complete recitation of the scope of the disclosure, wherein:

[0041] Fig. 1 is a diagram of an example heat diffusion plate in accordance with an embodiment of the invention.

[0042] Fig. 2 is a diagram of an example liquid cooling system in accordance with an embodiment of the invention.

[0043] Fig. 3 is a diagram of an example liquid cooling system in accordance with an embodiment of the invention.

[0044] Fig. 4 is a diagram of an example liquid cooling system in accordance with an embodiment of the invention.

[0045] Fig. 5 is a diagram of an example liquid cooling system in accordance with an embodiment of the invention.

[0046] Fig. 6 is a diagram of an example liquid cooling system in accordance with an embodiment of the invention.

[0047] Fig. 7 is a diagram of an example liquid cooling system in accordance with an embodiment of the invention.

[0048] Fig. 8 illustrates a schematic of an example configuration for inlet / outlet ports and semiconductor chips on ceramic substrates.

[0049] Fig. 9 illustrates an example liquid cooling system in accordance with an embodiment of the invention.

[0050] Fig. 10 illustrates an example typical integrated circuit mounted on packaging in accordance with prior art.

[0051] Fig. 11 is a diagram of an example liquid cooling system in accordance with an embodiment of the invention.

[0052] Fig. 12 is an image of an example microchannel ceramic plate.

[0053] Fig. 13 is an example schematic of multiple green ceramic layers used to produce the ceramic microchannel cooling plate in accordance with an embodiment of the invention.

[0054] Fig. 14 is a cross sectional view of a ceramic microchannel cooling plate in accordance with an embodiment of the invention.

[0055] Fig. 15 is a cross-sectional view of an example liquid cooling system in accordance with an embodiment of the invention.

[0056] Fig. 16A is a schematic of a cooling system 1600 in accordance with an embodiment of the invention.

[0057] Fig. 16B is a schematic of a stack of a large array of chips which are each supported by a ceramic microchannel cooling plate in accordance with an embodiment of the invention.

[0058] Fig. 16C is a schematic of an array of stacks in accordance with an embodiment of the invention.

[0059] Fig. 17 is a schematic of a cooling system in accordance with an embodiment of the invention.

[0060] Fig. 18 is a schematic of a cooling system in accordance with an embodiment of the invention.

[0061] Fig. 19 is a schematic illustrating the positioning of chips on two sides of a microchannel cooling plate in accordance with an embodiment of the invention.

[0062] Fig. 20 is a schematic illustrating the positioning of chips on two sides of a microchannel cooling plate in accordance with an embodiment of the invention.DETAILED DESCRIPTION

[0063] The disclosed technology relates to a novel liquid cooling system. The liquid cooling system includes a heat diffusion plate. Fig. 1 is a diagram of an example heat diffusion plate in accordance with an embodiment of the invention. The heat diffusion plate may include a ceramic substrate 102. The ceramic substrate 102 includes microchannels 104. The microchannels 104 may include an inlet 110, an outlet 108, and a path 106. The microchannels 104 may support the flow of liquid through the inlet 110, through the path 106, and then out the outlet 108. The ceramic substrate 102 may include a top surface 102a. The top surface 102a may support one or more heat producingelements such as a plurality of semiconductor chips. Heat may be pulled from the heat producing elements by the liquid. In some examples, the liquid may be water or glycol.

[0064] While only one microchannel is illustrated, it is understood that many different microchannels may be present in the ceramic substrate 102. The microchannels 104 may include multiple branches such that the microchannels 104 can form 3D patterns in the x,y,z directions. The microchannels 104 may include multiple outlets or multiple inlets. For example, the microchannels 104 may include a single inlet and two outlets such that the path may branch off at somewhere in the path into the multiple outlets. Having different branches and multiple outlets may prevent failure by clogging a single path.

[0065] Fig. 2 is a diagram of an example liquid cooling system in accordance with an embodiment of the invention. The liquid cooling system includes a ceramic substrate 202. The ceramic substrate 202 includes microchannels 204. The microchannels 204 may include an inlet 210, an outlet 208, and a path 206. The microchannels 204 may support the flow of liquid through the inlet 210, through the path 206, and then out the outlet 208. The ceramic substrate 202 may support a plurality of semiconductor chips 212. Heat may be pulled from the plurality of semiconductor chips 212 by the liquid. The semiconductor chips 212 may be connected to electrical interconnects 214. The electrical interconnects 214 may pass from the surface of the ceramic substrate 202 supporting the plurality of semiconductor chips 212 to the opposite surface of the ceramic substrate 202. The electrical interconnects 214 may include copper or other electrically conductive metal. The ceramic substrate 202 may be embedded with electrical interconnects 216 that reside within the ceramic substrate 202. The electrical interconnects 216 may connect the plurality of semiconductor chips 212 together. The electrical interconnects 216 may also connect other electrical components together. The ceramic substrate 202 may include thermal interconnects 218. The thermal interconnects 218 may extend from the surface of the ceramic substrate 202 supporting the plurality of semiconductor chips 212 to the opposite surface of the ceramic substrate 202. The thermal interconnects 218 may include high thermal conductivity material such as copper or another metal. The electrical interconnects 214 may also act as thermal interconnects.

[0066] Fig. 3 is a diagram of an example liquid cooling system in accordance with an embodiment of the invention. The liquid cooling system includes a semiconductor chip304 which is connected to a substrate 302. The substrate 302 may be an interposer which may support other semiconductor chips which may be connected to the semiconductor chip 304. The semiconductor chip 304 may be connected to a power converter 310 by an electrical line 310. A heat diffusion plate 306 may be positioned on top of the semiconductor chip 304. The electrical line 310 may run through the heat diffusion plate 306 similar to the electrical interconnects 216 of Fig. 2. The electrical lines 310 may also run on the surface of the heat diffusion plate 306. The power converter 310 may be utilized to power the semiconductor chip 304. The power converter 310 may be attached to the heat diffusion plate 306. The heat diffusion plate 306 may cool both the semiconductor chip 304 and the power converter 310. The heat diffusion plate 306 may be the ceramic substrate described in connection with Figs. 1 and 2 which includes microchannels that cool the semiconductor chip 304 and the power converter 310.

[0067] The heat diffusion plate 306 may be bi-facial such that the heat diffusion plate 306 can cool both sides of the heat diffusion plate 306. Fig. 4 is a diagram of an example liquid cooling system in accordance with an embodiment of the invention. The liquid cooling system includes all of the features of the liquid cooling system described in connection with Fig. 3. The description from Fig. 3 is applicable to Fig. 4 and will not be repeated in detail. The electrical lines 310 include a branch 404 which passes through the heat diffusion plate 306 and connects to a semiconductor chip 406 on an opposite side of the heat diffusion plate 306. The semiconductor chip 406 may be positioned on a substrate 402. The substrate 402 may be an interposer which may support other semiconductor chips which may be connected to the semiconductor chip 406.

[0068] The ceramic substrate may provide many beneficial properties. The ceramic substrate may be an insulator which allows for interconnects to be placed on and embedded within the ceramic substrate. The ceramic substrate will not corrode when exposed to liquid. The ceramic substrate is compatible with a wide range of liquid coolants. The ceramic substrate may have a coefficient of thermal expansion (CTE) that matches the CTE of the semiconductor chip or closely matches the CTE of the semiconductor chip. The semiconductor chip may be silicon. CTE mismatches lead to structural failures of solder bonds after many temperature cycles. Thus, matched CTE improves reliability. The ceramic substrate may be designed with cooling channels toallow temperature uniformity across the area of the chip. The spatial temperature variation across the semiconductor chip should be minimal. Localized hot spots create points of failure that spread. The ceramic substrate may have low fluid pressure drop. Minimal pressure drop may reduce parasitic power draws and improve reliability of seals, materials, and connections. The ceramic substrate may have low flow rate. Low flow rate may be desirable and increases the effectiveness of the cooling system. Improved effectiveness results in higher fluid exit temperature which can allow the extracted ‘waste heat’ to be used for other useful work. This also allows the heat exchanger rejecting heat to the environment to be more efficient. The ceramic substrate may have low thermal resistance. The lower the thermal resistance of the cooling system and the entire heat flow path allows more heat to be dissipated while keeping the chip junction temperature at specified levels. The ceramic substrate may have parallelism. Parallel flow paths prevent single points of failure and create robust and reliable systems. The ceramic substrate may provide large area. The chip cooling systems have traditionally addressed the design issues of a single chip at a time. But the ceramic substrate may accommodate large arrays of chips or wafer scale integration. The ceramic substrate may accommodate a large variety of coolant types. The coolant impacts storage temperatures, operating temperatures, corrosion, and fouling issues.

[0069] The ceramic substrate may be thin and large (e.g. ~1mm or less in thickness). Both glass and silicon are fragile when handling that limits the physical size. Young’s modulus of glass may be ~70 gigapascals (GPa). Young’s modulus of silicon may be - 150 GPa. Whereas Young’s modulus of ceramic may be -400 GPa. Thus ceramic is ~5x stiffer than glass, and ceramic is ~2.5x stiffer than silicon. This property is beneficial for ceramic since it allows for larger substrates or interposers to be made (e.g. larger lateral size such as 300x300mm and can be handled by humans or machines). The stiffness of a material is proportional to the cube of the thickness. A material changed from 1 mm thick to 0.1 mm thick is 1000 times less stiff.

[0070] The ceramic substrate 306 may accommodate one or more sets of vias between the ceramic substrate 202 and the semiconductor chips 202. Fig. 5 is a diagram of an example liquid cooling system in accordance with an embodiment of the invention. The liquid cooling system includes all of the features of the liquid cooling systemdescribed in connection with Fig. 2. The description from Fig. 2 is applicable to Fig. 5 and will not be repeated in detail. The liquid cooling system includes multiple layers of electrical interconnects 502 which are positioned between the ceramic substrate 202 and the semiconductor chips 202. These layers 502 may be similar to those in a printed circuit board with lateral (xy plane) and z-direction patterns. The ceramic substrate may allow the semiconductor chips 202 to be placed close together (e.g. mm scale distances) which provides high speed electrical signals transmitted without need for extra re-timers and signal correction which may save cost, power, and space.

[0071] In some examples, two ceramic substrate may be stacked back to back or made as one part along with through interconnects. Fig. 6 is a diagram of an example liquid cooling system in accordance with an embodiment of the invention. The liquid cooling system is similar to the system described in connection with Fig. 5. The liquid cooling system includes a first ceramic substrate 602a including microchannels 604a. The microchannels 604a include an inlet 608a, a path 606a, and an outlet 610a. The first ceramic substrate 602a supports a first plurality of semiconductor chips 612a. There are multiple layers of electrical interconnects 614a positioned between the first ceramic substrate 602a and the first plurality of semiconductor chips 612a. The liquid cooling system further includes a second ceramic substrate 602b including microchannels 604b. The microchannels 604b include an inlet 608b, a path 606b, and an outlet 610b. The second ceramic substrate 602b supports a second plurality of semiconductor chips 612b. There is multiple layers of electrical interconnects 614b positioned between the second ceramic substrate 602b and the second plurality of semiconductor chips 612b.

[0072] The first ceramic substrate 602a may be positioned opposite to the second ceramic substrate 602b such that the bottom surface of the first ceramic substate 602a is positioned opposite to a bottom surface of the second ceramic substrate 602b. There may be a thermal insulator between the first ceramic substrate 602a and the second ceramic substrate 602b which may prevent a thermal short between the first ceramic substrate 602a and the second ceramic substrate 602b. The first ceramic substrate 602a and the second ceramic substrate 602b may be stacked back to back or made as one part along with thru interconnections or lateral interconnects. This would keep the chips in higher density and thus allow for higher speed interconnects at lower costs.

[0073] Fig. 7 is a diagram of an example liquid cooling system in accordance with an embodiment of the invention. The liquid cooling system includes a first ceramic substrate 702a including microchannels 704a. The microchannels 704a include an inlet 708a, a path 706a, and an outlet 710a. The first ceramic substrate 702a supports a first plurality of sem iconductor chips 712a. The first plurality of semiconductor chips 712a is positioned on a first electrical interposer 714a. The first electrical interposer 714a may house interconnects and may be single or double sided. For example, a second plurality of semiconductor chips 712b may be positioned on the opposite side of the electrical interposer 714a from the first plurality of semiconductor chips 712a. The liquid cooling system includes a second ceramic substrate 702b including microchannels 704b. The microchannels 704b include an inlet 708b, a path 706b, and an outlet 710b. The second ceramic substrate 702b may support the second plurality of semiconductor chips 714b. The second ceramic substrate 702b also supports a third plurality of semiconductor chips 712c. Multiple layers of electrical interconnects 716 may be positioned between the third plurality of semiconductor chips 712c and the second ceramic substrate 702b. While not illustrated, multiple layers of electrical interconnects may also be positioned between the first plurality of semiconductor chips 712a and the first ceramic substrate 702a and / or the second plurality of semiconductor chips 712b and the second ceramic substrate 702b. The third plurality of semiconductor chips 712c is positioned on a second electrical interposer 714b. A fourth plurality of semiconductor chips 712d is positioned on an opposite side of the second electrical interposer 714b from the third plurality of semiconductor chips 712c.

[0074] In some embodiments, additional elements may be stacked below the fourth plurality of semiconductor chips 712d. For example, a third ceramic substrate may be stacked below the fourth plurality of semiconductor chips. The first ceramic substrate 702a directly cools the first plurality of semiconductor chips 712a. The second ceramic substrate 702b directly cools the second plurality of semiconductor chips 712b and the third plurality of semiconductor chips 712c. Further, the first ceramic substrate 702a and the second ceramic substrate 702b cool the system as a whole such that the first ceramic substrate 702a and the second ceramic substrate 702b cool the first plurality of semiconductor chips 712a, the second plurality of semiconductor chips 712b, the thirdplurality of semiconductor chips 712c, and the fourth plurality of semiconductor chips 712d.

[0075] The ceramic substrates may be stacked to leave room for liquid inlet / outlet ports for each cold plate. Fig. 8 illustrates a schematic of an example configuration for inlet / outlet ports and semiconductor chips on ceramic substrates. The semiconductor chips may be placed in a central area of the ceramic substrates and the liquid inlet and outlet ports may be staggered on the sides of the ceramic substrates. The liquid inlet and outlet ports may be placed on alternating sides of the stacked ceramic substrates.

[0076] Semiconductor chips may be positioned on the ceramic substrate in a 2D array of chips on the semiconductor substrate. Fig. 9 illustrates an example liquid cooling system in accordance with an embodiment of the invention. A plurality of semiconductor chips 904 may be provided on a two dimensional array on a ceramic substrate 902. The plurality of semiconductor chips 904 may include different types such as one or more graphics processing units (GPU) and / or one or more high bandwidth memory (HBM).

[0077] Traditional PCBs made with woven fiberglass cloth (e.g. FR4) has very low thermal conductivity and the layers are not made with channels for liquid cooling. So excessive heat may be an issue. In some embodiments, it has been discovered that the discussed ceramic substrate may replace multiple components within a typical integrated circuit packaging. Specifically, typical chips are mounted on a various boards such as interposers and substrates. Fig. 10 illustrates an example typical integrated circuit mounted on packaging in accordance with prior art. As illustrated, a package substrate and interposer may be provided. Various redistribution layers may be provided on top of the interposer. The ceramic substrate discussed above may eliminate the need for separate packaging substrates and interposers such that the chips along with their redistribution layers may be positioned directly on top of the ceramic substrate.

[0078] Further, it has been discovered that by replacing the packaging substrates there may be less of coefficient of thermal expansion mismatch between the chips and the packaging by eliminating the packaging substrate. Packaging substrates (typically printed circuit boards) may have a drastically different coefficient of thermal expansion from the chips and / or the interposers. However, ceramic substrates may be provided to have a similar coefficient of thermal expansion from the chips.

[0079] The cold plate may be formed of a material that may be CTE-matched or substantially CTE matched with a component that is connected to it. The CTE of the cold plate may fall within a predetermined range relative to the CTE of the component connected to it. For example, the CTE’s of a cold plate and semiconductor device may be within 1 ppm / K, may be within 0.5 ppm / K, may be within 0.2 ppm / K, or may be within 0.1 ppm / K. The CTE of a cold plate may be greater than 0.50 times the CTE of the component connected to it (such as a semiconductor device), and less than 2.0 times the CTE of the component connected to it. Alternatively, the CTE of the cold plate may be greater than 0.5 times, 0.7 times, 0.75 times, 0.9 times, 1.0 times, 1.2 times, 1.3 times, 1.5 times, or 1.7 times, and / or less than 0.7 times, 0.9 times, 1.0 times, 1.2 times, 1.3 times, 1 .5 times, 1 .7 times, 1 .9 times, or 2.0 times the CTE of the component connected to it.

[0080] Some examples of materials that may be used to form the cold plate are ceramics, cermet, or a metal-matrix composite with a thin film insulator. Materials used to form the cold plate may include oxide ceramics, nitride ceramics, silicon-aluminum alloys or composites, tungsten-copper composites, and / or mixtures or combinations thereof.

[0081] The chips may include silicon and the ceramic substrate may be silicon nitride, silicon carbide, and / or aluminum oxide.

[0082] The ceramic material may be alumina, aluminum oxide, silicon nitride, silicon carbide, aluminum nitride, or other ceramics. High thermal conductivity may be advantageous and many of these materials have thermal conductivity of »100 W / mK. As discussed above, it may be advantageous to have the CTE (coefficient of thermal expansion) to be close to the CTE of the chip (in this case silicon with CTE ~ 3.0ppm / K). The ceramics can be engineered to CTE within an acceptable range of the silicon CTE for package assembly and reliability. In some examples, the chips may include silicon and the ceramic material may be alumina (AI2O3). The ceramic material may also be Silicon Nitride, Silicon Carbide, or Aluminum Nitride. The ceramic material may be one of two classes of ceramics, LTCC (low temperature co-fired) and HTCC (high temperature co-fired). Many of the materials with high thermal conductivity are HTCC which are a bit more difficult to work with. In some embodiments, the ceramic material may include channel structures in HTCC material.

[0083] In some embodiments, the ceramic material may be a hybrid engineer ceramic material which may have tailored properties such as specific coefficients of thermal expansion and thermal conductivity by creating composite or hybrid ceramic compositions. By blending two or more materials, the ceramic material may possess intermediate properties that better fit a specific application. The hybrid materials may be produced through powder blending and sintering which may include mixing powders of two or more ceramic materials in controlled proportions. This mixture is then compacted and sintered (heated without melting) to form a dense solid. During sintering, the powders coalesce, and the properties of the hybrid ceramic depend on the relative amounts of each component and how well they interact during the sintering process. The ceramic material may be produced by graded compositions which may be functionally graded materials (FGMs), where the composition changes gradually from one material to another. This can be useful for managing thermal stresses and optimizing thermal and mechanical properties simultaneously. The ceramic material may be produced by composite matrix reinforcement. One material may be used as a matrix and the other as a reinforcement. For example, silicon carbide fibers can be incorporated into an alumina matrix to improve toughness, thermal conductivity, or achieve a desired CTE.

[0084] Various embodiments of the liquid cooling may be provided for thermophotovoltaic power generation (TPV). TPV involves arrays of semiconductor chips that are exposed to high temperature. Some fraction of that thermal power is converted to electricity and the rest remains as heat and needs to be removed to allow the chip to function. Fig. 11 is a diagram of an example liquid cooling system in accordance with an embodiment of the invention. The liquid cooling system includes a heat diffusion plate 1102 similar to the heat diffusion plate described in connection with Fig. 1. A thermophotovoltaic power generator 1104 is positioned on top of the heat diffusion plate 1102. A heat source 1106 provides thermal energy to the thermophotovoltaic power generator 1104. The thermophotovoltaic power generator 1104 converts a fraction of the thermal energy into power. However, a fraction of the thermal energy remains within the thermophotovoltaic power generator 1104 which may be removed to keep the thermophotovoltaic power generator 1104 running efficiently. The heat diffusion plate1102 removes at least a portion of the remaining thermal energy from the thermophotovoltaic power generator 1104.

[0085] Microchannel ceramic plates have been designed and fabricated. Fig. 12 is an image of an example microchannel ceramic plate. The microchannel ceramic plate has a 12cm x 12cm area and is 1 mm thick with tens of thousands of fluid channels.

[0086] The microchannel ceramic plate may be adapted such that each chip receives fresh coolant and is massively parallel with no serial liquid paths. Within each chip area, the liquid flow may also be parallel so there is no single points of failure and no hot spots. The plate may have tens of thousands of liquid flow channels embedded in the material and is likely the largest monolithic microchannel system of its kind. The plate may be 12cm x 12cm and 1 mm thick. In some embodiments, the ceramic plate may have a larger area such as 30cm x 30cm. The ceramic plate may also have different geometries and may accommodate different chip sizes. The ceramic plate may be configured for large numbers of discrete chips or wafer scale large area cooling with 100% fill factor. In some embodiments, the ceramic plate can dissipate >4kW heat load with heat flux of >250 W / cm2while keeping junction temp rise below 55°C. It is capable of heat loads exceeding 10kW in this same size. Total area of the ceramic plate may be 144 cm2.

[0087] Fig. 13 is an example schematic of multiple green ceramic layers used to produce the ceramic microchannel cooling plate in accordance with an embodiment of the invention. A first green ceramic layer 1302 includes a first hole 1302a which may correspond to one of an input port or an output port and a second hold 1302b which may correspond to the other of the input port or the output port. A second green ceramic layer 1304 includes a channel 1304a. When stacking the first green ceramic layer 1302 on top of the second green ceramic layer 1304, the first hole 1302a and the second hole 1302b are positioned at opposite ends of the channel 1304a. A third green ceramic layer 1306 is planar and without holes. During manufacturing, the second green ceramic layer 1304 is stacked on top of the first green ceramic layer 1302 and the third green ceramic layer 1306 is stacked on top of the second green ceramic layer 1304. The first green ceramic layer 1302, the second green ceramic layer 1304, and the third green ceramic layer 1306 may be cut independently and laminated together. While there are only three layersillustrated, it is understood that many other layers may be provided as well. However, the top green ceramic layer as is the third green ceramic layer 1306 is flat and solid.

[0088] In some embodiments, there may be 3D indentations in the ceramic microchannel cooling plate to accommodate chips that are of different height that touch the cooling plate.

[0089] The green ceramic layers may be ~25 microns in thickness and laminated together. The green ceramic layers may also be other thicknesses. There can be any number of layers from 1 to N where N can be any number two or larger. The thickness of each layer can be larger or smaller than 25 pm. The channels may be made of slots cut into layers and the remaining barriers. The slots can be ~25 pm, 100 pm, 200 pm, 300 pm wide or as desired. The barriers can be of similar dimension range and do not have to match the width of the slots. In some cases it is preferable to make the slots larger than the smallest particle filtration system used in the liquid system so that the channels will not clog with dirt or particles. So if the filter is for 25 pm, the channels would be larger than 25 pm in size (e.g. height and width). In some embodiments, the channels are not square and may be rectangular or other shape.

[0090] Fig. 14 is a cross sectional view of a ceramic microchannel cooling plate in accordance with an embodiment of the invention. The ceramic microchannel cooling plate 1400 may include multiple channels interspersed amongst different electrical interconnects and optical interconnects. As illustrated, the ceramic microchannel colling plate 1400 includes a first microchannel 1402, a second microchannel 1406, and a third microchannel 1410. There are electrical interconnects 1404 or vias between the first microchannel 1402 and the second microchannel 1406. There are optical interconnects 1408 between the second microchannel 1406 and the third microchannel 1410. While only a few layers are illustrated, there may be more layers which may include more microchannels and / or layers of electrical interconnects or optical interconnects. Optical waveguides may be fabricated on any of the surfaces of the cooling plate as desired.

[0091] Fig. 15 is a cross-sectional view of an example liquid cooling system in accordance with an embodiment of the invention. The liquid cooling system includes a chip 1502 which is positioned on a first circuit board 1504. The first circuit board 1504 includes alternating layers of metal 1504a and insulator 1504b. The metal 1504a andinsulator 1504b may be patterned to make circuit traces for power and interconnecting. The metal 1504a and / or insulator 1504b may be thin film deposited or thick film deposited. The metal 1504a and / or insulator 1504b may be patterned. In some embodiments, the insulator 1504b may have a high thermal conductivity. In some embodiments, the insulator 1504b may be silicon nitride which includes good thermal conductivity (~20-30). The insulator 1504b may be alumina. For these very thin insulating layers which may be in the microns range or less thickness, a thermal conductivity may be 20-30. Thin film diamond may also be utilized as an insulator with excellent thermal conductivity.

[0092] The liquid cooling system includes a ceramic microchannel cooling plate 1506. The ceramic microchannel cooling plate 1506 is positioned between the first circuit board 1504 and a second circuit board 1508. Similar to the first circuit board 1504, the second circuit board 1508 includes alternating layers of metal 1508a and insulator 1508b. A through via 1510 may connect through the ceramic microchannel cooling plate 1506 and connect both the first circuit board 1504 and the second circuit board 1508.

[0093] Fig. 16A is a schematic of a cooling system 1600 in accordance with an embodiment of the invention. The cooling system 1600 includes a ceramic microchannel cooling plate 1604 supporting four chips 1602. In some embodiments, the ceramic microchannel cooling plate 1604 may support more or less than four chips 1602. The ceramic microchannel cooling plate 1604 may provide interconnects, power and cooling for the chips 1602.

[0094] Fig. 16B is a schematic of a stack of a large array of chips which are each supported by a ceramic microchannel cooling plate in accordance with an embodiment of the invention. The stack 1650 includes multiple cooling systems 1600a, 1600b, 1600c. Each of the cooling systems 1600a, 1600b, 1600c are the cooling system 1600 described in connection with Fig. 16A. The cooling systems 1600a, 1600b, 1600c are stacked on top of each other to form the stack 1650.

[0095] Fig. 16C is a schematic of an array of stacks in accordance with an embodiment of the invention. The array of stacks includes multiple stacks 1650a, 1650b. Each of the stacks 1650a, 1650b are the stack 1650 described in connection with Fig. 16B.

[0096] Fig. 17 is a schematic of a cooling system in accordance with an embodiment of the invention. The cooling system includes a ceramic microchannel cooling plate 1706which supports a chip 1708. The chip 1708 includes a hot spot area 1710 which is hotter than other spots of the chip 1708. The ceramic microchannel cooling plate 1706 includes microchannels 1704. Microchannels 1702 which overlap the hot spot area 1710 are denser (e.g. have smaller width) than other microchannels 1704 overlapping other areas of the chip 1708.

[0097] In some embodiments, the cooling system may include silicon with channels. Fig. 18 is a schematic of a cooling system in accordance with an embodiment of the invention. The cooling system includes a cooling plate 1802. The cooling plate 1802 supports a top chip 1808 and a bottom chip 1810 on opposite sides of the cooling plate 1802. The cooling plate 1802 includes a middle plate 1806. The middle plate 1806 may be ceramic or glass. The middle plate 1806 may be chosen to have certain thermal conductivity properties. For example, in some cases, the middle plate 1806 may be a thermal insulator to act as a thermal break between two sides of the cooling plate 1802. In some examples, the middle plate 1806 may be a thermal conductor to allow thermal conductivity between the top side of the cooling plate 1802 and the bottom side of the cooling plate 1802. The cooling plate 1802 includes a top microchannel cooling layer 1802 with microchannels 1802a and a bottom microchannel cooling layer 1812 with microchannels 1812a. The top microchannel cooling layer 1802 may be utilized to cool the top chip 1808 whereas the bottom microchannel cooling layer 1812 may be utilized to cool the bottom chip 1810. In some embodiments, the middle plate 1806 creates a thermal barrier between the bottom microchannel cooling layer 1812 and the top microchannel cooling layer 1802.

[0098] The top microchannel cooling layer 1802 and / or the bottom microchannel cooling layer 1812 may include silicon and / or ceramic. The top microchannel cooling layer 1802 and the bottom microchannel cooling layer 1812 may be a different ceramic material than the middle plate 1806. The top microchannel cooling layer 1802 and the bottom microchannel cooling layer 1812 may each be silicon. The top microchannel cooling layer 1802 and the bottom microchannel cooling layer 1812 may each be ceramic. One of the the top microchannel cooling layer 1802 or the bottom microchannel cooling layer 1812 may be ceramic and the other one of the top microchannel cooling layer 1802 or the bottom microchannel cooling layer may be silicon.

[0099] Fig. 19 is a schematic illustrating the positioning of chips on two sides of a microchannel cooling plate in accordance with an embodiment of the invention. The arrangement may be similar to the arrangement illustrated and described in Fig. 6 or Fig. 18. A first chip 1902 may be located on a first side of the microchannel cooling plate. A plurality of second chips 1904 may be located on a second side of the microchannel cooling plate. As illustrated, the location of the first chip 1902 may be offset from the location of the plurality of second chips 1904. For example, the location of the first chip 1902 may overlap two adjacent second chips 1904. This would allow for shorter interconnect lines between the first chip 1902 and the plurality of second chips 1904.

[0100] Fig. 20 is a schematic illustrating the positioning of chips on two sides of a microchannel cooling plate in accordance with an embodiment of the invention. This is similar to the schematic of Fig. 19, except the first chip 1902 may be offset from four adjacent second chips 1904. Thus, shorter interconnect lines would be placed between the first chip 1902 and the plurality of second chips 1904.

[0101] While only a single first chip has been illustrated, this is merely exemplary and it is understood that there may be an array of chips on the first side. Furthermore, while only a few second chips are illustrated, this is merely exemplary and it is understood that there may be an array of chips on the second side. Further, the first chips on the first side may all be offset from the second chips on the second side.

[0102] In some examples, the microchannel cooling plate may have nested microchannels. Fig. 21 is a schematic of an example microchannel cooling plate with nested microchannels. The cooling plate 2102 may include a surface 2102a to accommodate a heat source. The cooling plate 2102 includes a first microchannel 2104a, a second microchannel 2104b, and a third microchannel 2104c. The first microchannel 2104a, the second microchannel 2104b, and the third microchannel 2104c have independent paths. Each of the first microchannel 2104a, the second microchannel 2104b, and the third microchannel 2104c may have different channel sizes which may be optimized for flow, pressure drop, and / or thermal performance. The input, output, and / or path may be different based on different factors.

[0103] The microchannel cooling plate may have three-dimensional structures. Fig. 22 illustrates a schematic for a microchannel path. The microchannel path may have a three-dimensional structure. Some channels can be larger size to allow more flow and reduce pressure drop such as before branches on the input and after combinations on the output.

[0104] Fig. 23 is an example schematic of a hybrid microchannel cooling plate in accordance with an embodiment of the invention. As illustrated, the hybrid microchannel cooling plate includes a first layer 2302 and a second layer 2304. The first layer may include inlets 2308 and outlets 2306. The inlets 2308 intake cool liquid whereas the outlets 2306 output hot liquid. The second layer 2304 includes microchannels 2310 which extend from the inlets 2308 through to the outlets 2306. A surface 2312 of the second layer 2304 may be positioned in proximity to a heat source such as semiconductor chips to cool the heat source. The first layer 2302 may be a different material than the second layer 2304. For example, the second layer 2304 may be silicon and the first layer may be glass. Thus, the first layer 2302 may have low thermal conductivity while the second layer 2304 may have high thermal conductivity.

[0105] Fig. 24 is an example schematic hybrid microchannel cooling plate in accordance with an embodiment of the invention. The hybrid microchannel cooling plate includes a first side 2400a and a second side 2400b. The first side 2400a includes a first layer 2402 and a second layer 2404. The second side 2400b includes a third layer 2408 and a fourth layer 2406. The fourth layer 2406 is positioned directly opposite to the first layer 2402. The first side 2400a and the second side 2400b are each the hybrid microchannel cooling plate described in connection with Fig. 23. The first layer 2402 and the fourth layer 2406 are the first layer 2302 of the microchannel cooling plate described in connection with Fig. 23. The second layer 2404 and the third layer 2408 are the second layer 2304 of the microchannel cooling plate described in connection with Fig. 23. The first layer 2402 and the fourth layer 2406 may be glass whereas the second layer 2404 and the third layer 2408 may be silicon. An input 2410a and an output 2410b may be formed in the first layer 2402 and the fourth layer 2406. Channels 2412 may be formed in the second layer 2404 and the third layer 2408. The input 2410a and the output 2410b may be separated on each side of the first layer 2402 and the fourth layer 2406 such that they do not go through the entire thickness. However, there may be vias 2414 from each of the first layer 2402 and the fourth layer 2406 that penetrate through both of these layersto connect opposite sides of the layers. Chip heat sources are positioned on opposite sides of the second layer 2404 and the third layer 2408.

[0106] The first layer 2402, the second layer 2404, the third layer 2408, and the fourth layer 2406 are but are shown separately for clarity. When bonded together they form a double sided cooling plate. The silicon on both sides may have high thermal conductivity and the glass may provide a low thermal conductivity thermal break. The four layers are shown as same thickness but each layer may be of different thickness. Direct wafer bonding can be used to attach the layers together. Also semiconductor chips may be direct wafer bonded to the cooling plate. Direct wafer bonding is a packaging technique where two surfaces are brought in contact under special conditions and they bond without needing any adhesive in between.DOCTRINE OF EQUIVALENTS

[0107] While the above description contains many specific embodiments of the invention, these should not be construed as limitations on the scope of the invention, but rather as an example of one embodiment thereof. It is therefore to be understood that the present invention may be practiced in ways other than specifically described, without departing from the scope and spirit of the present invention. Thus, embodiments of the present invention should be considered in all respects as illustrative and not restrictive. Accordingly, the scope of the invention should be determined not by the embodiments illustrated, but by the appended claims and their equivalents.

Claims

WHAT IS CLAIMED IS:1 . A liquid-cooled computing system comprising: a first plurality of semiconductor chips supported by a first substrate formed of a material selected from the group consisting of silicon, ceramic or a combination thereof; wherein the first substrate comprises microchannels, each microchannel comprises an inlet, an outlet, and a path; and wherein each microchannel is configured to support the flow of liquid through the inlet, through the path, and then out the outlet such that heat is pulled from the plurality of semiconductor chips by the liquid.

2. The liquid-cooled computing system of claim 1 , where the microchannels are positioned directly below at least one of the plurality of chips.

3. The liquid-cooled computing system of claim 1 , wherein the path winds laterally in one direction and then the opposite direction while traveling vertically up the substrate.

4. The liquid-cooled computing system of claim 1 , wherein the substrate further comprises electrical interconnects, and wherein the electrical interconnects comprise an interconnect that go completely through the substrate from a surface supporting the substrate to an opposite surface.

5. The liquid-cooled computing system of claim 4, wherein the interconnect connects to one of the plurality of chips.

6. The liquid-cooled computing system of claim 4, wherein the interconnect connects to a power source on the opposite side of the substrate.

7. The liquid-cooled computing system of claim 4, wherein the interconnect connects to another chip or component configured to provide signals to or receive signals from at least one of the plurality of chips.

8. The liquid-cooled computing system of claim 4, wherein the electrical interconnects comprise an interconnect that travels within the substrate.

9. The liquid-cooled computing system of claim 8, wherein the interconnect connects a first chip to a second chip of the one or more chips.

10. The liquid-cooled computing system of claim 1 , wherein the substrate further comprises one or more thermal vias comprising high thermal conductivity material.

11. The liquid-cooled computing system of claim 10, wherein the high thermal conductivity material comprises metal.

12. The liquid-cooled computing system of claim 1 , wherein the substrate comprises silicon carbide (SiC), silicon nitride (S13N4), and / or aluminum oxide (AI2O3).

13. The liquid-cooled computing system of claim 12, wherein the one or more chips comprise silicon (Si).

14. The liquid-cooled computing system of claim 1 , wherein the substrate further supports a power converter, wherein the one or more silicon chips comprises a first chip connected to the power converter through an interconnect supported by the substrate such that the power converter powers the first chip.

15. The liquid-cooled computing system of claim 14, wherein the first chip is connected to an interposer or substrate.

16. The liquid-cooled computing system of claim 14, further comprising a second chip supported on an opposite surface of the substrate from the one or more chips.

17. The liquid-cooled computer system of claim 16, wherein the interconnect passes through the substrate and electrically connects to the other chip such that the power converter powers both the first chip and the second chip.

18. The liquid-cooled computer system of claim 1 , further comprising layers of interconnects which are layered between the substrate and the plurality of chips which allow the plurality of chips to communicate.

19. The liquid-cooled computer system of claim 18, further comprising: a second plurality of semiconductor chips supported by a second substrate, wherein the second substrate comprises microchannels, each microchannel comprises an inlet, an outlet, and a path, wherein each microchannel is configured to support the flow of liquid through the inlet, through the path, and then out the outlet such that heat is pulled from the second plurality of semiconductor chips by the liquid, wherein a backside of the second ceramic substrate faces a backside of the first substrate.

20. The liquid-cooled computer system of claim 19, wherein a low thermal conductivity layer is positioned between the first substrate and the second substrate.21 . The liquid-cooled computer system of claim 1 , further comprising: a second plurality of semiconductor chips supported on an opposite side of the first substrate than the first plurality of semiconductor chips.

22. The liquid-cooled computer system of claim 21 , wherein the first substrate comprises an interconnect which electrically connects a chip of the second plurality of semiconductor chips with a chip of the first plurality of semiconductor chips.

23. The liquid-cooled computer system of claim 1 , wherein the first plurality of semiconductor chips are positioned on a center part of the first substrate and the inletand outlet of the microchannels are located on the outside part of the first substrate.

24. A liquid-cooled thermophotovoltaic power generator comprising: a thermophotovoltaic power generator comprising an array of semiconductor chips supported by a substrate; and a heat source configured to emit energy towards the thermophotovoltaic power generator such that a fraction of the energy is converted to electricity and the rest remains as heat, wherein the substrate comprises microchannels, each microchannel comprises an inlet, an outlet, and a path, wherein each microchannel is configured to support the flow of liquid through the inlet, through the path, and then out the outlet such that heat is pulled from the array of semiconductor chips by the liquid.

25. A manufacturing method for a liquid-cooling device, the method comprising: providing a first ceramic layer; patterning the first ceramic layer to include an inlet and an outlet for microchannels; providing a second ceramic layer; patterning the second ceramic layer to include a channel for the microchannels; providing a third ceramic layer; stacking the second ceramic layer on the first ceramic layer such that the inlet and the outlet are at opposite ends of the channel; stacking the third ceramic layer on the second ceramic layer such that the third ceramic layer provides a top surface to the channel; and firing the stack of the first ceramic layer, the second ceramic layer, and the third ceramic layer which merges the first ceramic layer, the second ceramic layer, and the third ceramic layer into a single ceramic structure.

26. The method of claim 25, wherein patterning the first ceramic layer further includes patterning a first hole corresponding to the inlet and a second holecorresponding to the outlet.

27. The method of claim 25, wherein patterning the first ceramic layer comprises cutting the first green ceramic layer.

28. The method of claim 25, wherein patterning the second ceramic layer further includes patterning a slot corresponding to the channel.

29. The method of claim 25, further comprising patterning the third ceramic layer to include vias and / or interconnect channels.

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