Power factor correction circuit and control method therefor, and device and storage medium

Abstract

The present application relates to the technical field of electronics. Disclosed are a power factor correction circuit and a control method therefor, and a device and a storage medium. The circuit comprises: a three-phase input voltage sampling unit, which is connected to a three-phase power supply terminal, and is used for collecting a three-phase input voltage and outputting same; a three-phase full-bridge rectifier unit, which is connected to the three-phase power supply terminal, and is used for receiving a control signal and adjusting a current on the basis of the control signal; an energy storage unit, which is connected to the three-phase full-bridge rectifier unit; a current sampling unit, which is connected to the energy storage unit, and is used for collecting a real-time current and outputting same; a bus voltage sampling unit, which is connected to the energy storage unit, and is used for collecting a real-time bus voltage and outputting same; and a control unit, which is used for receiving the three-phase input voltage, the real-time current and the real-time bus voltage and sending the control signal to the three-phase full-bridge rectifier unit, so as to adjust a power factor by means of the energy storage unit. The problem in the prior art whereby buck-type PFC is unfavorable to cost reduction due to same involving numerous components and complex circuits is solved.

Description

Power factor correction circuit, control method, device and storage medium thereof TECHNICAL FIELD

[0001] The present application relates to the technical field of electronics, in particular to a power factor correction circuit, a control method, a device and a storage medium thereof. BACKGROUND

[0002] At present, the DC motor controller adopts a rectification-inversion topology scheme. The scheme first converts three-phase alternating current input from a power grid into direct current through a three-phase full-bridge rectification circuit composed of diodes, and then converts the direct current into three-phase alternating current with adjustable amplitude and frequency through an inversion part composed of fully controlled devices such as MOSFET or IGBT to drive the motor.

[0003] The existing three-phase input current is distorted, and the input power factor of the system is reduced, so it is necessary to correct the input power factor of the system. The commonly used power factor correction schemes at present are passive PFC (Power Factor Correction) and active PFC. The passive PFC scheme simply inserts a reactor in the input circuit to filter out high-frequency harmonics in the input current, which cannot fundamentally improve the input power factor of the system. The active PFC generally adopts a scheme based on a boost circuit, which cannot reduce the bus voltage. The buck PFC mainly has types based on Buck circuits, Vienna rectification circuits, etc. However, the above circuits involve many devices and complex circuits, which are not conducive to cost reduction and have complex control methods, and are not suitable for small and medium power DC motor control systems. SUMMARY

[0004] Therefore, the present application provides a power factor correction circuit, a control method, a device and a storage medium thereof to solve the problem of many devices and complex circuits involved in the buck PFC in the prior art.

[0005] In a first aspect, the present application provides a power factor correction circuit, which comprises:

[0006] a three-phase input voltage sampling unit, connected with a three-phase power supply end, for collecting three-phase input voltage and outputting;

[0007] a three-phase full-bridge rectification unit, connected with the three-phase power supply end, for receiving a control signal and adjusting current based on the control signal;

[0008] an energy storage unit, connected with the three-phase full-bridge rectification unit;

[0009] A current sampling unit connected with the energy storage unit, configured to collect real-time current and output;

[0010] A bus voltage sampling unit connected with the energy storage unit, configured to collect real-time bus voltage and output;

[0011] A control unit connected with the three-phase input voltage sampling unit, the three-phase full-bridge rectification unit, the current sampling unit and the bus voltage sampling unit, configured to receive three-phase input voltage, real-time current and real-time bus voltage, obtain input line voltage phase based on the three-phase input voltage, obtain preset current based on the input line voltage phase, the preset bus voltage and the real-time bus voltage, and send a control signal to the three-phase full-bridge rectification unit based on the hysteresis comparison result of the real-time current and the preset current, so as to adjust the power factor through the energy storage unit.

[0012] The control unit sends a control signal to the three-phase full-bridge rectification unit, and the three-phase full-bridge rectification unit acts based on the control signal to adjust the size of the bus voltage through charging and discharging of the energy storage unit. At the same time, a double closed-loop control method of voltage outer loop and current inner loop is adopted, the three-phase input voltage, real-time current and real-time bus voltage are collected, the real-time bus voltage is adjusted to the preset bus voltage, and the three-phase full-bridge rectification unit is controlled based on the line voltage phase of the three-phase input voltage and the adjusted voltage value of the bus voltage to adjust the current, so that the current is controlled to have the same phase as the input voltage, the input current of the power grid is indirectly in phase with the input voltage, the input power factor of the system will be close to the unit power factor, thereby achieving the purpose of controlling the bus voltage output and power factor correction. Compared with the existing buck PFC, the number of devices is greatly reduced, and the circuit structure is simplified.

[0013] In an alternative embodiment, the power supply end includes: an A-phase power supply end, a B-phase power supply end and a C-phase power supply end, and the three-phase input voltage sampling unit includes:

[0014] A first resistor, a first end of the first resistor being connected with the A-phase power supply end, and a second end of the first resistor being connected with the control unit;

[0015] A second resistor, a first end of the second resistor being connected with the B-phase power supply end, and a second end of the second resistor being connected with the control unit;

[0016] A third resistor, a first end of the third resistor being connected with the C-phase power supply end, and a second end of the third resistor being connected with the control unit;

[0017] A fourth resistor, a first end of the fourth resistor being connected with the second end of the first resistor, and a second end of the fourth resistor being grounded;

[0018] A fifth resistor, a first end of the fifth resistor being connected with the second end of the second resistor, and a second end of the fifth resistor being grounded;

[0019] a sixth resistor, a first end of the sixth resistor is connected with the second end of the third resistor, and a second end of the sixth resistor is grounded.

[0020] In an alternative embodiment, the current sampling unit comprises:

[0021] a seventh resistor, a first end of the seventh resistor is connected with the three-phase full-bridge rectifying unit, and a second end of the seventh resistor is connected with the current sampling unit;

[0022] an eighth resistor, a first end of the eighth resistor is connected with the first end of the seventh resistor;

[0023] a ninth resistor, a first end of the ninth resistor is connected with the second end of the seventh resistor;

[0024] a comparator, a first input end of the comparator is connected with the second end of the eighth resistor, and a second input end of the comparator is connected with the second end of the ninth resistor;

[0025] a tenth resistor, a first end of the tenth resistor is connected with the first input end of the comparator, and a second end of the tenth resistor is connected with an output end of the comparator;

[0026] an eleventh resistor, a first end of the eleventh resistor is connected with a preset reference voltage end, and a second end of the eleventh resistor is connected with the second input end of the comparator;

[0027] a twelfth resistor, a first end of the twelfth resistor is connected with the output end of the comparator, and a second end of the twelfth resistor is connected with the control unit.

[0028] In an alternative embodiment, the current sampling unit further comprises:

[0029] a first capacitor, a first end of the first capacitor is connected with the first end of the eleventh resistor, and a second end of the first capacitor is connected with the second end of the eleventh resistor;

[0030] a second capacitor, a first end of the second capacitor is connected with the first end of the tenth resistor, and a second end of the second capacitor is connected with the second end of the tenth resistor;

[0031] a third capacitor, a first end of the third capacitor is connected with the second end of the twelfth resistor, and a second end of the third capacitor is grounded.

[0032] In an alternative embodiment, the three-phase full-bridge rectifying unit comprises:

[0033] a first full-controlled device, a control end of the first full-controlled device is connected with the control unit, and a first end of the first full-controlled device is connected with an A-phase power supply end;

[0034] a second full-controlled device, a control end of the second full-controlled device being connected with the control unit, a first end of the second full-controlled device being connected with the B-phase power supply end;

[0035] a third full-controlled device, a control end of the third full-controlled device being connected with the control unit, a first end of the third full-controlled device being connected with the C-phase power supply end, a second end of the third full-controlled device being connected with the second end of the first full-controlled device and the second end of the second full-controlled device, and serving as an output positive pole of the three-phase full-bridge rectifying unit;

[0036] a first diode, a first end of the first diode being connected with the A-phase power supply end;

[0037] a second diode, a first end of the second diode being connected with the B-phase power supply end;

[0038] a third diode, a first end of the third diode being connected with the C-phase power supply end, a second end of the third diode being connected with the second end of the first diode and the second end of the second diode, and serving as an output negative pole of the three-phase full-bridge rectifying unit;

[0039] In an alternative embodiment, the energy storage unit comprises:

[0040] a freewheeling diode, a first end of the freewheeling diode being connected with the second end of the first full-controlled device, a second end of the freewheeling diode being connected with the second end of the first diode;

[0041] an inductor, a first end of the inductor being connected with the first end of the freewheeling diode, a second end of the inductor being connected with the bus voltage sampling unit;

[0042] an output capacitor, a first end of the output capacitor being connected with the second end of the inductor, a second end of the output capacitor being connected with the second end of the seventh resistor.

[0043] In an alternative embodiment, the bus voltage sampling unit comprises:

[0044] a thirteenth resistor, a first end of the thirteenth resistor being connected with the second end of the inductor, a second end of the thirteenth resistor being connected with the control unit;

[0045] a fourteenth resistor, a first end of the fourteenth resistor being connected with the second end of the thirteenth resistor, a second end of the fourteenth resistor being grounded.

[0046] In a second aspect, the application provides a control method of a power factor correction circuit, applied to a control unit in the power factor correction circuit as above, the method comprising:

[0047] obtaining a bus voltage, a three-phase input voltage and a real-time current, and obtaining an input line voltage based on the three-phase input voltage;

[0048] The difference between the bus voltage and the preset bus voltage is determined, and the difference is input to the voltage regulator to obtain the current amplitude;

[0049] The preset current is obtained based on the phase of the input line voltage and the current amplitude;

[0050] Based on the hysteresis comparison result of the real-time current and the preset current, a control signal is sent to the three-phase full-bridge rectifier unit to adjust the power factor.

[0051] In a third aspect, the present application provides a computer device, comprising a memory and a processor, the memory and the processor are communicatively connected, the memory stores computer instructions, and the processor executes the computer instructions to perform the control method of the power factor correction circuit according to the first aspect or any one of the corresponding embodiments.

[0052] In a fourth aspect, the present application provides a computer readable storage medium, which stores computer instructions for making a computer execute the control method of the power factor correction circuit according to the first aspect or any one of the corresponding embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0053] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the drawings needed in the description of the specific embodiments or the prior art will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can obtain other drawings without creative labor on the basis of these drawings.

[0054] FIG. 1 is a conventional power factor correction circuit;

[0055] FIG. 2 is a power factor correction circuit structure diagram according to an embodiment of the present application;

[0056] FIG. 3 is a flowchart of a control method of a power factor correction circuit according to an embodiment of the present application;

[0057] FIG. 4 is a hardware structure schematic diagram of a computer device according to an embodiment of the present application. DETAILED DESCRIPTION

[0058] The technical solutions of the present application will be described in detail below with reference to the drawings. Obviously, the described embodiments are some embodiments of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0059] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third" are only for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0060] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the internal communication of two elements; it can be wireless connection, or it can be wired connection. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0061] In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as there is no conflict.

[0062] At present, the DC motor controller generally adopts the rectification-inversion topology scheme shown in Figure 1. The scheme first adopts a three-phase full-bridge rectification circuit composed of diodes to convert the three-phase alternating current input from the power grid into direct current, and then converts the direct current into three-phase alternating current with adjustable amplitude and frequency through an inversion part composed of full-controlled devices (MOSFET / IGBT) for driving the motor.

[0063] The front end of the existing related scheme adopts an uncontrollable rectification circuit, so the output voltage is not adjustable, and the rectification output direct current is completely determined by the input three-phase grid voltage. For export models, when the grid voltage is 460V / 570V or higher, the bus voltage will reach 650V or higher. On the one hand, the electrical stress borne by the power devices of the rear-end inversion circuit increases, and higher-voltage power devices and matching drive circuits need to be selected, increasing the system cost. On the other hand, due to the excessively high bus voltage, a larger electrical clearance and creepage distance are required, which puts higher requirements on the system insulation.

[0064] In addition, due to the uncontrollable rectifier scheme adopted by the front end, the three-phase input current is distorted, and the input power factor of the system is reduced, so it is necessary to correct the input power factor of the system. The commonly used power factor correction schemes at present are passive PFC and active PFC. The passive PFC scheme simply inserts a reactor in the input circuit to filter out high-frequency harmonics in the input current, but it cannot fundamentally improve the input power factor of the system. The active PFC generally uses a boost circuit-based scheme, which cannot reduce the bus voltage. The currently disclosed step-down PFC patents mainly include Buck (step-down conversion) circuit, Vienna rectifier circuit (pulse width modulation rectifier) and the like. However, the above circuits involve many devices, the circuit is complex, which is not conducive to cost reduction, and the control method is complex, which is not suitable for small and medium power DC motor control systems.

[0065] To this end, the embodiment provides a power factor correction circuit, as shown in FIG. 2, the circuit comprises:

[0066] A three-phase input voltage sampling unit 100 is connected with a three-phase power supply end, used for collecting three-phase input voltage and outputting;

[0067] A three-phase full-bridge rectifier unit 200 is connected with an input voltage end, used for receiving a control signal and adjusting current based on the control signal;

[0068] An energy storage unit 300 is connected with the three-phase full-bridge rectifier unit;

[0069] A current sampling unit 400 is connected with the energy storage unit, used for collecting real-time current and outputting;

[0070] A bus voltage sampling unit 500 is connected with the energy storage unit, used for collecting bus voltage and outputting;

[0071] A control unit 600 is connected with the three-phase input voltage sampling unit 100, the three-phase full-bridge rectifier unit 200, and the current sampling unit 400, respectively, used for receiving three-phase input voltage, real-time current and bus voltage, obtaining input line voltage phase based on the three-phase input voltage, obtaining preset current based on the input line voltage phase, preset bus voltage and real-time bus voltage, and sending a control signal to the three-phase full-bridge rectifier unit based on the hysteresis comparison result of the real-time current and the preset current, so as to adjust the power factor.

[0072] The control unit 600 sends a control signal to the three-phase full-bridge rectifier unit 200, and the three-phase full-bridge rectifier unit 200 acts based on the control signal, so that the line voltage of the three-phase power supply charges the energy storage unit 300 and supplies power to the load at the same time, thereby raising the bus voltage, and the energy storage unit 300 can also supply power to the load, thereby lowering the bus voltage. Further, by controlling the three-phase full-bridge rectifier unit 200 through the control unit 600, the magnitude of the bus voltage can be adjusted.

[0073] At the same time, if the current is controlled to have the same phase as the input voltage, the grid input current is indirectly made to have the same phase as the input voltage, and the input power factor of the system will be close to the unit power factor, thereby achieving the purpose of controlling the bus voltage output and power factor correction.

[0074] In the embodiment, a double-loop control method of voltage outer loop and current inner loop can be used, wherein the voltage outer loop control includes controlling the DC bus voltage Udc to be a preset bus voltage Udc*, and the current inner loop control includes controlling the real-time current IL to be the inductance current command IL* based on the phase of the input line voltage and the current inductance current command IL* obtained based on the voltage value to be adjusted by the outer loop.

[0075] Specifically, if the set DC bus reference voltage (i.e. the preset bus voltage) is Udc*, the control unit 600 obtains the real-time DC bus voltage Udc based on the bus voltage acquisition unit 50, and obtains the three-phase input voltage as the first input voltage Ua, the second input voltage Ub and the third input voltage Uc based on the three-phase input voltage sampling unit 100, and obtains the real-time current IL based on the current sampling unit. Then, the DC bus voltage Udc is compared with the preset bus voltage Udc*, and the difference between the DC bus voltage Udc and the preset bus voltage Udc* is input to the voltage regulator, which can be a PID (a basic regulation method of a control system in classical control theory) regulator, to obtain the inductance current amplitude command |IL*|, and the maximum and minimum values of the first input voltage Ua, the second input voltage Ub and the third input voltage Uc are determined, and the input line voltage corresponding to the maximum and minimum values is determined as the current input line voltage, and then the phase is extracted by dividing the input line voltage by the voltage amplitude k, wherein the voltage amplitude k is obtained according to formula (1).

[0076] The phase of the input line voltage is multiplied by the inductance current amplitude command |IL*| to obtain the inductance current command IL*. The current control is realized by hysteresis comparison, that is, when the inductance current command IL* is greater than the real-time current IL, a control signal is sent to the three-phase full-bridge rectification unit 200, so that the grid input voltage charges the energy storage unit 300, and the inductance current rises; when the inductance current command IL* is less than the real-time current IL, another control signal is sent to the three-phase full-bridge rectification unit 200, so that the grid input voltage stops charging the energy storage unit 300, and the inductance current decreases, finally making the bus voltage Udc the same as the preset bus voltage Udc*, and the real-time current IL makes its phase the same as the input voltage, indirectly making the grid input current in phase with the input voltage, and the input power factor of the system will be close to the unit power factor, thereby achieving the purpose of controlling the bus voltage output and power factor correction.

[0077] In some optional embodiments, as shown in FIG. 3, which is another power factor correction circuit structure diagram according to the embodiments of the present application, the power supply end includes: an A-phase power supply end, a B-phase power supply end and a C-phase power supply end, and the input voltage sampling unit 100 includes:

[0078] a first resistor R1, a first end of the first resistor R1 being connected with the A-phase power supply end UA, and a second end of the first resistor being connected with the control unit 600;

[0079] a second resistor R2, a first end of the second resistor R2 being connected with the B-phase power supply end UB, and a second end of the second resistor R2 being connected with the control unit 600;

[0080] a third resistor R3, a first end of the third resistor R3 being connected with the C-phase power supply end UC, and a second end of the third resistor R3 being connected with the control unit 600;

[0081] a fourth resistor R4, a first end of the fourth resistor R4 being connected with the second end of the first resistor R1, and a second end of the fourth resistor R4 being grounded;

[0082] a fifth resistor R5, a first end of the fifth resistor R5 being connected with the second end of the second resistor R2, and a second end of the fifth resistor R5 being grounded;

[0083] a sixth resistor R6, a first end of the sixth resistor R6 being connected with the second end of the third resistor R3, and a second end of the sixth resistor R6 being grounded.

[0084] The input voltage sampling unit 100 can specifically include a first voltage dividing circuit, a second voltage dividing circuit and a third voltage dividing circuit. The first voltage dividing circuit is connected with the A-phase power terminal UA and the control unit 600 respectively, and is used to collect the first input voltage Ua of the A-phase power terminal UA and then send it to the control unit 600. The second voltage dividing circuit is connected with the B-phase power terminal UB and the control unit 600, and is used to collect the second input voltage Ub of the B-phase power terminal UB and then send it to the control unit 600. The third voltage dividing circuit is connected with the C-phase power terminal UC and the control unit 600, and is used to collect the third input voltage Uc of the C-phase power terminal UC and then send it to the control unit 600.

[0085] Specifically, the control unit 600 measures the first input voltage Ua of the A-phase power terminal UA through voltage division of the first resistor R1 and the fourth resistor R4. The control unit 600 measures the second input voltage Ub of the B-phase power terminal UB through voltage division of the second resistor R2 and the fifth resistor R5. The control unit 600 measures the third input voltage Uc of the C-phase power terminal UC through voltage division of the third resistor R3 and the sixth resistor R6.

[0086] In some optional embodiments, as shown in FIG. 2, the inductance current sampling unit 400 includes:

[0087] A seventh resistor R7, a first end of the seventh resistor R7 is connected with the three-phase full-bridge rectifier unit 200, and a second end of the seventh resistor R7 is connected with the current sampling unit 50;

[0088] An eighth resistor R8, a first end of the eighth resistor R8 is connected with the first end of the seventh resistor R7;

[0089] A ninth resistor R9, a first end of the ninth resistor R9 is connected with the second end of the seventh resistor R7;

[0090] An operational amplifier A1, a first input end of the operational amplifier A1 is connected with a second end of the eighth resistor R8, and a second input end of the operational amplifier A1 is connected with a second end of the ninth resistor R9;

[0091] A tenth resistor R10, a first end of the tenth resistor R10 is connected with the first input end of the operational amplifier A1, and a second end of the tenth resistor R10 is connected with an output end of the operational amplifier A1;

[0092] An eleventh resistor R11, a first end of the eleventh resistor R11 is connected with a preset reference voltage terminal Vref, and a second end of the eleventh resistor R11 is connected with the second input end of the operational amplifier A1;

[0093] A twelfth resistor R12, a first end of the twelfth resistor R12 is connected with the output end of the operational amplifier A1, and a second end of the twelfth resistor R12 is connected with the control unit 600.

[0094] In the embodiment, the seventh resistor R7 is a sampling resistor, the voltage based on the sampling resistor is used for biasing and controlling the control unit 600 after being amplified by the operational amplifier A1, and the control unit 600 performs operation on the amplified voltage and the sampling resistor to obtain the real-time current IL.

[0095] In some optional embodiments, as shown in FIG. 2, the inductive current sampling unit further comprises:

[0096] a first capacitor C1, a first end of the first capacitor C1 is connected with a first end of the eleventh resistor R11, and a second end of the first capacitor C1 is connected with a second end of the eleventh resistor R11;

[0097] a second capacitor C2, a first end of the second capacitor C2 is connected with a first end of the tenth resistor R10, and a second end of the second capacitor C2 is connected with a second end of the tenth resistor R10;

[0098] a third capacitor C3, a first end of the third capacitor C3 is connected with a second end of the twelfth resistor R12, and a second end of the third capacitor C3 is grounded.

[0099] In the embodiment, the first capacitor functions to filter the preset reference voltage end Vref, the second capacitor C2 functions to filter the voltage transmitted by the operational amplifier A1, and the third capacitor C3 transmits the voltage amplified by the operational amplifier A1 after being filtered.

[0100] In some optional embodiments, as shown in FIG. 2, the three-phase full-bridge rectifying unit 200 comprises:

[0101] a first full-controlled device Q1, a control end of the first full-controlled device Q1 is connected with the control unit 600, and a first end of the first full-controlled device Q1 is connected with the A-phase power supply end UA;

[0102] a second full-controlled device Q2, a control end of the second full-controlled device Q2 is connected with the control unit 600, and a first end of the second full-controlled device Q2 is connected with the B-phase power supply end UB;

[0103] a third full-controlled device Q3, a control end of the third full-controlled device Q3 is connected with the control unit 600, a first end of the third full-controlled device Q3 is connected with the C-phase power supply end UC, and a second end of the third full-controlled device Q3 is connected with a second end of the first full-controlled device Q1 and a second end of the second full-controlled device Q2, and functions as an output positive electrode of the three-phase full-bridge rectifying unit 200;

[0104] a first diode D1, a first end of the first diode D1 is connected with the A-phase power supply end UA;

[0105] a second diode D2, a first end of the second diode D2 is connected with the B-phase power supply end UB;

[0106] The third diode D3 has a first end connected to the C-phase power terminal UC and a second end connected to the second end of the first diode D1 and the second end of the second diode D2, and serves as an output negative terminal of the three-phase full-bridge rectifier unit 200.

[0107] In the embodiment, the three-phase full-bridge rectifier unit 200 is composed of full-controlled devices and diodes, and can have other full-bridge rectifier connection modes in addition to the connection mode shown in FIG. 2.

[0108] Specifically, the first full-controlled device Q1, the second full-controlled device Q2, and the third full-controlled device Q3 form an upper bridge arm, the first diode D1, the second diode D2, and the third diode D3 form a lower bridge arm, and the first full-controlled device Q1, the second full-controlled device Q2, and the third full-controlled device Q3 at the front end are controlled by the control unit 600 to realize the increase and decrease of the bus voltage through the energy storage unit, and the phase of the real-time current IL is the same as the phase of the input power terminal, which indirectly makes the grid input current in phase with the input voltage, and the input power factor of the system will be close to the unit power factor, thereby achieving the purpose of controlling the bus voltage output while performing power factor correction. Compared with the traditional Buck circuit, Vienna rectifier circuit, and other types of bus current reduction methods, the number of devices is reduced, the circuit complexity is reduced, and the method is suitable for small and medium power DC motor control systems.

[0109] It should be noted that the first full-controlled device Q1, the second full-controlled device Q2, and the third full-controlled device Q3 can be IGBT (Insulate-Gate Bipolar Transistor) or MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), and specifically can be NMOS (N-Metal-Oxide-Semiconductor). The bridge arm corresponding to the A-phase voltage terminal is the first full-controlled device Q1 and the first diode D1, the bridge arm corresponding to the B-phase voltage terminal is the second full-controlled device Q2 and the second diode D2, and the bridge arm corresponding to the C-phase voltage terminal is the third full-controlled device Q3 and the third diode D3.

[0110] Specifically, if the A-phase input voltage is the highest and the B-phase input voltage is the lowest in the three-phase voltage, at this time, the first controllable device Q1 of the A-phase bridge arm is turned on, the line voltage UAB is applied to the loop of the energy storage unit 300, at this time, the line voltage UAB charges the energy storage unit 300 while supplying power to the load, and the bus voltage rises; after the first controllable device Q1 of the A-phase bridge arm is turned off, the load is supplied with power through the energy storage unit 300, and the bus voltage decreases, so by controlling the turn-on duty cycle of the controllable device, the size of the bus voltage can be adjusted, and at the same time, if the real-time current IL is controlled to have the same phase as the input line voltage UAB, the input current of the power grid is indirectly made to be in phase with the input voltage, so as to achieve the purpose of controlling the bus voltage output while correcting the power factor. The operation principles of the other two-phase input voltages are the same as the above principle, which will not be described one by one here.

[0111] In some optional embodiments, as shown in FIG. 2, the energy storage unit 300 includes:

[0112] a freewheeling diode D0, a first end of the freewheeling diode D0 is connected with a second end of the first controllable device Q1, and a second end of the freewheeling diode D0 is connected with a second end of the first diode D1;

[0113] an inductor L1, a first end of the inductor L1 is connected with the first end of the freewheeling diode D0, and a second end of the inductor L1 is connected with the bus voltage sampling unit 50;

[0114] an output capacitor C0, a first end of the output capacitor C0 is connected with the second end of the inductor L1, and a second end of the output capacitor C0 is connected with a second end of the seventh resistor R7.

[0115] In this embodiment, it is assumed that the A-phase input voltage is the highest and the B-phase input voltage is the lowest in the three-phase voltage, at this time, the first controllable device Q1 of the A-phase bridge arm is turned on, the line voltage UAB is applied to the loop composed of the inductor L1, the output capacitor C0 and the load, at this time, the line voltage UAB charges the inductor L1 while supplying power to the load, and the bus voltage rises; after the first controllable device Q1 of the A-phase bridge arm is turned off, the inductor supplies power to the load through the freewheeling diode D0, and the bus voltage decreases. Thus, the function of adjusting the bus voltage is achieved.

[0116] In some optional embodiments, as shown in FIG. 2, the bus voltage sampling unit 500 includes:

[0117] a thirteenth resistor R13, a first end of the thirteenth resistor R13 is connected with the second end of the inductor L1, and a second end of the thirteenth resistor R13 is connected with the control unit 600;

[0118] a fourteenth resistor R14, a first end of the fourteenth resistor R14 is connected with the second end of the thirteenth resistor R13, and a second end of the fourteenth resistor R14 is grounded.

[0119] In the embodiment, the thirteenth resistor R13 and the fourteenth resistor R14 constitute a voltage dividing resistor, and the control unit 600 collects the bus voltage based on the thirteenth resistor R13 and the fourteenth resistor R14.

[0120] The embodiment provides a control method of a power factor correction circuit, which is applied to a control unit in the power factor correction circuit as above. As shown in FIG. 3, the method comprises the following steps.

[0121] (1) acquiring a bus voltage, a three-phase input voltage and a real-time current, and obtaining an input line voltage based on the three-phase input voltage;

[0122] (2) determining a difference value of the bus voltage and a preset bus voltage, inputting the difference value to a voltage regulator to obtain a current amplitude;

[0123] (3) obtaining a preset current based on a phase of the input line voltage and the current amplitude;

[0124] (4) based on a hysteresis comparison result of the real-time current and the preset current, sending a control signal to a three-phase full-bridge rectifier unit to adjust the power factor.

[0125] In the embodiment, if the set direct current bus reference voltage (i.e. the preset bus voltage) is Udc*, the control unit 600 collects the real-time direct current bus voltage Udc based on the bus voltage collecting unit 50, and collects the three-phase input voltage based on the three-phase input voltage sampling unit 100, and the three-phase input voltage is the first input voltage Ua, the second input voltage Ub and the third input voltage Uc respectively, and the real-time current IL is collected based on the current sampling unit. Then, the direct current bus voltage Udc is compared with the preset bus voltage Udc*, and the difference value between the direct current bus voltage Udc and the preset bus voltage Udc* is input to the voltage regulator (PID) to obtain the inductance current amplitude instruction |IL*|, and the maximum value and the minimum value in the first input voltage Ua, the second input voltage Ub and the third input voltage Uc are determined, and the input line voltage corresponding to the maximum value and the minimum value is determined as the current input line voltage, and then the phase is extracted by dividing the input line voltage by the voltage amplitude, wherein the voltage amplitude reference formula (2) is obtained.

[0126] The phase of the input line voltage is multiplied by the inductance current amplitude command IL* to obtain an inductance current command IL*, and the inductance current control is realized by using a hysteresis comparison method, that is, when the inductance current command IL* is greater than the real-time current IL (that is, the actual inductance current), the full-controlled device of the bridge arm where the maximum phase voltage is located is turned on, the input voltage of the power grid charges the inductor, and the inductance current rises; when the inductance current command IL* is less than the real-time current IL, the full-controlled device of the bridge arm where the maximum phase voltage is located is turned off, and the inductance current decreases, so that the bus voltage Udc is the same as the preset bus voltage Udc*, and the real-time current IL makes its phase the same as the input voltage, indirectly making the input current of the power grid in phase with the input voltage, and the input power factor of the system will be close to the unit power factor, so as to achieve the purpose of controlling the bus voltage output and power factor correction.

[0127] The embodiment also provides a computer device. Please refer to FIG. 4, which is a schematic diagram of the hardware structure of the computer device according to the embodiment of the present application. As shown in FIG. 4, the computer device comprises one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. The various components are communicatively connected with each other by different buses, and can be installed on a common mainboard or in other manners as needed. The processor can process instructions executed in the computer device, including instructions stored in the memory or the memory to display graphical information of a GUI on an external input / output device (such as a display device coupled to the interface). In some optional embodiments, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories, if necessary. Also, multiple computer devices can be connected, and each device provides part of the necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). One processor 10 is taken as an example in FIG. 4.

[0128] The processor 10 can be a central processor, a network processor, or a combination thereof. The processor 10 can further include a hardware chip. The hardware chip can be an application specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device can be a complex programmable logic device, a field programmable logic gate array, a generic array logic, or any combination thereof.

[0129] The memory 20 stores instructions executable by the at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0130] The memory 20 can include a program storage area and a data storage area. The program storage area can store an operating system, application programs required for at least one function, and the like. The data storage area can store data created according to usage of the computer device, and the like. In addition, the memory 20 can include a volatile memory such as a random access memory, and can further include a non-volatile memory such as at least one of a magnetic disk storage device, a flash memory device, or other non-volatile solid state memory device. In some alternative embodiments, the memory 20 can optionally include memory that is remotely located with respect to the processor 10, which can be connected to the computer device through a network. Examples of the network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0131] The memory 20 can include a volatile memory such as a random access memory, and can further include a non-volatile memory such as at least one of a magnetic disk storage device, a flash memory device, or other non-volatile solid state memory device. In some alternative embodiments, the memory 20 can optionally include memory that is remotely located with respect to the processor 10, which can be connected to the computer device through a network. Examples of the network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0132] [Corrected according to Rule 91 on 18.06.2025] The computer device further includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30, and the output device 40 can be connected through a bus or other means, and are connected through a bus in FIG. 4 as an example.

[0133] The input device 30 can receive input digital or character information, and generate key signal input related to user settings and function controls of the computer device, such as a touch screen, a keypad, a mouse, a trackpad, a touchpad, a pointing stick, one or more mouse buttons, a trackball, a joystick, and the like. The output device 40 can include a display device, an auxiliary lighting device (e.g., an LED), a haptic feedback device (e.g., a vibration motor), and the like. The display device includes, but is not limited to, a liquid crystal display, a light emitting diode, a display, and a plasma display. In some alternative embodiments, the display device can be a touch screen.

[0134] The embodiment also provides a computer readable storage medium, and the method according to the embodiment described above can be implemented in hardware, firmware, or recorded in a storage medium, or implemented through computer code originally stored in a remote storage medium or non-transitory machine readable storage medium downloaded through a network and stored in a local storage medium, so that the method described herein can be processed by such software on a storage medium using a general purpose computer, a special purpose processor, or programmable or special hardware. Wherein, the storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk or a solid state disk, etc. Further, the storage medium can also include a combination of the above-mentioned types of memories. It can be understood that the computer, processor, microprocessor controller or programmable hardware includes a storage component that can store or receive software or computer code, when the software or computer code is accessed and executed by the computer, processor or hardware, the method shown in the above embodiment is implemented.

[0135] Although the embodiments of the present application are described in conjunction with the accompanying drawings, various modifications and changes can be made by those skilled in the art without departing from the spirit and scope of the present application, and such modifications and changes fall within the scope defined by the appended claims.

Claims

1. A power factor correction circuit, characterized by, The circuit comprises: a three-phase input voltage sampling unit connected with a three-phase power supply end, for collecting three-phase input voltage and outputting; a three-phase full-bridge rectification unit connected with the three-phase power supply end, for receiving a control signal and adjusting current based on the control signal; an energy storage unit connected with the three-phase full-bridge rectification unit; a current sampling unit connected with the energy storage unit, for collecting real-time current and outputting; a bus voltage sampling unit connected with the energy storage unit, for collecting real-time bus voltage and outputting; a control unit connected with the three-phase input voltage sampling unit, the three-phase full-bridge rectification unit, the current sampling unit and the bus voltage sampling unit respectively, for receiving the three-phase input voltage, the real-time current and the real-time bus voltage, obtaining input line voltage phase based on the three-phase input voltage, obtaining preset current based on the input line voltage phase, preset bus voltage and real-time bus voltage, and sending the control signal to the three-phase full-bridge rectification unit based on the hysteresis comparison result of the real-time current and the preset current, so as to adjust power factor through the energy storage unit.

2. The circuit of claim 1, wherein, The power supply end comprises: an A-phase power supply end, a B-phase power supply end and a C-phase power supply end, and the three-phase input voltage sampling unit comprises: a first resistor, a first end of the first resistor being connected with the A-phase power supply end, and a second end of the first resistor being connected with the control unit; a second resistor, a first end of the second resistor being connected with the B-phase power supply end, and a second end of the second resistor being connected with the control unit; a third resistor, a first end of the third resistor being connected with the C-phase power supply end, and a second end of the third resistor being connected with the control unit; a fourth resistor, a first end of the fourth resistor being connected with the second end of the first resistor, and a second end of the fourth resistor being grounded; a fifth resistor, a first end of the fifth resistor being connected with the second end of the second resistor, and a second end of the fifth resistor being grounded; a sixth resistor, a first end of the sixth resistor being connected with the second end of the third resistor, and a second end of the sixth resistor being grounded.

3. The circuit of claim 2, wherein, The current sampling unit comprises: a seventh resistor, a first end of the seventh resistor being connected with the three-phase full-bridge rectification unit, and a second end of the seventh resistor being connected with the current sampling unit; an eighth resistor, a first end of the eighth resistor being connected with the first end of the seventh resistor; a ninth resistor, a first end of the ninth resistor being connected with the second end of the seventh resistor; a comparator, a first input end of the comparator being connected with the second end of the eighth resistor, and a second input end of the comparator being connected with the second end of the ninth resistor; a tenth resistor, a first end of the tenth resistor being connected with the first input end of the comparator, and a second end of the tenth resistor being connected with an output end of the comparator; an eleventh resistor, a first end of the eleventh resistor being connected with a preset reference voltage end, and a second end of the eleventh resistor being connected with the second input end of the comparator; A twelfth resistor, a first end of the twelfth resistor being connected with an output end of the comparator, and a second end of the twelfth resistor being connected with the control unit.

4. The circuit of claim 3, wherein, The current sampling unit further comprises: A first capacitor, a first end of the first capacitor being connected with a first end of the eleventh resistor, and a second end of the first capacitor being connected with a second end of the eleventh resistor; A second capacitor, a first end of the second capacitor being connected with a first end of the tenth resistor, and a second end of the second capacitor being connected with a second end of the tenth resistor; A third capacitor, a first end of the third capacitor being connected with a second end of the twelfth resistor, and a second end of the third capacitor being grounded.

5. The circuit of claim 4, wherein, The three-phase full-bridge rectifying unit comprises: A first full-controlled device, a control end of the first full-controlled device being connected with the control unit, and a first end of the first full-controlled device being connected with the A-phase power supply end; A second full-controlled device, a control end of the second full-controlled device being connected with the control unit, and a first end of the second full-controlled device being connected with the B-phase power supply end; A third full-controlled device, a control end of the third full-controlled device being connected with the control unit, a first end of the third full-controlled device being connected with the C-phase power supply end, a second end of the third full-controlled device being connected with a second end of the first full-controlled device and a second end of the second full-controlled device, and the second end of the third full-controlled device serving as an output positive pole of the three-phase full-bridge rectifying unit; A first diode, a first end of the first diode being connected with the A-phase power supply end; A second diode, a first end of the second diode being connected with the B-phase power supply end; A third diode, a first end of the third diode being connected with the C-phase power supply end, a second end of the third diode being connected with a second end of the first diode and a second end of the second diode, and the second end of the third diode serving as an output negative pole of the three-phase full-bridge rectifying unit.

6. The circuit of claim 5, wherein, The energy storage unit comprises: A freewheeling diode, a first end of the freewheeling diode being connected with a second end of the first full-controlled device, and a second end of the freewheeling diode being connected with a second end of the first diode; An inductor, a first end of the inductor being connected with a first end of the freewheeling diode, and a second end of the inductor being connected with the bus voltage sampling unit; An output capacitor, a first end of the output capacitor being connected with a second end of the inductor, and a second end of the output capacitor being connected with a second end of the seventh resistor.

7. The circuit of claim 6, wherein, The bus voltage sampling unit comprises: A thirteenth resistor, a first end of the thirteenth resistor being connected with a second end of the inductor, and a second end of the thirteenth resistor being connected with the control unit; A fourteenth resistor, a first end of the fourteenth resistor being connected with a second end of the thirteenth resistor, and a second end of the fourteenth resistor being grounded.

8. A control method of a power factor correction circuit, characterized by, The method is applied to the control unit in the power factor correction circuit as described in any one of the above 1 to 7, and the method comprises: Obtaining a bus voltage, a three-phase input voltage and a real-time current, and obtaining an input line voltage based on the three-phase input voltage; Determining a difference value of the bus voltage and a preset bus voltage, inputting the difference value to a voltage regulator to obtain a current amplitude; obtaining a preset current based on the phase of the input line voltage and the current amplitude; sending a control signal to a three-phase full-bridge rectification unit based on a hysteresis comparison result of the real-time current and the preset current to adjust the power factor.

9. A computer device, comprising: comprise: a memory and a processor, which are in communication connection with each other, and the memory stores computer instructions, and the processor executes the computer instructions to perform the control method of the power factor correction circuit according to claim 8.

10. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer instructions for making a computer execute the control method of the power factor correction circuit according to claim 8.

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