Chip packaging structure, integrated circuit, transceiving system, and electronic device

Abstract

The present application provides a chip packaging structure, an integrated circuit, a transceiving system, and an electronic device. The chip packaging structure comprises a packaging substrate, a package body, a chip, at least one waveguide structural member, and a dielectric layer. The package body and the packaging substrate are stacked in a first direction. The chip is packaged in the package body and electrically connected to the packaging substrate. Each waveguide structural member is coupled and connected to the chip. The dielectric layer is filled between the package body and the packaging substrate. A first cavity is provided at a position of the dielectric layer corresponding to each waveguide structural member, and the first cavity passes through the dielectric layer in the first direction. In the chip packaging structure provided in the embodiments of the present application, a cavity structure can be used in a specific region, and the remaining regions are filled with a medium, so that a waveguide cavity and a chip can be packaged while the reliability is ensured, thereby reducing the transmission loss of high-frequency signals and improving the signal transmission quality.

Description

Chip packaging structure, integrated circuit, transceiver system and electronic device

[0001] The present application claims priority from the Chinese patent application No. 202411301757.4 filed on September 14, 2024, and entitled "Chip packaging structure, integrated circuit, transceiver system and electronic device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of chip packaging, in particular to a chip packaging structure, an integrated circuit, a transceiver system and an electronic device. BACKGROUND

[0003] Traditional base station products mostly use microstrip lines for signal transmission. The microstrip line has small loss to low-frequency signals and has little impact on the transmission quality of low-frequency products. However, future wireless communication 5.5G, 6G will promote to higher frequency bands such as 8G, 13G, and microwave devices will evolve to D band (frequency range 130GHz-174.8GHz) and other frequency bands. Higher frequency bands have super large bandwidth, can provide wider spectrum channels, support higher transmission capacity, and can greatly improve user experience. However, the dielectric constant of the transmission medium in the microstrip line is high, which causes large loss to high-frequency signals, seriously affecting the characteristics of the product. The waveguide transmission solution has become an evolution trend for low-loss high-frequency signal transmission, which can greatly improve the competitiveness of the product.

[0004] In the TRX (Transceiver) link of a wireless radio frequency system, to solve the problem of large loss of high-frequency signal transmission, different devices can transmit signals through a waveguide cavity. The waveguide cavity is a cavity structure surrounded by a metal wall, and the internal transmission medium is air. The dielectric constant of air is low, which can greatly reduce the transmission loss of signals. Through contrast experiments and simulation measurement, it is found that under the same scenario, the microstrip line transmission has a signal insertion loss of 1.9dB / 10mm for D band, while the waveguide cavity has a signal insertion loss of only 0.25dB / 10mm for D band. It can be seen that waveguide transmission has obvious advantages.

[0005] The communication product generally packages the chip, and if a waveguide transmission scheme is used, a cavity structure needs to be designed in the chip packaging structure to encapsulate the waveguide cavity and the chip together. Currently, the cavity structure type devices mainly include microwave radio frequency devices and Saw (Surface Acoustic Wave) filters. The microwave radio frequency device mainly adopts a WB (Wire bonding, wire bonding, the chip is electrically connected to the external pin or substrate through a metal wire) type packaging structure, and the device is a full cavity structure. The Saw filter mainly adopts an FC (Flip Chip, flip chip, the active surface of the chip faces down, and is directly connected to the substrate or packaging carrier through the bumps on the chip) type packaging structure, and the device is also a full cavity structure. The full cavity structure has great reliability risks, and has process problems such as tin stringing short circuit and cutting pollution.

[0006] It can be seen that the chip packaging structure in the prior art cannot encapsulate the waveguide cavity structure and the chip on the basis of ensuring reliability, which is not conducive to reducing the transmission loss of high-frequency signals and improving the signal transmission quality of high-frequency communication products. SUMMARY

[0007] The chip packaging structure, integrated circuit, transceiver system and electronic equipment provided by the embodiments of the present application solve the problem that the chip packaging structure in the prior art cannot encapsulate the waveguide cavity structure and the chip on the basis of ensuring reliability, which is not conducive to reducing the transmission loss of high-frequency signals and improving the signal transmission quality of high-frequency communication products.

[0008] The first aspect of the embodiments of the present application provides a chip packaging structure, which comprises a packaging substrate, a packaging body, a chip, at least one waveguide structure and a dielectric layer.

[0009] The packaging body and the packaging substrate are stacked in a first direction, and the first direction is parallel to the thickness direction of the chip packaging structure. The chip is packaged in the packaging body and is electrically connected to the packaging substrate through a plurality of solder joints, and each waveguide structure is coupled to the chip.

[0010] The dielectric layer is filled between the packaging body and the packaging substrate, and the plurality of solder joints are wrapped in the dielectric layer. The dielectric layer is provided with a first cavity at a position corresponding to each waveguide structure, and the first cavity penetrates the dielectric layer in the first direction.

[0011] The chip packaging structure provided by the embodiments of the present application comprises a stacked packaging substrate and a packaging body, and the packaging body encapsulates a chip and a waveguide structure. The waveguide structure is a functional device that uses a waveguide structure for signal transmission, and the chip is a functional device of a non-waveguide transmission type.

[0012] The medium layer is arranged between the packaging substrate and the package body, supports the two, reinforces the chip packaging structure, and improves the anti-deformation and anti-impact capacity of the whole structure. The first cavities corresponding to the waveguide structure are arranged in the medium layer, that is, the waveguide cavities, the first cavities can be coupled with the waveguide structure to realize waveguide transmission, and the remaining parts are filled with medium to ensure the reliability of the whole chip packaging structure, that is, the chip packaging mode of "cavity structure in specific area and medium filling in remaining area" is realized.

[0013] Therefore, the chip packaging structure provided by the embodiments of the present application can realize the cavity structure in specific area and the medium filling in remaining area, can combine the waveguide cavity and the chip on the basis of ensuring the reliability, is beneficial to reducing the transmission loss of high-frequency signals and improving the signal transmission quality of high-frequency communication products.

[0014] In a possible implementation manner, the medium layer is embedded with a ring-shaped wall at positions corresponding to the first cavities, the wall penetrates the medium layer in the first direction and itself surrounds the first cavities.

[0015] By using the above scheme, the ring-shaped wall can block the medium material from flowing into the inside, and the cavity in the inside forms the first cavity.

[0016] In a possible implementation manner, the wall is a dam glue structure.

[0017] In a possible implementation manner, the material of the dam glue structure is any one of an epoxy resin glue, an acrylic ester resin glue, an organic silicon resin glue, and a polyurethane resin glue.

[0018] By using the above scheme, the material has high viscosity and small flowability, which is beneficial to the forming of the first cavity, and the height of the wall can be set to be relatively high.

[0019] In a possible implementation manner, the medium layer is a bottom filling glue layer.

[0020] In a possible implementation manner, the medium layer is a non-conductive glue film.

[0021] By using the above scheme, the first cavities can be formed by processing a pattern on a whole piece of non-conductive glue film material, and the process is simple and easy to operate.

[0022] In a possible implementation manner, the chip packaging structure further includes a re-distribution layer, one end of the re-distribution layer is electrically connected to the front surface of the chip and the at least one waveguide structure along the first direction, the other end is welded to the plurality of soldering points, and the plurality of soldering points are welded to and electrically connected to the packaging substrate.

[0023] According to the above scheme, the waveguide structure and the chip can communicate through the metal structure in the redistribution layer, and on the other hand, the devices in the package can be electrically connected to the packaging substrate through the redistribution layer, and the packaging substrate can be re-routed to facilitate electrical connection with external circuit boards and other devices.

[0024] In a possible implementation, the inner wall surface of the first cavity is a metal surface.

[0025] According to the above scheme, the metal surface can form a shielding cavity to concentrate the signal transmission in the first cavity.

[0026] In a possible implementation, the projection of the first cavity on the package in the first direction does not overlap with the metal structure in the redistribution layer.

[0027] According to the above scheme, there is no metal structure between the first cavity and the waveguide structure to avoid the metal structure from blocking the waveguide signal. In a possible implementation, the package includes a first sub-package and a second sub-package, and the second sub-package is arranged between the first sub-package and the dielectric layer in the first direction.

[0028] The chip and the at least one waveguide structure are packaged in the first sub-package, and the redistribution layer is packaged in the second sub-package, and the other end of the redistribution layer in the first direction is exposed outside the surface of the second sub-package away from the first sub-package.

[0029] According to the above scheme, the devices in the package and the redistribution layer are arranged in layers, which facilitates assembly and processing.

[0030] In a possible implementation, the packaging substrate is provided with a second cavity at a position corresponding to each first cavity, and the second cavity penetrates the packaging substrate in the first direction and communicates with the corresponding first cavity.

[0031] According to the above scheme, the second cavity can also serve as a waveguide cavity, and the first cavity and the second cavity can be coupled to increase the transmission path of the waveguide signal and reduce the loss of high-frequency signals in the packaging substrate.

[0032] In a possible implementation, the inner wall surface of the second cavity is a metal surface.

[0033] According to the above scheme, the metal surface can form a shielding cavity to concentrate the signal transmission in the second cavity.

[0034] In a possible implementation, the at least one waveguide structure includes a first waveguide structure and a second waveguide structure, and the chip is electrically connected to the first waveguide structure and the second waveguide structure through the redistribution layer.

[0035] In a possible implementation manner, the chip is a radio frequency chip, and the waveguide structure is a waveguide transmission structure or a filter.

[0036] A second aspect of the embodiment of the present application provides an integrated circuit, including a circuit board, and further including the chip packaging structure provided by the first aspect and any implementation manner thereof, the circuit board being arranged on a side of the packaging substrate away from the package body in the first direction and being electrically connected with the packaging substrate.

[0037] The integrated circuit provided by the embodiment of the present application reduces the transmission loss of high-frequency signals and can improve the signal transmission quality of high-frequency communication products.

[0038] In a possible implementation manner, when the packaging substrate is provided with the second cavity, the circuit board is provided with a third cavity at a position corresponding to the second cavity, the third cavity penetrating through the circuit board in the first direction and being in communication with the corresponding second cavity.

[0039] By using the above scheme, the third cavity can also be a waveguide cavity and constitute a part of the waveguide transmission path, thereby reducing the transmission loss of high-frequency signals in the circuit board.

[0040] In a possible implementation manner, the inner wall surface of the third cavity is a metal surface. The metal surface is used to form a shielding cavity to concentrate signals in the transmission in the third cavity.

[0041] A third aspect of the embodiment of the present application provides a transceiver system, including an antenna and the integrated circuit provided by the second aspect and any implementation manner thereof, the antenna being arranged on a side of the circuit board of the integrated circuit away from the chip packaging structure.

[0042] The transceiver system further includes a feeding structure layer, the feeding structure layer being arranged between the circuit board and the antenna, the feeding structure layer having a feeding structure, one end of the feeding structure being coupled with the third cavity of the circuit board, and the other end of the feeding structure being coupled with the antenna.

[0043] The transceiver system provided by the embodiment of the present application reduces the transmission loss of high-frequency signals and can improve the signal transmission quality of high-frequency communication products.

[0044] A fourth aspect of the embodiment of the present application provides an electronic device, including the transceiver system provided by the third aspect.

[0045] The electronic device provided by the embodiment of the present application has high high-frequency signal transmission quality. BRIEF DESCRIPTION OF DRAWINGS

[0046] FIG. 1 is a schematic diagram of a system architecture of an electronic device according to an embodiment of the present application;

[0047] FIG. 2 is a schematic diagram of a structure of a transceiver system according to an embodiment of the present application;

[0048] Fig. 3 is a structural schematic diagram of a chip packaging module in a first reference design;

[0049] Fig. 4 is a structural schematic diagram of a chip packaging module in a second reference design;

[0050] Fig. 5 is a structural schematic diagram of a first embodiment of a chip packaging structure according to the present application;

[0051] Fig. 6 is a top view structural schematic diagram of a dielectric layer in the first embodiment of the chip packaging structure according to the present application;

[0052] Fig. 7 is a structural schematic diagram of a first embodiment of an integrated circuit according to the present application;

[0053] Fig. 8 is a partial enlarged schematic diagram of part A in Fig. 7;

[0054] Figs. 9a-9d are schematic diagrams of a packaging process of the first embodiment of the chip packaging structure according to the present application;

[0055] Figs. 10a-10d are schematic diagrams of a packaging process of the first embodiment of the chip packaging structure according to the present application;

[0056] Fig. 11 is a structural schematic diagram of a second embodiment of a chip packaging structure according to the present application;

[0057] Fig. 12 is a structural schematic diagram of a second embodiment of an integrated circuit according to the present application;

[0058] Fig. 13 is a top view structural schematic diagram of a dielectric layer in the second embodiment of the chip packaging structure according to the present application;

[0059] Figs. 14a-14e are schematic diagrams of a packaging process of the second embodiment of the chip packaging structure according to the present application;

[0060] Fig. 15 is a structural schematic diagram of a third embodiment of a chip packaging structure according to the present application;

[0061] Fig. 16 is a top view structural schematic diagram of a dielectric layer in the third embodiment of the chip packaging structure according to the present application.

[0062] Legend of reference numerals: First reference design: 400', chip packaging structure; 4', packaging body; 5', dielectric layer; 6', packaging substrate; 43', radio frequency chip; 441', first waveguide structure; 442', second waveguide structure; 45', rewiring layer. Second reference design: 400'', chip packaging structure; 4'', packaging body; 6'', packaging substrate; 62'', waveguide cavity; 44'', waveguide structure; 46'', soldering point.

[0063] The application discloses: 100, an electronic device; 200, a transceiver system; 21, an antenna; 22, a feed structure layer; 300, an integrated circuit; 30, a circuit board; 301, a third cavity; 302, a fourth pad; 31, a first integrated circuit; 311, a first chip packaging structure; 312, a first circuit board; 313, a mixing module; 32, a second integrated circuit; 321, a second chip packaging structure; 322, a second circuit board; 323, a radio frequency module; 33, a first waveguide transmission path; 34, a second waveguide transmission path; 400, a chip packaging structure; 4, a package; 41, a first sub-package; 42, a second sub-package; 43, a chip; 43a, a front surface; 43b, a back surface; 431, a first pad; 44, a waveguide structure; 441, a first waveguide structure; 442, a second waveguide structure; 443, a metal structure; 444, a cavity; 45, a rewiring layer; 45a, one end; 45b, the other end; 451, a metal structure; 46, a solder joint; 5, a dielectric layer; 51, a first cavity; 52, an underfill adhesive layer; 53, a wall; 54, a non-conductive adhesive film; 55, a protective film; 6, a packaging substrate; 61, a pin array; 62, a second cavity; 63, a second pad; 64, a third pad; 7, a vent hole; 8, an eWLB structure; X, a first direction. DETAILED DESCRIPTION

[0064] The present application will become fully understood from the detailed description given hereinbelow and the accompanying drawings. While the application will be described in connection with certain embodiments, there is no intent to limit the application to these embodiments. On the contrary, the intent is to cover all alternatives, modifications, and equivalents. Many specific details are included for the purpose of providing a thorough understanding of the present application. However, it will be appreciated by those skilled in the art that the application can be practiced without these details. In other instances, well-known structures have been shown in block diagram form in order to not obscure the present application. Additionally, some specific details are not shown in order to avoid obscuring the present application. It should be borne in mind, that the specific embodiments illustrated, and the specific examples mentioned hereinbelow are examples only. As will be realized by those skilled in the art, the application is capable of further and different embodiments, and its details are capable of modifications in various obvious respects, all without departing from the application. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.

[0065] It is to be noted that, in the present description, similar references and letters indicate similar items in the following drawings, thus, once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings.

[0066] Hereinafter, the terms that can appear in the embodiments of the present application are explained.

[0067] In the description of the application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the application. In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance.

[0068] In the description of the application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium, or it can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the application can be understood according to the specific circumstances.

[0069] The parallel, vertical, same (for example, the same length, the same width, etc.) and the like mentioned in the embodiments of the application are all with respect to the current process level, rather than the absolutely strict definition in the mathematical sense. There can be a deviation within a predetermined angle range between two radiators parallel or vertical to each other, and in an embodiment, the predetermined angle is 10°, for example, the deviation can be within ±5°.

[0070] The co-linear, co-axial, coplanar, symmetric (for example, axisymmetric or central symmetric), parallel, vertical, same (for example, the same length, the same width, etc.) and the like mentioned in the embodiments of the application are all with respect to the current process level, rather than the absolutely strict definition in the mathematical sense. There can be a deviation within a predetermined angle (for example, ±5°, ±10°) between two structures parallel or vertical to each other.

[0071] In the description of the application, it should be understood that "electrically connected" in the application can be understood as physical contact and electrical conduction of components; it can also be understood as a form of connection between different components in the circuit structure through the entity line of the copper foil or wire of the printed circuit board (PCB) that can transmit electrical signals.

[0072] The circuit board can include a printed circuit board (PCB), such as an 8-layer, 10-layer, or 12- to 14-layer board having 8, 10, 12, 13, or 14 layers of conductive material, or elements separated and electrically insulated by a dielectric or insulating layer such as fiberglass, polymer, or the like. In one embodiment, the PCB board includes a dielectric substrate, a ground layer, and a trace layer, with the trace layer and the ground layer electrically connected by vias. The dielectric substrate in the PCB board can be a FR-4 dielectric board, a Rogers dielectric board, or a hybrid Rogers and FR-4 dielectric board. In one embodiment, components such as processors, memories, batteries, charging circuits, system on chip (SoC) structures, or the like can be mounted on or connected to the circuit board; or electrically connected to the trace layer and / or the ground layer in the circuit board. For example, the radio frequency unit is disposed on the trace layer.

[0073] Opposite / Relative: A and B can be opposite / relative to each other, which means that A and B are arranged face to face. For example, when two radiators are opposite to each other, the two radiators are arranged with at least a portion of the area overlapping in a certain direction. In one embodiment, the two opposite radiators are arranged adjacent to each other without other radiators or conductive bodies other than the antenna structure arranged therebetween.

[0074] Coupling: can be understood as direct coupling and / or indirect coupling, and "coupled connection" can be understood as direct coupled connection and / or indirect coupled connection. Direct coupling can also be referred to as "electrical connection", which means that the components are directly or indirectly in physical contact and electrically conductive, for example, in the form of connection between different components in a circuit structure through a physical circuit such as a copper foil or a wire on a printed circuit board (PCB) that can transmit electrical signals; "indirect coupling" can be understood as electrical conduction between two conductors through a space without contact. In one embodiment, indirect coupling can also be referred to as capacitive coupling, for example, through the coupling between the gap between two conductive parts to form an equivalent capacitor to achieve signal transmission.

[0075] In order to make the purpose, technical scheme and advantages of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the drawings.

[0076] To solve the problem that the chip packaging structure cannot package the waveguide cavity and the chip together on the basis of ensuring reliability, which is not conducive to reducing the transmission loss of high-frequency signals and improving the signal transmission quality of high-frequency communication products, the embodiments of the present application provide a chip packaging structure, an integrated circuit, a transceiver system and an electronic device, which package the waveguide cavity and the chip together in a specific area by using a cavity structure and filling the medium in the remaining area, realize low-loss transmission in the high-frequency band, and promote the evolution of communication products to a higher frequency band.

[0077] It should be noted that the technical solutions of the present application can be applied to any one or several of the following communication systems: radar system, long term evolution (LTE) system, LTE frequency division duplex (FDD) system, LTE time division duplex (TDD) system, universal mobile communication system (UMTS), worldwide microwave access (WiMAX) communication system or new radio (NR), device to device (D2D) system, vehicle to everything (V2X) system and future communication system, etc. The technical solutions of the present application can be applied to high-frequency communication systems such as D band, 5G (5th generation) system, 5.5G, 6G 8G, 13G, etc. They can also be applied to medium or low frequency communication systems.

[0078] Please refer to FIG. 1 to FIG. 2, FIG. 1 is a system architecture schematic diagram of the electronic device of the embodiments of the present application; FIG. 2 is a structure schematic diagram of the transceiver system of the embodiments of the present application.

[0079] As shown in FIG. 1, the embodiments of the present application provide an electronic device 100, which includes a transceiver system 200, and the transmission of signals in space can be realized through the transceiver system 200. The electronic device 100 may, for example, be a wireless base station product, a microwave product, etc., such as a macro base station, a micro base station, a pico base station, a distributed base station, a microwave antenna, a microwave transceiver, a microwave repeater, etc., and the present application does not limit this.

[0080] The electronic device 100 provided by the embodiments of the present application can be a device for communicating with a terminal device, including a base transceiver station (BTS) in a global system for mobile communications (GSM) system or a code division multiple access (CDMA) system, a Node B (NB) in a wideband code division multiple access (WCDMA) system, an evolved Node B (eNB or eNodeB) in an LTE system, a wireless controller in a cloud radio access network (CRAN) scenario, or a base station in a future communication network or a future evolved public land mobile network (PLMN) network, including a relay station, an access point, a vehicle-mounted device, a wearable device, and the like, and the embodiments of the present application are not limited thereto.

[0081] As shown in FIGS. 1 and 2, the transceiving system 200 includes an antenna 21, integrated circuits 300, and a feed structure layer 22. The antenna 21 is configured to receive and transmit signals, and the feed structure layer 22 has a feed structure for feeding the antenna 21 to excite a radiator of the antenna 21 to radiate signals. The integrated circuits 300 (e.g., first integrated circuit 31 and second integrated circuit 32) are signal generation, transmission, and processing units. The antenna 21 in the transceiving system 200 can be a planar printed antenna, a waveguide antenna, a metasurface antenna, a dipole antenna, and the like, and the present application is not limited thereto.

[0082] The integrated circuits 300 can include a chip packaging structure 400 and a circuit board 30, and the chip packaging structure 400 encapsulates a chip 43 and is electrically connected to the circuit board 30. In a possible implementation, the integrated circuits 300 can include a radio frequency module 323, which can send a radio frequency signal to the feed structure layer 22 to feed the antenna 21 through the feed structure on the feed structure layer 22. The radio frequency module 323 can include a radio frequency transceiver, such as a radio frequency integrated circuit (RFIC), which is communicatively connected to the antenna 21 through a radio frequency circuit, a feed structure, and the like. In some possible implementations, the integrated circuits 300 can further include a digital signal processor, a filter, a phase shifter, a mixer, and the like, and the present application is not limited thereto.

[0083] It should be noted that the number of integrated circuits 300 in the transceiver system 200 is not limited, and one or more integrated circuits 300 can be provided, for example, different circuit components of the transceiver system 200 are provided as different integrated circuits 300, and each integrated circuit 300 can be a radio frequency front-end integrated circuit, a signal processing integrated circuit, a control integrated circuit, etc., which is not limited in the present application.

[0084] As shown in FIG. 2, in one possible implementation, the transceiver system 200 includes a first integrated circuit 31 and a second integrated circuit 32. The first integrated circuit 31 includes a first chip packaging structure 311 and a first circuit board 312, and a mixing module 313 is integrated on the first integrated circuit 31, for example, a mixer chip is packaged in the first chip packaging structure 311. The second integrated circuit 32 includes a second chip packaging structure 321 and a second circuit board 322, and a radio frequency module 323 is integrated on the second integrated circuit 32, for example, a radio frequency chip is packaged in the second chip packaging structure 321. The mixing module 313 can mix an input signal with a signal generated by a local oscillator to generate a new frequency signal, which can be used for frequency conversion. In one possible implementation, the mixing module 313 on the first integrated circuit 31 converts an intermediate frequency signal into a high frequency signal and transmits the high frequency signal to the radio frequency module 323 on the second integrated circuit 32.

[0085] As shown in FIG. 2, in one possible implementation, the mixing module 313 transmits signals to the radio frequency module 323 through a first waveguide transmission path 33, and the radio frequency module 323 transmits radio frequency signals to the antenna 21 through a second waveguide transmission path 34. The first waveguide transmission path 33 and the second waveguide transmission path 34 can each be a waveguide transmission line composed of a plurality of waveguide cavities, and the specific path is not limited. For example, as shown in FIG. 2, in one possible implementation, the first waveguide transmission path 33 can pass through the first circuit board 312, extend to the second integrated circuit 32 through the feed structure layer 22, and pass through the second circuit board 322 of the second integrated circuit 32. The second waveguide transmission path 34 can pass through the second circuit board 322 and the feed structure layer 22 and extend to the antenna 21. In some possible implementations, signals can also be transmitted between the mixing module 313 and the radio frequency module 323 through a non-waveguide transmission path, such as a microstrip line, a metal trace, etc. Signals can also be transmitted between the radio frequency module 323 and the antenna 21 through a non-waveguide transmission structure, which is not limited in the present application.

[0086] Please refer to FIG. 3 and FIG. 4, FIG. 3 is a structural schematic diagram of a chip packaging module in a first reference design; and FIG. 4 is a structural schematic diagram of a chip packaging module in a second reference design.

[0087] Those skilled in the art can understand that the radio frequency module 323 in the second integrated circuit 32 receives and transmits signals through the waveguide transmission structure, which requires a waveguide cavity to be designed in the second chip packaging structure 321.

[0088] As shown in FIG. 3, in the first reference design, the chip packaging structure 400' includes a package 4', a medium layer 5' and a packaging substrate 6' arranged in layers, the package 4' encapsulates a radio frequency chip 43', a first waveguide structure 441' and a second waveguide structure 442', and further includes a redistribution layer 45'. The redistribution layer 45' is provided with metal traces, and the radio frequency chip 43' can communicate with the two waveguide structures through the redistribution layer 45'. However, in this scheme, the package 4' and the packaging substrate 6' are filled with the medium layer 5' throughout, without a cavity structure, and the two waveguide structures cannot receive or transmit waveguide signals.

[0089] As shown in FIG. 4, in the second reference design, the package 4'' and the packaging substrate 6'' of the chip packaging structure 400''' are not provided with a medium layer, i.e., a full cavity structure, and are only supported and connected by solder joints 46''. The packaging substrate 6'' has two waveguide cavities 62'' corresponding to the two waveguide structures 44'' on the packaging substrate 6''. Although the waveguide structures 44'' can be coupled to the waveguide cavities 62'' through the gap between the packaging substrate 6'' and the package 4'', the reliability of this structure is extremely poor and the risk of damage is high.

[0090] Some technologies can form a cavity structure below the chip (understood as the side of the chip facing the circuit board), but none of them can be applied to the scenario shown in FIG. 2. For example, one scheme forms a photoresist layer on the surface of the chip, then exposes and develops it, forms a sealing ring around the chip, and finally realizes a cavity structure at the acoustic filter. This scheme uses photolithography technology, which is costly, and the sealing ring formed by photolithography has a thickness range of 1-50 μm, which is relatively limited and cannot meet the larger spacing (bump height) between the package and the packaging substrate. Another scheme uses a precision steel mesh to surround the chip, injects packaging material on the surface of the steel mesh, and then peels off the precision steel mesh after solidification. After molding, a cavity structure is formed between the chip and the packaging substrate. This scheme can only realize a full cavity structure, and the packaging material is prone to flowing into the steel mesh during injection, making the operation more difficult. Another scheme uses a medium layer deposition process, a selective removal process and a controlled patterning process to form a cavity structure. This scheme not only has a complex process and high cost, but also uses an overmolding process, which cannot reserve a vent hole, and the reliability risk is high during subsequent reflow.

[0091] The chip packaging structure 400 of the present application can solve the problems in the above-mentioned reference schemes, which will be described in detail below with reference to the accompanying drawings. It should be noted that the first chip packaging structure 311 and the second chip packaging structure 321 in FIG. 2 can both apply the chip packaging structure 400 provided by the embodiments of the present application, and the following description will focus on the second chip packaging structure 321.

[0092] Please refer to FIGS. 5-6, FIG. 5 is a structural schematic diagram of a first embodiment of the chip packaging structure of the present application, and FIG. 6 is a top structural schematic diagram of a medium layer in the first embodiment of the chip packaging structure of the present application.

[0093] As shown in FIG. 5, the chip packaging structure 400 includes a packaging substrate 6 and a packaging body 4, and the packaging body 4 is stacked with the packaging substrate 6 in a first direction X, which is parallel to the thickness direction of the chip packaging structure 400. The packaging body 4 is an integrated whole encapsulating chips and other functional devices, and the packaging substrate 6 is used to connect the chips 43 and other functional devices in the packaging body 4 with external circuits and can provide protection and support for the packaging body 4. The packaging substrate 6 can be made of ceramic, plastic or other materials, and has circuit traces inside. The side of the packaging substrate 6 close to the packaging body 4 is electrically connected with the chips and other functional devices inside the packaging body 4, and the surface of the side away from the packaging body 4 is provided with a pin array 61 (for example, an array structure composed of multiple pads), which can be connected to external circuits (for example, the first circuit board 312 or the second circuit board 322) through the pin array 61. The specific structure of the packaging substrate 6 is not limited in the present application, and the accompanying drawings are only schematic.

[0094] As shown in FIG. 5, the chip packaging structure 400 further includes a chip 43 and at least one waveguide structure 44. The chip 43 is encapsulated in the packaging body 4 and electrically connected with the packaging substrate 6 through multiple solder joints 46, and each waveguide structure 44 is coupled with the chip 43.

[0095] The chip 43 can be specifically a silicon (Si) substrate chip, a sapphire substrate chip, a silicon carbide (SiC) substrate chip, a diamond substrate chip, etc., and the specific type of the chip 43 is not limited in the present application. As shown in FIG. 5, the chip 43 has a front surface 43a and a back surface 43b. The front surface 43a of the chip 43 can also be referred to as an active surface, and the front surface 43a is integrated with microelectronic components such as transistors, resistors, capacitors, etc. The back surface 43b of the chip 43 is opposite to the active surface. The front surface 43a of the chip 43 faces the packaging substrate 6, so as to electrically connect the electronic components of the front surface 43a with the packaging substrate 6.

[0096] The soldering point 46, also referred to as a bump, has one end electrically connected to the chip 43 in the first direction X, for example, directly soldered to the front surface 43a of the chip 43, or indirectly electrically connected to the chip 43 through other structures, and the other end soldered to the packaging substrate 6. In some possible implementation manners, the soldering point 46 can be a soldering ball, for example, a tin soldering ball. The shape of the soldering point 46 can be spherical, cylindrical, or the like, which is not limited in the present application. The number and layout manner of the soldering points 46 are not limited, and should be specifically set according to the circuit, which is only schematic in FIGS. 5 and 6.

[0097] The waveguide structure 44 is a device that uses a waveguide structure to transmit or process signals, and can be a waveguide transmission structure, for example, a waveguide cavity, or a waveguide functional device, for example, a filter using a waveguide structure, and the specific type of each waveguide structure 44 is not limited in the present application. The number of waveguide structures 44 is not limited, and can be one, two, three, or more.

[0098] It should be noted that the relative positions and coupling connections of the chip 43 and the waveguide structure 44 are not limited, as long as the signals can be transmitted. As shown in FIG. 5, in one possible implementation manner, the chip 43 and the waveguide structure 44 are spaced apart in a plane perpendicular to the first direction X and coupled through metal traces. In other possible implementation manners, the chip 43 and the waveguide structure 44 can also be directly in contact to achieve coupling connection, and in this case, the two are correspondingly arranged in the first direction X. For details, please refer to the related description of FIGS. 15 and 16 below.

[0099] As shown in FIG. 5, in one possible implementation, the chip packaging structure 400 further includes a rewiring layer 45, one end 45a of the rewiring layer 45 is electrically connected to the front surface 43a of the chip 43 and the waveguide structure 44 along the first direction X, and the other end 45b is provided with a plurality of soldering points 46 and is soldered and electrically connected to the packaging substrate 6 through the plurality of soldering points 46. Those skilled in the art can understand that the chip 43 and the waveguide structure 44 are provided with pads connected to the outside, and due to the size of the device, the original pad layout is not suitable for direct connection to the external circuit, and the rewiring layer 45 can rewire and distribute the chip 43 and the waveguide structure 44 to facilitate connection to the packaging substrate 6. The rewiring layer 45 has a metal structure 451 therein, which may, for example, be a circuit structure made of a metal material, such as copper, aluminum, etc. The rewiring layer 45 can adopt a one-layer or multi-layer structure, and each layer is separated by an insulating layer to prevent short circuit and interference between signals. The specific structure of the rewiring layer 45 is not limited in the present application, and the drawing is only schematic. Or it can be understood that the rewiring layer 45 is also provided in the package 4. On the one hand, the waveguide structure 44 and the chip 43 can communicate through the metal structure 451 in the rewiring layer 45. On the other hand, the devices in the package 4 can be electrically connected to the packaging substrate 6 through the rewiring layer 45, and rewire through the packaging substrate 6 to facilitate electrical connection with external devices such as the circuit board 30.

[0100] The soldering points 46 are electrically connected to the other end 45b of the rewiring layer 45 at one end in the first direction X, for example, can be in contact or soldered connection with the rewiring layer 45, and the other end is soldered to the packaging substrate 6. The rewiring layer 45 is electrically connected to the packaging substrate 6 through the soldering points 46, and the chip 43 is indirectly electrically connected to the packaging substrate 6.

[0101] In some possible implementations, the rewiring layer 45 can also not be provided, and the chip 43 and the waveguide structure 44 can also be directly coupled through the waveguide cavity, which will be described in detail later.

[0102] As shown in FIGS. 5 and 6, the chip packaging structure 400 further includes a dielectric layer 5 filled between the package 4 and the packaging substrate 6, and the soldering points 46 are wrapped in the dielectric layer 5. The dielectric layer 5 is composed of an insulating material, such as epoxy resin, polyimide, silicon dioxide, etc., and the specific material thereof is not limited in the present application. The insulating medium in the dielectric layer 5 is isolated between the rewiring layer 45 and the packaging substrate 6 and filled in the gap between different soldering points 46, which can prevent electric leakage and assist in heat dissipation of the chip packaging structure 400. Moreover, the dielectric layer 5 has a certain mechanical strength, which can improve the overall structural strength of the chip packaging structure 400, prevent the circuit board 30 from being deformed and damaged, and improve the reliability.

[0103] Further, the medium layer 5 is provided with a first cavity 51 corresponding to the position of each waveguide structure 44, and the first cavity 51 penetrates the medium layer 5 in the first direction X. The position corresponding to each waveguide structure 44 of the medium layer 5 can be understood as the region where the projection of each waveguide structure 44 on the medium layer 5 in the first direction X is located. For example, the positions below the two waveguide structures 44 (the first waveguide structure 441 and the second waveguide structure 442) in FIG. 5 are each provided with a first cavity 51, and the signals of each waveguide structure 44 can be transmitted in the first cavity 51. The first cavity 51 can be understood as a perforation or hollow structure on the medium layer 5, and the inside of the cavity is air, the dielectric constant of air is small, and the transmission loss of high-frequency signals in the first cavity 51 is low. As shown in FIG. 5, the other regions between the package 4 and the package substrate 6 except the first cavity 51 are still filled with the medium layer 5 (medium material), which can ensure the mechanical properties of the chip package structure 400, and has higher reliability compared with the full-cavity scheme in FIG. 4.

[0104] The chip package structure 400 provided by the embodiment of the present application includes the package substrate 6 and the package 4 which are arranged in a stack, and the chip 43 and the waveguide structure 44 are packaged in the package 4. The waveguide structure 44 is a functional device that uses a waveguide structure for signal transmission, and the chip 43 is a functional device of a non-waveguide transmission type.

[0105] The package substrate 6 and the package 4 are further provided with the medium layer 5 which is supported therebetween, and the medium layer 5 reinforces the chip package structure 400 and improves the anti-deformation and anti-impact capabilities of the whole structure. The first cavity 51 (waveguide cavity) is arranged in the medium layer 5 corresponding to the position of the waveguide structure 44, the first cavity 51 can be coupled with the waveguide structure 44 to realize waveguide transmission, and the remaining parts are filled with medium to ensure the reliability of the whole chip package structure 400, that is, the chip package mode of “using cavity structure in specific region and filling medium in the remaining region” is realized. In the packaging process of the chip, filling the medium in the other regions except the waveguide cavity can also avoid problems such as solder short circuit (for example, short circuit caused by the melting of solder balls and the connection of other solder balls together) and cutting pollution (in the process of cutting a wafer of assembled workpieces into single chip package structures 400, foreign substances such as particles, metal debris, and the like are attached to the chip package structure 400, affecting the circuit function), and improves the assembly yield.

[0106] Therefore, the chip package structure 400 provided by the embodiment of the present application can realize the chip package mode of “using cavity structure in specific region and filling medium in the remaining region”, and can package the waveguide cavity and the chip 43 on the basis of ensuring reliability, which is conducive to reducing the transmission loss of high-frequency signals and improving the signal transmission quality of high-frequency communication products.

[0107] As shown in FIG. 5, in one possible implementation, the package 4 includes two waveguide structures 44, i.e., a first waveguide structure 441 and a second waveguide structure 442, and the chip 43 is a radio frequency chip, and the waveguide structures 44 are waveguide transmission structures, which can realize the scenario shown in FIG. 2. For example, the transmission path of the transmitted signal can be as follows:

[0108] 1. The mixing module 313 transmits the signal to the first waveguide structure 441 through the first waveguide transmission path 33, and the first cavity 51 below the first waveguide structure 441 belongs to the first waveguide transmission path 33.

[0109] 2. The first waveguide structure 441 transmits the signal to the radio frequency chip through the redistribution layer 45.

[0110] 3. The radio frequency chip transmits the radio frequency signal to the second waveguide structure 442 through the redistribution layer 45.

[0111] 4. The second waveguide structure 442 transmits the signal to the antenna 21 through the second waveguide transmission path 34, and the first cavity 51 below the second waveguide structure 442 belongs to the second waveguide transmission path 34.

[0112] The transmission path of the received signal can be opposite to the above process, which will not be described herein again.

[0113] In one possible implementation, the first waveguide structure 441 and the second waveguide structure 442 can be waveguide converters. The waveguide converter is a waveguide transmission structure, which can convert the waveguide signal into a non-waveguide signal, or convert the non-waveguide signal into a waveguide signal, so that the waveguide structure 44 can couple the received waveguide signal to the redistribution layer 45, or couple the signal in the redistribution layer 45 to the waveguide cavity inside the waveguide structure 44.

[0114] The above scenario is only an example, and the chip package structure 400 provided by the embodiments of the present application can also be applied to other scenarios other than FIG. 2, which is not limited in the present application.

[0115] It should be noted that the shape of the first cavity 51 is not limited in the present application. As shown in FIG. 6, in one possible implementation, the cross section of the first cavity 51 is rectangular, and the regular shape of the rectangular cavity is convenient for processing. In some possible implementations, the cross section of the first cavity 51 can also be circular, triangular, irregular, etc.

[0116] As shown in FIG. 5, in one possible implementation, the projection of the first cavity 51 on the package 4 along the first direction X does not overlap with the metal structure 451 (i.e., the black structure block in FIG. 5) in the redistribution layer 45. Or, it can be understood that there is no metal structure 451 between the first cavity 51 and the waveguide structure 44, so as to avoid the metal structure 451 from blocking the waveguide signal. In some possible implementations, a small amount of metal structure 451 can be present between the first cavity 51 and the waveguide structure 44 without affecting the waveguide signal transmission, which is not limited in the present application.

[0117] As shown in FIG. 5, in one possible implementation, the package 4 includes a first sub-package 41 and a second sub-package 42, and the second sub-package 42 is arranged between the first sub-package 41 and the dielectric layer 5 along the first direction X. The chip 43 and the waveguide structure 44 are encapsulated in the first sub-package 41, and the redistribution layer 45 is encapsulated in the second sub-package 42. The other end 45b of the redistribution layer 45 along the first direction X is exposed to the surface of the second sub-package 42 away from the first sub-package 41, for connection with the solder joint 46. Or, it can be understood that the package 4 is divided into two layers, one of which is used to encapsulate the chip 43 and the waveguide structure 44, i.e., the first sub-package 41, and the other of which is used to encapsulate the redistribution layer 45, i.e., the second sub-package 42. With this structure, the devices in the package 4 and the redistribution layer 45 are arranged in layers, which facilitates assembly and processing. The first sub-package 41 and the second sub-package 42 can be made of the same encapsulation material, or can be made of different encapsulation materials. For example, a plastic encapsulation film can be used to encapsulate the chip 43 and the waveguide structure 44 to form the first sub-package 41, and then a filling dielectric material is used to encapsulate the redistribution layer 45 to form the second sub-package 42. Alternatively, the same kind of dielectric material can be used to encapsulate the chip 43, the waveguide structure 44 and the redistribution layer 45 at the same time, which is not limited in the present application.

[0118] As shown in FIG. 5, in one possible implementation, the package substrate 6 is provided with a second cavity 62 at a position corresponding to each first cavity 51, and the second cavity 62 penetrates through the package substrate 6 along the first direction X and communicates with the corresponding first cavity 51. The second cavity 62 can also serve as a waveguide cavity, and the first cavity 51 and the second cavity 62 can be coupled for signal transmission, which increases the transmission path of the waveguide signal and reduces the loss of high-frequency signals in the package substrate 6.

[0119] In a possible implementation, the inner wall surface of the first cavity 51 and the second cavity 62 is a metal surface, which can form a shielding cavity to concentrate the signal transmission in the waveguide cavity. The metal surface can be, for example, a metal coating on the inner wall of the cavity, which is not limited in the application. The inner wall surface of the first cavity 51 and / or the second cavity 62 can also be a non-metal surface. The signal can be reflected by the metal part such as the solder joint 46 around the first cavity 51 to concentrate the signal transmission in the first cavity 51, or the signal can be reflected by the metal via around the second cavity 62 to concentrate the waveguide signal transmission in the second cavity 62, which is not limited in the application.

[0120] Referring to FIG. 7, FIG. 7 is a structural schematic diagram of the first embodiment of the integrated circuit provided in the application.

[0121] As shown in FIG. 7, the integrated circuit 300 provided in the application includes a circuit board 30 and a chip packaging structure 400. The circuit board 30 is arranged on the side of the packaging substrate 6 away from the package 4 in the first direction X and is electrically connected to the packaging substrate 6. The circuit board 30 can be, for example, a PCB (Printed Circuit Board) or a TRX (Transceiver) single board, which is not limited in the application. The integrated circuit 300 provided in the application reduces the transmission loss of high-frequency signals and can improve the signal transmission quality of high-frequency communication products.

[0122] As shown in FIG. 7, in a possible implementation, when the packaging substrate 6 is provided with the second cavity 62, the circuit board 30 is provided with a third cavity 301 at a position corresponding to the second cavity 62. The third cavity 301 penetrates the circuit board 30 in the first direction X and is in communication with the corresponding second cavity 62. The third cavity 301 can also be a waveguide cavity and constitute a part of the waveguide transmission path to reduce the transmission loss of high-frequency signals in the circuit board 30.

[0123] In a possible implementation, the inner wall surface of the third cavity 301 is a metal surface, which is used to form a shielding cavity to concentrate the signal transmission in the third cavity 301. The inner wall surface of the third cavity 301 can also be a non-metal surface, and a shielding cavity can be formed by using metal traces in the circuit board 30, which is not limited in the application.

[0124] As shown in FIG. 7, in one possible implementation, the first cavity 51, the second cavity 62, and the third cavity 301 corresponding to each waveguide structure 44 are communicated, and the whole of the three cavities can be used as the vent hole 7 to ventilate the integrated circuit 300 during the reflow soldering process. The reflow soldering refers to a process of heating at high temperature to melt the solder on the workpiece to realize the electrical and mechanical connection between components. Generally, the chip package structure 400 and the circuit board 30 can be placed in a reflow soldering furnace as a whole to be heated, so that the solder between the layers of the structure is melted and welded, such as the solder joint 46 under the package 4, the solder paste on the package substrate 6, the solder pad, and the like. Those skilled in the art can understand that, if the vent hole 7 is not provided (for example, only the first cavity 51 is provided, and the second cavity 62 and the third cavity 301 are not provided), the first cavity 51 is relatively closed during the reflow soldering process, and the air inside the first cavity 51 expands under the action of high temperature, which can easily cause the workpiece to burst, that is, the "popcorn" effect occurs, which affects the production yield. The three cavities are communicated, the waveguide transmission can be performed through the three cavities, and the three cavities can be used as the vent hole 7 as a whole to ventilate the workpiece during the reflow soldering or other high-temperature working links, so that the high-temperature "popcorn" effect is prevented. In addition, the waveguide cavities are multiplexed as the vent hole 7, so that the space utilization of the package substrate 6 and the circuit board 30 is improved, the structural perforation is reduced, and the processing flow during production is simplified. In one possible implementation, the vent hole can also be provided separately outside the waveguide cavity, and the present application does not limit this.

[0125] As shown in FIGS. 2 and 7, in one possible implementation, the antenna 21 in the transceiver system 200 is arranged on the side of the circuit board 30 away from the chip package structure 400, the feed structure layer 22 is arranged between the circuit board 30 and the antenna 21, one end of the feed structure in the feed structure layer 22 is coupled with the third cavity 301 of the circuit board 30, and the other end of the feed structure is coupled with the antenna 21, so as to realize the signal transmission between the circuit board 30 and the antenna 21. In one possible implementation, the feed structure in the feed structure layer 22 is also a waveguide cavity, and the two ends of the waveguide cavity are coupled with the third cavity 301 and the antenna 21 respectively. The waveguide cavity in the feed structure layer 22 also constitutes a part of the waveguide transmission path, so as to reduce the transmission loss of the high-frequency signal in the feed structure layer 22. In one possible implementation, the antenna 21 can be a waveguide antenna 21, and the signal radiation is performed through the waveguide cavity. Therefore, the signal transmission is performed through the waveguide cavity in each part of the transceiver system 200, so as to minimize the transmission loss.

[0126] Please refer to FIG. 8, which is a partial enlarged view of part A in FIG. 7.

[0127] It should be noted that the present application does not limit the connection mode between the layers of the integrated circuit 300. As shown in FIG. 8, the metal trace is filled with a single layer of shading, and the pad is filled with a double layer of shading. Taking the transmission path from the chip 43 to the circuit board 30 as an example, in one possible implementation, the front surface 43a of the chip 43 is provided with a first pad 431, and the metal structure 451 of one end 45a of the redistribution layer 45 is welded to realize electrical connection. Among them, one end 45a of the redistribution layer 45 can be provided as a metal pin (such as a metal column), and the metal pin is welded with the corresponding first pad 431. Further, the metal structure 451 of the other end 45b of the redistribution layer 45 protrudes from the surface of the second sub-package 42 and contacts the solder joint 46. The other end 45b can also be provided as a metal pin, and the metal pin is welded with the corresponding solder joint 46 to realize electrical connection. Further, in one possible implementation, the surface of the packaging substrate 6 facing the chip 43 side is provided with a second pad 63, the surface facing the circuit board 30 side is provided with a third pad 64, and the side of the circuit board 30 facing the packaging substrate 6 is provided with a fourth pad 302. The second pad 63 is welded with the solder joint 46 to electrically connect the metal trace in the packaging substrate 6 with the chip 43, and the third pad 64 is welded with the fourth pad 302 on the circuit board 30 to realize electrical connection between the packaging substrate 6 and the circuit board 30. In actual scenarios, the above-mentioned pads, metal pins and solder joints 46 can be flexibly replaced, and the present application does not limit this.

[0128] It should be noted that the present application does not limit the formation mode of the first cavity 51, and two formation modes and the corresponding assembly process are exemplarily described below in conjunction with the drawings.

[0129] In one possible implementation, the medium layer 5 is an underfill layer 52. Those skilled in the art can understand that the underfill layer 52 is usually formed after the underfill material between the packaging body 4 and the packaging substrate 6 is poured and flows, and the underfill material has fluidity and is difficult to directly form a cavity structure. As shown in FIGS. 5 and 6, in one possible implementation, the medium layer 5 is embedded with a ring-shaped wall 53 at the position corresponding to each first cavity 51, the wall 53 penetrates the medium layer 5 in the first direction X and itself surrounds the first cavity 51. The ring-shaped wall 53 is provided at the position of the first cavity 51, and the medium material cannot flow into the inside of the ring-shaped wall 53, and the cavity inside the ring-shaped wall 53 forms the first cavity 51.

[0130] In a possible implementation, the wall 53 is a dam structure. Those skilled in the art can understand that the dam also has a certain fluidity. To prevent the dam from flowing and deforming and damaging the forming of the first cavity 51, a resin with high viscosity can be selected as the dam, for example, epoxy resin, acrylic resin, silicone resin, polyurethane resin, and the like, which are not limited in the present application. The high-viscosity material has small fluidity, which is beneficial to the forming of the first cavity 51, and the height of the wall 53 can be set to be higher, supporting a higher bump height (i.e., the height of the solder joint 46).

[0131] Please refer to FIGS. 9a-10d, FIGS. 9a-9d are schematic diagrams of a packaging process of a first embodiment of the chip packaging structure of the present application; and FIGS. 10a-10d are schematic diagrams of another packaging process of the first embodiment of the chip packaging structure of the present application.

[0132] In the drawings, FIGS. 9a-9d are top views, i.e., views perpendicular to the first direction X. FIGS. 10a-10d are side views.

[0133] As shown in FIG. 5, in a possible implementation, the chip package adopts an eWLB structure 8 (Embedded Wafer Level Ball Grid Array). In the eWLB structure, the diced chip 43 is usually placed with the front surface 43a facing down on a carrier wafer, and then the chip 43 and the carrier wafer are packaged by molding compound. Then a series of process steps are performed, such as removing the carrier wafer, forming a redistribution layer 45 on the pads of the chip 43, making solder joints 46 (such as ball planting) on the redistribution layer 45, and the like. Finally, the packaged wafer is cut into individual chip packaging units. Alternatively, the solder joints 46 can be soldered on the redistribution layer 45 of the packaged package 4, and the solder joints 46 and the package 4 are packaged as a whole with other structures, which is the eWLB structure 8. The eWLB structure 8 has higher integration. In some possible implementations, the chip 43 can also be packaged in other ways, such as an FC structure, which is not limited in the present application.

[0134] For example, the process of packaging the eWLB structure 8 with the packaging substrate 6 can include:

[0135] Step 1: As shown in FIGS. 9a and 10a, dispensing glue on the packaging substrate 6. Specifically, the packaging substrate 6 is provided with a second cavity 62, and a ring-shaped wall 53 is formed by dispensing glue (such as dam glue) around the opening of the second cavity 62.

[0136] Step 2: As shown in FIG. 9b and FIG. 10b, the eWLB structure 8 is soldered on the package substrate 6. Specifically, the soldering points 46 in the eWLB structure 8 can be soldered with the corresponding soldering pads on the package substrate 6. The process can adopt reflow soldering or TCB (Thermal Compression Bonding) process, which is not limited in the present application.

[0137] Step 3: As shown in FIG. 9c and FIG. 10c, the gap between the package substrate 6 and the package 4 is filled with a bottom filling material, and the bottom filling material forms the dielectric layer 5 after solidification. During the filling process, the annular wall 53 is used to block the bottom filling material from entering the first cavity 51.

[0138] Step 4: As shown in FIG. 9d and FIG. 10d, the package substrate 6 is cut to form a single chip package structure 400. Those skilled in the art can understand that, in order to improve production efficiency, a plurality of eWLB structures 8 can be soldered on a whole substrate for batch production, and then the batch production module is cut into a single chip after assembly. The number of chip package structures 400 in the batch production module is not limited, and only two are shown in the figure as an example.

[0139] In the above embodiment, the dispensing in step 1 can be solidified together with the bottom filling material in step 3, without the need for separate solidification, which can reduce the process and save processing time. The bottom filling material in step 3 can enter the gap from the side or the periphery of the package 4, which is not limited in the present application. The actual packaging process can include more or fewer steps, which is not limited in the present application.

[0140] Referring to FIG. 11 to FIG. 14e, FIG. 11 is a structural schematic diagram of a second embodiment of a chip package structure according to the present application; FIG. 12 is a structural schematic diagram of a second embodiment of an integrated circuit according to the present application; FIG. 13 is a top view structural schematic diagram of a dielectric layer in the second embodiment of the chip package structure according to the present application; and FIG. 14a to FIG. 14e are packaging process schematic diagrams of the second embodiment of the chip package structure according to the present application.

[0141] As shown in FIG. 11 and FIG. 12, in one possible implementation, the dielectric layer 5 is a non-conductive adhesive film 54 (NCF, Non-Conductive Film). The non-conductive adhesive film 54 can fill the gap between the package 4 and the package substrate 6, and provide buffering and supporting effects. Because of its non-conductive property, short circuit between adjacent conductive parts can be avoided. The specific material of the non-conductive adhesive film 54 can be epoxy resin, acrylate, silicone, etc., which is not limited in the present application.

[0142] As shown in FIG. 13, when the dielectric layer 5 is the non-conductive adhesive film 54, the first cavities 51 can be formed on the whole material by patterning, which is simple and easy to operate. Similarly, the eWLB packaging process can be used to combine the package 4 and the soldering points 46, and then package the eWLB structure 8 and the package substrate 6 together.

[0143] For example, the packaging process of the eWLB structure 8 and the package substrate 6 can include the following steps:

[0144] Step 1: As shown in FIG. 14a, the first cavities 51 are formed on the non-conductive adhesive film 54 by patterning.

[0145] Step 2: As shown in FIG. 14b, the eWLB structure 8 is placed with the front surface 43a of the chip 43 facing upward, and then the non-conductive adhesive film 54 is attached to the eWLB structure 8.

[0146] Step 3: As shown in FIG. 14c, the assembled eWLB structure 8 and the non-conductive adhesive film 54 are cut into single pieces.

[0147] Step 4: As shown in FIG. 14d, the eWLB structure 8 with the non-conductive adhesive film 54 is connected to the package substrate 6 by TCB or other processes, and in this process, the front surface 43a of the chip 43 faces downward.

[0148] Step 5: As shown in FIG. 14e, the package substrate 6 is cut to form a single chip package structure 400.

[0149] As understood by those skilled in the art, the non-conductive adhesive film 54 has adhesion on both sides, and to prevent adhesion during patterning, protective films 55 are attached to both sides of the non-conductive adhesive film 54. In step 2, the protective film 55 on one side can be removed first, and then the non-conductive adhesive film 54 with the protective film 55 removed on one side is attached to the eWLB structure 8, and in step 4, the protective film 55 on the other side of the non-conductive adhesive film 54 is removed and attached to the package substrate 6.

[0150] The non-conductive adhesive film 54 has certain fluidity and viscosity, and in step 2, the non-conductive adhesive film 54 can be completely attached to the eWLB structure 8 by vacuum lamination process, and after curing, the dielectric layer 5 is formed, so that the soldering points 46 are wrapped in the adhesive film. Finally, the non-conductive adhesive film 54 needs to be cured to form the dielectric layer 5 with supporting force, and the curing step can be placed after step 4, which is not limited. The actual packaging process can include more or fewer steps, which is not limited in the present application.

[0151] As understood by those skilled in the art, in addition to the process of forming the first cavities 51 on the dielectric layer 5, other steps of packaging the chip 43 can use existing processes, which has high compatibility with existing processes and can avoid increasing redundant costs.

[0152] Referring to FIGS. 15-16, FIG. 15 is a structural schematic diagram of a third embodiment of the chip packaging structure of the present application, and FIG. 16 is a top structural schematic diagram of the medium layer in the third embodiment of the chip packaging structure of the present application.

[0153] As shown in FIGS. 15-16, in one possible implementation, the chip packaging structure 400 can also not be provided with the redistribution layer 45, and the chip 43 and the waveguide structure 44 can also be directly coupled through the waveguide cavity. Specifically, each waveguide structure 44 is stacked with the chip 43 in the first direction X and is located at the side of the chip 43 close to the packaging substrate 6. Alternatively, each waveguide structure 44 is disposed on the front surface 43a of the chip 43. Each waveguide structure includes a cavity 444 for directly coupling with the chip 43 through the cavity 444. For example, the chip 43 can be internally provided with a waveguide structure for receiving signals from the waveguide structure 44 or transmitting signals to the waveguide structure 44, which is not limited in the present application.

[0154] As shown in FIGS. 15-16, in one possible implementation, each waveguide structure 44 includes a plurality of metal structures 443 arranged in a ring shape, and the plurality of metal structures surround the cavity 444 of the waveguide structure. Alternatively, the waveguide structure 44 is composed of the plurality of metal structures 443 and the cavity 444 surrounded thereby, and the metal structures 443 form a shielding cavity so that signals are concentrated in the cavity 444 for transmission. The specific form of the metal structure 443 is not limited, for example, it can be a metal column or the like. In one possible implementation, the waveguide structure 44 is disposed on the medium layer 5, and part of the solder joints 46 are reused as the metal structures 443. Specifically, the solder joints 46 near the inner wall surface of each first cavity 51 can be used as the metal structures 443. The part of the solder joints 46 can be located inside the first cavity 51, for example, as shown in FIGS. 15-16, or can be located outside the first cavity 51 and wrapped in the medium layer 5, which is not limited in the present application.

[0155] Obviously, those skilled in the art can make various modifications and variations to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application belong to the scope of the claims of the present application and their equivalent technologies, the present application also intends to include these modifications and variations.

Claims

1. A chip package structure, characterized by, The chip package structure comprises: a packaging substrate; a package body, which is arranged in a first direction in a stack with the packaging substrate, the first direction being parallel to a thickness direction of the chip package structure; a chip, which is packaged in the package body and is electrically connected to the packaging substrate through a plurality of solder joints; at least one waveguide structure, each of which is coupled to the chip; a dielectric layer, which is filled between the package body and the packaging substrate, and the plurality of solder joints are wrapped in the dielectric layer, the dielectric layer is provided with a first cavity at a position corresponding to each waveguide structure, and the first cavity penetrates the dielectric layer in the first direction.

2. The chip package structure of claim 1, wherein, The dielectric layer is embedded with a ring-shaped wall at a position corresponding to each first cavity, the wall penetrates the dielectric layer in the first direction, and itself surrounds the first cavity.

3. The chip package structure of claim 2, wherein, The wall is a dam glue structure.

4. The chip package structure of claim 3, wherein, The material of the dam glue structure is any one of epoxy resin glue, acrylate resin glue, silicone resin glue, and polyurethane resin.

5. The chip package structure of any one of claims 1-4, wherein, The dielectric layer is a bottom filling glue layer.

6. The chip package structure of claim 1, wherein, The dielectric layer is a non-conductive glue film.

7. The chip package structure of any one of claims 1-6, wherein, The chip package structure further comprises a re-wiring layer, one end of the re-wiring layer is electrically connected to the front surface of the chip and the at least one waveguide structure along the first direction, the other end is welded to the plurality of solder joints, and the re-wiring layer is welded and electrically connected to the packaging substrate through the plurality of solder joints.

8. The chip package structure of claim 7, wherein, The inner wall surface of the first cavity is a metal surface.

9. The chip package structure of claim 7 or 8, wherein, The projection of the first cavity on the package body in the first direction does not overlap with the metal structure in the re-wiring layer.

10. The chip package structure of any one of claims 7-9, wherein, The package body comprises a first sub-package body and a second sub-package body, the second sub-package body is arranged between the first sub-package body and the dielectric layer in the first direction; The chip and the at least one waveguide structure are packaged in the first sub-package body, the re-wiring layer is packaged in the second sub-package body, and the other end of the re-wiring layer is exposed to the surface of the second sub-package body away from the first sub-package body.

11. The chip package structure of any one of claims 1-10, wherein, The packaging substrate is provided with a second cavity at a position corresponding to each first cavity, the second cavity penetrates the packaging substrate in the first direction and communicates with the corresponding first cavity.

12. The chip package structure of claim 11, wherein, The inner wall surface of the second cavity is a metal surface.

13. The chip package structure of any one of claims 1-12, wherein, The at least one waveguide structure comprises a first waveguide structure and a second waveguide structure, when the chip package structure further comprises a re-wiring layer, the chip is electrically connected to the first waveguide structure and the second waveguide structure through the re-wiring layer respectively.

14. The chip package structure of any one of claims 1-13, wherein, The chip is a radio frequency chip, and the waveguide structure is a waveguide transmission structure or a filter.

15. An integrated circuit comprising a circuit board, characterized in that The chip package structure further comprises a circuit board, which is arranged on the side of the packaging substrate away from the package body in the first direction and is electrically connected to the packaging substrate.

16. The integrated circuit of claim 15, wherein, When the packaging substrate is provided with a second cavity, the circuit board is provided with a third cavity at a position corresponding to the second cavity, the third cavity penetrates the circuit board in the first direction and communicates with the corresponding second cavity.

17. The integrated circuit of claim 16, wherein, Inner wall surface of the third cavity is metal surface.

18. A transceiving system characterized by, The transceiver system further comprises a feed structure layer, the feed structure layer is arranged between the circuit board and the antenna, the feed structure layer has a feed structure, one end of the feed structure is coupled with the third cavity of the circuit board, and the other end of the feed structure is coupled with the antenna. The transceiver system further comprises a feed structure layer, the feed structure layer is arranged between the circuit board and the antenna, the feed structure layer has a feed structure, one end of the feed structure is coupled with the third cavity of the circuit board, and the other end of the feed structure is coupled with the antenna.

19. An electronic device, comprising: The transceiver system further comprises a feed structure layer, the feed structure layer is arranged between the circuit board and the antenna, the feed structure layer has a feed structure, one end of the feed structure is coupled with the third cavity of the circuit board, and the other end of the feed structure is coupled with the antenna.

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