Chiplet architecture for a technical system

Abstract

The invention relates to a chiplet architecture (2) for a technical system (1), comprising the following chiplets (3): - a system management controller (4) of the technical system (1), - an artificial intelligence hardware accelerator (5) for applications, - a central processing unit (6) for applications of the technical system (1), - an internal graphical processing unit (7), and - a working memory (8).

Description

[0001] R.415219

[0002] - 1 -

[0003] Description

[0004] title

[0005] Chiplet architecture for a technical system

[0006] The invention relates to a chiplet architecture for a technical system.

[0007] State of the art

[0008] Today's ECU architecture is characterized by one or more computing devices connected via Ethernet, PCIe, or other high-speed interfaces. This ECU architecture is increasingly reaching its limits in terms of performance, complexity, multi-domain integration, modularity, scalability, and future-proofing.

[0009] Increasing integration leads to so-called chiplet or multi-chip architectures, which integrate multiple dies (chips) on a single interposer or substrate. The method or architecture used to improve the aforementioned aspects requires optimization that considers a multitude of criteria.

[0010] Disclosure of the invention

[0011] The invention relates to a chiplet architecture with the features of claim 1. Further features and details of the invention will become apparent from the respective dependent claims, the description and the drawings.

[0012] The invention relates in particular to a chiplet architecture for a technical system, for example a vehicle, comprising the following chiplets: R.415219

[0013] - 2 - a control unit for system management of the technical system (English: "System Management Controller"), a hardware accelerator for applications using artificial intelligence (English: "Artificial Intelligence Hardware Accelerator"), a central processing unit for applications of the technical system (English: "Application Central Processing Unit"), an internal graphic processing unit (English: "Graphical Processing Unit"), and a main memory, wherein it may be provided that the main memory is not implemented as a chiplet.

[0014] In other words, the invention describes a specific chiplet architecture for technical systems such as vehicles, which covers specific tasks through specialized chiplets. Within the scope of the present invention, the chiplet architecture can also be referred to and understood as a multi-chip architecture. The chiplet architecture can be intended for use in a central, highly integrated control unit of the technical system or vehicle. The modular structure can advantageously provide reduced system complexity and independent scalability through the cascading of multiple chiplet architectures. The chiplet architecture according to the invention can thus better meet the requirements of various and future technical systems, particularly vehicle types. The chiplet architecture according to the invention can also advantageously simplify the software structure.The individual chiplets can be interconnected via interfaces, in particular die-to-die interfaces, preferably high-speed die-to-die interfaces. Die-to-die interfaces refer specifically to direct communication or connection between two semiconductor chips (or "dies") within a single package or on a common substrate. The control unit for system management preferably encapsulates specific components, such as sensor and system interfaces (e.g., for video processing, audio, PHYs, etc.) or safety cores (RISC-based) for ASIL-D applications. Additionally, system management and basic functions of a SoC, as well as an interconnect fabric enabling communication between the various chiplets on the substrate, can be integrated here. R.415219.

[0015] - 3 -

[0016] Another advantage is that the chiplet architecture can also include an interface for a power management integrated circuit (PMIC). This allows for the optimization of the chiplet architecture's power supply and management. In particular, the integration of a dedicated PMIC interface enables efficient management of energy flows within the chiplet architecture, which can lead to lower energy consumption and the achievement of high safety standards.

[0017] It is also advantageous if the chiplet architecture includes an interface for an external graphics processor. This allows graphics performance to be increased by a dedicated external graphics processor if needed, for example, to ensure the necessary flexibility for future requirements.

[0018] Another possibility is to implement a cascaded chiplet architecture, with at least two chiplet architectures interconnected via an interface, particularly a die-to-die interface. This can offer the advantage of modular performance expansion. Cascading multiple chiplet architectures allows resources and computing power to be pooled, enabling the execution of more complex tasks and increasing overall performance.

[0019] According to a further advantage, the control unit for system management can be provided to include at least one of the following components: at least one sensor interface, in particular at least one video, radar, and / or LiDAR sensor interface, preferably also including a corresponding component for processing acquired sensor data, at least one component for environmental interpretation, real-time cores in lockstep mode, at least one interface for at least one measurement application, a mirroring and / or at least one debug and / or replay application, R.415219

[0020] - 4 - a Network on Chip component, a Multi-Protocol Switch, for example for protocols such as LIN, CAN, Ethernet and / or PCIe.

[0021] This allows the control unit for system management to encapsulate specific functional components for a particular application area of ​​the technical system, especially the vehicle, while simultaneously providing basic functionality. Real-time cores in lockstep mode specifically refer to an operating mode in which two or more processors (or processor cores) operate synchronously and execute the same instructions with a one-clock-delay time difference. This can be used in safety-critical applications to increase diagnostic coverage. If one real-time core makes a mistake, comparison with another real-time core can detect this by identifying the faulty operation and triggering an appropriate response, such as shutting down the technical system or switching to a safe state.A Network-on-Chip (NoC) is, in particular, a special communication architecture that can be used within a System-on-Chip (SoC) to efficiently connect different components, such as processors, memory, and other peripheral devices.

[0022] Instead of relying on conventional bus or point-to-point connections, which reach their limits as chip complexity increases, one or more NoCs utilize a network-like communication scheme that transfers many of the advantages of classic computer networks to a single chip. This network-on-chip component is preferably designed to address bandwidth, latency, and security aspects, including the separation (firewalls) of different software workloads.

[0023] In this way, the control unit for system management in a vehicle can be used for comprehensive functions related to sensor integration, data processing, and control of critical vehicle functions. The integration of the sensor connected via at least one sensor interface enables, in particular, environmental perception, while the real-time cores can perform safety-relevant tasks with high precision. The integration of the network-on-chip component and the multi-protocol switch can be described in R.415219.

[0024] - 5 - ensure efficient communication within the chiplet architecture, which can lead to improved system performance and response time.

[0025] The encapsulation and centralization of system-relevant functionalities in the control unit for system management allows, in particular, a standardization of system behavior.

[0026] The interface for at least one measurement application, mirroring and / or at least one debug and / or replay application allows, for example, monitoring and optimization of data flows and rapid analysis of errors within the chiplet architecture.

[0027] Furthermore, the invention may provide that the chiplet architecture also includes interfaces, in particular die-to-die interfaces, for connecting chiplets to the control unit for system management and for cascading at least two control units for system management. This makes the chiplet architecture scalable and flexibly configurable. The optional interfaces allow for increasing the number of chiplets and connecting multiple control units for system management. This can lead to higher performance and improved management of complex technical systems.

[0028] Furthermore, it is conceivable that the control unit for system management also has a memory interface for connecting to the main memory. Therefore, the control unit for system management can directly retrieve data from the main memory and read it into its own area, which can lead to more efficient data exchange and shorter response times. The direct connection can enable faster processing of real-time data, which is important, for example, for tasks such as sensor analysis and the control of critical system / vehicle functions.

[0029] Furthermore, it may be provided that the control unit for system management includes the interface for the integrated circuit for power management, via which a power supply to the chiplets of the R.415219 can be controlled.

[0030] - 6 -

[0031] The chiplet architecture provides this capability. In other words, the system management control unit can control the power supply of individual chiplets within the architecture. This additional function allows for finer control of energy consumption, thereby optimizing the performance and efficiency of the entire chiplet architecture.

[0032] It is possible for the chiplet architecture according to the invention to be used in a vehicle. The vehicle can be, for example, a motor vehicle and / or passenger vehicle and / or autonomous vehicle. The vehicle can have vehicle equipment, for example, for providing an autonomous driving function and / or a driver assistance system in the various levels (L1, L2, L3, L4, L5). The vehicle equipment can be designed to control the vehicle at least partially automatically and / or accelerate and / or brake and / or steer.

[0033] Further advantages, features, and details of the invention will become apparent from the following description, in which exemplary embodiments of the invention are described in detail with reference to the drawings. The features mentioned in the claims and in the description can each be essential to the invention individually or in any combination. The drawings show:

[0034] Fig. 1 shows a schematic visualization of a technical system comprising a chiplet architecture according to exemplary embodiments of the invention.

[0035] Fig. 2 shows a schematic representation of a chiplet architecture according to exemplary embodiments of the invention,

[0036] Fig. 3 is a schematic representation of a cascaded chiplet architecture according to embodiments of the invention, R.415219

[0037] - 7 -

[0038] Fig. 4 shows a schematic representation of components of a control unit for management in a chiplet architecture according to exemplary embodiments of the invention.

[0039] In Fig. 1 a technical system 1 comprising a chiplet architecture 2 with several chiplets 3 according to exemplary embodiments of the invention is shown schematically.

[0040] Within the scope of the present invention, a concept is described that improves a chiplet architecture 2 with regard to performance, complexity, multi-domain integration, modularity, scalability and / or future-proofing.

[0041] The invention is described below according to exemplary embodiments with reference to Figures 2 to 4. Figure 2 shows a schematic representation of a chiplet architecture 2 according to exemplary embodiments of the invention. Figure 3 shows a schematic representation of a cascaded chiplet architecture 2 according to exemplary embodiments of the invention. Figure 4 shows a schematic representation of components of a control unit for a management system 4 in a chiplet architecture 2 according to exemplary embodiments of the invention.

[0042] A chiplet architecture 2 for a technical system 1, i.e., in particular an Automotive Chiplet Architecture (ACS), according to embodiments of the invention preferably comprises a control unit 4 for system management of the technical system 1 (English: "System Management Controller"), a hardware accelerator for applications using artificial intelligence 5 (English: "Artificial Intelligence Hardware Accelerator"), a central processing unit 6 for applications of the technical system 1 (English: "Application Central Processing Unit"), an internal graphic processing unit (English: "Graphical Processing Unit") 7, and a main memory 8, which is preferably connected via a special interface 27 C, Memory l / F").

[0043] The individual chiplets can each be interconnected via an interface 26, in particular a die-to-die interface. Optionally, the hardware accelerator is intended for applications under R.415219.

[0044] - 8 -

[0045] The use of artificial intelligence 5 has its own interface 29 to a private working memory 29a for the execution of memory-intensive acceleration procedures.

[0046] As additional circuitry, the chiplet architecture 2 requires, in particular, PMICs 9a for power or voltage supply. A PMIC (Power Management Integrated Circuit) 9a is, in particular, an integrated circuit for power management according to the present invention. For this purpose, the chiplet architecture 2 can have a corresponding interface 9.

[0047] Additionally, an interface 11 can be provided for the internal graphics processing unit 7 and / or further for an external graphics processing unit (GPU) 11a to increase performance for graphics-intensive applications, e.g. gaming.

[0048] To enable high scalability, the chiplet architecture 2 can be cascaded, in particular by connecting at least two chiplet architectures 2 via an interface 26, in particular a die-to-die interface.

[0049] The control unit for system management 4 of the chiplet architecture 2 comprises, according to exemplary embodiments, the following components: at least one sensor interface 13, including a multi-protocol switch, for example for protocols such as LIN, CAN, Ethernet and / or PCIe, and a corresponding component for processing the acquired sensor data (13a, 14, 15), including a component for environmental interpretation 14, and real-time cores 16 in lockstep mode 16 and high-performance application cores in lockstep mode 30. Furthermore, the control unit for system management 4 can include a controller for an operating mode (not shown), whereby power sequencing can be performed.Furthermore, interfaces (not shown) can be provided for at least one measurement application (data acquisition), mirroring (data forwarding from external sources), and at least one debugging application. Preferably, a Network on Chip (NoC) component 19 is also provided. A Network on Chip R.415219.

[0050] - 9 -

[0051] Component 19 is, in particular, a network-based communication subsystem on an integrated circuit, for example, between modules in a system on a chip. Furthermore, according to exemplary embodiments, die-to-die interfaces 26 are provided for connecting all chiplets to the control unit for system management 4 and for cascading

[0052] Control units for system management 4 are provided. A memory interface 27 can be provided for connecting the main memory 8. Furthermore, a voltage control interface 9 can be provided, via which the necessary power supply to all chiplets 3 can be controlled. The chiplet architecture 2 can also be configured to allow security and safety measures 28 to be implemented in order to achieve ISO 26262 compliance according to ASIL A to D. The preceding explanation of the embodiments describes the present invention exclusively by way of examples. Of course, individual features of the embodiments can be freely combined with one another, provided this is technically feasible, without departing from the scope of the present invention.

Claims

R.415219 - 10 - Claims 1. Chiplet architecture (2) for a technical system (1), comprising the following chiplets (3): a control unit (4) for system management of the technical system (1), a hardware accelerator for applications using artificial intelligence (5), a central processing unit (6) for applications of the technical system (1), an internal graphics processing unit (7), and a main memory (8).

2. Chiplet architecture (2) according to claim 1 , characterized in that the chiplet architecture (2) further comprises an interface for an integrated circuit for power management (9).

3. Chiplet architecture (2) according to one of the preceding claims, characterized in that the chiplet architecture (2) further comprises an interface for an external graphics processor (11).

4. Chiplet architecture (2) according to one of the preceding claims, characterized in that the chiplet architecture (2) is cascaded, wherein at least two chiplet architectures (2) are connected to each other via an interface (26), in particular a die-to-die interface (26). R.415219 - 11 - 5. Chiplet architecture (2) according to one of the preceding claims, characterized in that the control unit for system management (4) comprises at least one of the following components: at least one sensor interface (13), at least one component for an environment interpretation (14), Real-time cores (16) in lockstep mode, at least one interface (18a, 18b, 18c) for at least one measurement application, a mirroring and / or at least one debug and / or replay application, a network on chip component (19), a multi-protocol switch (21).

6. Chiplet architecture (2) according to one of the preceding claims, characterized in that the chiplet architecture (2) further comprises interfaces (26), in particular die-to-die interfaces (26), for connecting chiplets (3) to the control unit for system management (4) and for cascading at least two control units for system management (4). R.415219 - 12 - 7. Chiplet architecture (2) according to one of the preceding claims, characterized in that the control unit for system management (4) further comprises a memory interface (27) for connecting the main memory (8).

8. Chiplet architecture (2) according to any one of the preceding claims 2 to 7, characterized in that the control unit for system management (4) comprises the interface for the integrated circuit for power management (9) via which control of a power supply of the chiplets (3) of the chiplet architecture (2) is provided.

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