Process and apparatus for depositing a capping layer on metal pads

Abstract

A method includes, performing, by a chemical mechanical polishing (CMP) processing system, a CMP process on patterned device structures comprising an interconnect material disposed over a dielectric layer disposed over a substrate. The dielectric layer includes interconnect structures etched therein, wherein the interconnect material fills the interconnect structures, and is disposed over the interconnect structures and a field region of the dielectric layer. The CMP process removes portions of the interconnect material disposed on the field region of the dielectric layer and exposes pads within the interconnect structures of the patterned device structures. The method further includes depositing a capping layer using a capping layer deposition process over the exposed pads of the patterned device structures.

Description

PATENTAttorney Docket No.: 44024932 WO01PROCESS AND APPARATUS FOR DEPOSITING A CAPPING LAYER ON METAL PADSBACKGROUNDField

[0001] Embodiments of the present invention generally relate to a system and method for processing substrates, in particular, forming a forming a capping layer on pads to prevent oxidation during bonding.Description of the Related Art

[0002] Substrate processing units may perform chemical mechanical polishing (CMP), which is commonly used in the manufacturing of high-density integrated circuits to planarize or polish a layer of material deposited on a substrate. In a typical CMP process, a substrate is retained in a carrier head that presses the backside of the substrate towards a rotating polishing pad in the presence of a polishing fluid. Material is removed across the material layer surface of the substrate in contact with the polishing pad through a combination of chemical and mechanical activity which is provided by the polishing fluid and a relative motion of the substrate and the polishing pad. Typically, after one or more CMP processes are completed, a polished substrate is further processed by use of one or more post-CMP substrate processing operations in a CMP processing system. For example, the polished substrate may be further processed using one or more cleaning operations in a cleaning unit. Various cleaning operations may be performed in a cleaning unit having multiple cleaning stations, i.e., cleaning chambers. Once the post-CMP operations are complete, the substrate can be removed from a CMP processing system and then delivered to the next device manufacturing system, such as a lithography, etch, or deposition system.

[0003] After the CMP process, the polished substrate is bonded to a corresponding substrate. In one or more types of bonding, metal pads formed in interconnect structures of correspond substrates are aligned. However due to the CMP process there is dishing present on the metal pads. Therefore, after the substrates are bonding a post-bonding anneal process is performed to cause the pads to expand, contact, and then diffuse into one another. However, certain devices, such as memory devices,PATENTAttorney Docket No.: 44024932 WO01 have a limited thermal budget. Therefore, there is a need in the art to reduce the temperature required for post-bond annealing.SUMMARY

[0004] According to one or more embodiments a method includes, performing, by a chemical mechanical polishing (CMP) processing system, a CMP process on patterned device structures comprising an interconnect material disposed over a dielectric layer disposed over a substrate, the dielectric layer including interconnect structures etched therein, wherein the interconnect material fills the interconnect structures, and is disposed over the interconnect structures and a field region of the dielectric layer, the CMP process removing portions of the interconnect material disposed on the field region of the dielectric layer and exposing pads within the interconnect structures of the patterned device structures, and depositing a capping layer using a capping layer deposition process over the exposed pads of the patterned device structures.

[0005] According to one or more embodiments a chemical mechanical polishing (CMP) processing system includes, a polishing module, a capping layer deposition module, and a controller configured to cause the polishing module to configured to perform a CMP process on patterned device structures formed on a substrate, the CMP process removing portions of an interconnect material disposed on a field region of a dielectric layer formed over the substrate and exposing pads within interconnect structures of the patterned device structures etched into the dielectric layer, and the capping layer deposition module to deposit a capping layer on the exposed pads of the patterned device structures using a capping layer deposition process.

[0006] According to one or more embodiments, a chemical mechanical polishing (CMP) processing system includes a cleaning module configured to perform at least one pre-treatment process on patterned device structures formed on a substrate, a polishing module configured to perform a CMP process on the patterned device structures formed on the substrate, the CMP process removing portions of an interconnect material disposed on a field region of a dielectric layer formed over the substrate and exposing pads within interconnect structures of the patterned device structures etched into the dielectric layer, and a capping layer deposition module, thePATENTAttorney Docket No.: 44024932 WO01 capping layer deposition module configured to deposit a capping layer on the exposed pads of the patterned device structuresBRIEF DESCRIPTION OF THE DRAWINGS

[0007] So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only exemplary embodiments of the disclosure and are therefore not to be considered limiting of its scope, as the disclosure may admit to other equally effective embodiments.

[0008] Figures 1A-1 E illustrate schematic diagrams of a packaged device during bonding according to one or more embodiments.

[0009] Figure 2 illustrates operations for a method for hybrid bonding according to one or more embodiments.

[0010] Figure 3 is a schematic top view of an exemplary chemical mechanical polishing (CMP) processing system 300 described herein, according to one or more embodiments.

[0011] Figure 4 illustrates an example of a substrate processing sequence that can be performed in the CMP processing system of Figure 4, according to one or more embodiments.

[0012] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.DETAILED DESCRIPTION

[0013] Chemical mechanical polishing (CMP) is a process that is used multiple times in the semiconductor manufacturing process. In most instances, CMP is used to planarize a layer of a semiconductor device and create a smooth surface. In onePATENTAttorney Docket No.: 44024932 WO01 example, CMP is used during bonding between heterogeneous or homogenous dies. For example, during a hybrid bonding process a die may include a dielectric layer formed over a substrate. The substrate may also include multiple layers of dielectric materials and metal wiring known as back-end-of-the line (BEOL) layers. In one example, a dielectric layer can be the last layer of BEOL, or an additional layer deposited specifically for hybrid bonding. Interconnect structures can be etched and arranged into the dielectric layer and form bonding surfaces between the interconnect structures. The bonding surfaces are positioned so that interconnect structures of opposing dies can be mated to one other.

[0014] In one or more examples, the etched interconnect structures are filled with a conductive material such that the opposing interconnect structures of opposing dies can be mated and form interconnects. The conductive material is deposited over the dielectric layer, fills the interconnect structures, and covers the dielectric layer. Then a CMP process is performed to remove a portion of the conductive material from bonding surfaces to re-expose them and form / expose electrically conductive pads (herein described as “pads”) in the interconnect structures. After the CMP process, the substrate undergoes cleaning and other bonding processes. To cause the pads to mate, a post-bond annealing process is used to cause the conductive material on each die to expand, contact, and diffuse into one another. However, due to limited thermal budgets of memory devices, current post-bonding annealing processes are performed at too high of a temperature. Typical post bonding annealing temperatures are from about 350°C to about 400°C. Embodiments described herein disclose a process and apparatus for depositing a capping layer on the pads to reduce the temperature required for post-bond annealing.

[0015] Figures 1A-1 E illustrate schematic diagrams of a packaged device during bonding according to one or more embodiments. Figure 2 illustrates operations for a method 200 for hybrid bonding according to one or more embodiments.

[0016] At operation 202, an interconnect material is deposited over patterned device structures. For example, as shown in Figure 1A, a patterned device structure 100A includes a dielectric layer 101 formed over a die 105. In one or more examples, the patterned device structure 100A is one of numerous patterned device structuresPATENTAttorney Docket No.: 44024932 WO01(dies or chips) formed across a base substrate (i.e., “a substrate”). In one example, the numerous patterned device structures (also referred to as “dies”) are formed across the substrate in a grid-like fashion. In one example, the operations described herein are performed on each patterned device structure formed on the substrate. The substrate includes multiple layers of metal wiring in insulating dielectrics that are commonly referred to as the Back-End-of-Line (BEOL) layers. The dielectric layer 101 may comprise an inorganic dielectric material layer such as oxide, nitride, oxynitride, oxycarbide, carbides, carbonitrides, diamond, diamond like materials, glasses, ceramics, glass-ceramics, and the like. In one or more examples, the dielectric layer 101 is a layer deposited specifically for hybrid bonding and / or is the last of the BEOL layers.

[0017] In one example, interconnect structures 102 are embedded (i.e., are etched) in the dielectric layer 101. In one example, the interconnect structures 102 are positioned such that the interconnect structures 102 can be mated during bonding to form continuous conductive interconnects. The interconnect structures 102 may be formed using any suitable etching process such as a damascene etching process.

[0018] As noted above, an interconnect material 103 is deposited over the patterned device structure 100A. In one example, the interconnect material 103 covers the dielectric layer 101 and fills the interconnect structures 102. In one or more examples, the interconnect material 103 is a conductive material. The interconnect material 103 may comprise any suitable conductive material such as copper (Cu). In one example, the interconnect material 103 is a copper barrier seed layer (CuBS).

[0019] At operation 204, a chemical mechanical polishing (CMP) process is performed on each of the patterned device structures. For example, as shown in Figure 1B, the patterned device structure 100A undergoes a CMP process. In one or more examples, the CMP process is performed on the interconnect material 103. The CMP process removes the interconnect material 103 from a field region 107 (i.e., the unetched portions) of the dielectric layer 101 , leaving interconnect regions such as pads 109 formed within interconnect structures 102.PATENTAttorney Docket No.: 44024932 WO01

[0020] Performing the CMP process includes finishing the field region 107 of the dielectric layer 101 to meet dielectric roughness specifications. As shown in Figure 1 B, the CMP process removes the portions of the interconnect material 103 formed on the field region 107 of the dielectric layer 101 and exposes pads 109 in the interconnect structures 102. The pads 109 are configured to bond with corresponding pads of corresponding patterned interconnect structures formed on the same substrate or a different substrate to form bonded interconnect structures. The pads 109 are exposed through openings etched in the dielectric layer 101. In one example, the CMP process is performed in a CMP processing system (Figures 3-4). In one or more embodiments, the CMP process is used for dishing control onto the pads 109. In one or more embodiments, the CMP process is configured to include from about 3 nm of dishing to about 1 nm of protrusion. In one or more embodiments, the CMP process is performed until the pads 109 include a desired amount of protrusion. The desired amount of protrusion may be from about 0 to about 1 nm. In another embodiment, the CMP process is performed until the pads 109 include a desired amount of dishing. The desired amount of dishing may be from about -3 nm to about 0 nm.

[0021] At operation 206, at least one pretreatment process is performed on the patterned device structures (e.g., patterned device structure 100A). In one example, the at least one pretreatment process includes a cleaning process performed in the CMP processing system. Thus, in one example, the CMP process and cleaning process are performed in a same CMP processing system.

[0022] After the CMP processes, the substrate, and therefore, the patterned device structure 100A, is removed from the CMP processing tool and is stored and / or moved to a subsequent tool to undergo additional processing. When the patterned device structure 100A is transported between tools (or stored), the patterned device structure 100A is exposed to atmosphere. The exposure to atmosphere, problematically, as shown in Figure 1B, may cause an oxidation layer 111 to form on a top surface of the pads 109. The oxidation layer 111 may be removed by performing at least one pretreatment process. In one or more embodiments, operation 206 is optional.PATENTAttorney Docket No.: 44024932 WO01

[0023] At operation 208, a capping layer deposition process is performed on the patterned device structures. In one example, a capping layer 112 is selectively deposited over the exposed surface of the pads 109. For example, as illustrated in Figure 1C, a capping layer 112 is deposited over a top surface of the pads 109. In one or more examples, the capping layer 112 comprises a metal including, but not limited to silver, gold, platinum, titanium, or the like. In one or more embodiments, the capping layer 112 is deposited using an electro-less deposition process (e-less plating). In one or more embodiments, the capping layer 112 is deposited in the CMP processing tool. For example, the CMP process, one or more pretreatment processes, and the capping layer deposition process are performed in the same CMP processing system. Stated differently, the CMP process, the cleaning process, and the capping layer deposition all occur within the same tool. In other embodiments, the capping layer 112 is deposited in a separate dedicated tool. In embodiments in which the capping layer 112 is deposited within the CMP processing tool, the one or more pretreatment processes is optional.

[0024] In one or more embodiments, the capping layer deposition process includes spraying or rinsing the patterned device structure 100A with de-ionized (DI) water for a first duration of time ranging from about 0 to about 100 seconds. After spraying or rinsing the patterned device structure with DI water, a citric acid deoxidization process is performed on the patterned device structure 100A. In one or more embodiments, the citric acid deoxidization process includes exposing the patterned device structure 100A (e.g., a bath or a rinse) to a citric acid containing chemistry for a second duration of time. The second duration of time is from about 0 to about 300 seconds. In one or more embodiments, the patterned device structure 100A in citric acid chemistry includes a concentration of citric acid between about 0.1 to about 5 g / L, for example, 1g / L. After the citric acid deoxidation process, an immersion rinse is performed on the patterned device structure 100A. In one or more embodiments, the immersion rinse includes rinsing the patterned device structure 100A using DI water for a third duration of time from about 0 to about 100 seconds. Then a plating process is performed on the patterned device structure 100A. In one or more embodiments, the plating processes involves depositing the capping layer 112 onto the pads 109. In one or more embodiments, the plating process is an electro-less plating process. In one orPATENTAttorney Docket No.: 44024932 WO01 more embodiments, the electro-less (e-less) plating process involves exposing the patterning device structure to an electro-less plating solution including, but not limited, to silver sulfamate, silver cyanide, silver nitrate, and combinations thereof, for a fourth duration of time from about 0.1 to about 500 seconds, and then rinsing the patterned device structure 100A. In one or more embodiments, the e-less plating process is performed at a temperature from about 20° to about 50°C, for example from about 25° to about 35°C. The plating process is performed until the capping layer 112 has a desired thickness from about 0.1 to about 30 nm, for example from about 1 to about 15 nm. After the plating process, the patterned device structure 100A undergoes a spin, rinse, and dry (SRD) process performed on the patterned device structure 100A for a fifth duration of time from about 0 to about 600 seconds.

[0025] At operation 210, as shown in Figure 1 D corresponding the patterned device structures are bonded to each other. In one or more embodiments, patterned device structure 100A is bonded to a patterned device structure 100B (i.e., source and target dies) that are identical to each other. In one example, bonding corresponding patterned device structures includes, but is not limited to, loading the substrate into dedicated bonding tool. In one example the dedicated bonding tool, aligns the patterned device structures (i.e., the dies), cleans the patterned device structures, performs a degassing process on the patterned device structures, performs a plasma activation process on the patterned device structures, treats the patterned device structures with ultraviolet (UV) light, and bonds the source and target patterned device structures to one another. Although Figure 1 D illustrates a single die stack (i.e., one patterned device structure stacked on top of another), this is for exemplary purposes only, as multiple die stacks may be formed.

[0026] In one example, in the plasma activation process, each of the patterned device structures is exposed to a plasma which bombards the surface of each patterned device structure (e.g., patterned device structure 100A and 100B). The interaction between the plasma and the surface of the patterned device structures exposes the pads 109, and creates reactive sites that increase surface energy and wettability, promoting better adhesion and bonding quality in the hybrid bonding process. For example as illustrated in Figure 1 D, the patterned device structure 100APATENTAttorney Docket No.: 44024932 WO01 is flipped, aligned, and then bonded to the patterned device structure 100B. The patterned device structures are bonded in a manner such that the capping layer 112 formed on the pads 109 and the field region 107 (i.e., the unetched regions) of the dielectric layer 101 are aligned with one another.

[0027] At operation 212, a post-bonding annealing process is performed on the bonded patterned device structure (i.e., patterned device structure 100A bonded to patterned device structure 100B). In one or more embodiments, the post-bonding annealing process causes the pads 109 of the opposing patterned device structures to undergo thermal expansion, contact one another, and then diffuse into one another. As illustrated in Figure 1 E, the device structures 100A and 100B are exposed to heat for a sixth duration of time from about 1 to about 600 minutes. The annealing processes causes thermal expansion of the pads 109, which causes the opposing pads 109 to contact, which then causes the metal diffusion of the opposing pads of the aligned patterned device structures 100A and 100B. Advantageously, due to the capping layer 112, the annealing temperature is from about 180°C to about 250°C, such as less than 200°C. The capping layer 112 allows for a lower anneal temperature than typical post-bond annealing processes which is from about 350°C to about 400°C. The lower anneal temperature reduces the thermal budget of the post-bond annealing process and reduces stress build up during the post-bond annealing, especially for memory devices with a lower thermal budget or devices that include multi-die stacking which may include multiple bonding and post-bonding annealing processes. Furthermore, by performing the capping layer deposition process and the CMP process prevents a delay between the CMP process and the capping layer deposition process. Preventing a delay between the CMP and the capping layer deposition process which avoids a potential oxidization from forming on the surface of the pads 109 prior to the capping layer deposition process.

[0028] Figure 3 is a schematic top view of an exemplary chemical mechanical polishing (CMP) processing system 300 described herein, according to one or more embodiments. In one or more embodiments, the CMP processing system 300 is used to perform the CMP process, the at least one pre-treatment process and the capping layer deposition (i.e., operations 204-208) of method 200 described in Figures 1A-1CPATENTAttorney Docket No.: 44024932 WO01 and FIG. 2. While the disclosure provided herein primarily discusses various embodiments that can be used in conjunction with a CMP processing system 300, this configuration is not intended to be limiting as to the scope of the disclosure provided herein.

[0029] In the figures, certain parts of the housing and certain other internal and external components are omitted to more clearly show aspects of the CMP processing system 300. Here, the CMP processing system 300 is connected to a factory interface 302. The factory interface 302 may include one or more loading stations 302A. The loading stations 302A may be, for example, front opening unified pods (FOUPs) or cassettes. Each loading station 302A may include one or more substrates for CMP processing in the CMP processing system 300.

[0030] The CMP processing system 300 may include a polishing module 325, a first substrate handler 303 of the factory interface 302 and a cleaning system 306 that includes a second substrate handler 304. The first substrate handler 303 is positioned to transfer a substrate to and from one or more of the loading stations 302A. For example, the first substrate handler 303 transfers a substrate from a loading station 302A to the cleaning system 306, where the substrate can be picked up by the second substrate handler 304.

[0031] The CMP processing system 300 may include a capping layer deposition module 310. For the reasons described above, the capping layer deposition module 310 is configured to deposit the capping layer 112 over exposed pads 109 on the substrate. In one example, the capping layer deposition module 310 deposits the capping layer using an e-less plating or any other suitable deposition process. For example, the capping layer 112 is deposited over the exposed pads 109 of the patterned device structure 100A (and the patterned device structure 100B) allowing for a lower temperature during post-bond annealing. Therefore, the first substrate handler 303 transfers a substrate from the cleaning system 306, to the capping layer deposition module 310, and then transfers the substrate to the loading station 302A.

[0032] Generally, a substrate that is initially positioned in a loading station 302A has been subject to a prior manufacturing process or processes — such as, forPATENTAttorney Docket No.: 44024932 WO01 example, watering, lithography, etching, and / or deposition processes — on a processing surface thereof. The first substrate handler 303 transfers the substrate to and from the loading station 302A with the processing surface facing up.

[0033] The second substrate handler 304 may be, for example, a cleaner wet robot. The second substrate handler 304 is positioned to transfer a substrate to and from the polishing module 325 with the processing surface facing in an up or down orientation. For example, the second substrate handler 304 receives a substrate from the first substrate handler 303 and then transfers the substrate to a transfer station 326 within the polishing module 325.

[0034] As another example, the second substrate handler 304 retrieves a substrate from the transfer station 326 within the polishing module 325 and then transfers the substrate to a first cleaning chamber that comprises a first cleaning module 307 in the cleaning system 306. In some embodiments, the second substrate handler 304 transfers the substrate to a sulfuric peroxide mixture (SPM) module 128 that may be included in the cleaning system 306. In some embodiments, the second substrate handler 304 can include a substrate flipping capability (e.g., rotating blade wrist assembly) that allows the orientation of a substrate to be flipped from a polished surface of a substrate facing up to the polished surface of the substrate facing down orientation, or vice versa. This ability to flip the substrate during a cleaning process sequence can be useful to allow the cleaning processes performed in the cleaning system 306 to be performed on the front side of the substrate, backside of the substrate, or sequentially performed on both sides of the substrate.

[0035] The polishing module 325 is a substrate polishing system that may include a plurality of polishing stations. The polishing module 325 includes one or more polishing assemblies 318 that are used to polish a substrate received from the second substrate handler using one or more CMP processes. Typically, each of the one or more polishing assemblies 318 will include the use of a polishing platen and polishing head, which is configured to urge the substrate against a polishing pad disposed on the polishing platen. For example, the interconnect material 103 deposited over the dielectric layer 101 is urged against the polishing pad to expose the non-etched portions of the dielectric layer 101 and the pads 109 (Figures 1A-1 B). ResidualPATENTAttorney Docket No.: 44024932 WO01 abrasive particles and / or liquids such as acidic or basic chemicals may remain on the substrate after undergoing CMP processing in the polishing module 325. Accordingly, the cleaning system 306 is positioned between the polishing module 325 and the factory interface 302 in order to clean the substrate prior to returning the substrate to the loading station 302A.

[0036] As shown in Figure 3, the polishing module 325 comprises a transfer station 326, and one or more polishing stations 321. The transfer station 326 is disposed within the polishing module 325 and is configured to accept the substrate from the second substrate handler 304. The transfer station 326 transfers the substrate to a carrier head 324 of a polishing station 321 that retains the substrate during polishing.

[0037] The polishing stations 321 each include a rotatable disk-shaped platen on which a polishing pad 319 is situated. The platen is operable to rotate about an axis. The polishing pad 319 can be a two-layer polishing pad with an outer polishing layer and a softer backing layer. The polishing stations 321 each further includes a dispensing arm 322, to dispense a polishing liquid, e.g., an abrasive slurry, onto the polishing pad 319. In the abrasive slurry, the abrasive particles can be silicon oxide, but some polishing processes use cerium oxide abrasive particles. Each polishing station 321 can also include a conditioner head 323 to maintain the polishing pad 319 at a consistent surface roughness.

[0038] The polishing stations 321 each includes at least one carrier head 324. The carrier head 324 is operable to hold a substrate against the polishing pad 319 during polishing operation. Following a polishing operation performed on a substrate, the carrier head 324 transfers the substrate back to the transfer station 326.

[0039] The second substrate handler 304 then removes the substrate from the polishing module 325 through an opening connecting the polishing module 325 with the remainder of the CMP processing system 300. The second substrate handler 304 removes the substrate in a horizontal orientation from the polishing module 325 and transfers the substrate to the cleaning system 306.

[0040] In one or more examples, the polishing module 325 further includes a noncontact cleaning unit 340 that may employ methods like megasonic cleaning and / orPATENTAttorney Docket No.: 44024932 WO01 jet spray cleaning to eliminate particles and contaminants from the substrate surface. For example, the non-contact cleaning unit 340 may include megasonic cleaning, which utilizes high-frequency sound waves to create cavitation bubbles in the cleaning solution. The implosion of these bubbles generates shock waves that dislodge particles and contaminants from the substrate surface. Alternatively, the non-contact cleaning unit 340 may include spray cleaning, where high-pressure jets of cleaning solution are used to dislodge particles and contaminants. The non-contact cleaning unit 340 may be a single-arm spray cleaning module, employing a single spray arm moving back and forth across the substrate or a dual-arm spray cleaning module with two spray arms moving in opposite directions. Further, the non-contact cleaning unit 340 may be a rotating spray cleaning module that features a rotating spray head above the substrate, spraying cleaning solution from all angles. Additionally, the non-contact cleaning unit 340 may be an inline spray cleaning module integrated into the CMP process line, transporting the substrate on a conveyor belt and spraying it from multiple angles. Conversely, an off-line spray cleaning module operates independently, cleaning substrates outside the CMP process line, which may be loaded manually or with the second substrate handler 304.

[0041] As shown in Figure 3, the cleaning system 306 may be comprised of two cleaning units 306A, 306B disposed in parallel to one another on opposite sides of the second substrate handler 304. The cleaning units 306A, 306B include a plurality of cleaning chambers. The cleaning chambers positioned within the cleaning system 306 can be include one or more first cleaning modules, one or more second cleaning modules, one or more third cleaning modules, one or more fourth cleaning modules, one or more fifth cleaning modules, one or more sixth cleaning modules and / or one or more seventh cleaning modules, as discussed below.

[0042] As can be appreciated from Figure 3, and as described above, cleaning unit 306B is essentially a duplicate of the cleaning unit 306A. Accordingly, the description herein and the depiction of cleaning unit 306A in the Figures is to be understood inferentially as also a description and depiction of cleaning unit 306B. However, while the disclosure provided herein primarily illustrates and discloses a configuration where the cleaning unit 306A and the cleaning unit 306B are duplicates, this configuration isPATENTAttorney Docket No.: 44024932 WO01 not intended to be limiting as to the scope of the disclosure provided herein, since the cleaning units can include different types and / or different numbers of cleaning modules without deviating from the scope of the disclosure provided herein.

[0043] The cleaning units 306A, 306B may be separated by a robot tunnel in which the second substrate handler 304 is positioned. In some embodiments, each cleaning unit 306A, 306B includes a first cleaning module 307, a third substrate handler, a second cleaning module 309, an optional a third cleaning module (not shown), and a rinse and dry module 334. In some embodiments, the first cleaning module 307, while not intending to be limiting as to the scope of the disclosure provided herein is often referred to herein as the horizontal pre-clean module 307. However, as noted above, the first cleaning module 307 could be replaced by a vertical input station or a horizontal input station that are each generally configured to support a substrate in a desired physical orientation while assuring that the surfaces of the substrate remain wet prior to subsequent cleaning processes being performed thereon. In some embodiments, the second cleaning module 309, while not intending to be limiting as to the scope of the disclosure provided herein is often referred to herein as the vertical cleaning module 309. In some embodiments, the capping layer deposition module 310 may be included within each cleaning unit. For example, the capping layer deposition module 310 may be presented as a first capping layer deposition module 310A and a second capping layer deposition module 310B. In other embodiments, the capping layer deposition module 310 may be a stand-alone module within the CMP processing system 300. In some embodiments, the vertical cleaning module 309 may be provided as a first vertical cleaning module 309A and a second vertical cleaning module 309B. The first vertical cleaning module 309A and the second vertical cleaning module 309B may each include a door 309C. In one example, a third substrate handler may transfer the substrate to the first vertical cleaning module 309A and a second vertical cleaning module 309B via the door 309C.

[0044] The horizontal pre-clean module 307 is configured to process a substrate disposed in a substantially horizontal orientation, i.e., in the X-Y plane, with the processing surface facing up. In some embodiments, each cleaning unit 306A, 306B includes two vertical cleaning modules 309A, 309B configured to process a substratePATENTAttorney Docket No.: 44024932 WO01 disposed in a substantially vertical orientation, i.e., in the Z-Y plane, with the processing surface facing the factory interface 302.

[0045] As noted above, in some embodiments of the cleaning system 306, the horizontal pre-clean module 307 receives a substrate that has been polished from the second substrate handler 304 through a first door 307A formed in a first side panel of the horizontal pre-clean module 307. The first door 307A may be, for example, a slit valve that is configured to isolate an interior region of the horizontal pre-clean module 307 from the exterior region of the horizontal pre-clean module 307. The substrate is received in a horizontal orientation by the horizontal pre-clean module 307 for positioning on a horizontally disposed substrate support surface therein. The horizontal pre-clean module 307 then performs a pre-clean process, such as a buffing process, on the substrate before the substrate is transferred therefrom. In some embodiments, the buffing process will include sweeping a buffing pad across a surface of the substrate that is positioned on the horizontally disposed substrate support surface to remove leftover slurry, scratches and other imperfections found on the surface of the substrate. The buffing pad may include a material such as a polyurethane, acrylate or other polymeric material

[0046] The CMP processing system 300 includes a controller 360, which generally includes one or more processors, memory, and support circuits. The one or more processors may include a central processing unit (CPU) and may be one of any form of a general purpose processor that can be used in an industrial setting. The memory, or non-transitory computer-readable medium, is accessible by the one or more processors and may be one or more of memory such as random access memory (RAM), read only memory (ROM), floppy disk, hard disk, or any other form of digital storage, local or remote. The support circuits are coupled to the one or more processors and may include cache, clock circuits, input / output subsystems, power supplies, and the like. The various methods disclosed herein may generally be implemented under the control of the one or more processors by the one or more processors executing computer instruction code stored in the memory as, for example, a software routine. When the computer instruction code is executed by the one orPATENTAttorney Docket No.: 44024932 WO01 more processors, the one or more processors controls the CMP system 100 to perform processes in accordance with the various methods disclosed herein.Cleaning System Configurations

[0047] The various cleaning chambers, which can include one or more cleaning modules 307, 309 within the cleaning system 306 are modular. Accordingly, the modules 307, 309 can be changed as required by, for example, service and / or routine maintenance, or by a particular application. Referring back to Figure 3, according to an embodiment in which either cleaning unit 306A, 306B is configured with capping layer deposition modules 310A, 310B, the third substrate handler may transfer the substrate from the rinse and dry module 334 to an available one of the capping layer deposition modules 310A, 310B. That is, while one substrate is subject to a capping layer deposition process in one of the capping layer deposition modules 310A, 310B, a third substrate handler (not shown) may transfer the substrate to the other one of the capping layer deposition modules 310A, 310B (generically, integrated capping layer deposition module 310) that is not currently occupied by a substrate. During transfer of the substrate from the vertical cleaning module 309B to the available capping layer deposition module 310, the third substrate handler may rotate the substrate by 90 degrees about the Y-axis so that the processing side of the substrate is facing upward, i.e., in the Z-direction, when positioned in the capping layer deposition module 310.

[0048] The third substrate handler may transfer the substrate to an available one of the capping layer deposition modules 310A, 310B through a first door 310C formed in a first side panel of the available one of the capping layer deposition modules 310A, 310B. The first door 310C may be, for example, a slit valve. The first substrate handler 303 may transfer the substrate from the integrated capping layer deposition module 310 (i.e., capping layer deposition modules 310A, 310B) via a second door 310D formed in a second side panel of the capping layer deposition module 310. The first side panel of the capping layer deposition module 310 and the second side panel of the capping layer deposition module 310 may be parallel to one another and on opposite sides of the integrated capping layer deposition module. The second door 310D may be, for example, a slit valve. The first substrate handler 303 may transferPATENTAttorney Docket No.: 44024932 WO01 the substrate from the capping layer deposition module 310 to one of the loading stations 302A.

[0049] In one example of a cleaning process sequence, substrates 400 are moved between the horizontal pre-clean module 307 and the vertical cleaning modules, between individual ones of the second vertical cleaning modules 309A, 309B, and between the second vertical cleaning module 309A, 309B and the capping layer deposition modules 310A, 310B using the third substrate handler.Process Sequence Examples

[0050] Figure 4 illustrates an example of a substrate processing sequence that can be performed in a CMP processing system 300 by use of the controller 360 and other supporting components found within the CMP processing system 300. While Figure 4 illustrates different substrate processing sequences that can be performed in the CMP processing system illustrated in Figure 3, this CMP processing system configuration example is not intended to be limiting as to the scope of the disclosure provided herein.

[0051] In one embodiment, substrate processing sequences 400A and 400B include the same processing sequence operations that are performed in parallel on opposing sides of the cleaning system 306. Therefore, in one example, the process sequence 400A includes the operations of method 200 described above. As shown in Figure 4, the processing sequence begins with the first substrate handler 303 removing a substrate from a loading station 302A and passing the substrate to the second substrate handler 304, as illustrated by path 401. The second substrate handler 304 then transfers the substrate to the transfer station 326 of the polishing module 325, as illustrated by path 402. After the substrate has been processed within one or more of the polishing stations 321 within polishing module 325 the substrate is once again placed within the transfer station 326. The processes performed within the polishing module 325 can include one or more CMP polishing processes (operation 204) that are configured to remove and planarize at least a portion of the interconnect material 103. Next, a cleaning process is performed on the substrate. The second substrate handler 304 then transfers the substrate from the transfer station 326 to thePATENTAttorney Docket No.: 44024932 WO01 first cleaning module 307, as illustrated by path 403. After a cleaning process is performed in the first cleaning module 307, the third substrate handler then transfers the substrate through the cleaning modules within the cleaning unit 306A, 306B, and the capping layer deposition module 310, as illustrated by path 404. In one example, as described above the substrate processing operations performed along path 404 include a processing sequence that includes the performance of cleaning processes in a first cleaning module 307 and two second cleaning processes performed in two second vertical cleaning modules 309A, 309B, a rinse and dry process in the rinse and dry module 334, and depositing a capping layer 112 over the exposed pads 109 in the capping layer deposition module 310. After the processes are performed within the path 404, the first substrate handler 303 then removes the substrate from a capping layer deposition module 310 and positions the substrate within the loading station 302A, as illustrated by path 405. As noted above, while the process sequence 400A is being sequentially performed on a plurality of substrates, the process sequence 400B can also be sequentially performed on a different plurality of substrates simultaneously.

[0052] After the substrate is positioned in the loading station 302A, the substrate is removed from the CMP processing system 300 and is provided to a subsequent processing tool for further processing. In one more examples, during hybrid bonding the substrate is transferred to an integrated hybrid bonding platform for advanced packaging. As described above, the substrate is exposed to atmosphere when it is transferred from the CMP processing system 300 to the integrated hybrid bonding platform. Advantageously, the capping layer 104 protects the pads 109 from the exposure to atmosphere while the substrate is transferred.

[0053] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

PATENTAttorney Docket No.: 44024932WO01What is claimed is:1 . A method, comprising: performing, by a chemical mechanical polishing (CMP) processing system, a CMP process on patterned device structures comprising an interconnect material disposed over a dielectric layer disposed over a substrate, the dielectric layer including interconnect structures etched therein, wherein the interconnect material fills the interconnect structures, and is disposed over the interconnect structures and a field region of the dielectric layer, the CMP process removing portions of the interconnect material disposed on the field region of the dielectric layer and exposing pads within the interconnect structures of the patterned device structures; and depositing a capping layer using a capping layer deposition process over the exposed pads of the patterned device structures.

2. The method of claim 1 , further comprising bonding corresponding patterned device structures to each other.

3. The method of claim 1 , wherein the CMP process is performed until the pads include a desired amount of protrusion or a desired amount of dishing.

4. The method of claim 3, wherein the post-bond annealing process is performed at an annealing temperature less than 200°C.

5. The method of claim 1 , wherein the capping layer deposition process comprises: spraying or rinsing the patterned device structures with de-ionized (DI) water for first duration of time; performing a citric acid deoxidization process on the patterned device structures for a second duration of time; performing an immersion rinse of the patterned device structures for a third duration of time; performing a plating process on the patterned device structures for a fourth duration of time; and8641303 19PATENTAttorney Docket No.: 44024932WO01 performing a rinse spin and dry (SRD) process on the patterned device structures for a fifth duration of time.

6. The method of claim 5, wherein the plating process is an electro-less plating (e-less) process.

7. The method of claim 5, wherein the performing the plating process comprises exposing the patterning device structure to an electro-less (e-less) plating solution until the capping layer reaches a desired thickness.

8. The method of claim 7, wherein the desired thickness is from about 0.1 nm to about 30 nm.

9. The method of claim 7, wherein the e-less plating solution includes silver sulfamate, silver cyanide, silver nitrate, or combinations thereof.

10. The method of claim 1 , wherein the capping layer deposition process is performed by the CMP processing system.11 . The method of claim 1 , further comprising performing a pre-treatment process on the patterned device structures after the CMP process and prior to the capping layer deposition process.

12. A chemical mechanical polishing (CMP) processing system, comprising: a polishing module; a capping layer deposition module; and a controller configured to cause: the polishing module to configured to perform a CMP process on patterned device structures formed on a substrate, the CMP process removing portions of an interconnect material disposed on a field region of a dielectric layer formed over the substrate and exposing pads within8641303 20PATENTAttorney Docket No.: 44024932WO01 interconnect structures of the patterned device structures etched into the dielectric layer; and the capping layer deposition module to deposit a capping layer on the exposed pads of the patterned device structures using a capping layer deposition process.

13. The CMP processing system of claim 12, further comprising a cleaning module, the controller further configured to cause the cleaning module to perform at least one pre-treatment process on the patterned device structures prior to depositing the capping layer on the exposed pads of the patterned device structures.

14. The CMP processing system of claim 12, wherein the capping layer includes at least one of silver, gold, platinum, or titanium.

15. The CMP processing system of claim 12, wherein the capping layer deposition process comprises: spraying or rinsing the patterned device structures with de-ionized (DI) water for a first duration of time; performing a citric acid deoxidization process on the patterned device structures for a second duration of time; performing an immersion rinse of the patterned device structures for a third duration of time; performing a plating process on the patterned device structures for a fourth duration of time; and performing a rinse spin and dry (SRD) process on the patterned device structures for a fifth duration of time.

16. The CMP processing system of claim 12, wherein the capping layer deposition process comprises exposing the patterned device structures to an electroless plating solution until the capping layer reaches a desired thickness.8641303 21PATENTAttorney Docket No.: 44024932WO0117. The CMP processing system of claim 16, wherein the desired thickness is from about 0.1 nm to about 30 nm.

18. A chemical mechanical polishing (CMP) processing system, comprising: a cleaning module configured to perform at least one pre-treatment process on patterned device structures formed on a substrate; a polishing module configured to perform a CMP process on the patterned device structures formed on the substrate, the CMP process removing portions of an interconnect material disposed on a field region of a dielectric layer formed over the substrate and exposing pads within interconnect structures of the patterned device structures etched into the dielectric layer; and a capping layer deposition module, the capping layer deposition module configured to deposit a capping layer on the exposed pads of the patterned device structures.

19. The CMP processing system of claim 18, wherein the capping layer comprises at least one of silver, gold, platinum, or titanium.

20. The CMP processing system of claim 19, wherein the capping layer has a thickness from about 0.1 nm to about 30 nm.8641303 22

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