Semiconductor device and power conversion device

Abstract

In a semiconductor device (100), an analog-to-digital conversion unit (101) converts a gate signal (Vgs, Ig) representing a voltage or current to be applied to a control electrode (G) of a power semiconductor element (113) into a digital value and outputs the digital value on a time-series basis. A data acquisition unit (121) extracts, from time-series data based on the digital value of the gate signal outputted from the analog-to-digital conversion unit (101) on a time-series basis, the time-series data during turn-on or turn-off of the power semiconductor element (113). An inference unit uses a machine-learning trained model (123) to output an estimated value of a principal current (Ids) in an on-state of the power semiconductor element (113) from the time-series data during turn-on or turn-off acquired by the data acquisition unit (121).

Description

Semiconductor Device and Power Conversion Device

[0001] The present disclosure relates to a semiconductor device and a power conversion device.

[0002] The current value of the main line connecting the main electrode of a power semiconductor device (for example, an IGBT (Insulated Gate Bipolar Transistor)) incorporated in a power module and the load is generally fed back to a control system using a microcomputer. As a method for measuring the current of the main line of the power module, mainly there are methods using a current transformer, a shunt resistor, or a magnetoresistive element.

[0003] Specifically, by attaching a current transformer to the main line, a current proportional to the current of the main line, for example, at a ratio of 1000:1, can be obtained. Further, by attaching a load resistor to the secondary side of the current transformer, this current can be obtained as a voltage. However, current transformers are often expensive, have a large component volume, and poor frequency characteristics.

[0004] By attaching a shunt resistor to the main line, the current value of the main line can be detected based on the voltage generated in the shunt resistor. However, there are problems with heat generation and increased loss in the shunt resistor. Further, it is necessary to use an isolated power supply, an isolated ADC (Analog-to-Digital Converter (A / D converter)), and an isolated amplifier to convert the voltage between the terminals of the shunt resistor into a digital value while insulating it. Also, when the shunt resistor is attached to the emitter terminal (or source terminal) of the upper-arm power semiconductor device, similarly, heat generation in the shunt resistor becomes a problem, and an isolated power supply, an isolated ADC, and an isolated amplifier are required. When the shunt resistor is attached to the emitter terminal (or source terminal) of the lower-arm power semiconductor device, the circuit scale becomes smaller than when the shunt resistor is attached to the main line. However, due to negative feedback, there is an obstacle to the gate control of the power semiconductor device. Thus, when using a shunt resistor, problems such as an increase in circuit area and cost due to an increase in the number of components, heat generation, and insulation occur.

[0005] By placing a magnetoresistive element on the main wire, the magnetic field generated by the current flowing through the main wire can be extracted as a voltage, allowing for the detection of the current value in the main wire. However, magnetoresistive elements themselves are expensive and not readily available. While there is little need for an isolated power supply, the system is technically challenging due to its susceptibility to surrounding magnetic fields.

[0006] A new method involves estimating the collector-emitter current (or drain-source current) of power semiconductor devices such as IGBTs using the gate-emitter voltage (or gate-source voltage). This estimation method utilizes an isolated gate voltage, thus eliminating the risk of electrical short circuits. Furthermore, since power semiconductor devices are typically driven by PWM (Pulse Width Modulation) signals, the gate voltage rises and falls hundreds to thousands of times per second, allowing for a comparable sampling rate to obtain an estimated collector current.

[0007] For example, J. Chen et al. ("A Smart IGBT Gate Driver IC With Temperature Compensated Collector Current Sensing," IEEE Transactions on Power Electronics, vol.34, no.5, pp.4613-4627, May 2019) (Non-Patent Literature 1) reported on an IGBT gate driver IC (Integrated Circuit) equipped with a collector current sensing circuit and an on-chip CPU (Central Processing Unit) for local data processing. The collector current sensing circuit estimates the collector current using the gate current during the IGBT's Miller period. Since the Miller effect during turn-on and turn-off is caused by the charging and discharging of the gate-collector capacitance, the gate-emitter voltage during the Miller period mainly depends on the collector current. Therefore, the collector current can be estimated by measuring the gate-emitter voltage or gate current during the Miller period.

[0008] A similar description can be found in the fourth embodiment (paragraphs

[0099] to

[0104] ) of Japanese Patent Publication No. 2017-118792 (Patent Document 1). Specifically, the switching element control circuit in this document includes a Miller voltage detection circuit that acquires Miller voltage data, which is the gate-emitter voltage when the Miller capacitance of the switching element is being charged and discharged. The control unit estimates the collector current of the switching element using the Miller voltage data due to the Miller effect.

[0009] Japanese Patent Publication No. 2017-118792

[0010] J. Chen et al., "A Smart IGBT Gate Driver IC With Temperature Compensated Collector Current Sensing", IEEE Transactions on Power Electronics, vol.34, no.5. pp.4613-4627, May 2019.

[0011] The above-mentioned document discloses a device that estimates collector current based on measured values ​​of gate voltage or gate current during the Miller period at turn-on and turn-off. However, it does not adequately consider changes in the gate signal waveform during the Miller period due to the effects of parasitic inductance and resistance of the wiring, manufacturing variations of power semiconductor elements, and changes in the characteristics of power semiconductor elements over time, and therefore has problems in terms of robustness.

[0012] This disclosure addresses the above-mentioned problems, and one of its objectives is to provide a method for improving the robustness of current value estimation in a semiconductor device that estimates the magnitude of the main current based on transient changes in the gate signal during the turn-on or turn-off of a power semiconductor element.

[0013] One embodiment of the semiconductor device comprises an analog-to-digital conversion unit and a processing circuit. The processing circuit includes a data acquisition unit and an inference unit. The analog-to-digital conversion unit converts a gate signal representing the voltage or current applied to the control electrode of a power semiconductor element into a digital value in a time series and outputs it. The data acquisition unit extracts time series data of the power semiconductor element at turn-on or turn-off from the time series data based on the digital value of the gate signal output in a time series from the analog-to-digital conversion unit. The inference unit uses a first trained model for estimating the magnitude of the main current flowing between the main electrodes of the power semiconductor element in the ON state from the time-varying waveform of the gate signal at turn-on or turn-off of the power semiconductor element, and outputs an estimated value of the main current in the ON state of the power semiconductor element from the time series data of the turn-on or turn-off acquired by the data acquisition unit.

[0014] According to the above embodiment, the magnitude of the main current is estimated from the transient gate signal change during the turn-on or turn-off of the power semiconductor element by inference using a pre-trained machine learning model, thereby improving the robustness of the main current estimation.

[0015] This is a block diagram showing an example configuration of a semiconductor device according to Embodiment 1. This diagram illustrates an example of a trained model in Figure 1. This is a flowchart showing the processing by the processing circuit in Figure 1. This is a block diagram showing an example configuration of a semiconductor device as a learning device for generating the trained model in Figure 1. This is a flowchart showing the learning process by the learning device in Figure 4. This diagram shows an example of the time change of the gate current when a power semiconductor element is turned on. This is a block diagram showing an example configuration of a semiconductor device according to Embodiment 2. This is a block diagram showing the configuration of a semiconductor device as a learning device for generating the trained model in Figure 7. This is a block diagram showing an example configuration of a semiconductor device according to Embodiment 3. This is a block diagram showing an example configuration of a semiconductor device as a learning device for generating the trained model in Figure 9. This is a block diagram showing an example configuration of a semiconductor device according to Embodiment 4. This is a block diagram showing an example configuration of a semiconductor device according to Embodiment 5. This is a block diagram showing an example configuration of a power conversion system to which the power conversion device according to Embodiment 6 is applied.

[0016] Each embodiment will be described in detail below with reference to the drawings. Note that the same or corresponding parts will be denoted by the same reference numerals, and their descriptions will not be repeated.

[0017] Embodiment 1. [Configuration of Semiconductor Device] Figure 1 is a block diagram showing an example configuration of the semiconductor device 100 of Embodiment 1. In Figure 1, in addition to the semiconductor device 100, a power semiconductor element 113 and its drive circuit 117 are also shown.

[0018] The semiconductor device 100 estimates the drain-source current Ids of the power semiconductor element 113 in the ON state based on the time change of the transient gate-source voltage Vgs when the power semiconductor element 113 is turned on or turned off. This estimation is based on machine learning using a neural network. Normally, the power semiconductor element 113 is driven by a PWM (Pulse Width Modulation) signal, so the rising and falling edges of the gate-source voltage Vgs occur hundreds to thousands of times per second. Therefore, an estimated value of the drain-source current Ids can be obtained at a similar sampling rate. Hereafter, the drain-source current Ids will also be referred to simply as drain current, and the gate-source voltage Vgs will also be referred to simply as gate voltage.

[0019] The type of power semiconductor element 113 is not particularly limited; as shown in Figure 1, it may be an N-channel power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) or an IGBT. Furthermore, the material of the power semiconductor element 113 is not particularly limited; it may be silicon (Si), silicon carbide (SiC), or gallium nitride (GaN).

[0020] In the case of an IGBT, the drain terminal D in Figure 1 is replaced with the collector terminal, and the source terminal S is replaced with the emitter terminal. In this specification, the gate terminal G is also referred to as the control electrode, the drain terminal D (or collector terminal) is also referred to as the first main electrode, and the source terminal (or emitter terminal) is also referred to as the second main electrode.

[0021] As an example of a drive circuit 117 for a power semiconductor element 113, the drive circuit 117 in Figure 1 comprises a voltage source 110, a driver 111, and a gate resistor 112. The voltage source 110 generates a voltage VG0 which is the source of the gate drive current. When the power semiconductor element 113 is driven by PWM, the voltage source 110 outputs a PWM signal. The driver 111 generates a drive current and drive voltage that drives the gate terminal G of the power semiconductor element 113 based on the output voltage of the voltage source 110 (i.e., by amplifying the PWM signal). The output terminal of the driver 111 is connected to the gate terminal G of the power semiconductor element 113 via the gate resistor 112.

[0022] The ground terminal of the voltage source 110 is connected to a reference potential VSS, and the reference potential VSS is connected to the source terminal S (or emitter terminal) of the power semiconductor element 113 via source wiring. This source wiring includes parasitic resistance 114 and parasitic inductance 115. The circuit diagram in Figure 1 represents these parasitic components as an equivalent circuit. If a busbar is used as the source wiring, parasitic capacitance is further added to the equivalent circuit. A voltage detector 116 for detecting the drain-source voltage Vds of the power semiconductor element 113 may also be provided.

[0023] The drain terminal D (or collector terminal) of the power semiconductor element 113 may be totem-pole connected to other similar power semiconductor elements. In this case, the drain terminal (or collector terminal) of the power semiconductor element 113 is connected to a load, thereby supplying current from a high-voltage power supply to the load.

[0024] The semiconductor device 100 includes an ADC 101 and a processing circuit 102. The processing circuit 102 may be configured as an MCU (Micro Controller Unit) or MPU (Micro Processing Unit) that incorporates a CPU and memory. Alternatively, the processing circuit 102 may be configured as a PLD (Programmable Logic Device) such as an FPGA (Field Programmable Gate Array), or as an ASIC (Application Specific Integrated Circuit). Alternatively, the processing circuit 102 may be configured as a combination of two or more of the above-mentioned MCU (or MPU), FPGA, and ASIC. Note that the driver 111 and the processing circuit 102 may be combined to form a gate driver IC.

[0025] The ADC 101 acquires the gate signal, which represents the voltage or current applied to the gate terminal G of the power semiconductor element 113, in a time series at a constant clock and performs A / D conversion. In the case of Figure 1, the gate-source voltage Vgs applied between the gate terminal G and the source terminal S is input to the ADC 101 as the gate signal. The digital value of the digitally converted gate signal is input to the processing circuit 102. The processing circuit 102 extracts the transient gate signal time series data for turn-on and turn-off from the time series data obtained by arranging the digital values ​​generated by the ADC 101 in chronological order.

[0026] Alternatively, instead of directly inputting the gate-source voltage Vgs to the ADC 101 as shown in Figure 1, the gate-source voltage Vgs may be multiplied by a constant (including 1) by the differential amplifier 401 and input to the ADC 101 as the gate signal, as shown in Figures 11 and 12.

[0027] As a concrete example, in an IGBT product with a rated current of 100 amperes (for example, Mitsubishi Electric's CM100TX-34T), if the gate resistance is 0Ω, the collector current rises in about 100 to 300 nanoseconds. Therefore, if you want to secure a sampling rate of about 10 points, a sampling frequency of about 30 MHz to 100 MHz is required. Note that the sampling speed can be eased by increasing the resistance of the gate resistor, so it is considered that ADCs with sampling speeds of about 4 MHz to 20 MHz are also perfectly usable.

[0028] Functionally, the processing circuit 102 functions as an inference unit 120, a trained model storage unit 123, and a drive circuit control unit 130. The inference unit 120 includes a data acquisition unit 121 and an inference unit 122. The functions of the inference unit 120 and the drive circuit control unit 130 are realized, for example, by the operation of an MCU or MPU according to a program. The trained model storage unit 123 corresponds, for example, to the memory provided by the MCU or MPU.

[0029] The trained model storage unit 123 stores a trained model obtained through machine learning for inferring the value of the drain-source current Ids in the ON state from time-series data of transient gate signals during the turn-on or turn-off of the power semiconductor element 113.

[0030] The data acquisition unit 121 stores the digital values ​​of the gate signals output from the ADC 101 in chronological order. The inference unit 122 inputs the time-series data of the transient gate signals acquired from the data acquisition unit 121 during turn-on or turn-off into a trained model, and outputs the value of the drain-source current Ids in the ON state, which is inferred from this time-series data of the gate signals. The drive circuit control unit 130 controls the drive circuit 117 (voltage source 110 and driver 111) of the power semiconductor element 113 based on the inferred value of the drain-source current Ids.

[0031] [Trained Model] Figure 2 is a diagram illustrating an example of the trained model shown in Figure 1. In this example, the trained model is based on a Convolutional Neural Network (CNN) 140. The CNN 140 shown in the example in Figure 2 comprises an input buffer 141, an input layer 142, a pooling layer 143, and an output layer 144. The input buffer 141 is the input to the input layer 142, the output of the input layer 142 becomes the input to the pooling layer 143, and the output of the pooling layer 143 becomes the input to the output layer 144.

[0032] The input buffer 141 receives time-series data of the gate signal that transiently changes when the power semiconductor element 113 is turned on or turned off. That is, the input buffer 141 receives data values ​​(also called elements) in a one-dimensional manner, with a number of data points determined according to the capacity of the input buffer 141, going back from the latest current value of the gate signal to past values. In the first embodiment, time-series data of the gate-source voltage Vgs is used as the time-series data of the gate signal.

[0033] The input layer 142 performs a sum-of-products operation on the elements of the input buffer 141. That is, each element of the input layer 142 is input a value obtained by multiplying the local elements of the input buffer 141 by a weight coefficient and then accumulating them. Alternatively, one or more intermediate layers may be provided between the input layer 142 and the pooling layer 143 to perform sum-of-products operations on the local elements of the input layer 142.

[0034] The pooling layer 143 calculates statistics on the input layer 142 of the previous layer or the output of the hidden layer. That is, each element of the pooling layer 143 is input with the result of a statistical calculation, such as the mean or maximum value, for the local elements of the previous layer. Alternatively, the pooling layer 143 may extract some values ​​in descending order from the output of the previous layer and discard the remaining values.

[0035] The output layer 144 generates output data by multiplying each element of the output of the pooling layer 143 by a weighting coefficient and then accumulating all elements (i.e., fully coupling). The output data may also be generated by applying a nonlinear function to the result of the fully coupling. In this embodiment, the output data is a value proportional to the drain-source current Ids (also referred to as collector-emitter current or main current) in the ON state of the power semiconductor element 113.

[0036] The input layer 142, the hidden layer, and the output layer 144 can quantify the characteristics of the gate waveform shape according to the values ​​of the weight coefficients. For example, if a coefficient matrix that switches from -1 to 1, such as [-1, -1, ..., -1, -1, 1, 1, ..., 1, 1] is used as the weight coefficient sequence, a large absolute value can be obtained as the sum-of-products result for waveforms that rise or fall rapidly. On the other hand, the sum-of-products result for waveforms that change smoothly will be a small absolute value because they cancel each other out.

[0037] By providing the pooling layer 143, unnecessary waveform information unrelated to the estimation of the drain-source current Ids can be abstracted and eliminated. Further intermediate layers and pooling layers may be added depending on the gate voltage waveform, or layers that do not function well as a result of actually operating the CNN may be removed.

[0038] When the power semiconductor element 113 is PWM driven, the rising and falling edges of the gate-source voltage Vgs, which serves as the gate signal, occur hundreds to thousands of times per second. Therefore, in order to improve estimation accuracy, the CNN 140 may be configured to estimate the drain-source current Ids in the ON state based on time-series data of the gate signal for multiple sets of turn-on or turn-off periods. For example, the drain-source current Ids is estimated based on time-series data of the gate signal for multiple consecutive turn-on or turn-off periods. In this case, the input layer 142, the intermediate layer, and the pooling layer 143 are configured in two dimensions (number of data points × number of sets).

[0039] [Estimation Process of Drain-Source Current] Figure 3 is a flowchart showing the processing by the processing circuit 102 in FIG. 1. Hereinafter, referring to FIG. 3, the processing of the inference device 120 and the drive circuit control unit 130 of the processing circuit 102 in FIG. 1 will be summarized.

[0040] In step S10 of FIG. 3, the data acquisition unit 121 of the inference device 120 acquires time-series data of a transient gate signal based on the digital value of the gate signal output in time series from the ADC 101 when the power semiconductor element 113 is turned on or off. In the case of Embodiment 1, time-series data of the gate-source voltage Vgs is used as the time-series data of the gate signal.

[0041] In the next step S20, the inference unit 122 inputs the time-series data of the gate-source voltage Vgs at the time of turn-on or turn-off acquired by the data acquisition unit 121 into the learned model stored in the learned model storage unit 123. Note that the learned model is different between the turn-on and turn-off times of the power semiconductor element 113.

[0042] In the next step S30, the inference unit 122 outputs an estimated value of the drain-source current Ids in the on state of the power semiconductor element 113 as a result of the data input process in step S20. Since the mirror voltage varies according to the magnitude of the drain-source current Ids in the on state, by using a learned model that has learned the relationship between the transient change of the gate-source voltage Vgs at the time of turn-on or turn-off and the drain-source current Ids in the on state, the drain-source current Ids in the on state can be estimated.

[0043] In the next step S40, the drive circuit control unit 130 controls the drive circuit 117 of the power semiconductor element 113 according to the magnitude of the estimated drain-source current Ids.

[0044] [Generation Process of Learned Model] Next, the generation process of the learned model stored in the learned model storage unit 123 in FIG. 1 will be described.

[0045] FIG. 4 is a block diagram showing a configuration example of the semiconductor device 150 as a learning device for generating the learned model of FIG. 1. In FIG. 4, in addition to the semiconductor device 150, the power semiconductor element 113 and its drive circuit 117 are also shown.

[0046] In FIG. 4, a current sensor 152 for measuring the drain-source current Ids is provided in the wiring on the drain side of the power semiconductor element 113. The current sensor 152 may be provided in the wiring on the source side of the power semiconductor element 113. Any of a current transformer, a shunt resistor, a magnetoresistive element, etc. may be used as the current sensor 152, and it is not particularly limited.

[0047] Note that the value of the drain-source current Ids can be set to various values by changing the power supply voltage and load impedance of the load circuit (not shown) to which the power semiconductor element 113 is connected.

[0048] The semiconductor device 150 includes ADCs 151 and 153, and a processing circuit 154. The processing circuit 154 may be configured as a MCU or MPU, or may be configured as an FPGA, or may be configured as an ASIC. Alternatively, the processing circuit 154 may be configured as a combination of two or more of these.

[0049] The ADC 151 acquires the gate signal of the power semiconductor element 113 at a constant clock and performs A / D conversion to generate the digital value of the gate signal in time series. In the case of Embodiment 1, the gate-source voltage Vgs is used as the gate signal. The sampling frequency of the ADC 151 is selected so that about 10 sampling values can be obtained in each of the turn-on period and the turn-off period.

[0050] The ADC 153 acquires the output of the current sensor 152 at a constant clock and performs A / D conversion to generate the digital value of the drain-source current Ids in time series. The sampling frequency of the ADC 153 is selected to be about the same as that of the ADC 151, for example.

[0051] Functionally, the processing circuit 154 functions as a learning device 160 and a learned model storage unit 163. The learning device 160 includes a data acquisition unit 161 and a model generation unit 162. The functions of the learning device 160 are realized, for example, by the operation of an MCU or MPU according to a program. The learned model storage unit 163 corresponds, for example, to a memory provided in the MCU or MPU.

[0052] The data acquisition unit 161 acquires the digital value of the gate signal (i.e., the gate-source voltage Vgs) from the ADC 151 in a time series, and acquires the digital value of the drain-source current Ids from the ADC 153 in a time series.

[0053] Furthermore, the data acquisition unit 161 extracts data from the time-series data obtained by arranging the above digital values ​​in chronological order, which includes data showing the transient change of the gate signal at the time of turn-on (i.e., the gate-source voltage Vgs) and the corresponding current value of the drain-source current Ids in the on state after turn-on, as learning data. Note that the current value of the drain-source current Ids may be the average of multiple current values ​​during the on period.

[0054] Similarly, the data acquisition unit 161 extracts data showing the transient change of the gate-source voltage Vgs at the time of turn-off and the corresponding drain-source current Ids in the ON state before turn-off from the time-series data obtained by arranging the above digital values ​​in chronological order, as training data. Note that the current value of the drain-source current Ids may be the average of multiple current values ​​during the ON period.

[0055] The model generation unit 162 generates a trained model that infers the on-state drain-source current Ids from the time-series data of the gate signal at turn-on, based on training data created from a combination of time-series data of the gate signal at turn-on (i.e., gate-source voltage Vgs) and the corresponding on-state drain-source current Ids. Furthermore, the model generation unit 162 generates a trained model that infers the on-state drain-source current Ids from the time-series data of the gate signal at turn-off, based on training data created from a combination of time-series data of the gate signal at turn-off (i.e., gate-source voltage Vgs) and the corresponding on-state drain-source current Ids. The weight coefficient group used in the CNN 140, as described with reference to Figure 2, is stored in the trained model storage unit 163 as a trained model. The range of the estimated drain-source current Ids may be within the range of the current values ​​of the drain-source current Ids prepared as training data.

[0056] In Figure 4, the learning device 160 and the learned model storage unit 163 are configured as a semiconductor device 150 connected to the power semiconductor element 113, but they may be configured as separate devices from the semiconductor device 150. For example, the data acquisition unit 161 of the learning device 160 may acquire learning data from the semiconductor device 150 by being connected to the semiconductor device 150 via a network, or it may acquire learning data via a non-volatile storage medium.

[0057] Figure 5 is a flowchart showing the learning process performed by the learning device 160 in Figure 4. The learning process in Figure 5 is performed during semiconductor chip assembly and during maintenance of equipment incorporating the power semiconductor element 113. This allows for addressing manufacturing variations of the power semiconductor element and changes in its characteristics over time. The learning process of the learning device 160 will now be explained, summarizing the above explanation.

[0058] In step S100 of Figure 5, the data acquisition unit 161 of the learning device 160 acquires time-series data of the gate signal (gate-source voltage Vgs in the first embodiment) and time-series data of the drain-source current Ids of the power semiconductor element 113. From the acquired time-series data, the data acquisition unit 161 generates learning data consisting of a combination of time-series data of the gate signal showing transient changes during turn-on and the corresponding value of the drain-source current Ids in the on state, which is the correct answer data. Furthermore, the data acquisition unit 161 may also generate learning data consisting of a combination of time-series data of the gate signal showing transient changes during turn-off and the corresponding value of the drain-source current Ids in the on state, which is the correct answer data.

[0059] In the next step S110, the model generation unit 162 of the learning device 160 generates a trained model by so-called supervised learning, according to the training data generated by the data acquisition unit 161. In this case, the trained model includes the weight coefficients used in the CNN 140 in Figure 2.

[0060] In the next step S120, the trained model storage unit 163 stores the trained model generated by the model generation unit 162.

[0061] [Effects of Embodiment 1] As described above, the semiconductor device 100 of Embodiment 1 implements an inference device 120 based on a neural network. The inference device 120 estimates the value of the main current (specifically, the drain-source current Ids) from time-series data of the gate signal (specifically, the gate-source voltage Vgs) that changes transiently during turn-on or turn-off. By using a neural network, the gate signal waveform can be abstracted to improve the information extraction capability. Therefore, even if the gate signal waveform is distorted or shifted over time due to parasitic resistance, parasitic inductance, parasitic capacitance, etc., the value of the main current can be estimated with high accuracy, thereby increasing robustness. Furthermore, robustness can be further improved by increasing the number of intermediate layers in the neural network.

[0062] Furthermore, the neural network can be trained at any time after the manufacturing of the power semiconductor element 113, such as during semiconductor chip assembly or maintenance of equipment incorporating the power semiconductor element 113, and the set of weight coefficients used in the neural network can be rewritten. This allows for addressing manufacturing variations of the power semiconductor element and changes in the characteristics of the power semiconductor element over time.

[0063] Embodiment 2. Embodiment 2 describes a case in which the gate current input to or output from the gate terminal G of the power semiconductor element 113 is used as the gate signal used to estimate the drain-source current Ids.

[0064] [Examples of Gate Current Waveforms] Figure 6 shows an example of the time variation of the gate current when a power semiconductor device is turned on. Figure 6(A) shows the current waveforms when the collector current is 15A (solid line), 30A (dashed line), and 45A (dotted line). The graph in Figure 6(B) shows the waveform data in Figure 6(A) with a moving average filter having a window length of 100 data points applied.

[0065] In the case of Figure 6(A), ringing occurs, making it difficult to distinguish the difference in gate current waveform due to differences in collector current values. In contrast, as shown in Figure 6(B), applying a moving average filter makes the difference in gate current waveform corresponding to differences in collector current values ​​clearer.

[0066] Specifically, as shown in Figure 6(B), the gate current increases sharply immediately after turn-on, showing a first peak, then decreases to show a first bottom, then increases again to show a second peak, and then decreases again, gradually decreasing to zero while oscillating. The time period around when the gate current shows the first bottom value corresponds to the Miller period.

[0067] A key feature here is that the first bottom value of the gate current (i.e., the gate current value during the Miller period) decreases as the collector current value increases. More specifically, as shown in Figure 6(B), if the increase in collector current doubles, the decrease in the gate current value during the Miller period also doubles. In other words, the relationship between the collector current and the gate current during the Miller period can be approximated by a linear function. Therefore, the collector current can be estimated by utilizing this feature.

[0068] Furthermore, when estimating the collector current value using a neural network as described in this disclosure, the filtering process described above is not particularly necessary. The neural network-based inference device 120 can accurately estimate the collector current in the ON state by abstracting the overall time waveform of the gate current during turn-on or turn-off.

[0069] [Configuration of Semiconductor Device] Figure 7 is a block diagram showing an example configuration of the semiconductor device 200 of Embodiment 2. In Figure 7, in addition to the semiconductor device 200, a power semiconductor element 113 and its drive circuit 117 are also shown. The following describes the differences from the inference semiconductor device 100 described with reference to Figure 1, and the same or corresponding parts are denoted by the same reference numerals and the description is not repeated.

[0070] The semiconductor device 200 estimates the drain-source current Ids of the power semiconductor element 113 in the ON state based on the time change of the transient gate current Ig during the turn-on or turn-off of the power semiconductor element 113. This estimation is based on machine learning using a neural network.

[0071] As shown in Figure 7, the semiconductor device 200 differs from the semiconductor device 100 in Figure 1 in that, in addition to the ADC 101 and processing circuit 102, it further includes a differential amplifier 201. The differential input terminals of the differential amplifier 201 are connected across the gate resistor 112. As a result, the differential amplifier 201 amplifies the potential difference across the gate resistor 112, that is, the signal obtained by multiplying the gate current Ig by the resistance value of the gate resistor 112, and outputs it to the ADC 101.

[0072] The amplification factor of the differential amplifier 201 is set appropriately so that the voltage value input to the ADC 101 is suitable for the A / D conversion processing in the ADC 101. Therefore, the amplification factor may be greater than or less than 1. When the amplification factor is 1, the differential amplifier 201 functions as a buffer, and when the amplification factor is less than 1, the differential amplifier 201 functions as an attenuator.

[0073] Furthermore, although Figure 7 shows that a single-ended signal is output from the differential amplifier 201, a differential signal may also be output from the differential amplifier 201 to the ADC 101. This configuration improves noise immunity.

[0074] The ADC 101 acquires the output signal of the differential amplifier 201 (i.e., a constant multiple of the gate current Ig of the power semiconductor element 113) as a gate signal at a constant clock and performs A / D conversion. The digital value of the gate signal after A / D conversion, output sequentially from the ADC 101, is input to the processing circuit 102. The inference processing in the processing circuit 102 is the same as in the first embodiment described with reference to Figures 1 to 3, so the explanation will not be repeated.

[0075] As explained with reference to Figure 6, the value of the gate current Ig during the Miller period changes according to the magnitude of the drain-source current Ids. Therefore, as in the first embodiment, the inference device 120 can accurately estimate the drain-source current Ids based on the waveform change of the gate current Ig as a gate signal during turn-on or turn-off.

[0076] Furthermore, the gate current Ig of the power semiconductor element 113 is generated only during the turn-on and turn-off periods, and not during the on and off states. Therefore, the inference unit 122 of the inference device 120 will not mistakenly acquire time-series data from other periods as time-series data of the gate signal during turn-on and turn-off, thereby reducing the possibility of malfunction.

[0077] [Generation of a Trained Model] Figure 8 is a block diagram showing the configuration of a semiconductor device 250 as a learning device for generating the trained model shown in Figure 7. In Figure 8, in addition to the semiconductor device 250, a power semiconductor element 113 and its drive circuit 117 are also shown. Furthermore, in Figure 8, a current sensor 152 for measuring the drain-source current Ids is provided on the wiring on the drain side of the power semiconductor element 113. The current sensor 152 may also be provided on the wiring on the source side of the power semiconductor element 113.

[0078] In the following, we will describe the differences from the learning semiconductor device 150 described with reference to Figure 4 of Embodiment 1, and the same or corresponding parts will be denoted by the same reference numerals and will not be repeated in the description.

[0079] The semiconductor device 250 differs from the semiconductor device 150 in Figure 4 in that, in addition to the ADCs 151 and 153 and the processing circuit 154, it further includes a differential amplifier 251. The differential input terminals of the differential amplifier 251 are connected across the gate resistor 112. As a result, the differential amplifier 251 amplifies the potential difference across the gate resistor 112, that is, the voltage value obtained by multiplying the gate current Ig by the resistance value of the gate resistor 112, and outputs it to the ADC 151.

[0080] The amplification factor of the differential amplifier 251 is set appropriately so that the voltage value input to the ADC 151 is suitable for the A / D conversion processing in the ADC 151. The amplification factor may be greater than or less than 1. The output signal of the differential amplifier 251 may be a single-ended signal or a differential signal, as shown in Figure 7.

[0081] The ADC 151 acquires the output signal of the differential amplifier 251 (i.e., a constant multiple of the gate current Ig of the power semiconductor element 113) as a gate signal at a constant clock and performs A / D conversion. The sampling frequency of the ADC 151 is selected so that approximately 10 sampling points are obtained during both the turn-on and turn-off periods. The digital value of the gate signal after A / D conversion, output sequentially from the ADC 151, is input to the processing circuit 102.

[0082] As explained with reference to Figure 4, the ADC 153 acquires the output of the current sensor 152 at a constant clock and performs A / D conversion to generate a digital value of the drain-source current Ids in a time series. The sampling frequency of the ADC 153 is selected to be approximately the same as that of the ADC 151. The digital value of the drain-source current Ids after A / D conversion, output in a time series from the ADC 153, is input to the processing circuit 102.

[0083] The learning process in the processing circuit 102 is the same as in the first embodiment described with reference to Figures 4 and 5, so we will not repeat the explanation.

[0084] [Effects of Embodiment 2] As described above, the semiconductor device 200 of Embodiment 2 implements an inference device 120 based on a neural network. The inference device 120 estimates the value of the main current (specifically, the drain-source current Ids) from time-series data of a gate signal (specifically, a constant multiple of the gate current Ig) that changes transiently during turn-on or turn-off.

[0085] Therefore, similar to the first embodiment, even if the gate signal waveform is distorted or shifted over time due to parasitic resistance, parasitic inductance, parasitic capacitance, etc., the value of the main current can be estimated with high accuracy, thereby improving robustness. Furthermore, since the neural network learning process can be performed at any time after manufacturing, it is possible to address manufacturing variations of power semiconductor elements and changes in the characteristics of power semiconductor elements over time.

[0086] Embodiment 3. Embodiment 3 describes an example in which, in addition to the gate signal, the detected temperature of the power semiconductor element 113 is used as a signal input to the processing device for estimating the drain-source current Ids. In Embodiment 3, the case in which the gate-source voltage Vgs is used as the gate signal is described as described in Embodiment 1, but the gate current Ig may also be used as the gate signal as described in Embodiment 2.

[0087] [Configuration of Semiconductor Device] Figure 9 is a block diagram showing an example configuration of the semiconductor device 300 of Embodiment 3. In addition to the semiconductor device 300, Figure 9 also shows a power semiconductor element 113, its drive circuit 117, and a temperature sensor 301 for detecting the temperature of the power semiconductor element 113. In the following description, parts common to the semiconductor device 100 for inference processing in Embodiment 1, which was described with reference to Figure 1, will be given the same reference numerals and will not be repeated.

[0088] The semiconductor device 300 includes ADCs 101 and 302 and a processing circuit 303. In this disclosure, ADC 101 and ADC 302 are collectively referred to as the analog-to-digital conversion unit.

[0089] The processing circuit 303 may be configured as an MCU or MPU incorporating a CPU and memory, as well as as a PLD such as an FPGA, or as an ASIC. Alternatively, the processing circuit 303 may be configured as a combination of two or more of the above. Furthermore, the driver 111 and the processing circuit 303 may be combined to form a gate driver IC.

[0090] Similar to the first embodiment, the ADC 101 acquires the gate signal of the power semiconductor element 113 at a constant clock and performs A / D conversion to generate the digital value of the gate signal in a time series. In this embodiment, the gate-source voltage Vgs is used as the gate signal.

[0091] The ADC 302 acquires the value detected by the temperature sensor 301 at a constant clock cycle and performs A / D conversion. The temperature sensor 301 detects the temperature of the power semiconductor element 113.

[0092] Functionally, the processing circuit 303 functions as an inference unit 320, a trained model storage unit 323, and a drive circuit control unit 130. The inference unit 320 includes a data acquisition unit 321 and an inference unit 322. The functions of the inference unit 320 and the drive circuit control unit 130 are realized, for example, by the operation of an MCU or MPU according to a program. The trained model storage unit 323 corresponds, for example, to the memory provided by the MCU or MPU.

[0093] The trained model storage unit 323 stores a trained model obtained through machine learning for inferring the value of the drain-source current Ids in the ON state from the time-series data of the transient gate signal during the turn-on or turn-off of the power semiconductor element 113 and the corresponding detected value of the temperature sensor 301 (i.e., the temperature of the power semiconductor element 113).

[0094] The data acquisition unit 321 stores the digital value of the gate signal output from the ADC 101 and the detected value of the temperature sensor 301 output from the ADC 302 in chronological order. The inference unit 322 inputs the time-series data of the transient gate signal at turn-on or turn-off acquired from the data acquisition unit 321 and the detected value of the temperature sensor 301 corresponding to the turn-on or turn-off into a learned model, and outputs the value of the drain-source current Ids in the ON state, which is inferred from this time-series data of the gate signal and the temperature of the power semiconductor element 113. The drive circuit control unit 130 controls the drive circuit 117 (voltage source 110 and driver 111) of the power semiconductor element 113 based on the inferred value of the drain-source current Ids.

[0095] [Process for generating trained models] Figure 10 is a block diagram showing an example configuration of a semiconductor device 350 as a learning device for generating the trained model shown in Figure 9. In Figure 10, in addition to the semiconductor device 350, a power semiconductor element 113, its drive circuit 117, a current sensor 152 for measuring the drain-source current Ids, and a temperature sensor 301 for detecting the temperature of the power semiconductor element 113 are also shown. In the following description, parts common to the semiconductor device 150 for the learning process in Embodiment 1, which was described with reference to Figure 4, will be given the same reference numerals and will not be repeated.

[0096] The semiconductor device 350 comprises ADCs 151, 153, and 302, and a processing circuit 351. The processing circuit 351 may be configured as an MCU or MPU, as an FPGA, or as an ASIC. Alternatively, the processing circuit 351 may be configured as a combination of two or more of these.

[0097] Similar to the first embodiment, the ADC 151 acquires the gate signal of the power semiconductor element 113 at a constant clock and performs A / D conversion to generate the digital value of the gate signal in a time series. In this embodiment, the gate-source voltage Vgs is used as the gate signal.

[0098] Similar to the first embodiment, the ADC 153 acquires the output of the current sensor 152 at a constant clock and performs A / D conversion to generate a digital value of the drain-source current Ids in a time series.

[0099] The ADC 302 acquires the value detected by the temperature sensor 301 at a constant clock cycle, as in the case of Figure 9, and performs A / D conversion. The temperature sensor 301 detects the temperature of the power semiconductor element 113.

[0100] Functionally, the processing circuit 351 functions as a learning device 360 ​​and a learned model storage unit 363. The learning device 360 ​​includes a data acquisition unit 361 and a model generation unit 362. The functions of the learning device 360 ​​are realized, for example, by the operation of an MCU or MPU according to a program. The learned model storage unit 363 corresponds, for example, to a memory provided in the MCU or MPU.

[0101] The data acquisition unit 361 acquires the digital value of the gate signal (i.e., the gate-source voltage Vgs) from ADC 151 in a time series, the digital value of the drain-source current Ids from ADC 153 in a time series, and the digital value of the temperature sensor 301 (i.e., the temperature of the power semiconductor element 113) from ADC 302 in a time series.

[0102] Furthermore, the data acquisition unit 361 extracts data from the time-series data obtained by arranging the above digital values ​​in chronological order, which includes data showing the transient change of the gate signal at the time of turn-on (i.e., the gate-source voltage Vgs), the corresponding current value of the drain-source current Ids in the on state after turn-on, and the detected value of the temperature sensor 301 in that on state, as training data. Note that the current value of the drain-source current Ids may be the average of multiple current values ​​during the on period, and the detected value of the temperature sensor 301 may be the average of multiple temperature detection values ​​during the on period.

[0103] Similarly, the data acquisition unit 361 extracts data from the time-series data obtained by arranging the above digital values ​​in chronological order, which includes data showing the transient change of the gate signal at the time of turn-off (i.e., the gate-source voltage Vgs), the corresponding current value of the drain-source current Ids in the ON state before turn-off, and the detected value of the temperature sensor 301 in that ON state, as training data. The current value of the drain-source current Ids may be the average of multiple current values ​​during the ON period, and the detected value of the temperature sensor 301 may be the average of multiple temperature detection values ​​during the ON period.

[0104] The model generation unit 362 generates a trained model that infers the on-state drain-source current Ids from the time-series data of the gate signal at turn-on and the corresponding detected value of the temperature sensor 301, based on training data created from a combination of time-series data of the gate signal at turn-on (i.e., gate-source voltage Vgs), the corresponding on-state drain-source current Ids, and the detected value of the temperature sensor 301 in the on-state. Furthermore, the model generation unit 362 generates a trained model that infers the on-state drain-source current Ids from the time-series data of the gate signal at turn-off and the corresponding detected value of the temperature sensor 301, based on training data created from a combination of time-series data of the gate signal at turn-off (i.e., gate-source voltage Vgs), the corresponding on-state drain-source current Ids, and the detected value of the temperature sensor 301 in the on-state. Specifically, the weight coefficients used in the CNN are stored as a trained model in the trained model storage unit 363.

[0105] In Figure 10, the learning device 360 ​​and the learned model storage unit 363 are configured as a semiconductor device 350 connected to the power semiconductor element 113, but they may be configured as separate devices from the semiconductor device 350.

[0106] [Effects of Embodiment 3] In the semiconductor device 300 of Embodiment 3, in addition to the gate signal (specifically, the gate-source voltage Vgs), the detected temperature of the power semiconductor element 113 is used as the signal input to the inference device for estimating the drain-source current Ids. As the temperature of the power semiconductor element 113 rises more as the drain-source current Ids increases, the semiconductor device 300 of Embodiment 3 can estimate the value of the main current with greater accuracy than the semiconductor device 100 of Embodiment 1, and its robustness can be further enhanced.

[0107] Embodiment 4. In the semiconductor device 400 of Embodiment 4, a clock is supplied to the processing circuit 102 as an inference device 120 only during the turn-on period or the turn-off period. This reduces the current consumption of the semiconductor device 400 and reduces the possibility of malfunction. The following will be explained in detail with reference to Figure 11.

[0108] In Embodiment 4, similar to Embodiment 1, an example will be described in which the gate-source voltage Vgs is used as the gate signal for estimating the drain-source current Ids. Alternatively, the gate current Ig may be used as the gate signal, as in Embodiment 2, or the gate signal and the detected temperature of the power semiconductor element 113 may be used to estimate the drain-source current Ids, as in Embodiment 3.

[0109] [Configuration of Semiconductor Device] Figure 11 is a block diagram showing an example configuration of the semiconductor device 400 of Embodiment 4. In Figure 11, in addition to the semiconductor device 400, a power semiconductor element 113 and its drive circuit 117 are also shown. In the following description, the same reference numerals are used for parts that are common to the power semiconductor element 113, its drive circuit 117, and the semiconductor device 100, which were described with reference to Figure 1, and the description will not be repeated.

[0110] The semiconductor device 400 includes an ADC 101, a processing circuit 102, a differential amplifier 401, a comparator 402, a pulse edge detection circuit 404, a voltage source 403, and a clock generator 405. The comparator 402, the pulse edge detection circuit 404, and the voltage source 403 constitute a clock control unit 406 that controls the operation of the clock generator 405.

[0111] The gate terminal G of the power semiconductor element 113 is connected to the positive input terminal of the differential amplifier 401, and the source terminal S of the power semiconductor element 113 is connected to the negative input terminal of the differential amplifier 401. Therefore, the differential amplifier 401 amplifies the gate-source voltage Vgs of the power semiconductor element 113.

[0112] The amplification factor of the differential amplifier 401 is set appropriately so that the voltage value input to the ADC 101 is suitable for the A / D conversion processing in the ADC 151. The amplification factor may be greater than or less than 1. The output signal of the differential amplifier 401 may be a single-ended signal or a differential signal, as shown in Figure 11.

[0113] The ADC 101 acquires the output signal of the differential amplifier 401 (i.e., a constant multiple of the gate-source voltage Vgs of the power semiconductor element 113) as a gate signal at a constant clock and performs A / D conversion. The sampling frequency of the ADC 101 is selected so that approximately 10 sampling values ​​are obtained during both the turn-on period and the turn-off period. The digital value of the gate signal after A / D conversion, output sequentially from the ADC 101, is input to the processing circuit 102. The inference processing in the processing circuit 102 is the same as in the first embodiment described with reference to Figures 1 to 3, so the explanation will not be repeated.

[0114] The negative input terminal of the pulse edge detection circuit 404 is connected to the reference potential VSS, and the positive input terminal of the pulse edge detection circuit 404 is connected to the positive terminal of the voltage source 110. The pulse edge detection circuit 404 outputs a first control signal to the clock generator 405 that is active (e.g., high level) at the rising edge of the output voltage of the voltage source 110 (i.e., the PWM signal) and inactive (e.g., low level) at the falling edge of the output voltage of the voltage source 110.

[0115] The negative input terminal of comparator 402 is connected to the positive terminal of voltage source 403, and the ground terminal of voltage source 403 is connected to the reference potential VSS. The positive input terminal of comparator 402 is connected to the gate terminal G of power semiconductor element 113. The output voltage of voltage source 403 is set to the gate voltage from the end of the Miller period when power semiconductor element 113 is turned on until the gate voltage reaches the maximum voltage. With this configuration, comparator 402 outputs a second control signal to clock generator 405 that becomes active (e.g., high level) after the end of the Miller period when turned on, and inactive (e.g., low level) before the start of the Miller period when turned off.

[0116] The clock generator 405 outputs a clock for operating the ADC 101 and the processing circuit 102. For example, the clock generator 405 includes first and second control input terminals to which the first control signal and the second control signal are input, an input terminal from a built-in oscillator or an external oscillator that is the source of the clock, a register whose state changes in response to the first control signal and the second control signal, and a switch that turns the clock output on and off according to the state of the register.

[0117] The above register is configured to set the open / closed state of the switch. Specifically, from the time the first control signal is switched to active (i.e., the rising edge of the output voltage of the voltage source 110) until the time the second control signal is switched to active (i.e., after the Miller period at turn-on has ended), that is, during the rise time of the gate voltage, the above register is set to indicate that the switch is closed. Therefore, only during the rise time of the gate voltage, the clock generator 405 supplies a clock to the ADC 101 and the processing circuit 102 via the closed switch.

[0118] [Modification of the clock control unit 406] As a modification of the above, the clock generator 405 may supply a clock to the ADC 101 and the processing circuit 102 only during the falling edge period of the gate voltage.

[0119] Specifically, the pulse edge detection circuit 404 outputs a first control signal to the clock generator 405 that is active (e.g., high level) at the falling edge of the output voltage of the voltage source 110 (i.e., the PWM signal) and inactive (e.g., low level) at the rising edge of the output voltage of the voltage source 110.

[0120] The positive input terminal of comparator 402 is connected to the positive terminal of voltage source 403, and the negative input terminal of comparator 402 is connected to the gate terminal G of power semiconductor element 113. The output voltage of voltage source 403 is set to the gate voltage from the end of the Miller period until the gate voltage reaches zero voltage when power semiconductor element 113 is turned off. Therefore, comparator 402 outputs a second control signal to clock generator 405 that becomes active (e.g., high level) after the end of the Miller period when turned off, and inactive (e.g., low level) before the start of the Miller period when turned on.

[0121] According to the above configuration, from the time the first control signal is switched to active (i.e., the falling edge of the output voltage of the voltage source 110) until the time the second control signal is switched to active (i.e., after the end of the Miller period during turn-off), that is, during the falling period of the gate voltage, the above register is set to indicate that the switch is closed. Therefore, only during the falling period of the gate voltage, the clock generator 405 supplies a clock to the ADC 101 and the processing circuit 102 via the closed switch.

[0122] The clock generator 405 may be configured to supply a clock to the ADC 101 and the processing circuit 102 only during both the rising and falling periods of the gate voltage.

[0123] [Effects of Embodiment 4] As described above, according to the semiconductor device 400 of Embodiment 4, the clock generator 405 supplies a clock to the ADC 101 and the processing circuit 102 only during the rise time of the gate voltage or the fall time of the gate voltage. This reduces the current consumption of the semiconductor device 400 and reduces the possibility of malfunction.

[0124] In the above description, an example was given in which the semiconductor device 100 of Embodiment 1 is combined with the clock generator 405 and the clock control unit 406. Similarly, the above-described clock generator 405 and clock control unit 406 can be combined with either the semiconductor device 200 of Embodiment 2 or the semiconductor device 300 of Embodiment 3.

[0125] Embodiment 5. Embodiment 5 describes a detailed example of the operation of the drive circuit control unit (130 in Embodiments 1 to 4) for controlling the drive circuit (117 in Embodiments 1 to 4) of the power semiconductor element 113. As described below, the drive circuit control unit changes the gate current waveform according to the estimated value of the drain-source current Ids.

[0126] In Embodiment 5, a modified configuration of the semiconductor device 400 and the driver 111 for the power semiconductor element 113 of Embodiment 4 will be described, but Embodiment 5 can be combined with any of Embodiments 1 to 4.

[0127] [Configuration of Semiconductor Device] Figure 12 is a block diagram showing an example configuration of the semiconductor device 500 of Embodiment 5. In Figure 12, in addition to the semiconductor device 500, a power semiconductor element 113 and its drive circuit 511 are also shown. In the following description, parts common to the power semiconductor element 113 and its drive circuit 117 described with reference to Figure 1, and the semiconductor device 400 described with reference to Figure 11, will be given the same reference numerals and will not be repeated in the description.

[0128] The drive circuit 511 of the power semiconductor element 113 in Figure 12 differs from the drive circuit 117 in Figure 1 in that it includes a variable driver 510 with a variable output current instead of the driver 111. The waveform of the gate current Ig output from the variable driver 510 is controlled by the drive circuit control unit 502 of the processing circuit 501, which will be described later.

[0129] The semiconductor device 500 includes an ADC 101, a differential amplifier 401, a clock control unit 406, a clock generator 405, and a processing circuit 501. The operation of the ADC 101, differential amplifier 401, clock control unit 406, and clock generator 405 is the same as in the case of the semiconductor device 400 described with reference to Figure 11, so the explanation will not be repeated.

[0130] The processing circuit 501 may be configured as an MCU or MPU incorporating a CPU and memory, as well as as a PLD such as an FPGA, or as an ASIC. Alternatively, the processing circuit 501 may be configured as a combination of two or more of the above-mentioned MCU (or MPU), FPGA, and ASIC. The variable driver 510 and the processing circuit 501 may be combined to form a gate driver IC.

[0131] Functionally, the processing circuit 501 functions as an inference device 120, a trained model storage unit 123, and a drive circuit control unit 502. The inference device 120 includes a data acquisition unit 121 and an inference unit 122. The configuration and functions of the inference device 120 and the trained model storage unit 123 are the same as in Embodiment 1, which was described with reference to Figures 1 to 3, so the description will not be repeated.

[0132] The drive circuit control unit 502 outputs a control signal to the variable driver 510 for controlling the gate current according to the estimated value of the drain-source current Ids output from the inference unit 122 of the inference device 120.

[0133] As shown in Figure 12, the drive circuit control unit 502 includes a table switching control unit 503 and a table 504 that stores transient change data of the gate current. The table switching control unit 503 and the table 504 may be configured as an integrated unit, or they may be configured as a driver IC integrated with the variable driver 510. The function of the table switching control unit 503 is realized, for example, by the operation of an MCU or MPU according to a program. The table 504 corresponds, for example, to a memory provided in the MCU or MPU.

[0134] The possible values ​​of the drain-source current Ids are divided into several intervals, and table 504 stores transient change data of the gate current during turn-on and turn-off of the power semiconductor element 113 for each interval. The table switching control unit 503 acquires transient change data of the gate current for the corresponding interval from table 504 according to the estimated value of the drain-source current Ids output from the inference unit 122. The table switching control unit 503 outputs a control signal to the variable driver 510 to control the output current of the variable driver 510, mainly based on the transient change data of the gate current. As a result, the waveform of the gate current discharged from the variable driver 510 to the gate terminal G or drawn in from the gate terminal G to the variable driver 510 is controlled at the rising and falling edges of the pulse voltage (i.e., PWM signal) output from the voltage source 110.

[0135] [Effects of Embodiment 5] As described above, according to the semiconductor device 500 of Embodiment 5, the transient waveform change of the gate current is controlled according to the estimated value of the drain-source current Ids output from the inference unit 122 of the inference device 120. This makes it possible to suppress losses and noise in the power semiconductor element 113.

[0136] Embodiment 6. This embodiment applies the semiconductor devices described in each of Embodiments 1 to 5 above to a power converter. The power converter to which the semiconductor devices of this disclosure are applied is not limited to a specific power converter, but below, as Embodiment 6, we will describe the case in which the semiconductor devices of this disclosure are applied to a three-phase inverter.

[0137] Figure 13 is a block diagram showing an example configuration of a power conversion system to which the power conversion device according to Embodiment 6 is applied.

[0138] The power conversion system shown in Figure 13 comprises a power supply 610, a power converter 600, and a load 620. The power supply 610 is a DC power supply and supplies DC power to the power converter 600. The power supply 610 can be made up of various components, for example, a DC grid, a solar cell, or a battery, or it may be made up of a rectifier circuit or AC / DC converter connected to an AC grid. Alternatively, the power supply 610 may be made up of a DC / DC converter that converts DC power output from a DC grid into DC power having a different voltage.

[0139] The power converter 600 is a three-phase inverter connected between the power supply 610 and the load 620. It converts the DC power supplied from the power supply 610 into AC power and supplies the AC power to the load 620. As shown in Figure 13, the power converter 600 includes a main conversion circuit 601 that converts DC power into AC power and outputs it, and a control circuit 603 that outputs a control signal to the main conversion circuit 601 to control the main conversion circuit 601.

[0140] Load 620 is a three-phase motor driven by AC power supplied from power converter 600. Note that load 620 is not limited to a specific application and is a motor mounted in various electrical equipment, such as hybrid or electric vehicles, railway vehicles, elevators, or air conditioning equipment.

[0141] The details of the power converter 600 are described below. The main conversion circuit 601 is equipped with switching elements and freewheeling diodes (not shown), and by switching the switching elements, it converts the DC power supplied from the power supply 610 into AC power and supplies it to the load 620. There are various specific circuit configurations for the main conversion circuit 601, but the main conversion circuit 601 in this embodiment is a two-level three-phase full-bridge circuit and includes a semiconductor module 602 equipped with six switching elements and six freewheeling diodes antiparallel to each switching element. Each switching element and each freewheeling diode of the main conversion circuit 601 corresponds to the power semiconductor element 113 in the embodiments 1 to 5 described above. The six switching elements are connected in series in pairs to form upper and lower arms, and each upper and lower arm constitutes each phase (U phase, V phase, W phase) of the full-bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 601, are connected to the load 620.

[0142] Furthermore, the main conversion circuit 601 includes a drive circuit (not shown) for driving each switching element. The drive circuit may be built into the semiconductor module 602, or it may be configured to be a separate drive circuit from the semiconductor module 602. The drive circuit generates a drive signal to drive the switching elements of the main conversion circuit 601 and supplies it to the control electrodes of the switching elements of the main conversion circuit 601. The drive circuit corresponds to the drive circuit 117 in Embodiments 1 to 4 and the drive circuit 511 in Embodiment 5 described above.

[0143] Specifically, the drive circuit outputs a drive signal to turn on the switching element and a drive signal to turn off the switching element to the control electrode of each switching element, in accordance with the control signal from the control circuit 603 described later. When the switching element is kept in the ON state, the drive signal is a voltage signal (ON signal) that is equal to or greater than the threshold voltage of the switching element, and when the switching element is kept in the OFF state, the drive signal is a voltage signal (OFF signal) that is equal to or less than the threshold voltage of the switching element.

[0144] The control circuit 603 controls the switching elements of the main converter circuit 601 so that the desired power is supplied to the load 620. Specifically, it calculates the time (referred to as the on-time) that each switching element of the main converter circuit 601 should be in the ON state based on the power to be supplied to the load 620. For example, the main converter circuit 601 can be controlled by PWM control, which modulates the on-time of the switching elements according to the voltage to be output. The control circuit 603 then outputs a control command (also referred to as a control signal) to the drive circuit of the main converter circuit 601 so that an ON signal is output to the switching elements that should be in the ON state at each point in time, and an OFF signal is output to the switching elements that should be in the OFF state. The drive circuit outputs an ON signal or an OFF signal as a drive signal to the control electrode of each switching element according to this control command.

[0145] Furthermore, the control circuit 603 includes one of the semiconductor devices 100, 200, 300, 400, or 500 in Embodiments 1 to 5. As a result, the control circuit 603 estimates the collector current flowing through at least one of the six switching elements based on the gate signal supplied to that switching element. The control circuit 603 then controls the operation of the drive circuit for each switching element based on the estimated collector current.

[0146] In the power converter according to this embodiment, as described in Embodiments 1 to 5, the control circuit 603 implements an inference device based on a neural network, so that the collector current value can be estimated with high accuracy and robustness can be enhanced. Furthermore, by performing neural network learning processing in a timely manner, the control circuit 603 can easily deal with manufacturing variations of switching elements and changes in the characteristics of switching elements over time.

[0147] In this embodiment, an example of applying the present invention to a two-level three-phase inverter has been described, but the present invention is not limited to this and can be applied to various power conversion devices. In this embodiment, a two-level power conversion device is used, but a three-level or multi-level power conversion device may also be used, and the present invention may be applied to a single-phase inverter when supplying power to a single-phase load. Furthermore, when supplying power to a DC load, the present invention can also be applied to a DC / DC converter or an AC / DC converter.

[0148] Furthermore, the power conversion device to which the present invention is applied is not limited to cases where the load is an electric motor, but can also be used, for example, as a power supply device for electrical discharge machining, laser processing machines, induction heating cookers, or non-contact power supply systems, and can even be used as a power conditioner for solar power generation systems and energy storage systems.

[0149] The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of this application is indicated by the claims and not by the foregoing description, and all modifications within the meaning and scope equivalent to the claims are intended to be included.

[0150] 100, 150, 200, 250, 300, 350, 400, 500 Semiconductor device, 101, 151, 153, 302 ADC, 102, 154, 303, 351, 501 Processing circuit, 110, 403 Voltage source, 111 Driver, 112 Gate resistor, 113 Power semiconductor element, 114 Parasitic resistor, 115 Parasitic inductance, 116 Voltage detector, 117, 511 Drive circuit, 120, 320 Inference device, 121, 161, 321, 361 Data acquisition unit, 122, 322 Inference unit, 123, 163, 323, 363 Learned model storage unit, 130, 502 Drive circuit control unit, 141 Input buffer, 142 Input layer, 143 Pooling layer, 144 Output layer, 152 Current sensor, 160, 360 Learning device, 162, 362 Model generation unit, 201, 251, 401 Differential amplifier, 301 Temperature sensor, 402 Comparator, 404 Pulse edge detection circuit, 405 Clock generator, 406 Clock control unit, 503 Table switching control unit, 504 Table, 510 Variable driver, 600 Power converter, 601 Main converter circuit, 602 Semiconductor module, 603 Control circuit, 610 Power supply, 620 Load, D Drain terminal (main electrode), G Gate terminal (control electrode), Ids Drain-source current, Ig Gate current, S Source terminal (main electrode), VSS Reference potential, Vds Drain-source voltage, Vgs Gate-source voltage Vgs.

Claims

1. A semiconductor device comprising: an analog-to-digital conversion unit that converts a gate signal representing a voltage or current applied to the control electrode of a power semiconductor element into a digital value in a time series and outputs it; and a processing circuit, wherein the processing circuit includes: a data acquisition unit that extracts time series data of the power semiconductor element at the time of turn-on or turn-off from time series data based on the digital value of the gate signal output in a time series from the analog-to-digital conversion unit; and an inference unit that uses a first learned model for estimating the magnitude of the main current flowing between the main electrodes of the power semiconductor element in the ON state from the time series data of the turn-on or turn-off acquired by the data acquisition unit.

2. The semiconductor device according to claim 1, wherein the gate signal is a signal of the gate voltage or a constant multiple thereof applied to the control electrode of the power semiconductor element.

3. The semiconductor device according to claim 1, wherein the gate signal is a gate current or a constant multiple thereof, input to or output from the control electrode of the power semiconductor element.

4. The semiconductor device according to any one of claims 1 to 3, wherein the trained model is a neural network model.

5. The semiconductor device according to any one of claims 1 to 4, wherein the analog-to-digital conversion unit further converts the detected temperature of the power semiconductor element into a digital value and outputs it, the data acquisition unit acquires the detected temperature of the power semiconductor element output from the analog-to-digital conversion unit, and the inference unit uses a second trained model for estimating the magnitude of the main current flowing between the main electrodes of the power semiconductor element in the ON state from the time-varying waveform of the gate signal at the time of turn-on or turn-off of the power semiconductor element and the temperature of the power semiconductor element, and outputs an estimated value of the main current of the power semiconductor element in the ON state from the time-series data at the time of turn-on or turn-off acquired by the data acquisition unit and the detected temperature of the power semiconductor element.

6. The semiconductor device according to any one of claims 1 to 5, wherein a pulse width modulated signal amplified by a driver is input to the control electrode of the power semiconductor element.

7. The semiconductor device according to claim 6, further comprising: a clock generator that outputs an operating clock to the analog-to-digital conversion unit and the processing circuit; and a clock control unit that controls the operation of the clock generator only during at least one of the turn-on period and the turn-off period of the power semiconductor element.

8. The semiconductor device according to claim 7, wherein the clock control unit operates the clock generator only during the turn-on period of the power semiconductor element based on the detection result of the rising edge of the pulse width modulation signal and a comparison of the gate voltage applied to the control electrode of the power semiconductor element with a constant voltage, and the clock control unit operates the clock generator only during the turn-off period of the power semiconductor element based on the detection result of the falling edge of the pulse width modulation signal and a comparison of the gate voltage applied to the control electrode of the power semiconductor element with a constant voltage.

9. The semiconductor device according to any one of claims 6 to 8, wherein the output current of the driver is variable, and the processing circuit further includes a drive circuit control unit that controls the output current of the driver according to an estimated value of the main current of the power semiconductor element in the ON state output from the inference unit.

10. The semiconductor device according to claim 9, wherein the possible values ​​of the main current of the power semiconductor element are divided into a plurality of intervals, and the drive circuit control unit includes a table for storing transient change data of the driver's output current when the power semiconductor element is turned on or turned off, for each interval of the main current, and a table switching control unit that, according to the estimated value of the main current of the power semiconductor element output from the inference unit, obtains transient change data of the driver's output current for the corresponding interval from the table, and outputs a control signal to the driver for controlling the driver's output current based on the obtained transient change data.

11. A power conversion device having the semiconductor device described in any one of claims 1 to 10, comprising a main conversion circuit that converts and outputs input power, and a control circuit that outputs a control signal to the main conversion circuit for controlling the main conversion circuit.

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