Multilayer ceramic capacitor

Abstract

The purpose of the present invention is to provide a multilayer ceramic capacitor capable of suppressing deterioration of insulation resistance of a dielectric layer due to hydrogen generated in a plating step of forming an external electrode.　This multilayer ceramic capacitor according to the present invention comprises: a laminate including a plurality of laminated dielectric layers and a plurality of internal electrode layers laminated on the dielectric layers, the laminate having a first surface and a second surface facing each other in a lamination direction, a third surface and a fourth surface facing each other in a first direction orthogonal to the lamination direction, and a fifth surface and a sixth surface facing each other in a second direction orthogonal to the lamination direction and the first direction; a first internal electrode layer disposed on the plurality of dielectric layers and led out to the third surface; a second internal electrode layer disposed on the plurality of dielectric layers and led out to the fourth surface; a first external electrode disposed on the third surface and connected to the first internal electrode layer; and a second external electrode disposed on the fourth surface and connected to the first internal electrode layer. The laminate comprises: a capacity formation part in which the first internal electrode layer and the second internal electrode layer face each other to form electrostatic capacity; a first lead-out part located between the capacity formation part and the first external electrode; and a second lead-out part located between the capacity formation part and the second external electrode. At least one of the first internal electrode layer of the first lead-out part and the second internal electrode layer of the second lead-out part has an Ni-O oxide region, where the 0 / Ni ratio of the Ni-O region is 0.05-0.47.

Description

Multilayer ceramic capacitor

[0001] The present invention relates to a multilayer ceramic capacitor.< / END>

[0002] Conventionally, multilayer ceramic capacitors are known as multilayer ceramic electronic components. Generally, a multilayer ceramic capacitor includes a laminate in which a plurality of dielectric layers and internal electrode layers are alternately laminated, and a pair of external electrodes formed on the surface of the laminate so as to conduct with the internal electrodes drawn out on the surface of the laminate. And, Ni plating is applied to the surface of the external electrode to prevent solder erosion during mounting, and further, Sn plating is applied on the Ni plating film to improve the solderability during soldering and mounting. This plating such as Ni and Sn is usually formed by an electrolytic plating method.< / END>

[0003] Patent Document 1 describes that hydrogen is generated by a chemical reaction in the plating process, and this hydrogen is occluded in the internal electrode, and the occluded hydrogen gradually reduces the surrounding dielectric layer, causing problems such as deterioration of insulation resistance. And, as a solution thereto, when an internal electrode mainly composed of a noble metal (for example, an Ag—Pd alloy) is used, it is described that a metal (for example, Ni) that suppresses the absorption of hydrogen is added to the internal electrode.< / END>

[0004] Japanese Patent Laid-Open No. 1-80011< / END>

[0005] However, in recent years, in order to reduce material costs, base metals such as Ni are often used as the material for the internal electrode instead of noble metals such as Ag and Pd. Further, although Patent Document 1 describes that Ni is a “metal that inactivates the absorption of hydrogen”, according to the research of the inventors, it has been found that even when Ni is used for the internal electrode, deterioration of insulation resistance occurs due to the influence of hydrogen.< / END>

[0006] Furthermore, some base metals used as constituent materials for internal electrodes and external electrodes, including the plating layer, have a high capacity to absorb hydrogen, such as Ni. It is known that under certain temperature conditions, they release a certain amount of absorbed hydrogen. This is particularly evident when high-temperature, high-humidity load tests are conducted, in which case the absorbed hydrogen is released and diffuses into the dielectric layer, potentially leading to a deterioration of the insulation resistance (IR).

[0007] This invention has been made in view of such problems, and aims to provide a multilayer ceramic capacitor that can suppress the deterioration of the insulating resistance of the dielectric layer due to hydrogen generated in the plating process for forming the external electrodes.

[0008] The multilayer ceramic capacitor according to this invention includes a plurality of stacked dielectric layers and a plurality of internal electrode layers stacked on the dielectric layers, and comprises a laminate having a first surface and a second surface facing each other in the stacking direction, a third surface and a fourth surface facing each other in a first direction perpendicular to the stacking direction, and a fifth surface and a sixth surface facing each other in a second direction perpendicular to the stacking direction and the first direction, a first internal electrode layer disposed on the plurality of dielectric layers and drawn out to the third surface, a second internal electrode layer disposed on the plurality of dielectric layers and drawn out to the fourth surface, and a third internal electrode layer disposed on the third surface and connected to the first internal electrode layer. The laminate comprises a first external electrode and a second external electrode arranged on a fourth surface and connected to a second internal electrode layer, and the laminate comprises a capacitance forming section where the first internal electrode layer and the second internal electrode layer face each other to form a capacitance, a first lead section located between the capacitance forming section and the first external electrode, and a second lead section located between the capacitance forming section and the second external electrode, wherein at least one of the first internal electrode layer of the first lead section and the second internal electrode layer of the second lead section has a Ni-O oxide region, and the Ni-O oxide region has an O / Ni ratio of 0.05 or more and 0.47 or less, making it a multilayer ceramic capacitor.

[0009] The multilayer ceramic capacitor according to this invention comprises a first lead portion located between a capacitance forming portion and a first external electrode, and a second lead portion located between a capacitance forming portion and a second external electrode. At least one of the first internal electrode layer of the first lead portion and the second internal electrode layer of the second lead portion has a Ni-O oxide region, and the Ni-O oxide region has an O / Ni ratio of 0.05 to 0.47. This reduces the amount of Ni contained in the internal electrode layer that diffuses into the Cu contained in the external electrode during the firing of the external electrode. As a result, the diffusion of hydrogen to the capacitance forming portion via Ni diffused in the external electrode is reduced, and the deterioration of insulation resistance is suppressed. Furthermore, the Ni-O oxide regions arranged in the internal electrode layers located in the first and second lead portions reduce the diffusion of hydrogen to the capacitance forming portion via Ni contained in the internal electrode layer, thereby suppressing the deterioration of insulation resistance.

[0010] According to the present invention, it is possible to provide a multilayer ceramic capacitor that can suppress the deterioration of the insulating resistance of the dielectric layer due to hydrogen generated in the plating process for forming the external electrodes.

[0011] The above-mentioned objectives, other objectives, features, and advantages of the present invention will become even clearer from the following description of embodiments for carrying out the invention, with reference to the drawings.

[0012] This is an external perspective view showing an example of a two-terminal multilayer ceramic capacitor according to the first embodiment of the present invention. This is a front view showing an example of a two-terminal multilayer ceramic capacitor according to the first embodiment of the present invention. This is a cross-sectional view along line III-III in Figure 1. This is a cross-sectional view along line IV-IV in Figure 1. This is a cross-sectional view along line V-V in Figure 3. This is a cross-sectional view along line VI-VI in Figure 3. This is an external perspective view showing an example of a three-terminal multilayer ceramic capacitor according to the second embodiment of the present invention. This is a top view showing an example of a three-terminal multilayer ceramic capacitor according to the second embodiment of the present invention. This is a bottom view showing an example of a three-terminal multilayer ceramic capacitor according to the second embodiment of the present invention. This is a front view showing an example of a three-terminal multilayer ceramic capacitor according to the second embodiment of the present invention. This is a cross-sectional view along line XI-XI in Figure 7. This is a cross-sectional view along line XII-XII in Figure 7. This is a cross-sectional view along line XIII-XIII in Figure 10. This is a cross-sectional view along line XIV-XIV in Figure 10.

[0013] A. First Embodiment 1. Two-Terminal Multilayer Ceramic Capacitor As a multilayer ceramic capacitor according to the first embodiment of the present invention, a two-terminal multilayer ceramic capacitor 10 will be described with reference to Figures 1 to 6.

[0014] Figure 1 is an external perspective view showing an example of a two-terminal multilayer ceramic capacitor according to the first embodiment of the present invention. Figure 2 is a front view showing an example of a two-terminal multilayer ceramic capacitor according to the first embodiment of the present invention. Figure 3 is a cross-sectional view taken along line III-III in Figure 1. Figure 4 is a cross-sectional view taken along line IV-IV in Figure 1. Figure 5 is a cross-sectional view taken along line V-V in Figure 3. Figure 6 is a cross-sectional view taken along line VI-VI in Figure 3.

[0015] As shown in Figures 1 to 4, the multilayer ceramic capacitor 10 includes a rectangular parallelepiped laminate 12 and external electrodes 30 arranged on the surface of the laminate 12.

[0016] The laminate 12 has a plurality of stacked dielectric layers 14 and a plurality of internal electrode layers 16 stacked on the dielectric layers 14. The internal electrode layer 16 has a first internal electrode layer 16a and a second internal electrode layer 16b. Details of the first internal electrode layer 16a and the second internal electrode layer 16b will be described later.

[0017] The laminate 12 has a first surface 12a and a second surface 12b that are opposite to the stacking direction x, a third surface 12c and a fourth surface 12d that are opposite to the first direction y which is perpendicular to the stacking direction x, and a fifth surface 12e and a sixth surface 12f that are opposite to the second direction z which is perpendicular to the stacking direction x and the first direction y.

[0018] The laminate 12 has a rectangular parallelepiped shape, and it is preferable that the corners and edges of the laminate 12 are rounded. The corners are the parts where three faces of the laminate 12 intersect, and the edges are the parts where two faces of the laminate 12 intersect. In addition, some or all of the first face 12a and the second face 12b, the third face 12c and the fourth face 12d, and the fifth face 12e and the sixth face 12f may have irregularities or other features formed on them.

[0019] Here, the dimension of the laminate 12 in the first direction y is denoted as dimension l, the dimension of the laminate 12 in the second direction z is denoted as dimension w, and the dimension of the laminate 12 in the stacking direction x is denoted as dimension t.

[0020] The laminate 12 includes a volume-forming portion 18, and a first outer layer portion 20a located on the first surface 12a side and a second outer layer portion 20b located on the second surface 12b side, which are arranged to sandwich the volume-forming portion 18 in the stacking direction x.

[0021] In the capacitance forming section 18, a first internal electrode layer 16a and a second internal electrode layer 16b are alternately stacked via a dielectric layer 14.

[0022] Furthermore, as shown in Figures 3, 5, and 6, the laminate 12 has a first pull-out portion 23a located between the volume-forming portion 18 and the third surface 12c, and a second pull-out portion 23b located between the volume-forming portion 18 and the fourth surface 12d. The first pull-out portion 23a and the second pull-out portion 23b are also called L-gap.

[0023] The first outer layer 20a is located on the first surface 12a side of the laminate 12 and is an assembly of multiple dielectric layers 14 located between the first surface 12a and the capacitance forming portion 18 closest to the first surface 12a. The second outer layer 20b is located on the second surface 12b side of the laminate 12 and is an assembly of multiple dielectric layers 14 located between the second surface 12b and the capacitance forming portion 18 closest to the second surface 12b. Furthermore, the region sandwiched between the first outer layer 20a and the second outer layer 20b is the capacitance forming portion 18.

[0024] As shown in Figure 4, the laminate 12 has side portions (W gaps) 24a and 24b located between the volume-forming portion 18 and the fifth surface 12e, and between the volume-forming portion 18 and the sixth surface 12f.

[0025] The dielectric layer 14 can be formed from a dielectric material, such as a ceramic material. Such a dielectric material can be a dielectric ceramic containing components such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3. When the above dielectric material is the main component, depending on the desired properties of the laminate 12, a material with a lower content of minor components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, or Ni compounds may be added.

[0026] The thickness of the dielectric layer 14 in the laminate 12 after firing is preferably about 0.44 μm or more and 0.50 μm or less.

[0027] The number of dielectric layers 14 to be stacked is preferably 345 or more and 680 or less. However, this number of dielectric layers 14 is the total number of dielectric layers 14 constituting the capacitance forming portion 18 and the number of dielectric layers in the first outer layer portion 20a and the second outer layer portion 20b.

[0028] (Internal Electrode Layers) The laminate 12 has a plurality of internal electrode layers 16, consisting of a plurality of first internal electrode layers 16a and a plurality of second internal electrode layers 16b. The plurality of first internal electrode layers 16a and the plurality of second internal electrode layers 16b are substantially parallel to the first surface 12a and the second surface 12b, and are embedded so as to be alternately arranged along the stacking direction x of the laminate 12, with the dielectric layer 14 in between.

[0029] The first internal electrode layer 16a is arranged on a plurality of dielectric layers 14 and is located inside the laminate 12. The first internal electrode layer 16a has a first opposing electrode portion 25a facing the second internal electrode layer 16b, and a first leading electrode portion 26a located on one end side of the first internal electrode layer 16a, extending from the first opposing electrode portion 25a to the third surface 12c of the laminate 12. Therefore, the ends of the plurality of first leading electrode portions 26a are led out to the surface of the third surface 12c and exposed from the laminate 12.

[0030] The shape of the first opposing electrode portion 25a of the first internal electrode layer 16a is not particularly limited, but is preferably rectangular in plan view. However, the corners may be rounded in plan view, or the corners may be formed at an angle in plan view (tapered). It may also be tapered in plan view with a slope towards one side.

[0031] The shape of the first lead-out electrode portion 26a of the first internal electrode layer 16a is not particularly limited, but is preferably rectangular in plan view. However, the corners may be rounded in plan view, or the corners may be formed at an angle in plan view (tapered). It may also be tapered in plan view with a slope towards one side.

[0032] The width of the first opposing electrode portion 25a of the first internal electrode layer 16a and the width of the first leading electrode portion 26a of the first internal electrode layer 16a may be the same, or one of them may be narrower.

[0033] The second internal electrode layer 16b is arranged on a plurality of dielectric layers 14 and is located inside the laminate 12. The second internal electrode layer 16b has a second opposing electrode portion 25b facing the first internal electrode layer 16a, and a second leading electrode portion 26b located on one end side of the second internal electrode layer 16b, extending from the second opposing electrode portion 25b to the fourth surface 12d of the laminate 12. Therefore, the ends of the plurality of second leading electrode portions 26b are drawn out to the surface of the fourth surface 12d and exposed from the laminate 12.

[0034] The shape of the second opposing electrode portion 25b of the second internal electrode layer 16b is not particularly limited, but is preferably rectangular in plan view. However, the corners may be rounded in plan view, or the corners may be formed at an angle in plan view (tapered). It may also be tapered in plan view with a slope towards one side.

[0035] The shape of the second lead-out electrode portion 26b of the second internal electrode layer 16b is not particularly limited, but is preferably rectangular in plan view. However, the corners may be rounded in plan view, or the corners may be formed at an angle in plan view (tapered). It may also be tapered in plan view with a slope towards one side.

[0036] The width of the second opposing electrode portion 25b of the second internal electrode layer 16b and the width of the second leading electrode portion 26b of the second internal electrode layer 16b may be the same width, or one of them may be narrower.

[0037] Within the laminate 12, the first opposing electrode portion 25a of the first internal electrode layer 16a and the second opposing electrode portion 25b of the second internal electrode layer 16b face each other. In this embodiment, the first opposing electrode portion 25a of the first internal electrode layer 16a and the second opposing electrode portion 25b of the second internal electrode layer 16b face each other via the dielectric layer 14, thereby forming capacitance and exhibiting capacitor characteristics.

[0038] Furthermore, by including a Sn layer between the first internal electrode layer 16a and the second internal electrode layer 16b and the dielectric layer 14, electric field concentration at the interface between the internal electrode layer 16 and the dielectric layer 14 can be mitigated, leading to improved high-temperature load reliability.

[0039] The first internal electrode layer 16a and the second internal electrode layer 16b can be made of a suitable conductive material such as metals like Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals, such as Ag-Pd alloys.

[0040] The thickness of the first internal electrode layer 16a is not particularly limited, but is preferably, for example, 0.38 μm or more and 0.45 μm or less. The thickness of the second internal electrode layer 16b is not particularly limited, but is preferably, for example, 0.38 μm or more and 0.45 μm or less.

[0041] The total number of the first internal electrode layer 16a and the second internal electrode layer 16b is preferably 325 to 660. The number of the first internal electrode layer 16a is not particularly limited, but is preferably 162 to 330. The number of the second internal electrode layer 16b is not particularly limited, but is preferably 163 to 330.

[0042] At least one of the first internal electrode layer 16a located in the first extraction portion 23a and the second internal electrode layer 16b located in the second extraction portion 23b has a Ni-O oxide region 40.

[0043] The O / Ni ratio in the Ni-O oxide region 40 located in at least one of the first internal electrode layer 16a located in the first extraction portion 23a and the second internal electrode layer 16b located in the second extraction portion 23b is 0.05 or more and 0.47 or less.

[0044] The amount of Ni contained in the internal electrode layer 16 diffusing into Cu contained in the base electrode layer 32 of the external electrode 30 is reduced by the Ni-O oxide region 40 disposed in the internal electrode layer 16 located in the first lead-out portion 23a and the second lead-out portion 23b. Thereby, the diffusion of hydrogen to the capacitance forming portion 18 through Ni diffused into the external electrode 30 is reduced, and the deterioration of the insulation resistance is suppressed. Further, the diffusion of hydrogen to the capacitance forming portion 18 through Ni contained in the internal electrode layer 16 is reduced by the Ni-O oxide region 40 disposed in the internal electrode layer 16 located in at least one of the first lead-out portion 23a and the second lead-out portion 23b, and the deterioration of the insulation resistance is suppressed.

[0045] It is preferable that the oxygen concentration of the dielectric layer 14 in the region within 0.5 μm from the third surface 12c (surface region) is higher than the oxygen concentration of the dielectric layer 14 in the region from 2 μm or more to 5 μm or less from the third surface 12c (inner region). Similarly, it is preferable that the oxygen concentration of the dielectric layer 14 in the region within 0.5 μm from the fourth surface 12d (surface region) is higher than the oxygen concentration of the dielectric layer 14 in the region from 2 μm or more to 5 μm or less from the fourth surface 12d (inner region).

[0046] The dielectric layer 14 in the region within 0.5 μm from the third surface 12c (surface region) preferably has an O / Ti ratio of 0.97 or more and 1.64 or less, and the dielectric layer 14 in the region from 2 μm or more to 5 μm or less from the third surface 12c (inner region) preferably has an O / Ti ratio of 0.68 or more and 0.93 or less. Similarly, the dielectric layer 14 in the region within 0.5 μm from the fourth surface 12d (surface region) preferably has an O / Ti ratio of 0.97 or more and 1.64 or less, and the dielectric layer 14 in the region from 2 μm or more to 5 μm or less from the fourth surface 12d (inner region) preferably has an O / Ti ratio of 0.68 or more and 0.93 or less.

[0047] The ratio of the O / Ti ratio of the dielectric layer 14 in the region (inner region) of 2 μm or more and 5 μm or less from the third surface 12c to the O / Ti ratio of the dielectric layer 14 in the region (surface region) within 0.5 μm from the third surface 12c is 1.43 or more and 1.76 or less. Similarly, the ratio of the O / Ti ratio of the dielectric layer 14 in the region (inner region) of 2 μm or more and 5 μm or less from the fourth surface 12d to the O / Ti ratio of the dielectric layer 14 in the region (surface region) within 0.5 μm from the fourth surface 12d is 1.43 or more and 1.76 or less.

[0048] Here, the O / Ni ratio in the Ni-O oxide region 40 is measured as follows. That is, first, as the Ni-O oxide region 40, the LT cross-section is exposed, and in the region of 0.5 μm or more and 5 μm or less from the third surface 12c or the fourth surface 12d with respect to the LT cross-section, a reflected electron image (acceleration voltage: 15.0 kV, field of view: 10,000 times) obtained using a scanning electron microscope (for example, manufactured by JEOL Ltd., model JSM-7800M) is used to identify the location where NiO is formed. Subsequently, EDX analysis is performed on the NiO identified by the reflected electron image to detect the Ni element and the O element, and measure their respective values. Then, the O / Ni ratio can be calculated from the measured respective values.

[0049] The O / Ti ratio of the dielectric layer 14 in the region (surface region) within 0.5 μm from the third surface 12c or the fourth surface 12d is measured as follows. That is, first, the LT cross-section is exposed, and EDX analysis (acceleration voltage: 15.0 kV, field of view: 10,000 times) is performed on the dielectric layer 14 in the region (surface region) within 0.5 μm from the third surface 12c or the fourth surface 12d with respect to the LT cross-section using a scanning electron microscope (for example, manufactured by JEOL Ltd., model JSM-7800M) to detect the Ti element and the O element, and measure their respective values. Then, the O / Ti ratio can be calculated from the measured respective values.

[0050] Furthermore, the O / Ti ratio of the dielectric layer 14 in the region between 2 μm and 5 μm (inner region) from the third surface 12c or the fourth surface 12d is measured as follows. Specifically, first, the LT cross section is exposed, and EDX analysis (acceleration voltage: 15.0 kV, field of view: 10,000x) is performed on the dielectric layer 14 in the region between 2 μm and 5 μm (inner region) from the third surface 12c or the fourth surface 12d using a scanning electron microscope (for example, JEOL Ltd., model JSM-7800M) to detect the Ti and O elements and measure their respective values. Then, the O / Ti ratio can be calculated from the measured values.

[0051] (External electrodes) External electrodes 30 are provided on the third surface 12c and the fourth surface 12d of the laminate 12, as shown in Figures 1 to 4. The external electrodes 30 have a first external electrode 30a and a second external electrode 30b.

[0052] The first external electrode 30a is connected to the first internal electrode layer 16a and is positioned on at least the surface of the third surface 12c. Therefore, the first lead portion 23a described above is located between the capacitance forming portion 18 and the first external electrode 30a. Furthermore, the first external electrode 30a extends from the third surface 12c of the laminate 12 and is positioned on a part of the first surface 12a and a part of the second surface 12b, as well as a part of the fifth surface 12e and a part of the sixth surface 12f. In this case, the first external electrode 30a is electrically connected to the first lead electrode portion 26a of the first internal electrode layer 16a.

[0053] The second external electrode 30b is connected to the second internal electrode layer 16b and is positioned on at least the surface of the fourth surface 12d. Therefore, the second lead portion 23b described above is located between the capacitance forming portion 18 and the second external electrode 30b. The second external electrode 30b also extends from the fourth surface 12d of the laminate 12 and is positioned on a part of the first surface 12a and a part of the second surface 12b, as well as a part of the fifth surface 12e and a part of the sixth surface 12f. In this case, the second external electrode 30b is electrically connected to the second lead electrode portion 26b of the second internal electrode layer 16b.

[0054] The external electrode 30 includes a base electrode layer 32 placed on the surface of the laminate 12 and a plating layer 34 placed so as to cover the base electrode layer 32.

[0055] The base electrode layer 32 has a first base electrode layer 32a and a second base electrode layer 32b.

[0056] The plating layer 34 has a first plating layer 34a and a second plating layer 34b.

[0057] In other words, the first external electrode 30a has a first base electrode layer 32a and a first plating layer 34a. The second external electrode 30b has a second base electrode layer 32b and a second plating layer 34b.

[0058] The first base electrode layer 32a is placed on the surface of the third surface 12c of the laminate 12 and is formed to extend from the first end surface 12e and cover a portion of each of the first surface 12a, the second surface 12b, the fifth surface 12e, and the sixth surface 12f. The second base electrode layer 32b is placed on the surface of the fourth surface 12d of the laminate 12 and is formed to extend from the fourth surface 12d and cover a portion of each of the first surface 12a, the second surface 12b, the fifth surface 12e, and the sixth surface 12f. The first base electrode layer 32a may be placed only on the surface of the third surface 12c of the laminate 12, and the second base electrode layer 32b may be placed only on the surface of the fourth surface 12d of the laminate 12.

[0059] The base electrode layer 32 includes at least one selected from a baked layer, a conductive resin layer, a thin film layer, etc. The configurations when the base electrode layer 32 is the baked layer, conductive resin layer, or thin film layer will be described below.

[0060] (In the case of a baked layer) The baked layer contains a glass component and a metal component. The glass component of the baked layer contains at least one selected from B, Si, Ba, Mg, Al, Li, etc. The metal component of the baked layer contains at least one selected from, for example, Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The baked layer may consist of multiple layers. The baked layer is obtained by applying a conductive paste containing the glass component and the metal component to the laminate 12 and baking it. The baked layer may be obtained by simultaneously baking the laminate chip having the internal electrode layer 16 and the dielectric layer 14 and the conductive paste applied to the laminate chip, or by baking the laminate chip having the internal electrode layer 16 and the dielectric layer 14 to obtain a laminate, and then baking the conductive paste onto the laminate.

[0061] Furthermore, when firing a laminated chip having an internal electrode layer 16 and a dielectric layer 14 and a conductive paste applied to the laminated chip simultaneously, it is preferable to form the firing layer by firing a material with a dielectric material added instead of a glass component.

[0062] When the first base electrode layer 32a is formed as a baked layer, the thickness of the first base electrode layer 32a located on the third surface 12c in the center of the stacking direction is preferably, for example, 10 μm to 30 μm. Also, when the second base electrode layer 32b is formed as a baked layer, the thickness of the second base electrode layer 32b located on the fourth surface 12d in the center of the stacking direction is preferably, for example, 10 μm to 300 μm.

[0063] Furthermore, when a base electrode layer 32 is provided on the first surface 12a and the second surface 12b by a baking layer, the thickness of the first base electrode layer 32a located on the first surface 12a and the second surface 12b in the direction connecting the first surface 12a and the second surface 12b at the center of the first direction y is preferably, for example, 3 μm or more and 10 μm or less, and the thickness of the second base electrode layer 32b located on the first surface 12a and the second surface 12b in the direction connecting the first surface 12a and the second surface 12b at the center of the first direction y is preferably, for example, 3 μm or more and 10 μm or less.

[0064] Furthermore, when a base electrode layer 32 is provided on the fifth surface 12e and the sixth surface 12f by a baking layer, the thickness of the first base electrode layer 32a located on the fifth surface 12e and the sixth surface 12f in the direction connecting the fifth surface 12e and the sixth surface 12f at the center of the first direction y is preferably, for example, 3 μm or more and 10 μm or less, and the thickness of the second base electrode layer 32b located on the fifth surface 12e and the sixth surface 12f in the direction connecting the fifth surface 12e and the sixth surface 12f at the center of the first direction y is preferably, for example, 3 μm or more and 10 μm or less.

[0065] (In the case of a conductive resin layer) When a conductive resin layer is provided as the base electrode layer 32, the conductive resin layer may be arranged on the baking layer so as to cover the baking layer, or it may be arranged directly on the laminate 12 without providing a baking layer. The conductive resin layer may completely cover the baking layer, or it may cover a part of the base electrode layer. Furthermore, there may be multiple conductive resin layers.

[0066] The conductive resin layer contains a metal and a thermosetting resin. Because the conductive resin layer contains a thermosetting resin, it is more flexible than a baked layer made of, for example, a plated film or a fired conductive paste. Therefore, even if the two-terminal multilayer ceramic capacitor 10 is subjected to physical shock or shock caused by thermal cycling, the conductive resin layer functions as a buffer layer, preventing cracks in the two-terminal multilayer ceramic capacitor 10.

[0067] The metals that can be included in the conductive resin layer include Ag, Cu, Ni, Sn, Bi, or alloys containing these metals. Alternatively, metal powder with an Ag coating on its surface can be used. When using metal powder with an Ag coating, it is preferable to use Cu, Ni, Sn, Bi, or alloys thereof as the metal powder. The reason for using Ag conductive metal powder is that Ag has the lowest resistivity among metals, making it suitable for electrode materials; and because Ag is a noble metal, it does not oxidize and has high weather resistance. Furthermore, it allows for the use of less expensive base metals while maintaining the above-mentioned properties of Ag.

[0068] Furthermore, the metals included in the conductive resin layer can be Cu or Ni that have been treated to prevent oxidation. Alternatively, metal powders coated with Sn, Ni, or Cu can be used as the metals included in the conductive resin layer. When using metal powders coated with Sn, Ni, or Cu, it is preferable to use Ag, Cu, Ni, Sn, Bi, or alloys thereof as the metal powder.

[0069] The metals contained in the conductive resin layer are primarily responsible for the conductivity of the conductive resin layer. Specifically, conductive fillers come into contact with each other, forming an electrical pathway within the conductive resin layer.

[0070] The metal contained in the conductive resin layer can be spherical, flattened, or otherwise, but it is preferable to use a mixture of spherical and flattened metal powders.

[0071] As the resin for the conductive resin layer, various known thermosetting resins such as epoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin can be used. Among these, epoxy resin, which has excellent heat resistance, moisture resistance, and adhesion, is one of the most suitable resins.

[0072] Furthermore, it is preferable that the conductive resin layer contains a curing agent along with the thermosetting resin. When epoxy resin is used as the base resin, various known compounds such as phenolic, amine, acid anhydride, imidazole, active ester, and amide-imide compounds can be used as curing agents for the epoxy resin.

[0073] The thickest part of the conductive resin layer is preferably, for example, 20 μm or more and 40 μm or less.

[0074] (In the case of a thin film layer) When a thin film layer is provided as the base electrode layer 32, the thin film layer is formed by a thin film formation method such as sputtering or vapor deposition, and is a layer of 1 μm or less in thickness on which metal particles are deposited.

[0075] The plating layer 34 has a first plating layer 34a and a second plating layer 34b.

[0076] The first plating layer 34a is arranged to cover the surface of the first base electrode layer 32a. The second plating layer 34b is arranged to cover the surface of the second base electrode layer 32b.

[0077] The plating layer 34 contains at least one metal selected from, for example, Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc.

[0078] The plating layer 34 may be formed as a single layer or as multiple layers. When formed as multiple layers, it is preferable to have a two-layer structure of Ni plating and Sn plating, for example. By making the layer that is in direct contact with the underlying electrode layer a plating layer made of Ni plating, it is possible to prevent the underlying electrode layer from being corroded by the solder used for mounting when mounting the multilayer ceramic capacitor, especially when the underlying electrode layer is a conductive resin layer.

[0079] Furthermore, by making the upper layer of the Ni plating layer a Sn plating layer, the wettability of the solder used for mounting the two-terminal multilayer ceramic capacitor 10 to the mounting substrate is improved, making mounting easier.

[0080] The thickness of each plating layer 34 is preferably 1.0 μm or more and 6.0 μm or less.

[0081] Furthermore, the external electrode 30 may be formed using only the plating layer without providing the underlayer electrode layer 32. Although not shown in the figures, a structure in which the plating layer is provided without the underlayer electrode layer 32 will be described below.

[0082] The first external electrode 30a and the second external electrode 30b may each have a plating layer directly formed on the surface of the laminate 12 without providing an underlayment electrode layer. That is, the two-terminal multilayer ceramic capacitor 10 may have a structure that includes a plating layer electrically connected to the first internal electrode layer 16a or the second internal electrode layer 16b. In such a case, the plating layer may be formed after a catalyst is placed on the surface of the laminate 12 as a pretreatment.

[0083] Furthermore, when forming the plating layer directly on the laminate without providing a base electrode layer, the reduction in the thickness of the base electrode layer 32 can be used to lower the profile, i.e., to make it thinner, or to increase the thickness of the laminate 12, i.e., the thickness of the capacitance forming section, thereby improving the design flexibility of thin chips.

[0084] The plating layer preferably includes a lower plating electrode formed on the surface of the laminate 12 and an upper plating electrode formed on the surface of the lower plating electrode. The lower plating electrode and the upper plating electrode each preferably contain at least one metal selected from, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, or Zn, or an alloy containing such a metal. Furthermore, the lower plating electrode is preferably formed using Ni, which has solder barrier properties, and the upper plating electrode is preferably formed using Sn or Au, which has good solder wettability.

[0085] Furthermore, for example, when the first internal electrode layer 16a and the second internal electrode layer 16b are formed using Ni, it is preferable that the lower plated electrode be formed using Cu, which has good bonding properties with Ni. The upper plated electrode may be formed as needed, and the first external electrode 30a and the second external electrode 30b may each consist only of the lower plated electrode. The plating layer may have the upper plated electrode as the outermost layer, or other plated electrodes may be formed on the surface of the upper plated electrode.

[0086] In this case, when the external electrode 30 is formed using only the plating layer without providing the underlayer electrode layer 32, it is preferable that the thickness of each plating layer placed without the underlayer electrode layer 32 is 1.0 μm or more and 15.0 μm or less.

[0087] Furthermore, it is preferable that the plating layer does not contain glass. The metal content per unit volume of the plating layer is preferably 99% by volume or more.

[0088] The dimension in the first direction y of the two-terminal multilayer ceramic capacitor 10, including the laminate 12 and the external electrode 30, is defined as dimension L. Dimension L is preferably 1.0 mm or more and 1.3 mm or less. The dimension in the stacking direction x of the two-terminal multilayer ceramic capacitor 10, including the laminate 12 and the external electrode 30, is defined as dimension T. Dimension T is preferably 0.4 mm or more and 0.65 mm or less. The dimension in the second direction z of the two-terminal multilayer ceramic capacitor 10, including the laminate 12 and the external electrode 30, is defined as dimension W. Dimension W is preferably 0.4 mm or more and 0.95 mm or less.

[0089] The two-terminal multilayer ceramic capacitor 10 shown in Figure 1 includes a first lead portion 23a located between the capacitance forming portion 18 and the first external electrode 30a, and a second lead portion 23b located between the capacitance forming portion 18 and the second external electrode 30b. At least one of the first internal electrode layer 16a of the first lead portion 23a and the second internal electrode layer 16b of the second lead portion 23b has a Ni-O oxide region 40, and the Ni-O oxide region 40 has an O / Ni ratio of 0.05 to 0.47. This reduces the amount of Ni contained in the internal electrode layer 16 that diffuses into the Cu contained in the external electrode 30 during the firing of the external electrode 30. As a result, the diffusion of hydrogen to the capacitance forming portion 18 via Ni diffused in the external electrode is reduced, and the deterioration of the insulation resistance is suppressed. Furthermore, the Ni-O oxide regions 40 arranged in the internal electrode layer 16 located in the first extraction portion 23a and the second extraction portion 23b reduce the diffusion of hydrogen to the capacitance forming portion 18 via the Ni contained in the internal electrode layer 16, thereby suppressing the deterioration of the insulation resistance.

[0090] 2. Following the description of the manufacturing method for a two-terminal multilayer ceramic capacitor, the manufacturing method for a two-terminal multilayer ceramic capacitor will be explained.

[0091] First, a dielectric sheet for the dielectric layer and a conductive paste for the internal electrode layer are prepared. The dielectric sheet and the conductive paste for the internal electrode layer contain a binder and a solvent. The binder and solvent may be known substances.

[0092] Then, a conductive paste for the internal electrode layer is printed onto the dielectric sheet in a predetermined pattern, for example, by screen printing or gravure printing. This prepares a dielectric sheet with the pattern for the first internal electrode layer formed on it, and a dielectric sheet with the pattern for the second internal electrode layer formed on it.

[0093] More specifically, a gravure plate can be prepared for printing the first internal electrode layer and the second internal electrode layer, and the patterns for each internal electrode layer can be printed using a gravure printing machine.

[0094] Furthermore, regarding dielectric sheets, dielectric sheets for the outer layer that do not have the pattern of the internal electrode layer printed on them are also prepared.

[0095] Next, a predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked to form the second outer layer portion 20b on the second surface 12b side. Subsequently, the portion that will become the capacitance forming portion 18 formed in the above process is stacked on top of the portion that will become the second outer layer portion 20b. Next, a predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked on top of the portion that will become the capacitance forming portion 18 formed in the above process to form the first outer layer portion 20a on the first surface 12a side. This completes the production of the laminated sheet.

[0096] Next, the laminated sheets are pressed in the lamination direction by means of a hydrostatic press or other means to produce a laminated block.

[0097] The laminated block is then cut to a predetermined size, thereby producing laminated chips. At this time, the corners and edges of the laminated chips may be rounded by barrel polishing or other methods.

[0098] Next, the cut laminated chips are fired to produce the laminated body 12. The firing temperature depends on the materials of the dielectric layer 14 and the internal electrode layer 16, but is preferably between 900°C and 1400°C.

[0099] Subsequently, annealing is performed to promote grain growth and solid solution of additives. The annealing temperature depends on the materials of the dielectric layer and the internal electrode layer, but is preferably between 900°C and 1200°C.

[0100] (Re-oxidation treatment) Next, the annealed laminate 12 is subjected to a re-oxidation treatment. The conditions for the re-oxidation treatment are, for example, a heat treatment temperature of 700°C to 900°C and a heat treatment time of 30 minutes to 300 minutes. Furthermore, it is desirable to heat-treat the atmosphere on the oxidation side in a range of 10 to 100 times the equilibrium oxygen partial pressure (MPa) of Ni. This makes it possible to arrange Ni-O oxide regions 40 in the internal electrode layers 16 located in the first extraction portion 23a and the second extraction portion 23b. Note that if the hydrogen concentration in the atmospheric gas is too low, i.e., the oxygen concentration is too high, excessive surface oxides will be generated, reducing the connectivity between the internal electrode layer and the external electrode, or the internal stress will increase due to oxidative expansion of the internal electrode, causing cracks. For this reason, it is desirable to sinter the atmospheric gas on the oxidation side in a range of 100 times or less the equilibrium oxygen partial pressure (MPa) of Ni.

[0101] As a result of the re-oxidation treatment described above, the O / Ni ratio in the Ni-O oxide region 40 located in the internal electrode layer 16 at the first extraction portion 23a and the second extraction portion 23b can be arranged to be between 0.05 and 0.47.

[0102] Furthermore, the above-described re-oxidation treatment makes it possible to increase the oxygen concentration of the dielectric layer 14 in the region within 0.5 μm from the third surface 12c and the fourth surface 12d to a higher level than the oxygen concentration of the dielectric layer 14 in the region between 2 μm and 5 μm from the third surface 12c and the fourth surface 12d. In addition, the O / Ti ratio in the dielectric layer 14 in the region within 0.5 μm from the third surface 12c and the fourth surface 12d can be set to 0.97 or more and 1.64 or less. Furthermore, the O / Ti ratio in the dielectric layer 14 in the region between 2 μm and 5 μm from the third surface 12c and the fourth surface 12d can be set to 0.68 or more and 0.93 or less. Therefore, by the above-described re-oxidation treatment, the ratio of the O / Ti ratio of the dielectric layer 14 in the region within 0.5 μm from the third surface 12c and the fourth surface 12d to the O / Ti ratio of the dielectric layer 14 in the region between 2 μm and 5 μm from the third surface 12c and the fourth surface 12d can be set to 1.43 or more and 1.76 or less.

[0103] (Formation of external electrodes) (a) In the case of a baked layer, the following explanation assumes that the base electrode layer is formed by a baked layer. When forming a baked layer, a conductive paste containing glass components and metal is prepared, applied, and then a baking process is performed to form the base electrode layer.

[0104] A first base electrode layer 32a for the first external electrode 30a and a second base electrode layer 32b for the second external electrode 30b are formed on the third surface 12c and the fourth surface 12d of the laminate 12 obtained by firing.

[0105] When forming a baked layer as the base electrode layer 32, a conductive paste containing glass and metal components is applied by a method such as dipping, and then a baking process is performed to form the baked layer as the base electrode layer 32. The temperature of the baking process at this time is preferably 700°C to 900°C. In this embodiment, the base electrode layer 32 is formed of a baked layer.

[0106] Furthermore, if the base electrode layer 32 is formed by a baked layer, the baked layer may contain ceramic components. In this case, ceramic components may be included instead of glass components, or both may be included.

[0107] The ceramic component is preferably the same type of ceramic material as the laminate 12. When the ceramic component is included in the baking layer, it is preferable to apply a conductive paste to the laminate chip before firing, and then bake (fire) the laminate chip and the conductive paste applied to the laminate chip simultaneously to form the laminate 12 with the baking layer. The baking temperature at this time is preferably 900°C or higher and 1400°C or lower.

[0108] (b) In the case of a conductive resin layer, if the base electrode layer 32 is formed of a conductive resin layer, the conductive resin layer can be formed by the following method. The conductive resin layer may be formed on the surface of the baked layer, or the conductive resin layer may be formed directly on the laminate 12 by itself without forming a baked layer.

[0109] The conductive resin layer is formed by applying a conductive resin paste containing a thermosetting resin and metal components onto the baked layer or the laminate 12, and then heat-treating it at a temperature of 250°C to 550°C to heat-cur the resin. The atmosphere during this heat treatment is preferably an N2 atmosphere. Furthermore, to prevent resin scattering and oxidation of the various metal components, the oxygen concentration is preferably kept below 100 ppm.

[0110] Furthermore, as a method for applying the conductive resin paste, similar to the method of forming the base electrode layer 32 with a baking layer, the conductive resin paste can be formed using, for example, a dip method.

[0111] (c) In the case of a thin film layer, if the base electrode layer 32 is formed as a thin film layer, the base electrode layer can be formed by covering areas other than the desired location for forming the external electrode 30 with masking, etc., and then applying a thin film formation method such as sputtering or vapor deposition to the exposed desired location. The base electrode layer formed as a thin film layer shall be a layer of 1 μm or less in thickness with metal particles deposited on it.

[0112] (Preparation of Plating Layer) Finally, the plating layer 34 is formed. The plating layer 34 may be formed on the surface of the base electrode layer 32, or it may be formed directly on the laminate 12. In this embodiment, the plating layer 34 is formed on the surface of the base electrode layer 32. More specifically, a Ni plating layer is formed on the base electrode layer 32 as the lower plating layer and a Sn plating layer is formed as the upper plating layer. When performing the plating process, either electrolytic plating or electroless plating may be used. However, electroless plating has the disadvantage of requiring pretreatment with a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, it is generally preferable to use electrolytic plating.

[0113] As described above, the two-terminal type multilayer ceramic capacitor 10 of the first embodiment is manufactured.

[0114] B. Second Embodiment 1. Three-Terminal Multilayer Ceramic Capacitor As a multilayer ceramic capacitor according to the second embodiment of the present invention, a three-terminal multilayer ceramic capacitor 110 will be described with reference to Figures 7 to 14.

[0115] Figure 7 is an external perspective view showing an example of a three-terminal multilayer ceramic capacitor according to a second embodiment of the present invention. Figure 8 is a top view showing an example of a three-terminal multilayer ceramic capacitor according to a second embodiment of the present invention. Figure 9 is a bottom view showing an example of a three-terminal multilayer ceramic capacitor according to a second embodiment of the present invention. Figure 10 is a front view showing an example of a three-terminal multilayer ceramic capacitor according to a second embodiment of the present invention. Figure 11 is a cross-sectional view taken along line XI-XI in Figure 7. Figure 12 is a cross-sectional view taken along line XII-XII in Figure 7. Figure 13 is a cross-sectional view taken along line XIII-XIII in Figure 10. Figure 14 is a cross-sectional view taken along line XIV-XIV in Figure 10.

[0116] As shown in Figures 7 to 12, the three-terminal multilayer ceramic capacitor 110 includes, for example, a laminate 112 and an external electrode 130.

[0117] The laminate 112 has a plurality of stacked dielectric layers 114 and a plurality of internal electrode layers 116 stacked on the dielectric layers 114. The internal electrode layer 116 has a first internal electrode layer 116a and a second internal electrode layer 116b. Details of the first internal electrode layer 116a and the second internal electrode layer 116b will be described later.

[0118] The laminate 112 has a first surface 112a and a second surface 112b that are opposite to the stacking direction x, a third surface 112c and a fourth surface 112d that are opposite to the first direction y which is perpendicular to the stacking direction x, and a fifth surface 112e and a sixth surface 112f that are opposite to the second direction z which is perpendicular to the stacking direction x and the first direction y.

[0119] The laminate 112 has a rectangular parallelepiped shape, and it is preferable that the corners and edges of the laminate 112 are rounded. The corners are the parts where three faces of the laminate 112 intersect, and the edges are the parts where two faces of the laminate 112 intersect. In addition, some or all of the first face 112a and the second face 112b, the third face 112c and the fourth face 112d, and the fifth face 112e and the sixth face 112f may have irregularities or other features formed on them.

[0120] Here, the dimension of the laminate 112 in the first direction y is denoted as dimension l, the dimension of the laminate 112 in the second direction z is denoted as dimension w, and the dimension of the laminate 112 in the stacking direction x is denoted as dimension t.

[0121] The laminate 112 includes a volume-forming portion 118, and a first outer layer portion 120a located on the first surface 112a side and a second outer layer portion 120b located on the second surface 112b side, which are arranged to sandwich the volume-forming portion 118 in the stacking direction x.

[0122] In the capacitance forming section 118, a first internal electrode layer 116a and a second internal electrode layer 116b are alternately stacked via a dielectric layer 114.

[0123] Furthermore, as shown in Figures 11 and 13, the laminate 112 has a first pull-out portion 123a located between the volume-forming portion 118 and the third surface 112c, and a second pull-out portion 123b located between the volume-forming portion 118 and the fourth surface 112d. The first pull-out portion 123a and the second pull-out portion 123b are also called L-gap.

[0124] As shown in Figures 12 and 14, the laminate 112 has a third pull-out portion 124a located between the volume-forming portion 118 and the fifth surface 112e, and a fourth pull-out portion 124b located between the volume-forming portion 118 and the sixth surface 112f. The third pull-out portion 124a and the fourth pull-out portion 124b are also called a W gap.

[0125] The first outer layer 120a is located on the first surface 112a side of the laminate 112 and is an assembly of multiple dielectric layers 114 located between the first surface 112a and the capacitance forming portion 118 closest to the first surface 112a. The second outer layer 120b is located on the second surface 112b side of the laminate 112 and is an assembly of multiple dielectric layers 114 located between the second surface 112b and the capacitance forming portion 118 closest to the second surface 112b. Furthermore, the region sandwiched between the first outer layer 120a and the second outer layer 120b is the capacitance forming portion 118.

[0126] The material of the dielectric layer 114 is the same as that of the two-terminal multilayer ceramic capacitor 10, so its explanation is omitted. Also, the average thickness of the dielectric layer 114 in the stacking direction x after firing is the same as that of the two-terminal multilayer ceramic capacitor 10, so its explanation is omitted.

[0127] (Internal Electrode Layers) The laminate 112 has a plurality of internal electrode layers 116, consisting of a plurality of first internal electrode layers 116a and a plurality of second internal electrode layers 116b. The plurality of first internal electrode layers 116a and the plurality of second internal electrode layers 116b are substantially parallel to the first main surface 112a and the second main surface 112b, and are embedded so as to be alternately arranged along the stacking direction x of the laminate 112 with the dielectric layer 114 in between.

[0128] The first internal electrode layer 116a is arranged on a plurality of dielectric layers 114. The first internal electrode layer 116a is also drawn out to a third surface 112c and a fourth surface 112d.

[0129] More specifically, as shown in Figure 13, the first internal electrode layer 116a extends between the third surface 112c and the fourth surface 112d of the laminate 112 and has a first opposing electrode portion 125a located in its central part, a first extracted electrode portion 126a extending from the first opposing electrode portion 125a and drawn out to the third surface 112c of the laminate 112, and a second extracted electrode portion 126b extending from the first opposing electrode portion 125a and drawn out to the fourth surface 112d of the laminate 112. The first opposing electrode portion 125a is located in the central part of the dielectric layer 114. The first extracted electrode portion 126a is exposed to the third surface 112c of the laminate 112, and the second extracted electrode portion 126b is exposed to the fourth surface 112d of the laminate 112. Therefore, the first internal electrode layer 116a is not exposed to the fifth surface 112e and the sixth surface 112f of the laminate 112.

[0130] The shape of the first internal electrode layer 116a is not particularly limited, but it is preferably rectangular in plan view. Similarly, the shapes of the first opposing electrode portion 125a, the first leading electrode portion 126a, and the second leading electrode portion 126b of the first internal electrode layer 116a are not particularly limited, but they are preferably rectangular in plan view. However, the corners may be rounded.

[0131] The second internal electrode layer 116b is arranged on a plurality of dielectric layers 114. The second internal electrode layer 116b is also drawn out to a fifth surface 112e and a sixth surface 112f. The second internal electrode layer 116b is arranged on a dielectric layer 114 that is different from the dielectric layer 114 on which the first internal electrode layer 116a is arranged.

[0132] More specifically, as shown in Figure 14, the second internal electrode layer 116b extends between the fifth surface 112e and the sixth surface 112f of the laminate 112 and has a second opposing electrode portion 125b located in its central part, a first extension portion 127a extending from the second opposing electrode portion 125b and drawn out to the fifth surface 112e, and a second extension portion 127b extending from the second opposing electrode portion 125b and drawn out to the sixth surface 112f. The second opposing electrode portion 125b is formed in a rectangular shape so as to extend in the direction of the third surface 112c and in the direction of the fourth surface 112d. The second opposing electrode portion 125b is located in the central part of the dielectric layer 114. The first extension 127a is exposed to the fifth surface 112e of the laminate 112, and the second extension 127b is exposed to the sixth surface 112f of the laminate 112. Therefore, the second internal electrode layer 116b is not exposed to the third surface 112c and the fourth surface 112d of the laminate 112.

[0133] The shapes of the second opposing electrode portion 125b, the first extension portion 127a, and the second extension portion 127b of the second internal electrode layer 116b are not particularly limited, but are preferably rectangular in plan view. However, the corners may be rounded.

[0134] The first opposing electrode portion 125a of the first internal electrode layer 116a and the second opposing electrode portion 125b of the second internal electrode layer 116b are facing each other. In this embodiment, the first opposing electrode portion 125a of the first internal electrode layer 116a and the second opposing electrode portion 125b of the second internal electrode layer 116b face each other via the dielectric layer 114, thereby forming capacitance and exhibiting capacitor characteristics.

[0135] The composition of the materials of the first internal electrode layer 116a and the second internal electrode layer 116b, and the composition within the layer in the stacking direction x, are the same as those of the first internal electrode layer 16a and the second internal electrode layer 16b of the two-terminal type multilayer ceramic capacitor 10 of the first embodiment.

[0136] The thickness of the first internal electrode layer 116a is not particularly limited, but is preferably, for example, 0.38 μm or more and 0.45 μm or less. The thickness of the second internal electrode layer 116b is not particularly limited, but is preferably, for example, 0.38 μm or more and 0.45 μm or less.

[0137] The total number of the first internal electrode layer 116a and the second internal electrode layer 116b is preferably 325 to 660. The number of the first internal electrode layer 116a is not particularly limited, but is preferably 162 to 330. The number of the second internal electrode layer 116b is not particularly limited, but is preferably 163 to 330.

[0138] At least one of the first internal electrode layer 116a located in the first extraction portion 123a and the first internal electrode layer 116a located in the second extraction portion 123b has a Ni-O oxide region 140.

[0139] The Ni-O oxide region 140 located in at least one of the first internal electrode layer 116a located in the first extraction portion 123a and the first internal electrode layer 116b located in the second extraction portion 123b has an O / Ni ratio of 0.05 or more and 0.47 or less.

[0140] The Ni-O oxide regions 140 located in the first internal electrode layer 116a at the first extraction portion 123a and the second extraction portion 123b reduce the amount of Ni contained in the first internal electrode layer 116 that diffuses into the Cu contained in the base electrode layer 132 of the external electrode 130 during the baking of the external electrode 130. This reduces the diffusion of hydrogen to the capacitance forming portion 118 via the Ni diffused in the external electrode 130, thereby suppressing the deterioration of insulation resistance.

[0141] Preferably, the oxygen concentration of the dielectric layer 114 in the region within 0.5 μm from the third surface 112c (surface region) is higher than the oxygen concentration of the dielectric layer 114 in the region between 2 μm and 5 μm from the third surface 112c (inner region). Similarly, preferably, the oxygen concentration of the dielectric layer 114 in the region within 0.5 μm from the fourth surface 112d (surface region) is higher than the oxygen concentration of the dielectric layer 114 in the region between 2 μm and 5 μm from the fourth surface 112 (inner region).

[0142] Preferably, the dielectric layer 114 in the region within 0.5 μm from the third surface 112c (surface region) has an O / Ti ratio of 0.97 or more and 1.64 or less, and the dielectric layer 114 in the region between 2 μm and 5 μm from the third surface 112c (inner region) has an O / Ti ratio of 0.68 or more and 0.93 or less. Similarly, preferably, the dielectric layer 114 in the region within 0.5 μm from the fourth surface 112d (surface region) has an O / Ti ratio of 0.97 or more and 1.64 or less, and the dielectric layer 114 in the region between 2 μm and 5 μm from the fourth surface 112d (inner region) has an O / Ti ratio of 0.68 or more and 0.93 or less.

[0143] The ratio of the O / Ti ratio of the dielectric layer 114 in the region within 0.5 μm from the third surface 112c (surface region) to the O / Ti ratio of the dielectric layer 114 in the region between 2 μm and 5 μm from the third surface 112c (inner region) is between 1.43 and 1.76. Similarly, the ratio of the O / Ti ratio of the dielectric layer 114 in the region within 0.5 μm from the fourth surface 112d (surface region) to the O / Ti ratio of the dielectric layer 114 in the region between 2 μm and 5 μm from the fourth surface 112d (inner region) is between 1.43 and 1.76.

[0144] At least one of the second internal electrode layer 116b located in the third extraction portion 124a and the second internal electrode layer 116b located in the fourth extraction portion 124b has a Ni-O oxide region 140.

[0145] The Ni-O oxide region 140 located in at least one of the second internal electrode layer 116b located in the third extraction portion 124a and the second internal electrode layer 116b located in the fourth extraction portion 124b has an O / Ni ratio of 0.05 or more and 0.47 or less.

[0146] The Ni-O oxide regions 140 located in the second internal electrode layer 116b at the third and fourth extraction portions 124a and 124b reduce the amount of Ni contained in the internal electrode layer 116 that diffuses into the Cu contained in the base electrode layer 132 of the external electrode 130 during the baking of the external electrode 130. This reduces the diffusion of hydrogen to the capacitance forming portion 118 via the Ni diffused in the external electrode 130, thereby suppressing the deterioration of insulation resistance.

[0147] The oxygen concentration of the dielectric layer 114 in the region within 0.5 μm from the fifth surface 112e (surface region) is preferably higher than the oxygen concentration of the dielectric layer 114 in the region between 2 μm and 5 μm from the fifth surface 112e (inner region). Similarly, the oxygen concentration of the dielectric layer 114 in the region within 0.5 μm from the sixth surface 112f (surface region) is preferably higher than the oxygen concentration of the dielectric layer 114 in the region between 2 μm and 5 μm from the sixth surface 112f (inner region).

[0148] Preferably, the dielectric layer 114 in the region within 0.5 μm from the fifth surface 112e (surface region) has an O / Ti ratio of 0.97 or more and 1.64 or less, and the dielectric layer 114 in the region between 2 μm and 5 μm from the fifth surface 112e (inner region) has an O / Ti ratio of 0.68 or more and 0.93 or less. Similarly, preferably, the dielectric layer 114 in the region within 0.5 μm from the sixth surface 112f (surface region) has an O / Ti ratio of 0.97 or more and 1.64 or less, and the dielectric layer 114 in the region between 2 μm and 5 μm from the sixth surface 112f (inner region) has an O / Ti ratio of 0.68 or more and 0.93 or less.

[0149] The ratio of the O / Ti ratio of the dielectric layer 114 in the region within 0.5 μm from the fifth surface 112e (surface region) to the O / Ti ratio of the dielectric layer 114 in the region between 2 μm and 5 μm from the fifth surface 112e (inner region) is between 1.43 and 1.76. Similarly, the ratio of the O / Ti ratio of the dielectric layer 114 in the region within 0.5 μm from the sixth surface 112f (surface region) to the O / Ti ratio of the dielectric layer 114 in the region between 2 μm and 5 μm from the sixth surface 112f (inner region) is between 1.43 and 1.76.

[0150] (External electrodes) External electrodes 130 are arranged on the third surface 112c and the fourth surface 112d, and on the fifth surface 112e and the sixth surface 112f of the laminate 112. The external electrodes 130 include a first external electrode 130a, a second external electrode 130b, a third external electrode 130c, and a fourth external electrode 130d.

[0151] The first external electrode 130a is connected to the first internal electrode layer 116a and is positioned on the third surface 112c. Therefore, the first lead portion 123a described above is located between the capacitance forming portion 118 and the first external electrode 130a. The first external electrode 130a may also be positioned on a part of the first surface 112a, a part of the second surface 112b, a part of the fifth surface 112e, and a part of the sixth surface 112f. In this case, the first external electrode 130a is electrically connected to the first lead electrode portion 126a of the first internal electrode layer 116a.

[0152] The second external electrode 130b is connected to the first internal electrode layer 116a and is positioned on the fourth surface 112d. Therefore, the second lead portion 123b described above is located between the capacitance forming portion 118 and the second external electrode 130b. The second external electrode 130b may also be positioned on a part of the first surface 112a, a part of the second surface 112b, a part of the fifth surface 112e, and a part of the sixth surface 112f. In this case, the second external electrode 130b is electrically connected to the second lead electrode portion 126b of the first internal electrode layer 116a.

[0153] The third external electrode 130c is connected to the second internal electrode layer 116b and positioned on the fifth surface 112e. Therefore, the third lead-out portion 124a described above is located between the capacitance forming portion 118 and the third external electrode 130c. The third external electrode 130c may also have a first covering portion 130c1 that covers the second internal electrode layer 116b exposed on the fifth surface 112e, a first folded portion 130c2 formed on the first surface 112a parallel to the second internal electrode layer 116b, and a second folded portion 130c3 formed on the second surface 112b parallel to the second internal electrode layer 116b. Having the second folded portion 130c3 allows for better maintenance of electrical connection reliability with the mounting substrate. In this case, the third external electrode 130c is electrically connected to the first extension portion 127a.

[0154] The fourth external electrode 130d is connected to the second internal electrode layer 116b and positioned on the sixth surface 112f. Therefore, the fourth lead-out portion 124b described above is located between the capacitance forming portion 118 and the fourth external electrode 130d. The fourth external electrode 130d is also connected to the second internal electrode layer 116b. Furthermore, the fourth external electrode 130d may have a second covering portion 130d1 (not shown) that covers the second internal electrode layer 116b exposed on the sixth surface 112f, a third folded portion 130d2 formed on the first surface 112a parallel to the second internal electrode layer 116b, and a fourth folded portion 130d3 formed on the second surface 112b parallel to the second internal electrode layer 116b. Having the fourth folded portion 130d3 allows for better maintenance of electrical connection reliability with the mounting substrate. In this case, the fourth external electrode 130d is electrically connected to the second extension 127b.

[0155] The external electrode 130 includes a base electrode layer 132 disposed on the surface of the laminate 112 and a plating layer 134 disposed to cover the base electrode layer 132.

[0156] The base electrode layer 132 includes a first base electrode layer 132a, a second base electrode layer 132b, a third base electrode layer 132c, and a fourth base electrode layer 132d.

[0157] The plating layer 134 has a first plating layer 134a, a second plating layer 134b, a third plating layer 134c, and a fourth plating layer 134d.

[0158] In other words, the first external electrode 130a has a first base electrode layer 132a and a first plating layer 134a. The second external electrode 130b has a second base electrode layer 132b and a second plating layer 134b. The third external electrode 130c has a third base electrode layer 132c and a third plating layer 134c. The fourth external electrode 130d has a fourth base electrode layer 132d and a fourth plating layer 134d.

[0159] The first base electrode layer 132a is placed on the surface of the third surface 112c of the laminate 112 and is formed to extend from the third surface 112c and cover a portion of each of the first surface 112a, the second surface 112b, the fifth surface 112e, and the sixth surface 112f. The second base electrode layer 132b is placed on the surface of the fourth surface 112d of the laminate 112 and is formed to extend from the fourth surface 112d and cover a portion of each of the first surface 112a, the second surface 112b, the fifth surface 112e, and the sixth surface 112f. The first base electrode layer 132a may be placed only on the surface of the third surface 112c of the laminate 112, and the second base electrode layer 132b may be placed only on the surface of the fourth surface 112d of the laminate 112.

[0160] The third base electrode layer 132c is placed on the surface of the fifth surface 112e of the laminate 112 and is formed to extend from the fifth surface 112e and cover parts of the first surface 112a and the second surface 112b, respectively. The fourth base electrode layer 132d is placed on the surface of the sixth surface 112f of the laminate 112 and is formed to extend from the sixth surface 112f and cover parts of the first surface 112a and the second surface 112b, respectively.

[0161] The base electrode layer 132 includes at least one selected from a baked layer, a conductive resin layer, a thin film layer, etc. The configurations of the base electrode layer 132 when it is a baked layer, a conductive resin layer, or a thin film layer will be described below.

[0162] (In the case of a baked layer) The baked layer contains a glass component and a metal component. The glass component of the baked layer contains at least one selected from B, Si, Ba, Mg, Al, Li, etc. The metal component of the baked layer contains at least one selected from, for example, Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The baked layer may consist of multiple layers. The baked layer is obtained by applying a conductive paste containing the glass component and the metal component to the laminate 112 and baking it. The baked layer may be obtained by simultaneously baking the laminate chip having the internal electrode layer 116 and the dielectric layer 114 and the conductive paste applied to the laminate chip, or by baking the laminate chip having the internal electrode layer 116 and the dielectric layer 114 to obtain the laminate 112, and then applying the conductive paste to the laminate 112 and baking it.

[0163] Furthermore, when firing a laminated chip having an internal electrode layer 116 and a dielectric layer 114 and a conductive paste applied to the laminated chip simultaneously, it is preferable to form the firing layer by firing a material to which a dielectric material has been added instead of a glass component.

[0164] Preferably, the thickness of the first base electrode layer 132a located on the third surface 112c in the first direction y connecting the third surface 112c and the fourth surface 112d at the center of the lamination direction x is 10 μm or more and 30 μm or less. Also, preferably, the thickness of the second base electrode layer 132b located on the fourth surface 112d in the first direction y connecting the third surface 112c and the fourth surface 112d at the center of the lamination direction x is 10 μm or more and 30 μm or less.

[0165] When the first base electrode layer 132a is provided on a part of the first surface 112a and a part of the second surface 112b, and a part of the fifth surface 112e and a part of the sixth surface 112f, the thickness in the stacking direction x connecting the first surface 112a and the second surface 112b at the center of the first direction y connecting the third surface 112c and the fourth surface 112d of the first base electrode layer 132a located on the first surface 112a and the second surface 112b is preferably, for example, 3 μm or more and 10 μm or less. Furthermore, the thickness of the first underlay electrode layer 132a located on the fifth surface 112e and the sixth surface 112f in the second direction z connecting the fifth surface 112e and the sixth surface 112f at the center of the first direction y connecting the third surface 112c and the fourth surface 112d is preferably, for example, 3 μm or more and 10 μm or less.

[0166] Furthermore, when a second base electrode layer 132b is provided on a part of the first surface 112a and a part of the second surface 112b, and a part of the fifth surface 112e and a part of the sixth surface 112f, the thickness in the stacking direction x connecting the first surface 112a and the second surface 112b at the center of the first direction y connecting the third surface 112c and the fourth surface 112d of the second base electrode layer 132b located on the first surface 112a and the second surface 112b is preferably, for example, 3 μm or more and 10 μm or less. Furthermore, the thickness of the second underlay electrode layer 132b located on the fifth surface 112e and the sixth surface 112f in the second direction z connecting the fifth surface 112e and the sixth surface 112f at the center of the first direction y connecting the third surface 112c and the fourth surface 112d is preferably, for example, 3 μm or more and 10 μm or less.

[0167] Preferably, the thickness in the second direction z connecting the fifth surface 112e and the sixth surface 112f at the center of the first direction y connecting the third surface 112c and the fourth surface 112d of the third base electrode layer 132c, located on the fifth surface 112e, is 10 μm or more and 30 μm or less. Also, preferably, the thickness in the second direction z connecting the fifth surface 112e and the sixth surface 112f at the center of the first direction y connecting the third surface 112c and the fourth surface 112d of the fourth base electrode layer 132d, located on the sixth surface 112f, is 10 μm or more and 30 μm or less.

[0168] The thickness of the third base electrode layer 132c, located on the first surface 112a and the second surface 112b, in the lamination direction x connecting the first surface 112a and the second surface 112b at the center of the first direction y connecting the third surface 112c and the fourth surface 112d, is preferably, for example, 3 μm or more and 10 μm or less. Similarly, the thickness of the fourth base electrode layer 132d, located on the first surface 112a and the second surface 112b, in the lamination direction x connecting the first surface 112a and the second surface 112b at the center of the first direction y connecting the third surface 112c and the fourth surface 112d, is preferably, for example, 3 μm or more and 10 μm or less.

[0169] (In the case of a conductive resin layer) When a conductive resin layer is provided as the base electrode layer 132, the conductive resin layer may be arranged on top of the baking layer so as to cover the baking layer, or it may be arranged directly on the laminate 112 without providing a baking layer. Furthermore, the conductive resin layer may completely cover the baking layer, or it may cover only a part of the baking layer. In addition, there may be multiple conductive resin layers.

[0170] The conductive resin layer contains a thermosetting resin and a metal. Because the conductive resin layer contains a thermosetting resin, it is more flexible than a baked layer made of, for example, a plated film or a fired conductive paste. Therefore, even if the three-terminal multilayer ceramic capacitor 110 is subjected to physical shock or shock caused by thermal cycling, the conductive resin layer functions as a buffer layer, preventing cracks in the three-terminal multilayer ceramic capacitor 110.

[0171] The metals that can be included in the conductive resin layer include Ag, Cu, Ni, Sn, Bi, or alloys containing these metals. Alternatively, metal powder with an Ag coating on its surface can be used. When using metal powder with an Ag coating, it is preferable to use Cu, Ni, Sn, Bi, or alloys thereof as the metal powder. The reason for using Ag conductive metal powder is that Ag has the lowest resistivity among metals, making it suitable for electrode materials; and because Ag is a noble metal, it does not oxidize and has high weather resistance. Furthermore, it allows for the use of less expensive base metals while maintaining the above-mentioned properties of Ag.

[0172] Furthermore, the metals included in the conductive resin layer can be Cu or Ni that have been treated to prevent oxidation. Additionally, metal powders coated with Sn, Ni, or Cu can be used as the metals included in the conductive resin layer. When using metal powders coated with Sn, Ni, or Cu, it is preferable to use Ag, Cu, Ni, Sn, Bi, or alloys thereof as the metal powder.

[0173] The metals contained in the conductive resin layer are primarily responsible for the conductivity of the conductive resin layer. Specifically, conductive fillers come into contact with each other, forming an electrical pathway within the conductive resin layer.

[0174] The metal contained in the conductive resin layer can be spherical, flattened, or otherwise, but it is preferable to use a mixture of spherical and flattened metal powders.

[0175] As the resin for the conductive resin layer, various known thermosetting resins such as epoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin can be used. Among these, epoxy resin, which has excellent heat resistance, moisture resistance, and adhesion, is one of the most suitable resins.

[0176] Furthermore, it is preferable that the conductive resin layer contains a curing agent along with the thermosetting resin. When epoxy resin is used as the base resin, various known compounds such as phenolic, amine, acid anhydride, imidazole, active ester, and amide-imide compounds can be used as curing agents for the epoxy resin.

[0177] The thickest part of the conductive resin layer is preferably, for example, 20 μm or more and 40 μm or less.

[0178] (In the case of a thin film layer) When a thin film layer is provided as the base electrode layer 132, the thin film layer is formed by a thin film formation method such as sputtering or vapor deposition, and is a layer of 1 μm or less in thickness on which metal particles are deposited.

[0179] The plating layer 134 has a first plating layer 134a, a second plating layer 134b, a third plating layer 134c, and a fourth plating layer 134d.

[0180] The first plating layer 134a is arranged to cover the surface of the first base electrode layer 132a. The second plating layer 134b is arranged to cover the surface of the second base electrode layer 132b. The third plating layer 134c is arranged to cover the surface of the third base electrode layer 132c. The fourth plating layer 134d is arranged to cover the surface of the fourth base electrode layer 132d.

[0181] The plating layer 134 includes at least one selected from, for example, Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc. The plating layer 134 may be formed as a single layer or as multiple layers. When formed as multiple layers, for example, a two-layer structure of Ni plating and Sn plating is preferred. By making the layer that is in direct contact with the underlying electrode layer a plating layer made of Ni plating, in particular when the underlying electrode layer is a conductive resin layer, it is possible to prevent the underlying electrode layer from being corroded by the solder used for mounting when mounting the multilayer ceramic capacitor.

[0182] Furthermore, by making the upper layer of the Ni plating layer a Sn plating layer, the wettability of the solder used for mounting the three-terminal multilayer ceramic capacitor 110 to the mounting substrate is improved, making mounting easier.

[0183] The plating layer 134 preferably has a thickness of 1.0 μm or more and 6.0 μm or less per layer.

[0184] The external electrode 130 may be formed using only the plating layer without providing the underlayer electrode layer 132. Although not shown in the figures, a structure in which the plating layer is provided without the underlayer electrode layer 132 will be described below.

[0185] The first external electrode 130a, the second external electrode 130b, the third external electrode 130c, and the fourth external electrode 130d, or each of them, may have a plating layer directly formed on the surface of the laminate 112 without providing an underlay electrode layer 132. That is, the three-terminal multilayer ceramic capacitor 110 may have a structure that includes a plating layer electrically connected to the first internal electrode layer 116a and the second internal electrode layer 116b. In such a case, the plating layer may be formed after a catalyst is placed on the surface of the laminate 112 as a pretreatment.

[0186] Furthermore, when forming the plating layer directly on the laminate without providing a base electrode layer, the reduction in the thickness of the base electrode layer 132 can be used to lower the profile, i.e., to make the chip thinner, or to increase the thickness of the laminate 112, i.e., the thickness of the capacitance forming section, thereby improving the design flexibility of the thin chip.

[0187] The plating layer preferably includes a lower plating electrode formed on the surface of the laminate 112 and an upper plating electrode formed on the surface of the lower plating electrode. The lower plating electrode and the upper plating electrode each preferably contain at least one metal selected from, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, or Zn, or an alloy containing such a metal. Furthermore, the lower plating electrode is preferably formed using Ni, which has solder barrier properties, and the upper plating electrode is preferably formed using Sn or Au, which has good solder wettability.

[0188] Furthermore, for example, when the first internal electrode layer 116a and the second internal electrode layer 116b are formed using Ni, it is preferable that the lower plated electrode be formed using Cu, which has good bonding properties with Ni. The upper plated electrode may be formed as needed, and the first external electrode 130a, the second external electrode 130b, the third external electrode 130c, and the fourth external electrode 130d may each consist only of the lower plated electrode. The plating layer may have the upper plated electrode as the outermost layer, or other plated electrodes may be formed on the surface of the upper plated electrode.

[0189] In this case, when the external electrode 130 is formed using only the plating layer without providing the underlayer electrode layer 132, it is preferable that the thickness of each plating layer placed without the underlayer electrode layer 132 is 1.0 μm or more and 15.0 μm or less.

[0190] Furthermore, it is preferable that the plating layer does not contain glass. The metal content per unit volume of the plating layer is preferably 99% by volume or more.

[0191] The dimension in the first direction y of the three-terminal multilayer ceramic capacitor 110, including the laminate 112 and the external electrode 130, is defined as dimension L. Dimension L is preferably 1.0 mm or more and 1.3 mm or less. The dimension in the stacking direction x of the three-terminal multilayer ceramic capacitor 110, including the laminate 112 and the external electrode 130, is defined as dimension T. Dimension T is preferably 0.4 mm or more and 0.65 mm or less. The dimension in the second direction z of the three-terminal multilayer ceramic capacitor 110, including the laminate 12 and the external electrode 130, is defined as dimension W. Dimension W is preferably 0.4 mm or more and 0.95 mm or less.

[0192] The three-terminal multilayer ceramic capacitor 110 shown in Figure 7 provides the same effects as the two-terminal multilayer ceramic capacitor 10 shown in Figure 1.

[0193] 2. Next, we will explain the manufacturing method for a three-terminal multilayer ceramic capacitor.

[0194] First, a dielectric sheet for the dielectric layer and a conductive paste for the internal electrode layer are prepared. The dielectric sheet and the conductive paste for the internal electrode layer contain a binder and a solvent. The binder and solvent may be known substances.

[0195] Then, a conductive paste for the internal electrode layer is printed onto the dielectric sheet in a predetermined pattern, for example, by screen printing or gravure printing. This prepares a dielectric sheet with the pattern for the first internal electrode layer formed on it, and a dielectric sheet with the pattern for the second internal electrode layer formed on it.

[0196] More specifically, a gravure plate can be prepared for printing the first internal electrode layer and the second internal electrode layer, and the patterns for each internal electrode layer can be printed using a gravure printing machine.

[0197] Furthermore, regarding dielectric sheets, dielectric sheets for the outer layer that do not have the pattern of the internal electrode layer printed on them are also prepared.

[0198] Next, a predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked to form a portion that will become the second outer layer 120b on the second surface 112b side. Subsequently, the portion that will become the capacitance forming portion 118 formed in the above process is stacked on top of the portion that will become the second outer layer 120b. Next, a predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked on top of the portion that will become the capacitance forming portion 118 formed in the above process to form a portion that will become the first outer layer 120a on the first surface 112a side. This completes the production of the laminated sheet.

[0199] Next, the laminated sheets are pressed in the lamination direction by means of a hydrostatic press or other means to produce a laminated block.

[0200] The laminated block is then cut to a predetermined size, thereby producing laminated chips. At this time, the corners and edges of the laminated chips may be rounded by barrel polishing or other methods.

[0201] Next, the cut laminated chips are fired to produce the laminated body 112. The firing temperature depends on the materials of the dielectric layer 114 and the internal electrode layer 116, but is preferably between 900°C and 1400°C.

[0202] Subsequently, annealing is performed to promote grain growth and solid solution of additives. The annealing temperature depends on the materials of the dielectric layer and the internal electrode layer, but is preferably between 900°C and 1200°C.

[0203] (Re-oxidation treatment) Next, the annealed laminate 112 is subjected to a re-oxidation treatment. The conditions for the re-oxidation treatment are, for example, a heat treatment temperature of 700°C to 900°C and a heat treatment time of 30 minutes to 300 minutes. Furthermore, it is desirable to perform the heat treatment on the oxidation side in an atmosphere range of 10 to 100 times the equilibrium oxygen partial pressure (MPa) of Ni. As a result, Ni-O oxide regions 140 can be arranged in the first internal electrode layer 116a located in the first extraction portion 123a and the second extraction portion 123b, and Ni-O oxide regions 140 can be arranged in the second internal electrode layer 116b located in the third extraction portion 124a and the fourth extraction portion 124b. Furthermore, if the hydrogen concentration in the atmospheric gas is too low, i.e., the oxygen concentration is too high, excessive surface oxides will be generated, leading to a decrease in connectivity between the internal electrode layer and the external electrode, or the internal stress will increase due to oxidative expansion of the internal electrode, causing cracks to form. For this reason, it is desirable to perform the calcination on the oxidation side within a range of 100 times or less the equilibrium oxygen partial pressure (MPa) of Ni in the atmospheric gas.

[0204] As a result of the re-oxidation treatment described above, the O / Ni ratio in the Ni-O oxide region 140 located in the first internal electrode layer 116a at the first extraction portion 123a and the second extraction portion 123b can be arranged to be between 0.05 and 0.47, and the O / Ni ratio in the Ni-O oxide region 140 located in the second internal electrode layer 116b at the third extraction portion 124a and the fourth extraction portion 124b can be arranged to be between 0.05 and 0.47.

[0205] (Formation of external electrodes) (a) In the case of a baked layer, the following explanation assumes that the base electrode layer is formed by a baked layer. When forming a baked layer, a conductive paste containing glass components and metal is prepared, applied, and then a baking process is performed to form the base electrode layer.

[0206] A third base electrode layer 132c of the third external electrode 130c is formed on the fifth surface 112e of the laminate 112 obtained by firing, and a fourth base electrode layer 132d of the fourth external electrode 130d is formed on the sixth surface 112f of the laminate 112.

[0207] When forming a baked layer as the base electrode layer 132, a conductive paste containing glass and metal components is applied by methods such as extruding it through a slit or using a roller transfer method, and then a baking process is performed to form the baked layer as the base electrode layer 132. The temperature of the baking process at this time is preferably 700°C to 900°C. In this embodiment, the base electrode layer 132 is formed of a baked layer.

[0208] Here, various methods can be used for forming the baked layer. For example, a method can be used in which the orientation of the laminate 112 is aligned using a camera or magnet so that the fifth surface 112e or the sixth surface 112f is facing downwards, and then the laminate 112 is held with a holding jig, and conductive paste is extruded and applied through slits or holes. In this method, by increasing the amount of conductive paste extruded, the third base electrode layer 132c and the fourth base electrode layer 132d can be formed not only on the fifth surface 112e and the sixth surface 112f, but also on a part of the first surface 112a and a part of the second surface 112b.

[0209] Next, a first base electrode layer 132a of the first external electrode 130a is formed on the third surface 112c of the laminate 112 obtained by firing, and a second base electrode layer 132b of the second external electrode 130b is formed on the fourth surface 112d of the laminate 112. In this embodiment, the first base electrode layer 132a and the second base electrode layer 132b are formed using a dip method so as to extend not only to the third surface 112c and the fourth surface 112d, but also to a part of the first surface 112a, a part of the second surface 112b, a part of the fifth surface 112e, and a part of the sixth surface 112f.

[0210] The baking process may involve baking the first base electrode layer 132a of the first external electrode 130a, the second base electrode layer 132b of the second external electrode 130b, the third base electrode layer 132c of the third external electrode 130c, and the fourth base electrode layer 132d of the fourth external electrode 130d simultaneously, or the first base electrode layer 132a of the first external electrode 130a and the second base electrode layer 132b of the second external electrode 130b, the third base electrode layer 132c of the third external electrode 130c, and the fourth base electrode layer 132d of the fourth external electrode 130d separately.

[0211] Furthermore, if the base electrode layer 132 is formed by a baked layer, the baked layer may contain ceramic components. In this case, ceramic components may be included instead of glass components, or both may be included.

[0212] The ceramic component is preferably, for example, the same type of ceramic material as the laminate 112. When the ceramic component is included in the baking layer, it is preferable to apply a conductive paste to the laminate chip before firing, and then bake (fire) the laminate chip and the conductive paste applied to the laminate chip before firing simultaneously to form the laminate 112 with the baking layer. The baking temperature at this time is preferably 900°C or higher and 1400°C or lower.

[0213] (b) Conductive resin layer When the base electrode layer 132 is formed of a conductive resin layer, the conductive resin layer can be formed by the following method. The conductive resin layer may be formed on the surface of the baked layer, or the conductive resin layer may be formed directly on the laminate 112 by itself without forming a baked layer.

[0214] The conductive resin layer is formed by applying a conductive resin paste containing a thermosetting resin and metal components onto the baked layer or the laminate 112, and then heat-treating it at a temperature of 250°C to 550°C to heat-cur the resin. The atmosphere during this heat treatment is preferably an N2 atmosphere. Furthermore, to prevent resin scattering and oxidation of the various metal components, the oxygen concentration is preferably kept below 100 ppm.

[0215] Furthermore, the conductive resin paste can be applied using a method similar to the method of forming the base electrode layer 132 with a baked layer, such as a dipping method, a method of applying the conductive resin paste by extruding it through a slit, or a roller transfer method.

[0216] (c) Thin film layer Also, when the base electrode layer 132 is formed as a thin film layer, the base electrode layer can be formed by covering areas other than the desired location for forming the external electrode 130 by masking, etc., and then applying a thin film formation method such as sputtering or vapor deposition to the exposed desired location. The base electrode layer formed as a thin film layer shall be a layer of 1 μm or less in thickness in which metal particles are deposited.

[0217] (Preparation of Plating Layer) Finally, the plating layer 134 is formed. The plating layer 134 may be formed on the surface of the base electrode layer 132, or it may be formed directly on the laminate 112. In this embodiment, the plating layer 134 is formed on the surface of the base electrode layer 132. More specifically, a Ni plating layer is formed on the base electrode layer 132 as the lower plating layer and a Sn plating layer is formed as the upper plating layer. When performing the plating process, either electrolytic plating or electroless plating may be used. However, electroless plating has the disadvantage of requiring pretreatment with a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, it is generally preferable to use electrolytic plating.

[0218] As described above, the three-terminal multilayer ceramic capacitor 110 according to the second embodiment is manufactured.

[0219] C. Experimental Examples Next, in order to confirm the effectiveness of the two-terminal multilayer ceramic capacitor according to the present invention described above, experiments were conducted to check for moisture resistance reliability, presence or absence of cracks, and contact between the internal electrode layer and the external electrode, and each quality was confirmed.

[0220] (1) Specifications of the multilayer ceramic capacitor fabricated as a sample for Experimental Example 1 Multilayer ceramic capacitors, which are the samples for Comparative Examples 1 to 3 and Examples 1 to 3, were fabricated using the manufacturing method according to the above embodiment. ・Structure of the multilayer ceramic capacitor: Multilayer ceramic capacitor shown in Figure 1 ・Dimensions of the multilayer ceramic capacitor in the first direction: 1.25 mm ・Dimensions of the multilayer ceramic capacitor in the second direction: 0.85 mm ・Dimensions of the multilayer ceramic capacitor in the stacking direction: 0.45 mm ・Thickness of the internal electrode layer: 0.46 μm ・Number of first internal electrode layers: 230 ・Number of second internal electrode layers: 230 ・Thickness of the first outer layer: 30 μm ・Thickness of the second outer layer: 30 μm ・Dimensions of the L gap: 45 μm ・Dimensions of the W gap: 67 μm

[0221] (2) Method for preparing the experimental sample The sample for the example was prepared by the method for manufacturing a two-terminal multilayer ceramic capacitor according to the first embodiment. Specifically, the oxygen partial pressure in the re-oxidation treatment was changed to prepare a sample in which the O / Ni ratio in the Ni-O oxide region of the internal electrode layer of the lead-out section was increased.

[0222] (3) Evaluation Methods for Each Test For humidity resistance reliability, a PCBT (Pressure Cooker Bias Test) test was performed. The test conditions were 125°C and 95% RH relative humidity. In this environment, an insulation test was conducted by applying a 4V DC voltage between the external electrodes of the multilayer ceramic capacitors on each sample for 72 hours. After this insulation test, the insulation resistance value of the multilayer ceramic capacitors on each sample was measured. A sample was considered unsatisfactory (NG) if the insulation resistance value after the humidity test was two orders of magnitude lower than the insulation resistance value before the insulation test. 72 samples were used for each test. To check for cracks, the cross-section was polished and internal cracks were observed under a microscope. 100 samples were used for each test. For contact between the internal electrode layer and the external electrode, capacitance was measured and the number of samples with reduced capacitance was counted. 100 samples were used for each test.

[0223] (3) Measurement methods for O / Ni and O / Ti (3-1) Measurement method for O / Ni in the oxide region of Ni-O First, the LT cross section was exposed as the oxide region of Ni-O, and the location where NiO was formed was identified by backscattered electron images (acceleration voltage: 15.0 kV, field of view: 10,000x) obtained using a scanning electron microscope (for example, JEOL Ltd., model JSM-7800M) in a region of 0.5 μm to 5 μm from the third or fourth surface of the LT cross section. Next, EDX analysis was performed on the NiO identified by the backscattered electron image to detect the Ni and O elements, and their respective values ​​were measured. Then, the O / Ni ratio was calculated from the measured values. (3-2) Method for measuring O / Ti of the dielectric layer First, the LT cross section was exposed, and EDX analysis (acceleration voltage: 15.0 kV, field of view: 10,000x) was performed on the dielectric layer in the region within 0.5 μm from the third or fourth surface (surface region) of the LT cross section using a scanning electron microscope (for example, JEOL Ltd., model JSM-7800M) to detect Ti and O elements and measure their respective values. Then, the O / Ti ratio was calculated from the measured values. The O / Ti ratio of the dielectric layer 14 in the region between 2 μm and 5 μm from the third or fourth surface (inner region) was calculated in the same manner.

[0224] (4) The results of the evaluation are shown in Table 1. Table 1 shows the evaluation of the moisture resistance reliability of the multilayer ceramic capacitors of each sample in response to changes in O / Ni in Ni and O / Ti in the dielectric layer, as well as the results of determining the presence or absence of cracks and capacitance defects.

[0225]

[0226] According to Table 1, in Examples 1 to 3, the O / Ni ratio in the Ni-O oxide region is 0.05 to 0.47, so a predetermined amount of NiO is placed in the extraction portion. This reduces the amount of Ni from the internal electrode layer that diffuses into the Cu of the base electrode layer during external electrode firing. This reduces the diffusion of hydrogen into the capacitance formation portion via Ni diffused in the external electrode, thereby suppressing the deterioration of insulation resistance. Furthermore, by placing NiO in the internal electrode layer of the extraction portion, the diffusion of hydrogen to the capacitance formation portion via Ni in the internal electrode layer is reduced, thereby suppressing the deterioration of insulation resistance. As a result, it was confirmed that humidity resistance reliability can be improved. On the other hand, in Comparative Example 1, the O / Ni ratio in the Ni-O oxide region is 0.03, so a predetermined amount of NiO is not placed in the extraction portion. This is thought to have resulted in deteriorated insulation resistance, and as a result, there were defective samples in the humidity resistance reliability test.

[0227] Furthermore, as shown in Table 1, in Examples 1 to 3, the O / Ni ratio in the Ni-O oxide region is 0.05 to 0.47, which reduces the diffusion of Cu from the base electrode layer into Ni in the internal electrode layer during external electrode firing. As a result, it was confirmed that the occurrence of cracks due to volume expansion of the internal electrode layer is suppressed. On the other hand, in Comparative Example 1, the O / Ni ratio in the Ni-O oxide region is 0.03, and since a predetermined amount of NiO is not placed in the extraction portion, Cu from the base electrode layer can diffuse into Ni in the internal electrode layer during external electrode firing. As a result, there were samples in which cracks occurred due to volume expansion of the internal electrode layer.

[0228] Furthermore, as shown in Table 1, in Examples 1 to 3, the O / Ni ratio in the Ni-O oxide region was 0.05 to 0.47, so it was confirmed that even if a predetermined amount of NiO was placed in the extraction portion, there was no decrease in connectivity between the internal electrode layer and the external electrode. On the other hand, in Comparative Examples 2 and 3, the O / Ni ratio in the Ni-O oxide region was greater than 0.47, indicating that an excess of oxide was placed, resulting in decreased connectivity between the internal electrode layer and the external electrode, and thus some samples showed a decrease in capacitance.

[0229] From the above results, it became clear that achieving both moisture resistance reliability, crack suppression, and connectivity between the internal electrode layer and the external electrode is possible when the O / Ni ratio of the Ni-O oxide region located in the internal electrode layer of the lead-out portion in Examples 1 to 3 is 0.05 or more and 0.47 or less. Furthermore, it became clear that in Examples 1 to 3, the O / Ti ratio in the surface region of the dielectric layer is 0.97 or more and 1.64 or less, and the O / Ti ratio in the inner region of the dielectric layer is 0.68 or more and 0.93 or less.

[0230] As described above, embodiments of the present invention are disclosed in the above description, but the present invention is not limited thereto.

[0231] Including those described above, the present invention can be modified in various ways with respect to the configuration, shape, material, quantity, position or arrangement, etc., without departing from the scope of the technical idea and objectives of the present invention, and such modifications are included in the present invention.

[0232] 10 Two-terminal multilayer ceramic capacitor 110 Three-terminal multilayer ceramic capacitor 12, 112 Laminate 12a, 112a First surface 12b, 112b Second surface 12c, 112c Third surface 12d, 112d Fourth surface 12e, 112e Fifth surface 12f, 112f Sixth surface 14, 114 Dielectric layer 16, 116 Internal electrode layer 16a, 116a First internal electrode layer 16b, 116b Second internal electrode layer 18 Capacitance forming section 20a, 120a First outer layer section 20b, 120b Second outer layer section 23a, 123a First lead section 23b, 123b Second lead section 24a, 24b Side section 124a Third lead section 124b Fourth lead portion 25a, 125a First counter electrode portion 25b, 125b Second counter electrode portion 26a First lead electrode portion 26b Second lead electrode portion 127a First extension portion 127b Second extension portion 30, 130 External electrodes 30a, 130a First external electrodes 30b, 130b Second external electrodes 30c, 130c Third external electrodes 30d, 130d Fourth external electrodes 32, 132 Underlay electrodes 32a, 132a First underlay electrode layer 32b, 132b Second underlay electrode layer 32, 132c Third underlay electrode layer 32d, 132d Fourth underlay electrode layer 34, 134 Plating layer 34a, 134a First plating layer 34b, 134b Second plating layer 134c Third plating layer 134d Fourth plating layer x Lamination direction y First direction z Second direction

Claims

1. A laminate comprising a plurality of stacked dielectric layers and a plurality of internal electrode layers stacked on the dielectric layers, having a first surface and a second surface facing each other in the stacking direction, a third surface and a fourth surface facing each other in a first direction perpendicular to the stacking direction, and a fifth surface and a sixth surface facing each other in a second direction perpendicular to the stacking direction and the first direction; a first internal electrode layer disposed on the plurality of dielectric layers and drawn out to the third surface; a second internal electrode layer disposed on the plurality of dielectric layers and drawn out to the fourth surface; a first external electrode disposed on the third surface and connected to the first internal electrode layer; and a second external electrode disposed on the fourth surface and connected to the second internal electrode layer, wherein the laminate comprises a capacitance forming portion where the first internal electrode layer and the second internal electrode layer face each other and form a capacitance; and a first drawing portion located between the capacitance forming portion and the first external electrode. A multilayer ceramic capacitor comprising: a second lead portion located between the capacitance forming portion and the second external electrode, wherein at least one of the first internal electrode layer of the first lead portion and the second internal electrode layer of the second lead portion has a Ni-O oxide region, and the Ni-O oxide region has an O / Ni ratio of 0.05 or more and 0.47 or less.

2. The multilayer ceramic capacitor according to claim 1, wherein the oxygen concentration of the dielectric layer in a region within 0.5 μm from the third surface and the fourth surface is higher than the oxygen concentration of the dielectric layer in a region between 2 μm and 5 μm from the end faces of the third surface and the fourth surface.

3. The multilayer ceramic capacitor according to claim 2, wherein the dielectric layer in a region within 0.5 μm from the third and fourth surfaces has an O / Ti ratio of 0.97 or more and 1.64 or less, and the dielectric layer in a region between 2 μm and 5 μm from the third and fourth surfaces has an O / Ti ratio of 0.68 or more and 0.93 or less.

4. The multilayer ceramic capacitor according to claim 3, wherein the ratio of the O / Ti ratio of the dielectric layer in a region within 0.5 μm from the third and fourth surfaces to the O / Ti ratio of the dielectric layer in a region between 2 μm and 5 μm from the third and fourth surfaces is 1.43 or more and 1.76 or less.

5. A laminate comprising a plurality of stacked dielectric layers and a plurality of internal electrode layers stacked on the dielectric layers, having a first surface and a second surface facing each other in the stacking direction, a third surface and a fourth surface facing each other in a first direction perpendicular to the stacking direction, and a fifth surface and a sixth surface facing each other in a second direction perpendicular to the stacking direction and the first direction; a first internal electrode layer disposed on the plurality of dielectric layers and drawn out to the third surface and the fourth surface; a second internal electrode disposed on the plurality of dielectric layers and drawn out to the fifth surface and the sixth surface, and a first external electrode disposed on the third surface and connected to the first internal electrode layer; a second external electrode disposed on the fourth surface and connected to the first internal electrode layer; a third external electrode disposed on the fifth surface and connected to the second internal electrode layer; and a fourth external electrode disposed on the sixth surface and connected to the second internal electrode layer, wherein the plurality of internal electrode layers are The laminate comprises: a first internal electrode layer exposed on the third and fourth surfaces; a second internal electrode layer exposed on the fifth and sixth surfaces; a capacitance forming portion where the first internal electrode layer and the second internal electrode layer face each other to form a capacitance; a first extraction portion located between the capacitance forming portion and the first external electrode; a second extraction portion located between the capacitance forming portion and the second external electrode; a third extraction portion located between the capacitance forming portion and the third external electrode; and a fourth extraction portion located between the capacitance forming portion and the fourth external electrode, wherein at least one of the first internal electrode layer of the first extraction portion and the first internal electrode layer of the second extraction portion has a Ni-O oxide region; and at least one of the second internal electrode layer of the third extraction portion and the second internal electrode layer of the fourth extraction portion has a Ni-O oxide region. The Ni-O oxide region is a multilayer ceramic capacitor in which the O / Ni ratio is 0.05 or more and 0.47 or less.

6. The multilayer ceramic capacitor according to claim 5, wherein the oxygen concentration of the dielectric layer in a region within 0.5 μm from the third and fourth surfaces is higher than the oxygen concentration of the dielectric layer in a region between 2 μm and 5 μm from the third and fourth surfaces, and the oxygen concentration of the dielectric layer in a region within 0.5 μm from the fifth and sixth surfaces is higher than the oxygen concentration of the dielectric layer in a region between 2 μm and 5 μm from the fifth and sixth surfaces.

7. The dielectric layer in the region within 0.5 μm from the third and fourth surfaces has an O / Ti ratio of 0.97 or more and 1.64 or less; the dielectric layer in the region between 2 μm and 5 μm from the third and fourth surfaces has an O / Ti ratio of 0.68 or more and 0.93 or less; the dielectric layer in the region within 0.5 μm from the fifth and sixth surfaces has an O / Ti ratio of 0.97 or more and 1.64 or less; and the dielectric layer in the region between 2 μm and 5 μm from the fifth and sixth surfaces has an O / Ti ratio of 0.68 or more and 0.93 or less, according to claim 6.

8. The multilayer ceramic capacitor according to claim 7, wherein the ratio of the O / Ti ratio of the dielectric layer in a region within 0.5 μm from the third and fourth surfaces to the O / Ti ratio of the dielectric layer in a region between 2 μm and 5 μm from the third and fourth surfaces is 1.43 or more and 1.76 or less, and the ratio of the O / Ti ratio of the dielectric layer in a region within 0.5 μm from the fifth and sixth surfaces to the O / Ti ratio of the dielectric layer in a region between 2 μm and 5 μm from the fifth and sixth surfaces is 1.43 or more and 1.76 or less.

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