Multilayer ceramic electronic component

Abstract

The present invention provides a multilayer ceramic electronic component in which occurrence of cracks in a multilayer body can be suppressed.　This multilayer ceramic capacitor (1) comprises an insulating layer (71). The insulating layer (71) is formed so as to cover at least a part of a first main surface (TS1) of a multilayer body (10) and a part of a first external electrode (40A) and a second external electrode (40B) that are disposed on the first main surface (TS1) side. A first overlap ratio (LB1 / LA1), which is the ratio of a length (LB1) in the length direction from a first tip (92A) of a first covering part (91A) on the second end surface (LS2) side to a tip (74A) of the insulating layer (71) on the first end surface (LS1) side, to a length (LA1) in the length direction from the first tip (92A) of the first covering part (91A) to the first end surface (LS1), is 1.9-84%. A second overlap ratio (LB2 / LA2), which is the ratio of a length (LB2) in the length direction from a second tip (92A) of a second covering part (91B) on the first end surface (LS1) side to a tip (94B) of the insulating layer (71) on the second end surface (LS2) side, to a length (LA2) in the length direction from the second tip (92B) of the second covering part (91B) to the second end surface (LS2), is 1.9-84%.

Description

Multilayer ceramic electronic components

[0001] This invention relates to multilayer ceramic electronic components.

[0002] Conventional multilayer ceramic capacitors, as electronic components, have an outer layer made of ceramics on both main surfaces of the laminate. External electrodes are arranged on both end faces of the laminate so as to cover the outer layer. When such a multilayer ceramic capacitor is mounted on a substrate using a bonding material such as solder, cracks may occur in the laminate starting from the tips of the external electrodes when the multilayer ceramic capacitor is subjected to thermal cycling or when the substrate flexes due to voltage application, etc.

[0003] Patent Document 1 discloses a multilayer ceramic capacitor for addressing such cracks. In this multilayer ceramic capacitor, internal electrodes are embedded in layers within dielectric ceramics, and terminal electrodes (external electrodes) consisting of a base electrode, a Ni plating layer, and a Sn-containing plating layer are formed at both ends. Furthermore, in this multilayer ceramic capacitor, a portion of the contact end of the terminal electrode with the dielectric ceramics is covered with an electrical insulating layer that has low wettability to solder.

[0004] Japanese Patent Application Publication No. 9-180957

[0005] In the case of the multilayer ceramic capacitor described in Patent Document 1, stress is relieved, and the occurrence of cracks in the laminate can be suppressed. However, in the technology described in Patent Document 1, the appropriate arrangement of the electrical insulating layer has not been sufficiently considered, so the stress relief effect does not function well, and in some cases, sufficient crack resistance of the laminate against substrate deflection cannot be obtained.

[0006] Therefore, the present invention aims to provide a multilayer ceramic electronic component that can suppress the occurrence of cracks in the laminate.

[0007] The multilayer ceramic electronic component according to the present invention comprises a laminate, a first external electrode, a second external electrode, and an insulating layer. The laminate includes a plurality of dielectric layers and a plurality of internal conductor layers, and has a first main surface and a second main surface facing each other in the height direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the height direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the height direction and the width direction. The first external electrode is disposed on the first end surface side and has a first covering portion that covers a part of the first main surface on the first end surface side. The second external electrode is disposed on the second end surface side and has a second covering portion that covers a part of the first main surface on the second end surface side. The insulating layer is formed to cover at least a part of the first main surface of the laminate, and a part of the first external electrode and the second external electrode disposed on the first main surface side. The first overlap ratio (LB1 / LA1), which is the ratio of the length LB1 from the first tip of the first cover portion to the tip of the first end face of the insulating layer to the length LA1 from the first tip of the first cover portion to the first end face of the first end face of the first cover portion, is 1.9% or more and 84% or less. The second ratio (LB2 / LA2), which is the overlap ratio of the length LB2 from the second tip of the second cover portion to the tip of the second end face of the insulating layer to the length LA2 from the second tip of the second cover portion to the second end face of the first end face of the second cover portion, is 1.9% or more and 84% or less.

[0008] According to the present invention, it is possible to provide a multilayer ceramic electronic component that can suppress the occurrence of cracks in the laminate.

[0009] This is a first external perspective view of a multilayer ceramic capacitor according to the first embodiment. This is a second external perspective view of a multilayer ceramic capacitor according to the first embodiment. This is a cross-sectional view taken along line III-III in Figure 1. This is a cross-sectional view taken along line IV-IV in Figure 3. This is a cross-sectional view taken along line VA-VA in Figure 3. This is a cross-sectional view taken along line VB-VB in Figure 3. This is an external perspective view of the mounting structure of a multilayer ceramic capacitor. This is a partial longitudinal cross-sectional view of the mounting structure of a multilayer ceramic capacitor. This is a cross-sectional view of a multilayer ceramic capacitor according to the second embodiment. This is a diagram showing a double-gang multilayer ceramic capacitor. This is a diagram showing a triple-gang multilayer ceramic capacitor. This is a diagram showing a quadruple-gang multilayer ceramic capacitor.

[0010] Hereinafter, a multilayer ceramic capacitor 1 as a multilayer ceramic electronic component according to the present disclosure will be described with reference to the drawings. Figure 1 is a first external perspective view of the multilayer ceramic capacitor 1 according to the first embodiment. Figure 2 is a second external perspective view of the multilayer ceramic capacitor 1 according to the first embodiment. Figure 3 is a cross-sectional view taken along line III-III of Figure 1. Figure 4 is a cross-sectional view taken along line IV-IV of Figure 3. Figure 5A is a cross-sectional view taken along line VA-VA of Figure 3. Figure 5B is a cross-sectional view taken along line VB-VB of Figure 3.

[0011] As shown in Figures 1 and 2, the multilayer ceramic capacitor 1 according to this embodiment has a substantially rectangular parallelepiped shape. The multilayer ceramic capacitor 1 comprises a laminate 10 having a substantially rectangular parallelepiped shape, and a pair of external electrodes 40 arranged spaced apart from each other at both ends of the laminate 10.

[0012] In Figures 1 and 2, arrow T indicates the height direction of the multilayer ceramic capacitor 1 and the laminate 10. This height direction T is also the thickness direction and height direction of the multilayer ceramic capacitor 1 and the laminate 10. In Figures 1 and 2, arrow L indicates the length direction of the multilayer ceramic capacitor 1 and the laminate 10, perpendicular to the height direction T. In Figures 1 and 2, arrow W indicates the width direction of the multilayer ceramic capacitor 1 and the laminate 10, perpendicular to the height direction T and the length direction L. A pair of external electrodes 40 are arranged at one end and the other end of the laminate 10 in the length direction L, respectively.

[0013] Figures 1 to 5B show the XYZ Cartesian coordinate system. The length direction L of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the X direction. The width direction W of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Y direction. The height direction T of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Z direction. Here, the cross section shown in Figure 3 is also called the LT cross section. The cross section shown in Figure 4 is also called the WT cross section. The cross sections shown in Figures 5A and 5B are also called the LW cross section.

[0014] As shown in Figures 1 to 5B, the laminate 10 includes a first main surface TS1 and a second main surface TS2 that are opposite to the height direction T, a first end surface LS1 and a second end surface LS2 that are opposite to the length direction L which is perpendicular to the height direction T, and a first side surface WS1 and a second side surface WS2 that are opposite to the width direction W which is perpendicular to the height direction T and the length direction L.

[0015] The mounting surface of the multilayer ceramic capacitor 1 is the first main surface TS1. The mounting surface is the surface that faces the wiring board when the multilayer ceramic capacitor 1 is mounted on a wiring board or the like.

[0016] As shown in Figures 1 and 2, the laminate 10 has a substantially rectangular parallelepiped shape. The length L dimension of the laminate 10 is not necessarily longer than the width W dimension. It is preferable that the corners and edges of the laminate 10 are rounded. The corners are the parts where three faces of the laminate intersect, and the edges are the parts where two faces of the laminate intersect. Some or all of the surfaces constituting the laminate 10 may have irregularities or bumps formed on them.

[0017] The dimensions of the laminate 10 are not particularly limited, but if the length L of the laminate 10 is denoted as dimension L, then dimension L is preferably 0.1 mm or more and 10 mm or less, and more preferably 0.2 mm or more and 10 mm or less. If the height T of the laminate 10 is denoted as dimension T, then dimension T is preferably 0.05 mm or more and 10 mm or less. If the width W of the laminate 10 is denoted as dimension W, then dimension W is preferably 0.05 mm or more and 10 mm or less, and more preferably 0.1 mm or more and 10 mm or less.

[0018] As shown in Figures 3 and 4, the laminate 10 has an inner layer 11 and a first main surface-side outer layer 12 and a second main surface-side outer layer 13 arranged to sandwich the inner layer 11 in the height direction T.

[0019] The inner layer 11 includes a plurality of dielectric layers 20 as a plurality of ceramic layers and a plurality of internal electrode layers 30 as a plurality of internal conductor layers, which are alternately stacked in the height direction T. The inner layer 11 includes the internal electrode layer 30 located on the first main surface TS1 side to the internal electrode layer 30 located on the second main surface TS2 side in the height direction T. In the inner layer 11, the plurality of internal electrode layers 30 are arranged facing each other via the dielectric layers 20. The inner layer 11 is the part that generates capacitance and functions substantially as a capacitor.

[0020] Multiple dielectric layers 20 are composed of a dielectric material. The dielectric material is, for example, BaTiO ３ CaTiO ３ SrTiO ３ , or CaZrO ３The dielectric ceramic may contain components such as the above. Alternatively, the dielectric material may have minor components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds added to these main components. The dielectric material may have BaTiO as its main component. ３ It is particularly preferable that the material contains [a specific substance].

[0021] The thickness of the dielectric layer 20 is preferably 0.2 μm or more and 15 μm or less. The number of dielectric layers 20 to be stacked is preferably 15 or more and 1200 or less. This number of dielectric layers 20 is the sum of the number of dielectric layers 20 in the inner layer portion 11 and the number of dielectric layers 20 in the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13.

[0022] The multiple internal electrode layers 30 include a plurality of first internal electrode layers 31 as a plurality of first internal conductor layers and a plurality of second internal electrode layers 32 as a plurality of second internal conductor layers. The first internal electrode layers 31 and the second internal electrode layers 32 are alternately arranged in the height direction T with a dielectric layer 20 in between them. The first internal electrode layers 31 are led out to the second end face LS2. The second internal electrode layers 32 are led out to the first end face LS1. In the following, when it is not necessary to explain the first internal electrode layers 31 and the second internal electrode layers 32 separately, the first internal electrode layers 31 and the second internal electrode layers 32 may be collectively referred to as the internal electrode layer 30.

[0023] As shown in Figure 5A, the first internal electrode layer 31 has a first opposing portion 31A and a first leading portion 31B. The first opposing portion 31A is a region that faces the second internal electrode layer 32 with the dielectric layer 20 in between, and is located inside the laminate 10. The first leading portion 31B is a portion that is drawn out from the first opposing portion 31A to the second end face LS2, and is exposed to the second end face LS2.

[0024] As shown in Figure 5B, the second internal electrode layer 32 has a second opposing portion 32A and a second leading portion 32B. The second opposing portion 32A is a region that faces the first internal electrode layer 31 with the dielectric layer 20 in between, and is located inside the laminate 10. The second leading portion 32B is a portion that is drawn out from the second opposing portion 32A to the first end face LS1, and is exposed to the first end face LS1.

[0025] In this embodiment, capacitance is formed when the first opposing portion 31A and the second opposing portion 32A face each other via the dielectric layer 20, and the characteristics of a capacitor are exhibited.

[0026] The shapes of the first opposing portion 31A and the second opposing portion 32A are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed at an angle. The shapes of the first pull-out portion 31B and the second pull-out portion 32B are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed at an angle.

[0027] The widthwise dimension W of the first opposing portion 31A and the widthwise dimension W of the first drawer portion 31B may be the same, or one of them may be smaller. The widthwise dimension W of the second opposing portion 32A and the widthwise dimension W of the second drawer portion 32B may be the same, or one of them may be narrower.

[0028] The first internal electrode layer 31 and the second internal electrode layer 32 are made of a suitable conductive material such as metals like Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals. When using an alloy, the first internal electrode layer 31 and the second internal electrode layer 32 may be made of, for example, an Ag-Pd alloy.

[0029] The thickness of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably, for example, 0.2 μm or more and 2.0 μm or less. The total number of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably 10 or more and 1000 or less.

[0030] As shown in Figures 3 and 4, the first main surface-side outer layer 12 is located on the second main surface TS2 side of the laminate 10. The first main surface-side outer layer 12 is an assembly of multiple dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 closest to the second main surface TS2. On the other hand, the second main surface-side outer layer 13 is located on the first main surface TS1 side of the laminate 10. The second main surface-side outer layer 13 is an assembly of multiple dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 closest to the first main surface TS1. The dielectric layers 20 used in the first main surface-side outer layer 12 and the second main surface-side outer layer 13 may be the same as the dielectric layers 20 used in the inner layer 11.

[0031] The portion where the first opposing portion 31A of the first internal electrode layer 31 and the second opposing portion 32A of the second internal electrode layer 32 face each other is the opposing electrode portion, and is configured as part of the inner layer 11.

[0032] As shown in Figures 1, 2, and 3, the external electrode 40 includes a first external electrode 40A positioned on the first end face LS1 side of the laminate 10, and a second external electrode 40B positioned on the second end face LS2 side of the laminate 10.

[0033] The basic configurations of the first external electrode 40A and the second external electrode 40B are the same. Furthermore, the first external electrode 40A and the second external electrode 40B have shapes that are generally symmetrical with respect to the WT cross-section at the center of the length L of the multilayer ceramic capacitor 1. Therefore, in the following, when it is not necessary to explain the first external electrode 40A and the second external electrode 40B separately, the first external electrode 40A and the second external electrode 40B may be collectively referred to as the external electrode 40.

[0034] The first external electrode 40A is positioned on the first end face LS1. The first external electrode 40A is in contact with the second lead-out portion 32B of each of the multiple second internal electrode layers 32 exposed on the first end face LS1. As a result, the first external electrode 40A is electrically connected to the multiple second internal electrode layers 32. The first external electrode 40A may also be positioned on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as on a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the first external electrode 40A is formed extending from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as on a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0035] The second external electrode 40B is positioned on the second end face LS2. The second external electrode 40B is in contact with the first lead-out portion 31B of each of the multiple first internal electrode layers 31 exposed on the second end face LS2. As a result, the second external electrode 40B is electrically connected to the multiple first internal electrode layers 31. The second external electrode 40B may also be positioned on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the second external electrode 40B is formed extending from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0036] As described above, within the laminate 10, capacitance is formed when the first opposing portion 31A of the first internal electrode layer 31 and the second opposing portion 32A of the second internal electrode layer 32 face each other via the dielectric layer 20. Therefore, capacitor characteristics are exhibited between the first external electrode 40A to which the second internal electrode layer 32 is connected and the second external electrode 40B to which the first internal electrode layer 31 is connected.

[0037] As shown in FIGS. 3, 5A, and 5B, the first external electrode 40A includes a first base electrode layer 50A and a first plating layer 60A disposed on the first base electrode layer 50A. The second external electrode 40B includes a second base electrode layer 50B and a second plating layer 60B disposed on the second base electrode layer 50B.

[0038] The first base electrode layer 50A is disposed on the first end face LS1. The first base electrode layer 50A is connected to each second lead-out portion 32B of the plurality of second internal electrode layers 32 exposed on the first end face LS1. In the present embodiment, the first base electrode layer 50A is formed to extend from the first end face LS1 to a part of the first main surface TS1, a part of the second main surface TS2, a part of the first side surface WS1, and a part of the second side surface WS2.

[0039] The second base electrode layer 50B is disposed on the second end face LS2. The second base electrode layer 50B is in contact with each first lead-out portion 31B of the plurality of first internal electrode layers 31 exposed on the second end face LS2. In the present embodiment, the second base electrode layer 50B is formed to extend from the second end face LS2 to a part of the first main surface TS1, a part of the second main surface TS2, a part of the first side surface WS1, and a part of the second side surface WS2.

[0040] The first base electrode layer 50A and the second base electrode layer 50B of the present embodiment are baking layers. The baking layer preferably contains either a metal component and a glass component or a ceramic component, or both. The metal component includes at least one selected from, for example, Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The glass component includes at least one selected from, for example, B, Si, Ba, Mg, Al, Li, etc. The ceramic component may be the same type of ceramic material as the dielectric layer 20 or a different type of ceramic material. The ceramic component is, for example, BaTiO ３ 、CaTiO ３ 、(Ba,Ca)TiO ３ 、SrTiO ３ 、CaZrO ３It includes at least one selected from the following.

[0041] The baking layer is formed by, for example, applying a conductive paste containing glass and metal to the laminate 10 and baking it. The baking layer can be formed by co-firing the pre-fired laminated chip, which is the material of the laminate 10 having a plurality of internal electrodes and dielectric layers, and the conductive paste applied to the laminated chip. Alternatively, it may also be formed by baking the laminated chip to obtain the laminate 10 and then applying and baking a conductive paste to the laminate 10. In the case of the above co-fire, it is preferable to form the baking layer by baking a material obtained by adding a ceramic material instead of the glass component. In that case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the ceramic material to be added. Note that the baking layer may be a plurality of layers.

[0042] The thickness corresponding to the length direction L of the first base electrode layer 50A located on the first end face LS1 is preferably, for example, about 2 μm or more and 220 μm or less at the central portion in the height direction T and the width direction W of the first base electrode layer 50A.

[0043] The thickness corresponding to the length direction L of the second base electrode layer 50B located on the second end face LS2 is preferably, for example, about 2 μm or more and 220 μm or less at the central portion in the height direction T and the width direction W of the second base electrode layer 50B.

[0044] When the first base electrode layer 50A is provided on at least a part of one of the first main surface TS1 or the second main surface TS2, the thickness corresponding to the height direction T of the first base electrode layer 50A provided in this part is, for example, preferably about 3 μm or more and 40 μm or less at the central portion in the length direction L and the width direction W of the first base electrode layer 50A provided in this part.

[0045] When the first base electrode layer 50A is also provided on a portion of at least one of the first side surface WS1 or the second side surface WS2, the thickness of the first base electrode layer 50A provided in this portion, corresponding to the width direction W, is preferably, for example, 3 μm or more and 40 μm or less at the center of the length direction L and height direction T of the first base electrode layer 50A provided in this portion.

[0046] When a second base electrode layer 50B is provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, the thickness of the second base electrode layer 50B provided in this portion, corresponding to the height direction T, is preferably, for example, 3 μm to 40 μm, at the center of the length direction L and width direction W of the second base electrode layer 50B provided in this portion.

[0047] When a second base electrode layer 50B is provided on a portion of at least one of the first side surface WS1 or the second side surface WS2, the thickness of the second base electrode layer 50B provided in this portion, corresponding to the width direction W, is preferably, for example, 3 μm to 40 μm at the center of the length direction L and height direction T of the second base electrode layer 50B provided in this portion.

[0048] The first plating layer 60A is positioned to cover the first underlay electrode layer 50A.

[0049] The second plating layer 60B is positioned to cover the second under electrode layer 50B.

[0050] The first plating layer 60A and the second plating layer 60B may each contain at least one selected from, for example, Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc. The first plating layer 60A and the second plating layer 60B may each be formed by multiple layers. Preferably, the first plating layer 60A and the second plating layer 60B have a two-layer structure in which a Sn plating layer is formed on top of a Ni plating layer.

[0051] The first plating layer 60A comprises a first Ni plating layer 61A and a first Sn plating layer 62A located on the first Ni plating layer 61A.

[0052] The second plating layer 60B comprises a second Ni plating layer 61B and a second Sn plating layer 62B located on the second Ni plating layer 61B.

[0053] The Ni plating layer prevents the first and second base electrode layers 50A and 50B from being corroded by solder when mounting the multilayer ceramic capacitor 1. The Sn plating layer improves the wettability of the solder when mounting the multilayer ceramic capacitor 1. This facilitates the mounting of the multilayer ceramic capacitor 1. The thickness of each of the first Ni plating layer 61A, the first Sn plating layer 62A, the second Ni plating layer 61B and the second Sn plating layer 62B is preferably between 2 μm and 15 μm.

[0054] The external electrode 40 in this embodiment may, for example, have a conductive resin layer containing conductive particles and a thermosetting resin. The conductive resin layer may be arranged to cover the baking layer. When the conductive resin layer is arranged to cover the baking layer, the conductive resin layer is placed between the baking layer and the plating layer (first plating layer 60A, second plating layer 60B). The conductive resin layer may completely cover the baking layer or cover a part of the baking layer.

[0055] A conductive resin layer containing a thermosetting resin is more flexible than a conductive layer made of, for example, a plated film or a fired conductive paste. Therefore, even when the multilayer ceramic capacitor 1 is subjected to physical shock or shock caused by thermal cycling, the conductive resin layer functions as a buffer layer. Thus, the conductive resin layer suppresses the occurrence of cracks in the multilayer ceramic capacitor 1.

[0056] The metal constituting the conductive particles may be Ag, Cu, Ni, Sn, Bi, or alloys containing these. The conductive particles preferably contain Ag. The conductive particles are, for example, Ag metal powder. Ag has the lowest resistivity among metals, making it suitable as an electrode material. Furthermore, since Ag is a noble metal, it is resistant to oxidation and has high weather resistance. Therefore, Ag metal powder is suitable as conductive particles.

[0057] Furthermore, the conductive particles may be metal powders with an Ag coating on their surface. When using metal powders with an Ag coating on their surface, the metal powders are preferably Cu, Ni, Sn, Bi, or alloys thereof. It is preferable to use Ag-coated metal powders in order to maintain the properties of Ag while making the base metal less expensive.

[0058] Furthermore, the conductive particles may be Cu or Ni that have been treated to prevent oxidation. Alternatively, the conductive particles may be metal powder coated with Sn, Ni, or Cu on the surface of the metal powder. When using metal powder coated with Sn, Ni, or Cu on the surface, the metal powder is preferably Ag, Cu, Ni, Sn, Bi, or an alloy of these.

[0059] The shape of the conductive particles is not particularly limited. Conductive particles can have shapes such as spherical or flattened, but it is preferable to use a mixture of spherical metal powder and flattened metal powder.

[0060] The conductive particles contained in the conductive resin layer primarily play a role in ensuring the conductivity of the conductive resin layer. Specifically, the contact between multiple conductive particles forms an electrical pathway within the conductive resin layer.

[0061] The resin constituting the conductive resin layer may include at least one selected from various known thermosetting resins such as epoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin. Among these, epoxy resin, which has excellent heat resistance, moisture resistance, and adhesion, is one of the most suitable resins. Furthermore, it is preferable that the resin in the conductive resin layer includes a curing agent together with the thermosetting resin. When epoxy resin is used as the base resin, the curing agent for the epoxy resin may be various known compounds such as phenolic, amine, acid anhydride, imidazole, active ester, and amide-imide compounds.

[0062] The conductive resin layer may be formed from multiple layers. Preferably, the thickness of the thickest part of the conductive resin layer is 10 μm or more and 150 μm or less.

[0063] The above describes the basic configuration of the multilayer ceramic capacitor 1 according to the embodiment. If the length L dimension of the multilayer ceramic capacitor 1, including the laminate 10 and the external electrode 40, is denoted as dimension L, then it is preferable that dimension L is 0.2 mm or more and 6 mm or less. If the height T dimension of the multilayer ceramic capacitor 1 is denoted as dimension T, then it is preferable that dimension T is 0.05 mm or more and 5 mm or less. Furthermore, if the width W dimension of the multilayer ceramic capacitor 1 is denoted as dimension W, then it is preferable that dimension W is 0.1 mm or more and 5 mm or less.

[0064] Figure 6 shows the mounting structure 100 of the multilayer ceramic capacitor 1. Figure 6 is an external perspective view of the mounting structure of the multilayer ceramic capacitor. The mounting structure 100 is a structure in which the multilayer ceramic capacitor 1 is mounted on a mounting substrate 80, which will be described in detail later.

[0065] The first external electrode 40A will be explained in more detail using Figure 7. Figure 7 is a partial longitudinal cross-sectional view of the mounting structure of the multilayer ceramic capacitor.

[0066] As shown in Figure 7, the first external electrode 40A has a first covering portion 91A that covers a part of the first end face LS1 side of the first main surface TS1. The first covering portion 91A is also called the main surface side external electrode. Specifically, the first covering portion 91A extends continuously from the portion formed on the first end face LS1 of the first external electrode 40A. More specifically, the first covering portion 91A is formed over the entire width W of the first main surface TS1. The first covering portion 91A has a first tip 92A (the tip of the first covering portion 91A on the second end face LS2 side). The length L in the longitudinal direction from the first end face LS1 (position D1) to the first tip 92A (position D2) is defined as "length LA1".

[0067] The second external electrode 40B will be explained in more detail using Figure 8. Figure 8 is a partial longitudinal cross-sectional view of the mounting structure of the multilayer ceramic capacitor.

[0068] As shown in Figure 8, the second external electrode 40B has a second covering portion 91B that covers a part of the second end face LS2 side of the first main surface TS1. The second covering portion 91B is also called the main surface side external electrode. Specifically, the second covering portion 91B extends continuously from the portion formed on the second end face LS2 of the second external electrode 40B. More specifically, the second covering portion 91B is formed over the entire width W of the first main surface TS1. The second covering portion 91B has a second tip 92B (the tip of the second covering portion 91B on the second end face LS2 side). The length L in the longitudinal direction from the second end face LS2 (position D1) to the second tip 92B (position D2) is defined as "length LA2".

[0069] The multilayer ceramic capacitor 1 further comprises an insulating layer 71. Before describing the details of the insulating layer 71, the inventor of the present invention will explain how he came up with the configuration of the insulating layer 71.

[0070] Through repeated studies, experiments, and simulations, the inventors of this invention have found that, in order to improve the bending crack resistance of multilayer ceramic capacitors, it is desirable to arrange an insulating layer so as to cover at least a portion of the first main surface of the laminate and a portion of the first and second external electrodes located on the first main surface side, and furthermore, to ensure that the arrangement of the insulating layer, specifically the overlapping range between the external electrodes and the insulating layer, is appropriate. This point will be explained below.

[0071] In conventional multilayer ceramic capacitors, stress is relieved, and the occurrence of cracks in the laminate can be suppressed. However, in conventional technology, the appropriate arrangement of the electrical insulating layer has not been sufficiently considered, so the stress relief effect does not function properly, and in some cases, sufficient crack resistance of the laminate against substrate deflection cannot be obtained.

[0072] Considering the above, the inventors of the present invention diligently investigated arrangements of the resin layers that can improve resistance to bending cracks. As a result, the inventors of the present invention found that the configuration of this embodiment can improve resistance to bending cracks. Specifically, the inventors of the present invention found that resistance to bending cracks can be improved by making the arrangement of the insulating layers, the overlapping range between the external electrodes and the insulating layers appropriate.

[0073] The configuration of the insulating layer 71 in this embodiment will be described in detail below.

[0074] As shown in Figures 2, 6, 7, and 8, the insulating layer 71 is formed to cover at least a portion of the first main surface TS1 of the laminate 10 and a portion of the first external electrode 40A and the second external electrode 40B which are located on the side of the first main surface TS1.

[0075] Specifically, the insulating layer 71 is formed over the entire surface of the first main surface TS1, including the first external electrode 40A and the second external electrode 40B that are exposed on the first main surface TS1 side of the laminate 10.

[0076] In other words, the insulating layer 71 is formed across the surface of the first external electrode 40A on the side of the first main surface TS1 of the laminate 10, the first main surface TS1 located between the first external electrode 40A and the second external electrode 40B, and the surface of the second external electrode 40B on the side of the first main surface TS1 of the laminate 10. Note that the insulating layer 71 may be formed on a part of the first main surface TS1 located between the first external electrode 40A and the second external electrode 40B, rather than the entire surface.

[0077] The insulating layer 71 is preferably an organic layer mainly composed of organic materials. More specifically, the insulating layer 71 is preferably a resin layer mainly composed of resin. The insulating layer 71 is, for example, an epoxy resin. However, the composition constituting the insulating layer 71 is not limited to this. For example, the insulating layer 71 may contain one or more of the following: epoxy resin, silicone resin, fluororesin, phenolic resin, urea resin, melamine resin, and unsaturated polyester resin. The insulating layer 71 is a layer having a low wettability surface that is lower in wettability than the surface of the external electrode 40. The insulating layer 71 may contain fillers.

[0078] The insulating layer 71 may be made of a material other than resin, and in that case, it is preferable that it has a surface with lower solder wettability than the external electrode 40.

[0079] More specifically, as shown in Figure 7, the insulating layer 71 has a first portion 72 formed on the first main surface TS1 and a second portion 73A that extends from the first portion 72 in the longitudinal direction L and reaches over a part of the first covering portion 91A of the first external electrode 40A.

[0080] The second portion 73A has a tip 74A on the first end face LS1 side. The length in the longitudinal direction from the first tip 92A (position D2) to the tip 74A (position D3) of the first covering portion 91A is defined as "length LB1". In this case, the first overlap ratio (LB1 / LA1), which is the ratio of length LB1 to length LA1, is 1.9% or more and 84% or less. The first overlap ratio (LB1 / LA1) is preferably 5% or more and 55% or less, and more preferably 20% or more and 40% or less.

[0081] The thickness of the insulating layer 71 in the height direction T is described below. In the insulating layer 71, the thickness at the first tip 92A of the first covering portion 91A is defined as the first thickness TH1. The first tip 92A corresponds to the boundary position between the first portion 72 and the second portion 73A of the insulating layer 71. The first thickness TH1 is 7 μm or more and 90 μm or less. If the first thickness TH1 is less than 7 μm, the effect of placing the insulating layer is weakened, and if it exceeds 90 μm, the mountability on the substrate decreases. In a modified example, the insulating layer 71 has a first thickness TH1 in the height direction T at the first tip 92A of the first covering portion 91A that is 7 μm or more and less than or equal to the maximum thickness of the first covering portion 91A. If the first thickness TH1 exceeds the maximum thickness of the first covering portion 91A, the mountability on the substrate decreases.

[0082] As shown in Figure 8, the insulating layer 71 has a third portion 73B that extends in the longitudinal direction L from the first portion 72 and reaches over a part of the second covering portion 91B of the second external electrode 40B.

[0083] The third portion 73B has a tip 74B on the second end face LS2 side. The length in the longitudinal direction from the second tip 92B (position D2) to the tip 74B (position D3) of the second covering portion 91B is defined as "length LB2". In this case, the second overlap ratio (LB2 / LA2), which is the ratio of length LB2 to length LA2, is 1.9% or more and 84% or less. The second overlap ratio (LB2 / LA2) is preferably 5% or more and 55% or less, and more preferably 20% or more and 40% or less.

[0084] In the insulating layer 71, the thickness at the second covering portion 91B is defined as the second thickness TH2. The second tip 92B corresponds to the boundary position between the first portion 72 and the third portion 73B of the insulating layer 71. The second thickness TH2 is 7 μm or more and 90 μm or less. If the second thickness TH2 is less than 7 μm, the effect of placing the insulating layer 71 is weakened, and if it exceeds 90 μm, the mountability on the substrate decreases. In a modified example, the insulating layer 71 has a second thickness TH2 in the height direction T at the second tip 92B of the second covering portion 91B that is 7 μm or more and less than or equal to the maximum thickness of the second covering portion 91B. If the second thickness TH2 exceeds the maximum thickness of the second covering portion 91B, the mountability on the substrate decreases.

[0085] The measurement method for the above parameters is described below. Cross-sectional polishing is performed from the first side WS1 or the second side WS2 to the center of the multilayer ceramic capacitor 1 (at the halfway point of the width W), and an image of the polished cross-section is acquired using an optical microscope or electron microscope. Subsequently, the lengths LA1, LA2, LB1, LB2, and the thickness of the insulating layer 71 are measured from the acquired image. Furthermore, the first ratio (LB1 / LA1) and the second ratio (LB2 / LA2) are calculated from the measured lengths LA1, LA2, LB1, and LB2.

[0086] The mounting structure 100 for the multilayer ceramic capacitor includes a multilayer ceramic capacitor 1 and a mounting substrate 80, as shown in Figures 6 to 8. The mounting substrate 80 includes a substrate body 81. The substrate body 81 is formed of, for example, a resin such as glass epoxy, or glass or ceramic. The substrate body 81 may be formed of, for example, a plurality of stacked insulating layers. One main surface of the substrate body 81 (the upper surface in the figure) is the mounting surface, and a land electrode 82 with a rectangular shape in plan view is provided on the mounting surface. The multilayer ceramic capacitor 1 is mounted by connecting and fixing the first external electrode 40A and the second external electrode 40B of the multilayer ceramic capacitor 1 to the land electrode 82 via solder 83. In this case, the first external electrode 40A and the second external electrode 40B located on the first main surface TS1 side of the laminate 10 and the land electrode 82 are mounted.

[0087] Next, the manufacturing method of the multilayer ceramic capacitor 1 of this embodiment will be described. The manufacturing method of the multilayer ceramic capacitor 1 of this embodiment is not limited as long as the above requirements are satisfied. However, a preferred manufacturing method comprises the following steps. The details of each step are described below.

[0088] A dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. Both the dielectric sheet for the dielectric layer 20 and the conductive paste for the internal electrode layer 30 contain a binder and a solvent. The binder and solvent may be known materials. The paste made of a conductive material is, for example, a metal powder to which an organic binder and an organic solvent are added.

[0089] A conductive paste for the internal electrode layer 30 is printed onto the dielectric sheet using a printing plate designed to form the shape of the internal electrode layer 30 in this embodiment, for example, by screen printing or gravure printing. This prepares a dielectric sheet with the pattern of the first internal electrode layer 31 formed on it and a dielectric sheet with the pattern of the second internal electrode layer 32 formed on it.

[0090] A predetermined number of dielectric sheets without the pattern of the internal electrode layer 30 printed on them are stacked to form the first main surface outer layer portion 12 on the first main surface TS1 side. On top of this, dielectric sheets with the pattern of the first internal electrode layer 31 printed on them and dielectric sheets with the pattern of the second internal electrode layer 32 printed on them are stacked alternately in sequence to form the inner layer portion 11. On top of this inner layer portion 11, a predetermined number of dielectric sheets without the pattern of the internal electrode layer 30 printed on them are stacked to form the second main surface outer layer portion 13 on the second main surface TS2 side. This results in a laminated sheet.

[0091] Next, the laminated sheets are pressed in the height direction by means of a hydrostatic press or other means to produce a laminated block.

[0092] Next, the laminated block is cut into predetermined sizes to form individual pieces, thereby obtaining multiple laminated chips. After this, the laminated chips may be polished by barrel polishing or other methods to round off the corners and edges.

[0093] Next, the laminated chips are fired to obtain the laminated body 10. The firing temperature at this time depends on the materials of the dielectric layer 20 and the internal electrode layer 30, but is preferably, for example, 900°C to 1400°C.

[0094] A conductive paste, which will serve as the base electrode layer 50, is applied to both end faces of the laminate 10. In this embodiment, the base electrode layer 50 is a baked layer. The baked layer can be formed by applying a conductive paste containing glass components and metal to the laminate 10, for example by dipping, and then performing a baking treatment. The temperature of the baking treatment at this time is preferably 700°C to 900°C.

[0095] Alternatively, the laminated chip before firing and the conductive paste applied to the laminated chip may be fired simultaneously. In this case, it is preferable to form the baked layer by baking a material with a ceramic component added instead of a glass component. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the added ceramic material. In this case, the conductive paste is applied to the laminated chip before firing, and the laminated chip and the conductive paste applied to the laminated chip are fired simultaneously to form a laminated body 10 with a baked layer.

[0096] Subsequently, a plating layer is formed on the surface of the base electrode layer 50, which consists of a baked layer. In this embodiment, a first plating layer 60A is formed on the surface of the first base electrode layer 50A. Also, a second plating layer 60B is formed on the surface of the second base electrode layer 50B. In this embodiment, a Ni plating layer and a Sn plating layer are formed as the plating layers. When performing the plating treatment, either electrolytic plating or electroless plating may be used. However, electroless plating has the disadvantage of complicating the process because it requires pretreatment with a catalyst or the like in order to improve the plating deposition rate. Therefore, it is generally preferable to use electrolytic plating. The Ni plating layer and the Sn plating layer are formed sequentially, for example, by barrel plating.

[0097] The multilayer ceramic capacitor body is manufactured through the above process.

[0098] Next, an insulating layer 71 is formed on the multilayer ceramic capacitor body. Specifically, the insulating layer 71 is formed by applying a resin paste to the ceramic capacitor body using a dispenser, screen printing, roller transfer, dipping, spray coating, etc. After that, the resin is cured by heat treatment in an oven at 100 to 200°C for a predetermined time. In this way, the multilayer ceramic capacitor 1 is manufactured.

[0099] In the process described above, the amount of overlap between the resin paste and the external electrode on the main surface, and the thickness of the resin, can be controlled by controlling the dispensing position, paste dispensing amount, paste viscosity, number of dispensing cycles, and temperature during application.

[0100] Next, as shown in Figures 7 and 8, the manufactured multilayer ceramic capacitor 1 is positioned so that its first main surface TS1 side faces the mounting substrate 80 on which the land electrodes 82 are provided, and the multilayer ceramic capacitor 1 is mounted on the mounting substrate 80.

[0101] Next, we will explain how the above-mentioned effects can be obtained using simulations.

[0102] The residual stress when the multilayer ceramic capacitor 1 is mounted on the substrate 80 and allowed to flex was calculated, taking into account the stress during the thermal history from the application of a resin paste forming an insulating layer 71 to the multilayer ceramic capacitor body on which the external electrodes 40 are formed until the paste is heat-cured. At that time, the values ​​of the maximum principal stress applied to the portion of the laminate 10 that is in contact with the main surface side external electrode layer (first cover portion 91A or second cover portion 91B) were compared.

[0103] Furthermore, the simulation was performed using a 3225-size multilayer ceramic capacitor as the base model for the chip and mounting board.

[0104] <First Simulation> Hereinafter, the first overlap ratio (LB1 / LA1) and the second overlap ratio (LB2 / LA2) will be collectively described as the overlap ratio (LB / LA) of the external electrode 40 and the insulating layer 71. Furthermore, the first covering portion 91A and the second covering portion 91B will be collectively described as the main surface side external electrode.

[0105] This section describes the results of simulations of the stress acting on the laminate by changing the overlap ratio (LB / LA). In the first simulation, the thickness of the insulating layer 71 was set to 60 μm.

[0106] The simulation results are shown in Table 1 below.

[0107]

[0108] In Table 1, "normal structure" refers to the case of a multilayer ceramic capacitor without an insulating layer 71. In other words, "normal structure" refers to the case where the overlap ratio (LB / LA) is 0%. If the stress ratio to the normal structure is 0.88 or less, it can be said that the stress has been sufficiently reduced. Furthermore, if the stress ratio to the normal structure is below 0.865, preferably 0.84 or less, it can be said that the stress has been reduced more effectively. And if the stress ratio to the normal structure is 0.82 or less, it can be said that the stress has been reduced even more effectively. On the other hand, if the stress ratio to the normal structure exceeds 0.88, the effect of stress relaxation cannot be said to be sufficient. In the stress value judgment in Table 1, "×" means unacceptable, "△" means sufficient (pass), "〇" means good, and "◎" means excellent.

[0109] As is clear from Table 1, when the overlap ratio (LB / LA) is between 1.9% and 84% (Examples 1-11), the stress acting on the laminate was found to be sufficiently low. Furthermore, as the overlap ratio increased from 1.9% to 25%, the stress acting on the laminate decreased, and when the overlap ratio (LB / LA) was 25% (Example 5), the stress value was minimized, and as the overlap ratio (LB / LA) increased further, the stress acting on the laminate continued to decrease.

[0110] From the above, it was found that the overlap rate (LB / LA) is preferably 1.9% or more and 84% or less, preferably 5% or more and 55% or less, and more preferably 20% or more and 40% or less. The overlap rate (LB / LA) may also be 10% or more and 45% or less, 20% or more and 36.4% or less, or 20% or more and 30% or less.

[0111] <Second Simulation> Next, we will explain the results of the simulation of the stress acting on the laminate when the first thickness TH1 and the second thickness TH2 of the insulating layer 71 are changed. Hereafter, the first thickness TH1 and the second thickness TH2 will be collectively referred to as the thickness TH of the insulating layer 71. In Examples 12 to 18 of the second simulation, the overlap ratio (LB / LA) was set to 54.7%.

[0112] Table 2 below shows the simulation results.

[0113]

[0114] In Table 2, "normal structure" refers to the case of a multilayer ceramic capacitor without an insulating layer 71. In other words, "normal structure" refers to the case where the thickness of the insulating layer 71 is 0 μm. If the stress ratio to the normal structure is 0.88 or less, it can be said that the stress has been sufficiently reduced. Furthermore, if the stress ratio to the normal structure is below 0.865, it can be said that the stress has been reduced even better. In the stress value judgment in Table 2, "△" means sufficient (pass), and "〇" means good.

[0115] Table 2 shows that as the thickness TH of the insulating layer 71 is increased, the stress values ​​acting on the laminate tend to decrease, as shown in Examples 12 to 18.

[0116] From the above, it was confirmed that the thickness TH of the insulating layer 71 is preferably 3 μm or more, and more preferably 7 μm or more.

[0117] However, if the thickness TH of the insulating layer 71 is made too large, the mounting stability of the multilayer ceramic capacitor 1 may deteriorate. Therefore, it is preferable that the thickness TH of the insulating layer 71 be 90 μm or less.

[0118] The multilayer ceramic capacitor 1 according to the second embodiment will be described using Figure 9. Figure 9 is a cross-sectional view of the multilayer ceramic capacitor according to the second embodiment. Since the multilayer ceramic capacitor 1 according to the second embodiment has the same basic configuration as that according to the first embodiment, only the differences will be described below.

[0119] The multilayer ceramic capacitor 1 has a second insulating layer 75 in addition to the insulating layer 71. The second insulating layer 75 is formed to cover at least a portion of the second main surface TS2 of the laminate 10 and a portion of the first external electrode 40A and the second external electrode 40B which are located on the side of the second main surface TS2.

[0120] Specifically, the second insulating layer 75 is formed over the entire surface of the second main surface TS2, including the first external electrode 40A and the second external electrode 40B that are exposed on the second main surface TS2 side of the laminate 10.

[0121] In other words, the second insulating layer 75 is formed across the surface of the first external electrode 40A, specifically the surface of the laminate 10 on the side of the first main surface TS1, the first main surface TS1 located between the first external electrode 40A and the second external electrode 40B, and the surface of the second external electrode 40B, specifically the surface of the laminate 10 on the side of the first main surface TS1.

[0122] The second insulating layer 75 may have the same shape and material as the insulating layer 71, or it may satisfy the various conditions of the insulating layer 71 described in the first embodiment.

[0123] Since the second insulating layer 75 is also formed on the second main surface TS2 side, the degree of freedom when mounting the multilayer ceramic capacitor 1 is increased.

[0124] In a third embodiment, the insulating layer may be formed on the first main surface TS1, the second main surface TS2, the first side surface WS1, and the second side surface WS2.

[0125] In this case, the four insulating layers may have the same shape and material as the insulating layer 71 of the first embodiment, or they may satisfy the various conditions of the insulating layer 71 described in the first embodiment.

[0126] Note that the configuration of the multilayer ceramic capacitor 1 is not limited to the configurations shown in Figures 1 to 9. For example, the multilayer ceramic capacitor 1 may be a double-gang, triple-gang, or quadruple-gang multilayer ceramic capacitor as shown in Figures 10A, 10B, and 10C.

[0127] The multilayer ceramic capacitor 1 shown in Figure 10A is a double-gang multilayer ceramic capacitor 1, and as an internal electrode layer 30, it includes a first internal electrode layer 33 and a second internal electrode layer 34, as well as a floating internal electrode layer 35 that is not drawn out to either the first end face LS1 or the second end face LS2. The multilayer ceramic capacitor 1 shown in Figure 10B is a triple-gang multilayer ceramic capacitor 1, which includes a first floating internal electrode layer 35A and a second floating internal electrode layer 35B as floating internal electrode layers 35. The multilayer ceramic capacitor 1 shown in Figure 10C is a quadruple-gang multilayer ceramic capacitor 1, which includes a first floating internal electrode layer 35A, a second floating internal electrode layer 35B, and a third floating internal electrode layer 35C as floating internal electrode layers 35. In this way, by providing floating internal electrode layers 35 as internal electrode layers 30, the multilayer ceramic capacitor 1 has a structure in which the opposing electrode portion is divided into multiple parts. As a result, multiple capacitor components are formed between the opposing internal electrode layers 30, and these capacitor components are connected in series. Therefore, the voltage applied to each capacitor component is reduced, and the voltage withstand capability of the multilayer ceramic capacitor 1 can be increased. It goes without saying that the multilayer ceramic capacitor 1 in this embodiment may also have a multi-gang structure of four or more units.

[0128] In the embodiments described above, a multilayer ceramic capacitor was given as an example of a multilayer ceramic electronic component in which a dielectric layer 20 made of dielectric ceramic is used as the ceramic layer. However, the multilayer ceramic electronic components of this disclosure are not limited to this. For example, the ceramic electronic components of this disclosure can also be applied to various multilayer ceramic electronic components such as piezoelectric components using piezoelectric ceramic as the ceramic layer, and thermistors using semiconductor ceramic as the ceramic layer. Examples of piezoelectric ceramics include PZT (lead zirconate titanate) ceramics, and examples of semiconductor ceramics include spinel ceramics.

[0129] The multilayer ceramic capacitor 1 according to the embodiment described above provides the following effects: (1) The multilayer ceramic capacitor 1 (multilayer ceramic electronic component 1) according to this embodiment includes a plurality of dielectric layers 20 (ceramic layers 20) and a plurality of internal electrode layers 30 (internal conductor layers 30), and has a laminate 1 having a first main surface TS1 and a second main surface TS2 facing the height direction T, a first side surface WS1 and a second side surface WS2 facing the width direction W perpendicular to the height direction T, and a first end surface LS1 and a second end surface LS2 facing the length direction L perpendicular to the height direction T and the width direction W. The laminate comprises: a first external electrode 40A positioned on the first end face LS1 side and having a first covering portion 91A that covers a part of the first end face LS1 side of the first main surface TS1; a second external electrode 40B positioned on the second end face LS2 side and having a second covering portion 91B that covers a part of the second end face LS2 side of the first main surface TS1; and an insulating layer 71 formed to cover at least a part of the first main surface TS1 of the laminate and a part of the first external electrode 40A and the second external electrode 40B positioned on the first main surface TS1 side. The first overlap ratio (LB1 / LA1), which is the ratio of the length LB1 from the first tip 92A of the first cover portion 91A to the tip 74A of the insulating layer 71 on the first end face LS1 side, to the length LA1 from the first tip 92A of the first cover portion 91A to the first end face LS1, is 1.9% or more and 84% or less. The second overlap ratio (LB2 / LA2), which is the ratio of the length LB2 from the second tip 92B of the second cover portion 91B to the tip 74B of the insulating layer 71 on the second end face LS2 side, to the length LA2 from the second tip 92B of the second cover portion 91B to the second end face LS2, is 1.9% or more and 84% or less.

[0130] This allows the stress values ​​acting on the first cover portion 91A and the second cover portion 91B of the external electrode 40 to be sufficiently low. Therefore, sufficient crack resistance of the laminate 10 against substrate deflection can be obtained, and as a result, the occurrence of cracks in the laminate 10 can be suppressed. As a result, a multilayer ceramic electronic component that can suppress the occurrence of cracks in the laminate can be provided.

[0131] (2) In the multilayer ceramic capacitor 1 (multilayer ceramic electronic component 1) according to this embodiment, the first overlap ratio (LB1 / LA1) is 5% or more and 55% or less, and the second overlap ratio (LB2 / LA2) is 5% or more and 55% or less.

[0132] This makes it possible to provide multilayer ceramic electronic components that can suppress the occurrence of cracks in the laminate.

[0133] (3) In the multilayer ceramic capacitor 1 (multilayer ceramic electronic component 1) according to this embodiment, the first overlap ratio (LB1 / LA1) is 20% or more and 40% or less, and the second overlap ratio (LB2 / LA2) is 20% or more and 40% or less.

[0134] This makes it possible to provide multilayer ceramic electronic components that can suppress the occurrence of cracks in the laminate.

[0135] (4) In the multilayer ceramic capacitor 1 (multilayer ceramic electronic component 1) according to this embodiment, the insulating layer 71 has a first thickness TH1 in the height direction of 7 μm or more and 90 μm or less at the first tip 92A of the first cover portion 91A, and the insulating layer 71 has a second thickness TH2 in the height direction of 7 μm or more and 90 μm or less at the second tip 92B of the second cover portion 91B.

[0136] This allows the stress values ​​acting on the first cover portion 91A and the second cover portion 91B of the external electrode 40 to be sufficiently low. Therefore, sufficient crack resistance of the laminate 10 against substrate deflection can be obtained, and as a result, the occurrence of cracks in the laminate 10 can be suppressed. As a result, a multilayer ceramic electronic component that can suppress the occurrence of cracks in the laminate can be provided.

[0137] (5) In the multilayer ceramic capacitor 1 (multilayer ceramic electronic component 1) according to this embodiment, the insulating layer 71 has a first thickness TH1 in the height direction of 7 μm or more at the first tip 92A of the first cover portion 91A, and is less than or equal to the maximum thickness of the first cover portion 91A. The insulating layer 71 has a second thickness TH2 in the height direction of 7 μm or more at the second tip 92B of the second cover portion 91B, and is less than or equal to the maximum thickness of the second cover portion 91B.

[0138] This makes it possible to provide multilayer ceramic electronic components that can suppress the occurrence of cracks in the laminate.

[0139] The present invention is not limited to the configuration of the above embodiments, and can be modified and applied as appropriate without altering the essence of the invention. Furthermore, a combination of two or more of the desirable configurations described in the above embodiments also constitutes the present invention.

[0140] 1: Multilayer ceramic capacitor (multilayer ceramic electronic component) 10: Laminate 20: Dielectric layer (ceramic layer) 30: Internal electrode layer (internal conductor layer) 40: External electrode 40A: First external electrode 40B: Second external electrode 71: Insulating layer 74A: First tip 74B: Second tip 91A: First cover 91B: Second cover 92A: First tip 92B: Second tip TH1: Thickness TH2: Thickness L: Length direction T: Height direction W: Width direction LS1: First end face LS2: Second end face TS1: First main surface TS2: Second main surface WS1: First side surface WS2: Second side surface

Claims

1. A laminate comprising a plurality of dielectric layers and a plurality of internal conductor layers, having a first main surface and a second main surface facing each other in the height direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the height direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the height direction and the width direction; a first external electrode disposed on the first end surface side and having a first covering portion that covers a part of the first end surface side of the first main surface; a second external electrode disposed on the second end surface side and having a second covering portion that covers a part of the second end surface side of the first main surface; and an insulating layer formed to cover at least a part of the first main surface of the laminate and a part of the first external electrode and the second external electrode disposed on the first main surface side. A multilayer ceramic electronic component in which the first overlap ratio (LB1 / LA1), which is the ratio of the length LB1 from the first tip of the first cover portion to the first end face of the insulating layer to the length LA1 from the first tip of the first cover portion to the first end face of the second end face of the first cover portion, is 1.9% or more and 84% or less, and the second overlap ratio (LB2 / LA2), which is the ratio of the length LB2 from the second tip of the second cover portion to the second end face of the insulating layer to the length LA2 from the second tip of the second cover portion to the second end face of the first end face of the second cover portion, is 1.9% or more and 84% or less.

2. The multilayer ceramic electronic component according to claim 1, wherein the first overlap ratio (LB1 / LA1) is 5% or more and 55% or less, and the second overlap ratio (LB2 / LA2) is 5% or more and 55% or less.

3. The multilayer ceramic electronic component according to claim 1, wherein the first overlap ratio (LB1 / LA1) is 20% or more and 40% or less, and the second overlap ratio (LB2 / LA2) is 20% or more and 40% or less.

4. The multilayer ceramic electronic component according to any one of claims 1 to 3, wherein the insulating layer has a first thickness in the height direction of 7 μm or more and 90 μm or less at the first tip of the first cover portion, and the insulating layer has a second thickness in the height direction of 7 μm or more and 90 μm or less at the second tip of the second cover portion.

5. The multilayer ceramic electronic component according to any one of claims 1 to 3, wherein the insulating layer has a first thickness in the height direction of 7 μm or more at the first tip of the first cover portion and is less than or equal to the maximum thickness of the first cover portion, and the insulating layer has a second thickness in the height direction of 7 μm or more at the second tip of the second cover portion and is less than or equal to the maximum thickness of the second cover portion.

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