Semiconductor module
WO2026063046A1PCT designated stage Publication Date: 2026-03-26FUJI ELECTRIC CO LTD
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-07-24
- Publication Date
- 2026-03-26
AI Technical Summary
Technical Problem
Existing semiconductor modules face challenges in reducing the inductance of gate wiring, which can lead to variations in wiring distance and increased inductance between semiconductor chips, causing gate vibration and inefficiencies.
Method used
The semiconductor module design includes a gate wiring configuration with branching and folded-back portions, along with auxiliary signal wiring, to minimize inductance and stabilize wiring distances, using a printed circuit board with specific intervals and connections to reduce inductance.
Benefits of technology
This configuration effectively reduces inductance and stabilizes wiring distances, suppressing gate vibration and improving the performance of semiconductor modules.
✦ Generated by Eureka AI based on patent content.
Smart Images
Figure JP2025026207_26032026_PF_FP_ABST
Abstract
The present invention reduces the inductance of gate wiring for a plurality of semiconductor chips. A plurality of semiconductor chips each having a gate electrode and a first main electrode on the upper surface thereof are disposed in two rows in a first direction orthogonal to a center line (CL) in a mirror image arrangement with the center line (CL) interposed therebetween. Gate wiring (31) of a printed circuit board (30) disposed on the upper side of the plurality of semiconductor chips includes: a first region extending in the first direction between a first semiconductor chip belonging to a first row and a second semiconductor chip belonging to a second row; a second region including a branch portion that branches into two branches in mutually opposite directions in a second direction orthogonal to the first direction from each of both ends facing each other in the first direction of the first region, and a folded portion that is folded back in the first direction from the branch portion such that the first region is put therebetween with a first gap therebetween; a gate terminal connection region (31c) that is a portion intersecting with the center line (CL) of the first region; and gate electrode connection regions (31d1-31d8) provided in the branch portion and the folded portion of the second region.
Need to check novelty before this filing date? Find Prior Art
Citation Information
Patent Citations
Semiconductor module
JP2021141219A
Semiconductor device
JP2022191879A
Power conversion device
WO2019064874A1