Multilayer ceramic capacitor

Abstract

The present invention provides a multilayer ceramic capacitor of which property defects at the time of manufacturing can easily be inhibited.　In a multilayer ceramic capacitor 1, a plurality of internal electrode layers 30 include a plurality of first internal electrode layers 31 connected to a first external electrode 40A, a plurality of second internal electrode layers 32 connected to a second external electrode 40B, and one or more capacitance adjustment layers 30A connected to the first external electrode 40A or the second external electrode 40B, facing the first internal electrode layer 31 or the second internal electrode layer 32, and including a plurality of divided electrodes 300A divided in the width direction W. At least one of the plurality of internal electrode layers 30 is connected to the first external electrode 40A or the second external electrode 40B via an insulation region IA.

Description

Multilayer ceramic capacitor

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] Conventionally, a multilayer ceramic capacitor as a multilayer ceramic electronic component has been known. Generally, a multilayer ceramic capacitor includes a laminate in which a plurality of dielectric layers and internal electrode layers are alternately laminated, and external electrodes connected to the internal electrode layers and provided on both end faces of the laminate (see Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2003-243249

[0004] In a multilayer ceramic capacitor having a general structure as in Patent Document 1, due to processing variations in each step of the manufacturing process and variations in the characteristics of the materials used, the capacitance varies, so the capacitance may deviate from the product specifications, and there is a problem that characteristic defects increase.

[0005] An object of the present invention is to provide a multilayer ceramic capacitor that can easily suppress characteristic defects during manufacturing.

[0006] The multilayer ceramic capacitor according to the present invention has a plurality of laminated dielectric layers and a plurality of internal electrode layers laminated on the dielectric layers, and has a first main surface and a second main surface facing each other in the height direction, a first side surface and a second side surface facing each other in the width direction orthogonal to the height direction, and a first end surface and a second end surface facing each other in the length direction orthogonal to the height direction and the width direction. A laminate, a first external electrode disposed on the first end surface, and a second external electrode disposed on the second end surface, wherein the plurality of internal electrode layers include a plurality of first internal electrode layers connected to the first external electrode, a plurality of second internal electrode layers connected to the second external electrode, and one or more capacitance adjustment layers including a plurality of divided electrodes connected to the first external electrode or the second external electrode and divided in the width direction so as to face the first internal electrode layer or the second internal electrode layer. At least one of the plurality of internal electrode layers is connected to the first external electrode or the second external electrode via an insulating region.

[0007] According to the present invention, it is possible to provide a multilayer ceramic capacitor that can easily suppress characteristic defects during manufacturing.

[0008] This is an external perspective view of a multilayer ceramic capacitor of an embodiment. This is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 1 along the line II-II. This is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 2 along the line III-III. This is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 2 along the line IVA-IVA. This is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 2 along the line IVB-IVB. This is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 2 along the line IVC-IVC. This is an example of an LT cross-sectional view of a laminate having a capacitance adjustment layer for adjusting capacitance. This is a diagram showing the case where an insulating region is formed in the capacitance adjustment layer in Figure 5A. This is an example of an LW cross-sectional view of a laminate having a capacitance adjustment layer for adjusting capacitance. This is an example of an LW cross-sectional view of a laminate having a capacitance adjustment layer for adjusting capacitance, in which case one dividing electrode is connected to an external electrode via an insulating region. This is an example of an LW cross-sectional view of a laminate having a capacitance adjustment layer for adjusting capacitance, in which case two dividing electrodes are connected to an external electrode via insulating regions. An example of a long wall cross-section of a laminate having a capacitance adjustment layer for adjusting capacitance, where all of the dividing electrodes are connected to the external electrode via an insulating region. An example of a long wall cross-section of the first internal electrode layer. An example of a long wall cross-section of the first internal electrode layer, where the first internal electrode layer is connected to the external electrode via an insulating region. An example of a long wall cross-section of a laminate having a capacitance adjustment layer when the number of dividing electrodes is six. A schematic diagram showing an example of the configuration of a double-gang multilayer ceramic capacitor. A schematic diagram showing an example of the configuration of a triple-gang multilayer ceramic capacitor. A schematic diagram showing an example of the configuration of a quadruple-gang multilayer ceramic capacitor.

[0009] The following describes a multilayer ceramic capacitor 1 according to an embodiment of this disclosure. Figure 1 is an external perspective view of the multilayer ceramic capacitor 1 of this embodiment. Figure 2 is a cross-sectional view of the multilayer ceramic capacitor 1 of Figure 1 along the line II-II. Figure 3 is a cross-sectional view of the multilayer ceramic capacitor 1 of Figure 2 along the line III-III. Figure 4A is a cross-sectional view of the multilayer ceramic capacitor 1 of Figure 2 along the line IVA-IVA. Figure 4B is a cross-sectional view of the multilayer ceramic capacitor 1 of Figure 2 along the line IVB-IVB. Figure 4C is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 2 along the line IVC-IVC.

[0010] Figure 5A is an example of a cross-sectional view of a laminate having a capacitance adjustment layer for adjusting capacitance. Figure 5B shows the case in Figure 5A where an insulating region is formed in the capacitance adjustment layer.

[0011] Figure 6A is an example of a long wall cross-section of a laminate having a capacitance adjustment layer for adjusting capacitance. Figure 6B is an example of a long wall cross-section of a laminate having a capacitance adjustment layer for adjusting capacitance, in which case one dividing electrode is connected to an external electrode via an insulating region. Figure 6C is an example of a long wall cross-section of a laminate having a capacitance adjustment layer for adjusting capacitance, in which case two dividing electrodes are connected to an external electrode via an insulating region. Figure 6D is an example of a long wall cross-section of a laminate having a capacitance adjustment layer for adjusting capacitance, in which case all dividing electrodes are connected to an external electrode via an insulating region.

[0012] Figure 7A is an example of a LW cross-sectional view of the first internal electrode layer. Figure 7B is another example of a LW cross-sectional view of the first internal electrode layer, in which the first internal electrode layer is connected to the external electrode via an insulating region. Figure 8 is an example of a LW cross-sectional view of a laminate having a capacitance adjustment layer when the number of divided electrodes is six.

[0013] The multilayer ceramic capacitor 1 comprises a laminate 10 and an external electrode 40.

[0014] Figures 1 to 4B show the XYZ Cartesian coordinate system. The length direction L of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the X direction. The width direction W of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Y direction. The height direction T of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Z direction. Here, the cross section shown in Figure 2 is also called the LT cross section. The cross section shown in Figure 3 is also called the WT cross section. The cross sections shown in Figures 4A and 4B are also called the LW cross section.

[0015] As shown in Figures 1 to 4B, the laminate 10 includes a first main surface TS1 and a second main surface TS2 that are opposite to the height direction T, a first side surface WS1 and a second side surface WS2 that are opposite to the width direction W which is perpendicular to the height direction T, and a first end surface LS1 and a second end surface LS2 that are opposite to the length direction L which is perpendicular to the height direction T and the width direction W.

[0016] As shown in Figure 1, the laminate 10 has a substantially rectangular parallelepiped shape. The length L dimension of the laminate 10 is not necessarily longer than the width W dimension. It is preferable that the corners and edges of the laminate 10 are rounded. The corners are the parts where three faces of the laminate intersect, and the edges are the parts where two faces of the laminate intersect. Some or all of the surfaces constituting the laminate 10 may have irregularities or bumps formed on them.

[0017] The dimensions of the laminate 10 are not particularly limited, but if the length L of the laminate 10 is denoted as dimension L, then it is preferable that dimension L is 0.2 mm or more and 2 mm or less. If the height T of the laminate 10 is denoted as dimension T, then it is preferable that dimension T is 0.1 mm or more and 1 mm or less. If the width W of the laminate 10 is denoted as dimension W, then it is preferable that dimension W is 0.1 mm or more and 1 mm or less.

[0018] As shown in Figures 2 and 3, the laminate 10 has an inner layer 11 and a first main surface-side outer layer 12 and a second main surface-side outer layer 13 arranged to sandwich the inner layer 11 in the height direction T.

[0019] The inner layer 11 includes a plurality of dielectric layers 20 and a plurality of internal electrode layers 30. In the height direction T, the inner layer 11 includes the internal electrode layer 30 located closest to the first main surface TS1 to the internal electrode layer 30 located closest to the second main surface TS2. In the inner layer 11, the plurality of internal electrode layers 30 are arranged facing each other via the dielectric layers 20. The inner layer 11 is the part that generates capacitance and functions substantially as a capacitor.

[0020] Multiple dielectric layers 20 are composed of a dielectric material. The dielectric material is, for example, BaTiO ３ CaTiO ３ SrTiO ３ , or CaZrO ３ The dielectric ceramic may contain components such as the above. Alternatively, the dielectric material may have minor components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds added to these main components. The dielectric material may have BaTiO as its main component. ３ It is particularly preferable that the material contains [a specific substance].

[0021] The thickness of the dielectric layer 20 is preferably 0.5 μm or more. For example, the thickness t of the dielectric layer 20 may be 0.5 μm or more and 10 μm or less. The number of dielectric layers 20 to be stacked is preferably 15 or more and 1200 or less. This number of dielectric layers 20 is the sum of the number of dielectric layers in the inner layer portion 11 and the number of dielectric layers in the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13.

[0022] The multiple internal electrode layers 30 include multiple first internal electrode layers 31, multiple second internal electrode layers 32, and one or more capacitance adjustment layers 30A. Although the capacitance adjustment layer 30A shown in Figure 2 is one layer, the capacitance adjustment layer 30A in this embodiment consists of three layers, and will be explained using Figures 5A to 7B.

[0023] For example, in the example shown in Figure 2, the plurality of internal electrode layers 30 have four first internal electrode layers 31, five second internal electrode layers 32, and one capacitance adjustment layer 30A. However, the number of the plurality of first internal electrode layers 31, plurality of second internal electrode layers 32, and one or more capacitance adjustment layers 30A that constitute the plurality of internal electrode layers 30 is not limited to this. The capacitance adjustment layer 30A may be two or more layers as described above, and the plurality of internal electrode layers 30 according to this embodiment have two first internal electrode layers 31, five second internal electrode layers 32, and three capacitance adjustment layers 30A.

[0024] As described later, the multiple first internal electrode layers 31, multiple second internal electrode layers 32, and one or more capacitance adjustment layers 30A that constitute the multiple internal electrode layers 30 are connected to the first external electrode 40A or the second external electrode 40B.

[0025] Multiple first internal electrode layers 31 are arranged on multiple dielectric layers 20. Multiple second internal electrode layers 32 are arranged on multiple dielectric layers 20. Capacitance adjustment layer 30A is arranged on dielectric layer 20. Multiple first internal electrode layers 31, multiple second internal electrode layers 32, and one or more capacitance adjustment layers 30A are stacked in the height direction T of the laminate 10 via dielectric layers 20.

[0026] Furthermore, the internal electrode layers connected to the first external electrode 40A and the internal electrode layers connected to the second external electrode 40B are arranged alternately. The internal electrode layer connected to the first external electrode 40A is either the first internal electrode layer 31 or the capacitance adjustment layer 30A. The internal electrode layer connected to the second external electrode 40B is either the second internal electrode layer 32 or the capacitance adjustment layer 30A. The first internal electrode layer 31, the second internal electrode layer 32, and the capacitance adjustment layer 30A are arranged so as to sandwich the dielectric layer 20.

[0027] Furthermore, it is preferable that the capacitance adjustment layer 30A is an internal electrode layer positioned closest to the first main surface TS1 or the second main surface TS2 among the multiple internal electrode layers 30. In this embodiment, one of the three capacitance adjustment layers 30A is an internal electrode layer positioned closest to the first main surface TS1 among the multiple internal electrode layers 30.

[0028] The first internal electrode layer 31 has a first opposing portion 31A that faces the second internal electrode layer 32 or the capacitance adjustment layer 30A, and a first leading portion 31B that is drawn out from the first opposing portion 31A to the first end face LS1. The first leading portion 31B is exposed to the first end face LS1. The first internal electrode layer 31 is connected to the first external electrode 40A, which will be described later.

[0029] The second internal electrode layer 32 has a second opposing portion 32A that faces the first internal electrode layer 31 or the capacitance adjustment layer 30A, and a second leading portion 32B that is drawn out from the second opposing portion 32A to the second end face LS2. The second leading portion 32B is exposed to the second end face LS2. The second internal electrode layer 32 is connected to the second external electrode 40B, which will be described later.

[0030] The multiple divided electrodes 300A of the capacitance adjustment layer 30A have a third opposing portion 300AA that faces the first internal electrode layer 31 or the second internal electrode layer 32, and a lead-out portion 300AB that is drawn out from the third opposing portion 300AA to the first end face LS1 or the second end face LS2. The lead-out portion 300AB is exposed to the first end face LS1 or the second end face LS2. The capacitance adjustment layer 30A is connected to the first external electrode 40A or the second external electrode 40B, which will be described later.

[0031] As shown in Figure 4A, the capacitance adjustment layer 30A has a plurality of dividing electrodes 300A divided in the width direction W, namely a first dividing electrode 300A1, a second dividing electrode 300A2, and a third dividing electrode 300A3.

[0032] When a multilayer ceramic capacitor 1 has multiple capacitance adjustment layers 30A, the number and dimensions (such as width) of each of the multiple divider electrodes 300A may differ. However, when a multilayer ceramic capacitor 1 has multiple capacitance adjustment layers 30A, it is more preferable that the number and dimensions of the multiple divider electrodes 300A in each of the capacitance adjustment layers 30A are approximately the same. This configuration reduces setup time and costs during manufacturing.

[0033] Furthermore, the capacitance adjustment layer 30A may have an insulating region IA as shown in Figures 2 and 4A, in which case it may be connected to the first external electrode 40A via the insulating region IA. At least one of the plurality of internal electrode layers 30 is connected to the first external electrode 40A or the second external electrode 40B via the insulating region IA. The insulating region IA is a region of the plurality of internal electrode layers 30 that is not electrically connected to the first external electrode 40A and the second external electrode 40B. For example, the insulating region IA may be an air gap. In this embodiment, the insulating region IA is an air gap.

[0034] However, the insulating region IA is not limited to these; it may be made of resin or a dielectric material. Examples of resins used for the insulating region IA include phenolic resin, polyurethane, epoxy resin, and melamine resin. As the dielectric material used for the insulating region IA, the same type of ceramic material as the dielectric layer 20 may be used, or a different type of ceramic material may be used. The ceramic component may include at least one selected from, for example, BaTiO3, CaTiO3, (Ba,Ca)TiO3, SrTiO3, CaZrO3, etc.

[0035] Furthermore, if the multilayer ceramic capacitor 1 has multiple capacitance adjustment layers 30A, at least one of the multiple capacitance adjustment layers 30A may be connected to the first external electrode 40A or the second external electrode 40B via an insulating region IA. In the example shown in Figure 2, one capacitance adjustment layer 30A is connected to the first external electrode 40A via an insulating region IA.

[0036] At least one of the multiple disconnecting electrodes 300A of each capacitance adjustment layer 30A may be connected to the first external electrode 40A or the second external electrode 40B via an insulating region IA. In the examples shown in Figures 4A and 6B, the first disconnecting electrode 300A1, described later, of the three disconnecting electrodes 300A of the capacitance adjustment layer 30A, is connected to the first external electrode 40A via an insulating region IA. In the example shown in Figure 6C, the first disconnecting electrode 300A1 and the second disconnecting electrode 300A2, described later, of the three disconnecting electrodes 300A of the capacitance adjustment layer 30A, are connected to the first external electrode 40A via an insulating region IA. In the example shown in Figure 6D, all three disconnecting electrodes 300A of the capacitance adjustment layer 30A are connected to the first external electrode 40A via an insulating region IA.

[0037] Furthermore, at least one of the internal electrode layers, the first internal electrode layer 31 and the second internal electrode layer 32, may be connected to the first external electrode 40A or the second external electrode 40B via an insulating region IA. More specifically, the first internal electrode layer 31 of the plurality of internal electrode layers 30 may be connected to the first external electrode 40A via an insulating region IA, or the second internal electrode layer 32 of the plurality of internal electrode layers 30 may be connected to the second external electrode 40B via an insulating region IA.

[0038] The multiple separation electrodes 300A include an effective separation electrode V directly connected to the first external electrode 40A or the second external electrode 40B, as shown in Figures 6B to 6D described later, and an ineffective separation electrode I connected to the first external electrode 40A or the second external electrode 40B via an insulating region IA.

[0039] The effective dividing electrode V is an internal electrode layer that is drawn out and exposed at the first end face LS1 or the second end face LS2 of the laminate 10, and is directly connectable to the first external electrode 40A or the second external electrode 40B, and is an electrode that contributes to the capacitance of the multilayer ceramic capacitor 1.

[0040] On the other hand, the ineffective dividing electrode I is an internal electrode layer that does not expose to the first end face LS1 or the second end face LS2 of the laminate 10, cannot be directly connected to the first external electrode 40A or the second external electrode 40B, and is an electrode that does not contribute to the capacitance of the multilayer ceramic capacitor 1.

[0041] In the multilayer ceramic capacitor 1 according to the present embodiment, in the capacitance adjustment process described later, by irradiating the effective dividing electrode V with a laser to form a hole, it can be processed to be changed into the ineffective dividing electrode I. Therefore, in the multilayer ceramic capacitor 1 according to the present embodiment, the capacitance of the multilayer ceramic capacitor 1 can be adjusted by reducing the capacitance of the effective dividing electrode V.

[0042] The lengths Le in the width direction W of the first dividing electrode 300A1, the second dividing electrode 300A2, and the third dividing electrode 300A3 are preferably substantially equal. Thereby, the capacitance of each dividing electrode 300A of the capacitance adjustment layer 30A can be unified, and the fine adjustment of the capacitance of the multilayer ceramic capacitor 1 can be made easier and more accurate.

[0043] The distance Ld between the first dividing electrode 300A1 and the second dividing electrode 300A2 and the distance Ld between the second dividing electrode 300A2 and the third dividing electrode 300A3 are preferably substantially equal. Thereby, while ensuring the area of the internal electrode as much as possible, the insulation between the dividing electrodes 300A of the capacitance adjustment layer 30A can be ensured.

[0044] The distance Ld between the first dividing electrode 300A1 and the second dividing electrode 300A2 and the distance Ld between the second dividing electrode 300A2 and the third dividing electrode 300A3 are preferably smaller than the distance L1 in the width direction W of the first side outer layer portion WG1 and the second side outer layer portion WG2. Thereby, while ensuring the area of the internal electrode as much as possible, the insulation with the outside can be enhanced.

[0045] The distance Ld between the first dividing electrode 300A1 and the second dividing electrode 300A2 and the distance Ld between the second dividing electrode 300A2 and the third dividing electrode 300A3 are preferably larger than the length d in the length direction L of the insulating region IA. Thereby, the capacitance of the multilayer ceramic capacitor 1 can be adjusted while reducing the amount of processing.

[0046] The length Le in the width direction W of the first dividing electrode 300A1, the second dividing electrode 300A2, and the third dividing electrode 300A3 is preferably larger than the length d in the length direction L of the insulating region IA. Thereby, while making the configuration capable of adjusting the capacitance, the maximum capacitance can be increased.

[0047] In the present embodiment, a capacitance is formed by the first opposing portion 31A, the second opposing portion 32A, and the third opposing portion 300AA facing each other through the dielectric layer 20, and the characteristics of the capacitor are exhibited.

[0048] The shapes of the first opposing portion 31A, the second opposing portion 32A, and the third opposing portion 300AA are not particularly limited, but are preferably rectangular. However, the corner portions of the rectangular shape may be rounded, or the corner portions of the rectangular shape may be formed obliquely. The shapes of the first lead-out portion 31B, the second lead-out portion 32B, and the third lead-out portion 300AB are not particularly limited, but are preferably rectangular. However, the corner portions of the rectangular shape may be rounded, or the corner portions of the rectangular shape may be formed obliquely.

[0049] The dimension in the width direction W of the first opposing portion 31A and the dimension in the width direction W of the first lead-out portion 31B may be formed with the same dimension, or either one of the dimensions may be formed smaller. The dimension in the width direction W of the second opposing portion 32A and the dimension in the width direction W of the second lead-out portion 32B may be formed with the same dimension, or either one of the dimensions may be formed narrower. The dimension in the width direction W of the third opposing portion 300AA and the dimension in the width direction W of the third lead-out portion 300AB may be formed with the same dimension, or either one of the dimensions may be formed narrower.

[0050] The first internal electrode layer 31, the second internal electrode layer 32, and the capacitance adjustment layer 30A are made of a suitable conductive material such as metals like Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals. When using an alloy, the first internal electrode layer 31, the second internal electrode layer 32, and the capacitance adjustment layer 30A may be made of, for example, an Ag-Pd alloy.

[0051] The thickness of each of the first internal electrode layer 31, the second internal electrode layer 32, and the capacitance adjustment layer 30A is preferably, for example, 0.2 μm or more and 2.0 μm or less. The total number of the first internal electrode layer 31, the second internal electrode layer 32, and the capacitance adjustment layer 30A is preferably 15 or more and 1000 or less.

[0052] The first main surface-side outer layer 12 is located on the side of the first main surface TS1 of the laminate 10. The first main surface-side outer layer 12 is an aggregate of multiple dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 closest to the first main surface TS1. The dielectric layers 20 used in the first main surface-side outer layer 12 may be the same as the dielectric layers 20 used in the inner layer 11.

[0053] The second main surface-side outer layer 13 is located on the second main surface TS2 side of the laminate 10. The second main surface-side outer layer 13 is an aggregate of multiple dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 closest to the second main surface TS2. The dielectric layers 20 used in the second main surface-side outer layer 13 may be the same as the dielectric layers 20 used in the inner layer 11.

[0054] Thus, the laminate 10 has a plurality of stacked dielectric layers 20 and a plurality of internal electrode layers 30 stacked on the dielectric layers 20. In other words, the multilayer ceramic capacitor 1 has a laminate 10 in which the dielectric layers 20 and internal electrode layers 30 are stacked alternately.

[0055] The laminate 10 has a counter electrode portion 11E. The counter electrode portion 11E is the portion where the first counter portion 31A of the first internal electrode layer 31, the second counter portion 32A of the second internal electrode layer 32, and the third counter portion 300AA of the capacitance adjustment layer 30A face each other. The counter electrode portion 11E is configured as part of the inner layer portion 11. Figures 4A to 4C show the width W and length L ranges of the counter electrode portion 11E. The counter electrode portion 11E is also called the capacitor effective portion.

[0056] The laminate 10 has a side outer layer. The side outer layer has a first side outer layer WG1 and a second side outer layer WG2. The first side outer layer WG1 is a portion that includes a dielectric layer 20 located between the opposing electrode portion 11E and the first side WS1. The second side outer layer WG2 is a portion that includes a dielectric layer 20 located between the opposing electrode portion 11E and the second side WS2. Figures 3, 4A to 4C show the width direction W range of the first side outer layer WG1 and the second side outer layer WG2. The side outer layer is also called a W gap or side gap.

[0057] The laminate 10 has an end-face outer layer. The end-face outer layer has a first end-face outer layer LG1 and a second end-face outer layer LG2. The first end-face outer layer LG1 is a portion that includes a dielectric layer 20 located between the opposing electrode portion 11E and the first end face LS1. The second end-face outer layer LG2 is a portion that includes a dielectric layer 20 located between the opposing electrode portion 11E and the second end face LS2. Figures 2, 4A to 4C show the range L in the longitudinal direction of the first end-face outer layer LG1 and the second end-face outer layer LG2. The end-face outer layer is also called an L gap or end gap.

[0058] The external electrode 40 includes a first external electrode 40A positioned on the first end face LS1 side and a second external electrode 40B positioned on the second end face LS2 side.

[0059] The first external electrode 40A is positioned on the first end face LS1. The first external electrode 40A is connected to the first internal electrode layer 31. The first external electrode 40A may also be positioned on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as on a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the first external electrode 40A is formed extending from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as on a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0060] The second external electrode 40B is positioned on the second end face LS2. The second external electrode 40B is connected to the second internal electrode layer 32. The second external electrode 40B may also be positioned on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as on a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the second external electrode 40B is formed extending from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as on a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0061] As described above, within the laminate 10, capacitance is formed by the opposition of the first opposing portion 31A of the first internal electrode layer 31, the second opposing portion 32A of the second internal electrode layer 32, and the third opposing portion 300AA of the capacitance adjustment layer 30A via the dielectric layer 20. Therefore, capacitor characteristics are exhibited between the first external electrode 40A, to which at least the first internal electrode layer 31 of the first internal electrode layer 31 and capacitance adjustment layer 30A is connected, and the second external electrode 40B, to which at least the second internal electrode layer 32 of the second internal electrode layer 32 of the capacitance adjustment layer 30A is connected.

[0062] The first external electrode 40A includes a first base electrode layer 50A and a first plating layer 60A disposed on the first base electrode layer 50A.

[0063] The second external electrode 40B includes a second base electrode layer 50B and a second plating layer 60B disposed on the second base electrode layer 50B.

[0064] The first base electrode layer 50A is positioned on the first end face LS1. The first base electrode layer 50A is connected to at least the first internal electrode layer 31 of the first internal electrode layer 31 and the capacitance adjustment layer 30A. In this embodiment, the first base electrode layer 50A is formed extending from the first end face LS1 to a part of the first main surface TS1 and a part of the second main surface TS2, as well as a part of the first side surface WS1 and a part of the second side surface WS2.

[0065] The second base electrode layer 50B is positioned on the second end face LS2. The second base electrode layer 50B is connected to at least the second internal electrode layer 32 of the second internal electrode layer 32 and the capacitance adjustment layer 30A. In this embodiment, the second base electrode layer 50B is formed extending from the second end face LS2 to a part of the first main surface TS1 and a part of the second main surface TS2, as well as a part of the first side surface WS1 and a part of the second side surface WS2.

[0066] The first base electrode layer 50A and the second base electrode layer 50B include at least one selected from a baked layer, a resin electrode layer, a thin film layer, etc. In this embodiment, the first base electrode layer 50A and the second base electrode layer 50B are baked layers. The baked layer includes a metal component and a glass component. The metal component includes at least one selected from, for example, Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The glass component includes at least one selected from, for example, B, Si, Ba, Mg, Al, Li, etc.

[0067] The baked layer is, for example, formed by applying a conductive paste containing glass and metal to a laminate (also called a laminated chip) and baking it. The baked layer may be formed by simultaneously firing the laminated chip having internal electrodes and a dielectric layer and the conductive paste applied to the laminated chip, or by firing the laminated chip having internal electrodes and a dielectric layer to obtain a laminate, and then applying the conductive paste to the laminate and baking it. When simultaneously firing the laminated chip having internal electrodes and a dielectric layer and the conductive paste applied to the laminated chip, it is preferable to form the baked layer by baking a material with a ceramic material added instead of glass. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the added ceramic material. The baked layer may consist of multiple layers.

[0068] The longitudinal thickness of the first base electrode layer 50A located at the first end face LS1 is preferably, for example, 10 μm to 150 μm at the center of the height T and width W of the first base electrode layer 50A.

[0069] The longitudinal thickness of the second base electrode layer 50B located at the second end face LS2 is preferably, for example, 10 μm to 150 μm at the center of the height T and width W of the second base electrode layer 50B.

[0070] When the first base electrode layer 50A is provided on a part of at least one of the first main surface TS1 or the second main surface TS2, it is preferable that the thickness of the first base electrode layer 50A in the height direction in this portion is, for example, 10 μm or more and 100 μm or less in the central part of the length direction L and width direction W of the first base electrode layer 50A provided in this portion.

[0071] When the first base electrode layer 50A is provided on a part of at least one of the first side surface WS1 or the second side surface WS2, it is preferable that the thickness of the first base electrode layer 50A in the width direction W provided in this part is, for example, 10 μm or more and 100 μm or less at the center of the length direction L and height direction T of the first base electrode layer 50A provided in this part.

[0072] When a second base electrode layer 50B is provided on a part of at least one of the first main surface TS1 or the second main surface TS2, it is preferable that the thickness of the second base electrode layer 50B in the height direction in this portion is, for example, 10 μm or more and 100 μm or less in the central part of the length direction L and width direction W of the second base electrode layer 50B provided in this portion.

[0073] When a second base electrode layer 50B is provided on at least one of the surfaces of the first side surface WS1 or the second side surface WS2, it is preferable that the thickness of the second base electrode layer 50B in the width direction W provided in this portion is, for example, 10 μm or more and 100 μm or less at the center of the length direction L and height direction T of the second base electrode layer 50B provided in this portion.

[0074] In this embodiment, the first external electrode 40A and the second external electrode 40B may have, for example, a conductive resin layer containing conductive particles and a thermosetting resin. When a conductive resin layer is provided as a base electrode layer (first base electrode layer 50A, second base electrode layer 50B), the conductive resin layer may be arranged to cover the baking layer, or it may be placed directly on the laminate 10 without providing a baking layer. When the conductive resin layer is arranged to cover the baking layer, the conductive resin layer is placed between the baking layer and the plating layer (first plating layer 60A, second plating layer 60B). The conductive resin layer may completely cover the baking layer, or it may cover a part of the baking layer.

[0075] A conductive resin layer containing a thermosetting resin is more flexible than a conductive layer made of, for example, a plated film or a fired conductive paste. Therefore, even when the multilayer ceramic capacitor 1 is subjected to physical shock or shock caused by thermal cycling, the conductive resin layer functions as a buffer layer. Thus, the conductive resin layer suppresses the occurrence of cracks in the multilayer ceramic capacitor 1.

[0076] The metal constituting the conductive particles may be Ag, Cu, or an alloy containing them. The conductive particles preferably contain Ag. The conductive particles are, for example, Ag metal powder. Ag has the lowest resistivity among metals, making it suitable as an electrode material. Furthermore, since Ag is a noble metal, it is resistant to oxidation and has high weather resistance. Therefore, Ag metal powder is suitable as conductive particles.

[0077] Furthermore, the conductive particles may be metal powder with an Ag coating on its surface. When using metal powder with an Ag coating on its surface, the metal powder is preferably Cu, Ni, or an alloy of these. It is preferable to use Ag-coated metal powder in order to maintain the properties of Ag while making the base metal inexpensive.

[0078] Furthermore, the conductive particles may be Cu that has been treated to prevent oxidation. Alternatively, the conductive particles may be metal powder coated with Ag on its surface. When using metal powder coated with Ag on its surface, the metal powder is preferably Cu, Ni, or an alloy of the two.

[0079] Preferably, the metal contained in the first and second conductive resin layers is present in an amount of 35 vol% to 75 vol% of the total volume of the conductive resin layers.

[0080] The shape of the conductive particles is not particularly limited. Conductive particles can be spherical, flattened, or otherwise, but it is preferable to use a mixture of spherical metal powder and flattened metal powder.

[0081] The average particle size of the conductive filler may be, for example, 0.3 μm or more and 10 μm or less.

[0082] The average particle size of the conductive filler contained in the conductive resin layer 60 is calculated using the laser diffraction particle size measurement method based on ISO 13320, regardless of the shape of the conductive filler.

[0083] The conductive particles contained in the conductive resin layer primarily play a role in ensuring the conductivity of the conductive resin layer. Specifically, the contact between multiple conductive particles forms an electrical pathway within the conductive resin layer.

[0084] The resin constituting the conductive resin layer may include at least one selected from various known thermosetting resins such as epoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin. Among these, epoxy resin, which has excellent heat resistance, moisture resistance, and adhesion, is one of the most suitable resins. Furthermore, it is preferable that the resin in the conductive resin layer includes a curing agent together with the thermosetting resin. When epoxy resin is used as the base resin, the curing agent for the epoxy resin may be various known compounds such as phenolic, amine, acid anhydride, and imidazole compounds.

[0085] The conductive resin layer may be formed from multiple layers. Preferably, the thickness of the thickest part of the conductive resin layer is 10 μm or more and 200 μm or less.

[0086] The first base electrode layer 50A and the second base electrode layer 50B are not limited to baked layers or conductive resin layers, but may also be thin film layers. The thin film layer is a layer in which metal particles are deposited, formed by a thin film formation method such as sputtering or vapor deposition. Preferably, the thin film layer contains at least one metal selected from the group consisting of Mg, Al, Ti, W, Cr, Cu, Ni, Ag, Co, Mo, and V. This can increase the adhesion force of the external electrode 40 to the laminate 10. The thin film layer may be a single layer or formed by multiple layers. For example, it may be formed by a two-layer structure consisting of a NiCr layer and a NiCu layer.

[0087] When a thin film layer as a base electrode is formed by sputtering using a sputtering electrode, it is preferable that the sputtering electrode is formed on a part of the first main surface TS1 and a part of the second main surface TS2 of the laminate 10. The sputtering electrode preferably contains at least one metal selected from, for example, Ni, Cr, Cu, etc. The thickness of the sputtering electrode is preferably 50 nm to 400 nm, and more preferably 50 nm to 130 nm.

[0088] As a base electrode layer, sputter electrodes may be formed on a portion of the first main surface TS1 and a portion of the second main surface TS2 of the laminate 10, while a baking layer may be formed on the first end surface LS1 and the second end surface LS2. Alternatively, the plating layer described later may be formed directly on the laminate 10 without forming a base electrode layer on the first end surface LS1 and the second end surface LS2. When a baking layer is formed on the first end surface LS1 and the second end surface LS2, the baking layer may extend not only to the first end surface LS1 and the second end surface LS2, but also to a portion of the first main surface TS1 and a portion of the second main surface TS2. In this case, the sputter electrodes may be arranged to overlap the baking layer.

[0089] The first plating layer 60A is positioned to cover the first underlay electrode layer 50A.

[0090] The second plating layer 60B is positioned to cover the second under electrode layer 50B.

[0091] The first plating layer 60A and the second plating layer 60B may each contain at least one selected from, for example, Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The first plating layer 60A and the second plating layer 60B may each be formed by multiple layers. Preferably, the first plating layer 60A and the second plating layer 60B have a two-layer structure in which a Sn plating layer is formed on top of a Ni plating layer.

[0092] The first plating layer 60A is arranged to cover the first underlay electrode layer 50A. In this embodiment, the first plating layer 60A has a first Ni plating layer 61A and a first Sn plating layer 62A located on the first Ni plating layer 61A.

[0093] The second plating layer 60B is arranged to cover the second under electrode layer 50B. In this embodiment, the second plating layer 60B includes a second Ni plating layer 61B and a second Sn plating layer 62B located on the second Ni plating layer 61B.

[0094] The Ni plating layer prevents the first underlay electrode layer 50A and the second underlay electrode layer 50B from being corroded by the solder used when mounting the multilayer ceramic capacitor 1. The Sn plating layer also improves the wettability of the solder used when mounting the multilayer ceramic capacitor 1. This facilitates the mounting of the multilayer ceramic capacitor 1. The thickness of each of the first Ni plating layer 61A, the first Sn plating layer 62A, the second Ni plating layer 61B, and the second Sn plating layer 62B is preferably between 1 μm and 15 μm.

[0095] It is also possible to omit the first base electrode layer 50A and the second base electrode layer 50B, and instead directly arrange the first plating layer 60A and the second plating layer 60B, as described later, on the laminate 10. In other words, the multilayer ceramic capacitor 1 may include a plating layer that is directly electrically connected to the first internal electrode layer 31 and the second internal electrode layer 32. In such a case, the plating layer may be formed after a catalyst is placed on the surface of the laminate 10 as a pretreatment.

[0096] In this case as well, it is preferable that the plating layer consists of multiple layers. The lower plating layer and the upper plating layer each preferably contain at least one metal selected from, for example, Cu, Ni, Pb, Au, Ag, Pd, etc., or an alloy containing these metals. The lower plating layer is more preferably formed using Ni, which has solder barrier properties. The upper plating layer is more preferably formed using Sn or Au, which has good solder wettability. For example, if the first internal electrode layer 31, the second internal electrode layer 32, and the capacitance adjustment layer 30A are formed using Ni, it is preferable that the lower plating layer be formed using Cu, which has good bonding properties with Ni. The upper plating layer may be formed as needed, and the external electrode 40 may consist only of the lower plating layer. Furthermore, the upper plating layer may be the outermost layer, or other plating layers may be formed on the surface of the upper plating layer.

[0097] The thickness of each plating layer, when placed without an undercoat electrode layer, is preferably 2 μm to 10 μm. Furthermore, the plating layer preferably does not contain glass. The metal content per unit volume of the plating layer is preferably 99% by volume or more.

[0098] Furthermore, when the plating layer is formed directly on the laminate 10, the thickness of the base electrode layer can be reduced. Therefore, by reducing the thickness of the base electrode layer, the height T dimension of the multilayer ceramic capacitor 1 can be reduced, thereby making the multilayer ceramic capacitor 1 lower profile. Alternatively, by reducing the thickness of the base electrode layer, the thickness of the dielectric layer 20 sandwiched between the first internal electrode layer 31, the second internal electrode layer 32, and the capacitance adjustment layer 30A can be increased, thereby improving the overall thickness. In this way, by forming the plating layer directly on the laminate 10, the design flexibility of the multilayer ceramic capacitor can be improved.

[0099] Furthermore, if the lengthwise dimension of the multilayer ceramic capacitor 1, including the laminated body 10 and the external electrodes 40, is denoted as dimension L, then it is preferable that dimension L is 0.2 mm or more and 2 mm or less. Also, if the heightwise dimension of the multilayer ceramic capacitor 1, is denoted as dimension T, then it is preferable that dimension T is 0.1 mm or more and 1 mm or less. Also, if the widthwise dimension W of the multilayer ceramic capacitor 1, is denoted as dimension W, then it is preferable that dimension W is 0.1 mm or more and 1 mm or less.

[0100] <Measurement Method for Insulating Region> An image of the cross-section of the multilayer chip is obtained using a SEM, and the divided electrode 300A, which is the metal filling portion, and the insulating region IA, which is the void portion, are determined. The details are explained below using the example shown in Figure 2.

[0101] First, the multilayer ceramic capacitor 1 is embedded in resin and polished from the first side WS1 or the second side WS2 to a position halfway across the width W dimension of the first dividing electrode 300A1 of the capacitance adjustment layer 30A. This exposes the LT cross section in the middle of the width W of the first dividing electrode 300A1 of the multilayer ceramic capacitor 1. Next, the portion of the LT cross section exposed by polishing, including the first dividing electrode 300A1, can be observed with a metallurgical microscope or SEM to determine the metal-filled portion and the void portion, and to measure various distances.

[0102] Next, the manufacturing method of the multilayer ceramic capacitor 1 of this embodiment will be described. Note that the manufacturing method of the multilayer ceramic capacitor 1 of this embodiment is not limited as long as it satisfies the requirements described above.

[0103] A dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. The dielectric sheet and the conductive paste for the internal electrode contain a binder and a solvent. The binder and solvent may be known substances.

[0104] A conductive paste for the internal electrode layer 30 is printed on the dielectric sheet in a predetermined pattern, for example, by screen printing or gravure printing. This prepares a dielectric sheet with the pattern for the first internal electrode layer 31, a dielectric sheet with the pattern for the second internal electrode layer 32, and a dielectric sheet with the pattern for the capacitance adjustment layer 30A.

[0105] A predetermined number of dielectric sheets without printed patterns for the internal electrode layers are stacked to form the first main surface outer layer portion 12 on the first main surface TS1 side. On top of this, dielectric sheets with the pattern for the first internal electrode layer 31 printed on them, dielectric sheets with the pattern for the second internal electrode layer 32 printed on them, and dielectric sheets with the pattern for the capacitance adjustment layer 30A printed on them are stacked sequentially in a predetermined order to form the inner layer portion 11.

[0106] The predetermined order is, as described above, an order in which internal electrode layers connected to the first external electrode 40A among the plurality of internal electrode layers 30 and internal electrode layers connected to the second external electrode 40B among the plurality of internal electrode layers 30 are arranged alternately. Furthermore, the predetermined order is preferably such that one or more capacitance adjustment layers 30A are arranged closest to the first main surface TS1 or closest to the second main surface TS2, as described above. By setting the predetermined order in this manner, the dielectric sheet with the capacitance adjustment layer 30A pattern printed on it only needs to be set up at the first or last timing in the lamination of the dielectric sheet, thereby suppressing a decrease in productivity.

[0107] A predetermined number of dielectric sheets, which do not have the pattern of the internal electrode layer printed on them, are laminated on top of this inner layer portion 11 to form the second main surface side outer layer portion 13 on the second main surface TS2 side. This creates a laminated sheet.

[0108] Laminated sheets are pressed in the height direction by means of hydrostatic pressing or other methods to produce laminated blocks.

[0109] The laminated block is cut to a predetermined size, thereby producing laminated chips. At this time, the corners and edges of the laminated chips may be rounded by barrel polishing or other methods.

[0110] The laminated chips are fired to produce the laminated body 10. The firing temperature depends on the materials of the dielectric layer 20 and the internal electrode layer 30, but is preferably between 900°C and 1400°C. The steps up to this point can be described as the process of producing the laminated body 10 including the capacitance adjustment layer 30A. Therefore, the method for manufacturing the multilayer ceramic capacitor 1 in this embodiment includes the step of producing the laminated body 10 including the capacitance adjustment layer 30A.

[0111] Furthermore, since the capacitance of the multilayer ceramic capacitor 1 according to this embodiment can be adjusted, the manufacturing method of the multilayer ceramic capacitor 1 according to this embodiment includes a capacitance adjustment step. The capacitance adjustment step further includes the steps of providing a conductive thin layer as a temporary electrode for temporary measurement of capacitance on the end face of the laminate 10, temporarily measuring the capacitance with the thin layer, and forming an insulating region according to the excess capacitance if the capacitance exceeds a specified value.

[0112] In the process of forming the insulating region, a laser is irradiated onto the WT side of the laminated chip to remove the internal electrodes, and a hole is made at the L-direction end of the laminated chip to form an air gap that serves as an insulating region. In other words, in this embodiment, the process of forming the insulating region includes a removal process to remove at least a portion of the internal electrode layer exposed on the end face of the laminate. Thus, the manufacturing method of the multilayer ceramic capacitor 1 according to this embodiment includes a removal process to remove at least a portion of the internal electrode layer exposed on the end face of the laminate.

[0113] The above removal step may be a step of removing the end of the capacitance adjustment layer 30A of the internal electrode layer 30, or a step of removing the end of the first internal electrode layer 31 or the second internal electrode layer 32.

[0114] Furthermore, the process of forming the insulating region may further include a step of filling the region from which the internal electrode layer has been removed in the laminate 10 with resin. Alternatively, the process of forming the insulating region may further include a step of filling the region from which the internal electrode layer has been removed in the laminate 10 with dielectric material.

[0115] In this configuration, within the void, the metals and other materials constituting the multiple internal electrode layers 30 are removed by laser to the extent that the internal electrode layers 30 and the external electrodes 40 are not electrically connected. As a result, the insulating region IA is not electrically connected to the first external electrode 40A and the second external electrode 40B, thereby reducing the effective area of ​​the internal electrodes that contribute to capacitance and allowing the capacitance to be adjusted.

[0116] Furthermore, the multilayer ceramic capacitor 1 according to this embodiment has a capacitance adjustment layer 30A that includes a plurality of divider electrodes 300A, and since the capacitance borne by each divider electrode 300A is smaller than that of the first internal electrode layer 31 or the second internal electrode layer 32, the capacitance can be adjusted more finely and accurately. In addition, if the plurality of divider electrodes 300A of the capacitance adjustment layer 30A are formed to have predetermined capacitances, the capacitance can be finely and accurately adjusted even more precisely.

[0117] For example, if only the first dividing electrode 300A1 of the multiple dividing electrodes 300A of the capacitance adjustment layer 30A shown in Figure 6A is drilled by processing the internal electrode layer 30 on the end face of the laminated chip, the state shown in Figure 6B will be obtained. In this case, the first dividing electrode 300A1 of the multiple dividing electrodes 300A of the capacitance adjustment layer 30A will not be exposed on the end face of the laminated chip, and only the second dividing electrode 300A2 and the third dividing electrode 300A3 of the multiple dividing electrodes 300A of the capacitance adjustment layer 30A will be exposed on the end face of the laminated chip.

[0118] Therefore, when the external electrode 40 is formed later, the first dividing electrode 300A1 of the three dividing electrodes 300A of the capacitance adjustment layer 30A is not connected to the external electrode 40 and becomes an inactive dividing electrode I, while the second dividing electrode 300A2 and the third dividing electrode 300A3 of the three dividing electrodes 300A of the capacitance adjustment layer 30A are connected to the external electrode 40 and become an active dividing electrode V. For this reason, the capacitance of the multilayer ceramic capacitor 1 in this case is reduced by the amount of the first dividing electrode 300A1, which is an inactive dividing electrode I that is not connected to the external electrode 40.

[0119] Furthermore, if the internal electrode layer 30 on the end face of the laminated chip is processed to create holes for the first and second dividing electrodes 300A1 and 300A2 of the multiple dividing electrodes 300A of the capacitance adjustment layer 30A shown in Figure 6A, the state shown in Figure 6C is obtained. In this case, the first and second dividing electrodes 300A1 and 300A2 of the multiple dividing electrodes 300A of the capacitance adjustment layer 30A are not exposed on the end face of the laminated chip, and only the third dividing electrode 300A3 of the multiple dividing electrodes 300A of the capacitance adjustment layer 30A is exposed on the end face of the laminated chip.

[0120] Therefore, when the external electrode 40 is formed later, the first and second dividing electrodes 300A1 and 300A2 of the three dividing electrodes 300A of the capacitance adjustment layer 30A are not connected to the external electrode 40 and become inactive dividing electrodes I, while the third dividing electrode 300A3 of the three dividing electrodes 300A of the capacitance adjustment layer 30A is connected to the external electrode 40 and becomes an active dividing electrode V. As a result, in this case, the capacitance of the multilayer ceramic capacitor 1 is reduced by the amount of the first and second dividing electrodes 300A1 and 300A2, which are inactive dividing electrodes I that are not connected to the external electrode 40.

[0121] Furthermore, when the internal electrode layer 30 on the end face of the laminated chip is processed to create holes in the first dividing electrode 300A1, the second dividing electrode 300A2, and the third dividing electrode 300A3 of the multiple dividing electrodes 300A of the capacitance adjustment layer 30A shown in Figure 6A, the state shown in Figure 6D is obtained. In this case, none of the multiple dividing electrodes 300A of the capacitance adjustment layer 30A are exposed on the end face of the laminated chip.

[0122] Therefore, when the external electrode 40 is formed later, none of the three dividing electrodes 300A of the capacitance adjustment layer 30A are connected to the external electrode 40, and they become inactive dividing electrodes I. As a result, in this case, the capacitance of the multilayer ceramic capacitor 1 is reduced by the amount of the inactive dividing electrodes I that are not connected to the external electrode 40: the first dividing electrode 300A1, the second dividing electrode 300A2, and the third dividing electrode 300A3.

[0123] In this way, in the multilayer ceramic capacitor 1 according to one embodiment of the present invention, the capacitance of each of the multiple divided electrodes 300A of the capacitance adjustment layer 30A can be adjusted more finely, so that even if there is variation in the capacitance of the manufactured multilayer ceramic capacitor 1, it can be adjusted to the required capacitance more reliably.

[0124] Furthermore, if there is a large variation in the capacitance of the manufactured multilayer ceramic capacitor 1, requiring a large amount of adjustment, the capacitance adjustment layer 30A may be modified by processing at least one of the multilayer chip end faces of the first internal electrode layer 31 and the second internal electrode layer 32 to create a hole. For example, if the internal electrode layer 30 on the end face of the multilayer chip is processed to create a hole in the first internal electrode layer 31 shown in Figure 7A, the state shown in Figure 7B is obtained. In this case, the first internal electrode layer 31 shown in Figure 7B is not exposed on the end face of the multilayer chip. Therefore, when the external electrode 40 is formed later, the first internal electrode layer 31 shown in Figure 7B is not connected to the external electrode 40, and the capacitance is reduced by the amount of the first internal electrode layer 31 shown in Figure 7B. The second internal electrode layer 32 is symmetrical to the first internal electrode layer 31 and has a similar configuration, so the reference numerals for the second internal electrode layer 32 are shown in Figures 7A and 7B, and a detailed explanation is omitted.

[0125] Furthermore, in the examples shown in Figures 6A to 6D, the capacitance adjustment layer 30A had three dividing electrodes 300A, but it is not limited to this; it may have two dividing electrodes 300A, or four or more dividing electrodes 300A. It is preferable that the number of dividing electrodes 300A be less than 14.

[0126] For example, the example shown in Figure 8 shows a capacitance adjustment layer 30B having four or more dividing electrodes 300B. The capacitance adjustment layer 30B has a plurality of dividing electrodes 300B, namely a first dividing electrode 300B1, a second dividing electrode 300B2, a third dividing electrode 300B3, a fourth dividing electrode 300B4, a fifth dividing electrode 300B5, and a sixth dividing electrode 300B6. In this case, since the capacitance adjustment layer 30B has six dividing electrodes 300B, the capacitance of each dividing electrode 300B becomes smaller, and furthermore, since it is possible to select a dividing electrode 300B from the six dividing electrodes 300B to be processed into an inactive dividing electrode I by drilling a hole, the capacitance can be adjusted more precisely.

[0127] A conductive paste, which will form the base electrode layers (first base electrode layer 50A, second base electrode layer 50B), is applied to both end faces of the laminate 10. In this embodiment, the base electrode layers are baked layers. A conductive paste containing glass components and metal is applied to the laminate 10 by a method such as dipping. A baking process is then performed to form the base electrode layers. The temperature of this baking process is preferably 700°C to 900°C.

[0128] Furthermore, when firing the laminated chip before firing and the conductive paste applied to the laminated chip simultaneously, it is preferable to form the baked layer by baking a ceramic material added instead of the glass component. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the added ceramic material. In this case, the conductive paste is applied to the laminated chip before firing, and the laminated chip and the conductive paste applied to the laminated chip are fired simultaneously to form a laminate 10 with a baked layer.

[0129] Subsequently, a plating layer is formed on the surface of the base electrode layer. In this embodiment, a first plating layer 60A is formed on the surface of the first base electrode layer 50A. Also, a second plating layer 60B is formed on the surface of the second base electrode layer 50B. In this embodiment, a Ni plating layer and a Sn plating layer are formed as the plating layers. When performing the plating process, either electrolytic plating or electroless plating may be used. However, electroless plating has the disadvantage of complicating the process because it requires pretreatment with a catalyst or the like to improve the plating deposition rate. Therefore, it is generally preferable to use electrolytic plating. The Ni plating layer and the Sn plating layer are formed sequentially, for example, by barrel plating.

[0130] When forming the base electrode layer as a thin film layer, masking or other methods are used to form the thin film layer as the base electrode layer in the area where the external electrode is to be formed. The thin film layer is formed by a thin film formation method such as sputtering or vapor deposition. The thin film layer is a layer of metal particles deposited on it that is 1.0 μm or less in thickness.

[0131] When a conductive resin layer is provided as the base electrode layer, the conductive resin layer may be arranged to cover the baking layer, or it may be placed directly on the laminate 10 without providing a baking layer. When a conductive resin layer is provided, a conductive resin paste containing a thermosetting resin and metal components is applied to the baking layer or the laminate 10, and then heat-treated at a temperature of 250 to 550°C or higher. This causes the thermosetting resin to heat-cur, forming a conductive resin layer. The atmosphere during this heat treatment is preferably an N2 atmosphere. Furthermore, to prevent resin scattering and oxidation of various metal components, the oxygen concentration is preferably 100 ppm or less.

[0132] Alternatively, the plating layer may be directly placed on the exposed portion of the internal electrode layer 30 of the laminate 10 without providing a base electrode layer. In this case, the first end face LS1 and the second end face LS2 of the laminate 10 are plated, and the plating layer is formed on the exposed portion of the internal electrode layer 30. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating has the disadvantage of complicating the process because it requires pretreatment with a catalyst or the like to improve the plating deposition rate. Therefore, electrolytic plating is generally preferred. Barrel plating is preferred as the plating method. Furthermore, if necessary, the upper plating layer formed on the surface of the lower plating layer may be formed using the same method as the lower plating layer.

[0133] A multilayer ceramic capacitor with external electrodes formed on it undergoes a full capacitance measurement. Therefore, the manufacturing method of the multilayer ceramic capacitor 1 in this embodiment includes a step of performing a full capacitance measurement of the multilayer ceramic capacitor 1 with external electrodes formed on it.

[0134] Through this manufacturing process, a multilayer ceramic capacitor 1 is produced.

[0135] As described above, the method for manufacturing a multilayer ceramic capacitor in this embodiment includes the steps of: manufacturing a laminate including a capacitance adjustment layer; providing a temporary electrode for preliminary capacitance measurement on the laminate; performing a preliminary capacitance measurement; forming an insulating region on a part of the end face side of the internal electrode layer if the capacitance exceeds a specified value in the preliminary measurement step; forming an external electrode on the laminate; and performing a final capacitance measurement of the multilayer ceramic capacitor on which the external electrode has been formed. This makes it possible to suppress characteristic defects during the manufacturing of the multilayer ceramic capacitor 1 more reliable and easier.

[0136] The process of forming the insulating region may include a removal process that removes at least a portion of the internal electrode layer exposed at the end face of the laminate. This makes it possible to easily form an insulating region on a portion of the end face of the internal electrode layer while more reliably and easily suppressing characteristic defects during the manufacturing of the multilayer ceramic capacitor 1.

[0137] The process of forming the insulating region may further include filling the region in the laminate 10 from which the internal electrode layer has been removed with resin. This makes it possible to easily form an insulating region on a part of the end face side of the internal electrode layer while suppressing characteristic defects during the manufacturing of the multilayer ceramic capacitor 1 more reliably and easily.

[0138] Furthermore, the process of forming the insulating region may also include a step of filling the region in the laminate 10 from which the internal electrode layer has been removed with a dielectric material. This makes it possible to form an insulating region on a part of the end face side of the internal electrode layer at a lower cost and more easily, while suppressing characteristic defects during the manufacturing of the multilayer ceramic capacitor 1 more reliably and easily.

[0139] Furthermore, the removal process may also be a process of removing the edges of the capacitance adjustment layer. This makes it possible to suppress characteristic defects during the manufacturing of the multilayer ceramic capacitor 1 more accurately, reliably, and easily.

[0140] Furthermore, the removal process may also be a process of removing the edges of the first internal electrode layer or the second internal electrode layer. This makes it possible to suppress characteristic defects during the manufacturing of the multilayer ceramic capacitor 1 more reliably and easily.

[0141] The multilayer ceramic capacitor 1 of this embodiment provides the following effects.

[0142] (1) The multilayer ceramic capacitor 1 of this embodiment has a plurality of stacked dielectric layers 20 and a plurality of internal electrode layers 30 stacked on the dielectric layers 20, and a laminate 10 having a first main surface TS1 and a second main surface TS2 facing the height direction T, a first side surface WS1 and a second side surface WS2 facing the width direction W perpendicular to the height direction T, and a first end surface LS1 and a second end surface LS2 facing the length direction L perpendicular to the height direction T and the width direction W, a first external electrode 40A disposed on the first end surface LS1, and a second external electrode disposed on the second end surface LS2 The multilayer ceramic capacitor comprises a portion electrode 40B, and the plurality of internal electrode layers 30 include a plurality of first internal electrode layers 31 connected to a first external electrode 40A, a plurality of second internal electrode layers 32 connected to a second external electrode 40B, and one or more capacitance adjustment layers 30A connected to the first external electrode 40A or the second external electrode 40B, facing the first internal electrode layer 31 or the second internal electrode layer 32, and including a plurality of divided electrodes 300A divided in the width direction W, and at least one of the plurality of internal electrode layers 30 is connected to the first external electrode 40A or the second external electrode 40B via an insulating region IA. This makes it possible to provide a multilayer ceramic capacitor that can easily suppress characteristic defects during manufacturing.

[0143] (2) The multilayer ceramic capacitor 1 of this embodiment includes a plurality of dividing electrodes 300A which include an effective dividing electrode V that is directly connected to the first external electrode 40A or the second external electrode 40B, and an inactive dividing electrode I that is connected to the first external electrode 40A or the second external electrode 40B via an insulating region IA. This makes it possible to suppress characteristic defects during manufacturing more reliably and easily.

[0144] (3) In this embodiment, at least one of the multiple divider electrodes 300A of the multilayer ceramic capacitor 1 is connected to the first external electrode 40A or the second external electrode 40B via an insulating region IA. This allows for fine adjustment of capacitance and makes it possible to suppress characteristic defects during manufacturing more reliable and easier.

[0145] (4) In the multilayer ceramic capacitor 1 of this embodiment, at least one of the first internal electrode layer 31 and the second internal electrode layer 32, the internal electrode layer 30, is connected to the first external electrode 40A or the second external electrode 40B via an insulating region IA. This makes it possible to suppress characteristic defects during manufacturing more reliably and easily.

[0146] (5) In this embodiment, the multilayer ceramic capacitor 1 has at least one of the first internal electrode layer 31 and the second internal electrode layer 32, the internal electrode layer 30, connected to the first external electrode 40A or the second external electrode 40B via an insulating region IA, and at least one of the multiple divider electrodes 300A, the divider electrode 300A, connected to the first external electrode 40A or the second external electrode 40B via an insulating region IA. This allows for fine adjustments while accommodating large capacitance deviations, and further ensures and facilitates the suppression of characteristic defects during manufacturing.

[0147] (6) In the multilayer ceramic capacitor 1 of this embodiment, at least one of the first internal electrode layer 31, the second internal electrode layer 32, and the capacitance adjustment layer 30A has an insulating region IA in a region of 1 μm to 3 μm in the direction toward the interior of the laminate 10 from the first end face LS1. This makes it possible to make fine adjustments while responding to large deviations in capacitance, and makes it possible to suppress characteristic defects during manufacturing more reliably and easily.

[0148] (7) In this embodiment, the multilayer ceramic capacitor 1 has an insulating region IA that is an air gap. This makes it possible to provide a multilayer ceramic capacitor that can easily suppress characteristic defects during manufacturing while keeping productivity and manufacturing costs down.

[0149] (8) In this embodiment, the capacitance adjustment layer 30A of the multilayer ceramic capacitor 1 is the internal electrode layer 30 closest to the first main surface TS1 or the second main surface TS2 among the plurality of internal electrode layers 30. This makes it possible to provide a multilayer ceramic capacitor that can easily suppress characteristic defects during manufacturing while keeping productivity and manufacturing costs down.

[0150] Note that the configuration of the multilayer ceramic capacitor 1 is not limited to the configurations shown in Figures 1 to 7B. For example, the multilayer ceramic capacitor 1 may be a double-gang, triple-gang, or quadruple-gang multilayer ceramic capacitor as shown in Figures 9, 10, and 11.

[0151] The multilayer ceramic capacitor 1 shown in Figure 9 is a double-gang multilayer ceramic capacitor 1, and as an internal electrode layer 30, it includes a first internal electrode layer 33 and a second internal electrode layer 34, as well as a floating internal electrode layer 35 that is not led out to either the first end face LS1 or the second end face LS2. The multilayer ceramic capacitor 1 shown in Figure 10 is a triple-gang multilayer ceramic capacitor 1, which includes a first floating internal electrode layer 35A and a second floating internal electrode layer 35B as floating internal electrode layers 35. The multilayer ceramic capacitor 1 shown in Figure 11 is a quadruple-gang multilayer ceramic capacitor 1, which includes a first floating internal electrode layer 35A, a second floating internal electrode layer 35B, and a third floating internal electrode layer 35C as floating internal electrode layers 35. In this way, by providing floating internal electrode layers 35 as internal electrode layers 30, the multilayer ceramic capacitor 1 has a structure in which the opposing electrode portion is divided into multiple parts. As a result, multiple capacitor components are formed between the opposing internal electrode layers 30, and these capacitor components are connected in series. Therefore, the voltage applied to each capacitor component becomes lower, and the voltage rating of the multilayer ceramic capacitor 1 can be increased. It goes without saying that the multilayer ceramic capacitor 1 in this embodiment may also have a multi-gang structure of four or more units.

[0152] The present invention is not limited to the configuration of the above embodiments, and can be modified and applied as appropriate without altering the essence of the invention. Furthermore, a combination of two or more of the desirable configurations described in the above embodiments also constitutes the present invention.

[0153] <1> A laminate having a plurality of stacked dielectric layers and a plurality of internal electrode layers stacked on the dielectric layers, and having a first main surface and a second main surface facing each other in the height direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the height direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the height direction and the width direction, comprising a first external electrode disposed on the first end surface and a second external electrode disposed on the second end surface, wherein the plurality of internal electrode layers have a plurality of first internal electrode layers connected to the first external electrode, a plurality of second internal electrode layers connected to the second external electrode, and one or more capacitance adjustment layers connected to the first external electrode or the second external electrode and facing the first internal electrode layer or the second internal electrode layer, and including a plurality of divided electrodes divided in the width direction, wherein at least one of the plurality of internal electrode layers is connected to the first external electrode or the second external electrode via an insulating region. <2> The multilayer ceramic capacitor according to <1>, wherein the plurality of dividing electrodes include an effective dividing electrode directly connected to the first external electrode or the second external electrode, and an inactive dividing electrode connected to the first external electrode or the second external electrode via the insulating region. <3> The multilayer ceramic capacitor according to <1> or <2>, wherein at least one of the plurality of dividing electrodes is connected to the first external electrode or the second external electrode via the insulating region. <4> The multilayer ceramic capacitor according to <1> or <2>, wherein at least one of the first internal electrode layer and the second internal electrode layer is connected to the first external electrode or the second external electrode via the insulating region. <5> The multilayer ceramic capacitor according to <1> or <2>, wherein at least one of the first internal electrode layer and the second internal electrode layer is connected to the first external electrode or the second external electrode via the insulating region, and at least one of the plurality of disconnecting electrodes is connected to the first external electrode or the second external electrode via the insulating region.<6> The multilayer ceramic capacitor according to any one of <1> to <5>, wherein at least one of the first internal electrode layer, the second internal electrode layer, and the capacitance adjustment layer has the insulating region arranged in a region of 1 μm to 3 μm in the direction toward the interior of the laminate from the first end face. <7> The multilayer ceramic capacitor according to any one of <1> to <6>, wherein the insulating region is an air gap. <8> The multilayer ceramic capacitor according to any one of <1> to <7>, wherein the capacitance adjustment layer is the internal electrode layer closest to the first main surface or the second main surface among the plurality of internal electrode layers.

[0154] 1 Multilayer ceramic capacitor 10 Laminate 20 Dielectric layer 30 Internal electrode layer 31 First internal electrode layer 32 Second internal electrode layer 30A Capacitance adjustment layer 300A Dividing electrode 40A First external electrode 40B Second external electrode IA Insulation region L Length direction LS1 First end face LS2 Second end face T Height direction TS1 First main surface TS2 Second main surface W Width direction WS1 First side surface WS2 Second side surface

Claims

1. A multilayer ceramic capacitor comprising: a plurality of stacked dielectric layers; a plurality of internal electrode layers stacked on the dielectric layers; a laminate having a first main surface and a second main surface facing each other in the height direction; a first side surface and a second side surface facing each other in the width direction perpendicular to the height direction; and a first end surface and a second end surface facing each other in the length direction perpendicular to the height direction and the width direction; a first external electrode disposed on the first end surface; and a second external electrode disposed on the second end surface, wherein the plurality of internal electrode layers comprises a plurality of first internal electrode layers connected to the first external electrode; a plurality of second internal electrode layers connected to the second external electrode; and one or more capacitance adjustment layers connected to the first external electrode or the second external electrode, facing the first internal electrode layer or the second internal electrode layer, and including a plurality of divided electrodes divided in the width direction, wherein at least one of the plurality of internal electrode layers is connected to the first external electrode or the second external electrode via an insulating region.

2. The multilayer ceramic capacitor according to claim 1, wherein the plurality of dividing electrodes include an effective dividing electrode directly connected to the first external electrode or the second external electrode, and an ineffective dividing electrode connected to the first external electrode or the second external electrode via the insulating region.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein at least one of the plurality of dividing electrodes is connected to the first external electrode or the second external electrode via the insulating region.

4. The multilayer ceramic capacitor according to claim 1 or 2, wherein at least one of the first internal electrode layer and the second internal electrode layer is connected to the first external electrode or the second external electrode via the insulating region.

5. The multilayer ceramic capacitor according to claim 1 or 2, wherein at least one of the first internal electrode layer and the second internal electrode layer is connected to the first external electrode or the second external electrode via the insulating region, and at least one of the plurality of disconnecting electrodes is connected to the first external electrode or the second external electrode via the insulating region.

6. The multilayer ceramic capacitor according to any one of claims 1 to 5, wherein at least one of the first internal electrode layer, the second internal electrode layer, and the capacitance adjustment layer has the insulating region arranged in a region of 1 μm to 3 μm in the direction toward the interior of the laminate from the first end face.

7. The multilayer ceramic capacitor according to any one of claims 1 to 6, wherein the insulating region is an air gap.

8. The multilayer ceramic capacitor according to any one of claims 1 to 7, wherein the capacitance adjustment layer is the internal electrode layer closest to the first main surface or the second main surface among the plurality of internal electrode layers.

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