Detection device

Abstract

Provided is a detection device with which it is possible to acquire a pulse wave propagation speed by using detection values simultaneously acquired at two different points, in a configuration having a plurality of optical sensors in a detection surface. This detection device: sequentially scans, in one frame period, optical sensor circuits (PAA) lined up in a second direction (Dy) in a first region (10A) and optical sensor circuits (PAA) lined up in the second direction (Dy) in a second region (10B), and simultaneously selects optical sensor circuits (PAA) lined up in a first direction (Dx) in the first region (10A) and optical sensor circuits (PAA) lined up in the first direction (Dx) in the second region (10B) to supply a drive signal; and acquires a pulse wave propagation speed on the basis of the detection value of an optical sensor circuit in the first region (10A) and the detection value of an optical sensor circuit in the second region (10B) simultaneously acquired in one frame period.

Description

Detection device

[0001] The present invention relates to a detection device.

[0002] A detection device having a plurality of optical sensors in a detection surface and capable of detecting a fingerprint pattern or a blood vessel pattern is known (for example, Patent Documents 1 and 2). In Patent Documents 1 and 2 below, the difference in the output timing of detection values obtained at two different points is corrected to calculate the pulse wave propagation speed.

[0003] Japanese Patent No. 7229492 Japanese Patent No. 7417968

[0004] In the above prior art, since the correction amount differs depending on the positions of the two points where the pulse wave is acquired, the calculation of the pulse wave propagation speed becomes complicated. Therefore, in a configuration having a plurality of optical sensors in the detection surface, a detection device capable of acquiring the pulse wave propagation speed using the detection values simultaneously acquired at two different points is desired.

[0005] An object of the present disclosure is to provide a detection device capable of acquiring a pulse wave propagation speed using detection values simultaneously acquired at two different points in a configuration having a plurality of optical sensors in a detection surface.

[0006] A detection device according to an aspect of the present disclosure includes a sensor region in which a plurality of optical sensor circuits each having an optical sensor are arranged in a first direction and a second direction intersecting the first direction, a drive circuit that supplies a drive signal to the plurality of optical sensor circuits, and a detection circuit that acquires detection values respectively output from the plurality of optical sensor circuits when the drive signal is supplied and acquires vital data of a detection object. The sensor region includes a first region and a second region provided side by side with the first region in the second direction. The drive circuit sequentially scans, in one frame period, the optical sensor circuits arranged in the second direction in the first region and the optical sensor circuits arranged in the second direction in the second region, and simultaneously selects the optical sensor circuits arranged in the first direction in the first region and the optical sensor circuits arranged in the first direction in the second region and supplies the drive signal. The detection circuit acquires a pulse wave propagation speed based on the detection values of the optical sensor circuits in the first region and the detection values of the optical sensor circuits in the second region simultaneously acquired within one frame period.

[0007] Figure 1 is a plan view showing a detection device according to Embodiment 1. Figure 2 is a diagram showing an example of the block configuration of the detection device according to Embodiment 1. Figure 3 is a circuit diagram showing the detection device according to Embodiment 1. Figure 4 is a circuit diagram showing the connection configuration between the optical sensor circuit and the AFE circuit. Figure 5 is a schematic partial cross-sectional view of the optical sensor according to Embodiment 1. Figure 6 is a timing waveform diagram showing an example of operation of the detection device according to Embodiment 1 during one frame period. Figure 7 is a conceptual diagram showing the scanning direction in the first and second regions of the detection device 1 according to Embodiment 1. Figure 8A is a diagram showing the pulse wave waveform acquired by the detection device according to Embodiment 1. Figure 8B is a diagram showing the pulse wave waveform acquired by the detection device according to Embodiment 1. Figure 8C is a diagram showing the pulse wave waveform acquired by the detection device according to Embodiment 1. Figure 9 is a flowchart showing an example of the detection processing flow in the detection device according to Embodiment 1. Figure 10 is a subflowchart showing an example of the detection value acquisition process. Figure 11 is a subflowchart showing an example of the pulse wave component extraction process. Figure 12 is a subflowchart showing an example of the first pulse wave component maximum value extraction process. Figure 13 is a subflowchart showing an example of the process for extracting the maximum value of the second pulse wave component. Figure 14 is a subflowchart showing an example of the process for acquiring the pulse wave propagation velocity. Figure 15 is a conceptual diagram showing the scanning directions in the first and second regions of the detection device 1 according to a modified example of Embodiment 1. Figure 16 is a subflowchart showing an example of the process for acquiring the pulse wave propagation velocity according to a modified example. Figure 17 is a circuit diagram showing the detection device according to Embodiment 2. Figure 18 is a circuit diagram showing the detection device according to a modified example of Embodiment 2.

[0008] Embodiments for carrying out the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the embodiments described below. Furthermore, the components described below include those that are easily conceivable to those skilled in the art, and those that are substantially the same. Moreover, the components described below can be combined as appropriate. Furthermore, the disclosure is merely an example, and any modifications that can be easily conceived by those skilled in the art while maintaining the spirit of the invention are naturally included within the scope of the present invention. In addition, the drawings may schematically represent the width, thickness, shape, etc., of each part compared to the actual embodiment in order to clarify the explanation, but these are merely examples and do not limit the interpretation of the present invention. Furthermore, in this specification and in each drawing, elements similar to those described above with respect to previously shown drawings are denoted by the same reference numerals, and detailed explanations may be omitted as appropriate.

[0009] (Embodiment 1) Figure 1 is a plan view showing a detection device according to Embodiment 1. In this disclosure, the detection device 1 is configured as a detection device that is attached to, for example, the finger or wrist of a subject and detects vital data, which is information about the subject's biological system.

[0010] As shown in Figure 1, the detection device 1 includes a sensor substrate 21, a sensor area 10, a gate line drive circuit 15, a signal line selection circuit 16, an AFE (Analog Front End) circuit 48, a control circuit 122, a power supply circuit 123, a first light source 61, and a second light source 62.

[0011] The detection device 1 is electrically connected to the host. The host is, for example, a higher-level control device of the equipment (not shown) to which the detection device 1 is applied. The detection device 1 according to Embodiment 1 transmits the acquired biological information to the host via the output circuit 126.

[0012] The control board 121 is electrically connected to the sensor substrate 21 via a flexible printed circuit board 71. An AFE circuit 48 is provided on the flexible printed circuit board 71. The control board 121 is provided with a control circuit 122, a power supply circuit 123, and an output circuit 126.

[0013] The control circuit 122 is, for example, a control integrated circuit (IC) that outputs logic control signals. The control circuit 122 may also be a programmable logic device (PLD) such as an FPGA (Field Programmable Gate Array).

[0014] The control circuit 122 supplies control signals to the sensor area 10, the gate line drive circuit 15, and the signal line selection circuit 16 to control the detection operation of the sensor area 10. The control circuit 122 also supplies control signals to the first light source 61 and the second light source 62 to control whether the first light source 61 and the second light source 62 are lit or not.

[0015] The power supply circuit 123 supplies a voltage signal such as the sensor power supply potential VDDSNS (see Figure 4) to the sensor area 10, the gate line drive circuit 15, and the signal line selection circuit 16. The power supply circuit 123 also supplies the power supply voltage to the first light source 61 and the second light source 62.

[0016] The output circuit 126 is, for example, a USB controller IC, which controls communication between the control circuit 122 and the host.

[0017] The sensor substrate 21 has a detection region AA and a peripheral region GA. The detection region AA is a region in which a plurality of optical sensors PD (see Figure 4) of the sensor region 10 are arranged in a matrix. The peripheral region GA is the region between the outer periphery of the detection region AA and the edge of the sensor substrate 21, and is a region in which no optical sensors PD are provided.

[0018] The gate line drive circuit 15 and the signal line selection circuit 16 are provided in the peripheral region GA. Specifically, the gate line drive circuit 15 is provided in the region of the peripheral region GA that extends along the second direction Dy. The signal line selection circuit 16 is provided in the region of the peripheral region GA that extends along the first direction Dx, and is provided between the sensor region 10 and the AFE circuit 48.

[0019] The first direction Dx is a single direction in a plane parallel to the sensor substrate 21. The second direction Dy is a single direction in a plane parallel to the sensor substrate 21 and is perpendicular to the first direction Dx. The second direction Dy may intersect the first direction Dx without being perpendicular to it.

[0020] Multiple first light sources 61 are provided on the first light source substrate 51 and are arranged along the second direction Dy. Multiple second light sources 62 are provided on the second light source substrate 52 and are arranged along the second direction Dy. The first light source substrate 51 and the second light source substrate 52 are electrically connected to the control circuit 122 and the power supply circuit 123, respectively, via terminals 124 and 125 provided on the control board 121.

[0021] The multiple first light sources 61 and the multiple second light sources 62 can be, for example, inorganic LEDs (Light Emitting Diodes) or organic EL (OLEDs: Organic Light Emitting Diodes).

[0022] The first light source 61 and the second light source 62 emit at least one of visible light, near-infrared light, and infrared light. The first light source 61 and the second light source 62 may each emit light of different wavelengths, or they may each emit light of the same wavelength. Specifically, for example, in a configuration having at least the first light source 61 (or the second light source 62), the first light emitted by the first light source 61 (or the second light source 62) may be red light or infrared light, or blue light or green light. Alternatively, for example, in a configuration having the first light source 61 and the second light source 62, the first light emitted by the first light source 61 may be red light, and the second light emitted by the second light source 62 may be infrared light. The present disclosure is not limited by the emission color of the first light source 61 and the second light source 62.

[0023] In this disclosure, light emitted from the first light source 61 and the second light source 62 is reflected or transmitted from, for example, the surface or inside of the subject's fingers or wrist, and enters the sensor area 10. This makes it possible to detect vital data, which is information about the body inside the finger Fg, etc. In the detection device 1 according to this disclosure, the vital data, which is information about the body, includes at least the subject's pulse wave. In addition to the subject's pulse wave, the vital data detectable by the detection device 1 may also include, for example, the subject's fingerprints, vascular image, blood oxygen saturation, etc.

[0024] Figure 2 is a block diagram showing an example configuration of a detection device according to an embodiment. As shown in Figure 2, the detection device 1 further includes a detection control circuit 11 and a detection circuit 40.

[0025] The sensor region 10 has multiple photosensitive sensors PD. The photosensitive sensors PD in the sensor region 10 are organic photodiodes (OPDs), and they output an electrical signal corresponding to the irradiated light as a detection signal Vdet to the signal line selection circuit 16. The sensor region 10 also performs detection according to the gate drive signal Vgcl supplied from the gate line drive circuit 15.

[0026] The detection control circuit 11 is a circuit that supplies control signals to the gate line drive circuit 15, the signal line selection circuit 16, and the detection circuit 40, respectively, and controls their operation. The detection control circuit 11 supplies various control signals such as the start signal STV, the clock signal CK, and the reset signal RST1 to the gate line drive circuit 15. The detection control circuit 11 also supplies various control signals such as the selection signal ASW to the signal line selection circuit 16. Furthermore, the detection control circuit 11 supplies various control signals to the first light source 61 and the second light source 62 to control their illumination and de-illumination.

[0027] The gate line drive circuit 15 is a circuit that drives multiple gate lines GCL (see Figure 3) based on various control signals. The gate line drive circuit 15 sequentially or simultaneously selects multiple gate lines GCL and supplies a gate drive signal Vgcl to the selected gate lines GCL. As a result, the gate line drive circuit 15 selects multiple optical sensors PD connected to the gate lines GCL.

[0028] The detection circuit 40 includes a signal line selection circuit 16, an AFE circuit 48, a signal processing circuit 44, a memory circuit 46, and a detection timing control circuit 47. The detection timing control circuit 47 controls the AFE circuit 48 and the signal processing circuit 44 to operate synchronously based on a control signal supplied from the detection control circuit 11.

[0029] The signal line selection circuit 16 is a switch circuit that sequentially or simultaneously selects a plurality of signal lines SGL (see Figure 3). The signal line selection circuit 16 is, for example, a multiplexer. Based on the selection signal ASW supplied from the detection control circuit 11, the signal line selection circuit 16 connects the selected signal line SGL to the AFE circuit 48. As a result, the signal line selection circuit 16 outputs the detection signal Vdet of the optical sensor PD to the AFE circuit 48.

[0030] The AFE circuit 48 detects the detection signals of each optical sensor PD output from the sensor area 10 in a time series. The AFE circuit 48 is, for example, an analog front-end IC.

[0031] The AFE circuit 48 is a signal processing circuit that has at least the functions of a detection signal amplification circuit 42 and an A / D conversion circuit 43. The detection signal amplification circuit 42 amplifies the detection signal Vdet. The A / D conversion circuit 43 converts the analog signal output from the detection signal amplification circuit 42 into a digital signal at a predetermined sampling period.

[0032] In this disclosure, the signal processing circuit 44 and the memory circuit 46 are included in the control circuit 122.

[0033] The signal processing circuit 44 acquires at least the pulse wave of the subject as biological information based on the detection values ​​of each optical sensor PD output from the AFE circuit 48. In addition, in this disclosure, the signal processing circuit 44 calculates the pulse wave propagation velocity based on the relationship between the difference between pulse waves acquired at two different points and the distance between the two points from which the pulse waves were acquired.

[0034] The memory circuit 46 temporarily stores the signals processed by the signal processing circuit 44. The memory circuit 46 may include, for example, RAM (Random Access Memory), ROM (Read Only Memory), EEPROM (Electrically Erasable Programmable Read Only Memory), etc. Alternatively, the memory circuit 46 may be a register circuit or the like.

[0035] Next, an example of the circuit configuration of the detection device 1 will be described. Figure 3 is a circuit diagram showing the detection device according to Embodiment 1.

[0036] In this disclosure, the sensor region 10 includes, as shown in Figure 3, a first region 10A in which a plurality of optical sensor circuits PAA (optical sensor PDs) are arranged in a first direction Dx and a second direction Dy intersecting the first direction Dx, and a second region 10B in which a plurality of optical sensor circuits PAA (optical sensor PDs) are arranged in the first direction Dx and the second direction Dy, and which is provided side by side with the first region 10A and the second direction Dy. In Figure 3, for convenience, the detection circuit 40 is exemplified as detection circuits 40A and 40B.

[0037] In Embodiment 1, a plurality of optical sensor circuits PAA (optical sensor PD) are arranged in a matrix in the first region 10A and the second region 10B, respectively.

[0038] The gate line GCL extends in the first direction Dx and is connected to multiple optical sensor circuits PAA arranged in the first direction Dx. Furthermore, the multiple gate lines GCL are arranged in the second direction Dy and each is connected to a gate line drive circuit 15.

[0039] In the first region 10A, the signal line SGL extends in the second direction Dy and is connected to the optical sensors PD of the multiple optical sensor circuits PAA arranged in the second direction Dy. The multiple signal lines SGL are also arranged in the first direction Dx and are connected to the detection circuit 40A and the reset circuit 17, respectively.

[0040] In the second region 10B, the signal line SGL extends in the second direction Dy and is connected to the optical sensor PD of a plurality of optical sensor circuits PAA arranged in the second direction Dy. Also, the plurality of signal lines SGL are arranged in the first direction Dx and are respectively connected to the detection circuit 40B and the reset circuit 17.

[0041] The resolution of the sensor is, for example, 508 dpi (dot per inch), and the number of cells is 252×256. The substantial area of one sensor is, for example, substantially 50×50 μm ２ and the area of the detection region AA is, for example, 12.6×12.8 mm ２ as such.

[0042] The gate line drive circuit 15 receives various control signals such as the start signal STV, the clock signal CK, the reset signal RST1, etc. from the control circuit 122 (see FIG. 1). Based on the various control signals, the gate line drive circuit 15 simultaneously selects the optical sensors PD arranged in the first direction Dx in the first region 10A and the optical sensors PD arranged in the first direction Dx in the second region 10B, and sequentially selects the optical sensors PD arranged in the second direction Dy in the first region 10A and the optical sensors PD arranged in the second direction Dy in the second region 10B respectively. Thereby, the optical sensors PD in the first region 10A and the optical sensors PD in the second region 10B are simultaneously selected. In FIG. 3, a mode in which the gate line GCL connected to the optical sensors PD arranged in the first direction Dx in the first region 10A and the gate line GCL connected to the optical sensors PD arranged in the first direction Dx in the second region 10B are respectively provided is illustrated, but the gate line GCL connected to the simultaneously selected optical sensors PD may be common to the first region 10A and the second region 10B.

[0043] The gate line drive circuit 15 supplies a gate drive signal Vgcl to the simultaneously selected optical sensors PD in the first region 10A and the second region 10B via the gate line GCL. The gate drive signal Vgcl has a pulsed waveform having the power supply voltage VDD which is a high level voltage and the power supply voltage VSS which is a low level voltage.

[0044] Figure 4 is a circuit diagram showing the connection configuration between the optical sensor circuit and the AFE circuit. As shown in Figure 4, the optical sensor circuit PAA includes an optical sensor PD, a capacitive element Ca, and a first switching element Tr. The first switching element Tr is constituted by a thin film transistor, and in this example, it is constituted by an n-channel MOS (Metal Oxide Semiconductor) type TFT (Thin Film Transistor).

[0045] The gate of the first switching element Tr is connected to the gate line GCL. The source of the first switching element Tr is connected to the signal line SGL. The drain of the first switching element Tr is connected to the cathode of the optical sensor PD and the capacitive element Ca.

[0046] The sensor power signal VDDSNS is supplied from the power supply circuit 123 to the anode of the optical sensor PD. Also, the reference signal COM, which is the initial potential of the signal line SGL and the capacitive element Ca, is supplied from the power supply circuit 123 to the signal line SGL and the capacitive element Ca.

[0047] Specifically, the control circuit 122 supplies the reset signal RST2 to the reset circuit 17. As a result, a plurality of fourth switching elements TrR are turned on, and the reference signal COM supplied from the power supply circuit 123 is supplied to each optical sensor circuit PAA.

[0048] When the optical sensor circuit PAA is irradiated with light, a current corresponding to the amount of light flows through the optical sensor PD, and thereby charges are accumulated in the capacitive element Ca. When the first switching element Tr is turned on, a current flows through the signal line SGL according to the charges accumulated in the capacitive element Ca. The signal line SGL is connected to the AFE circuit 48 via the third switching element TrS of the signal line selection circuit 16. Thereby, the detection device 1 can acquire a detection value corresponding to the amount of light irradiated to the optical sensor PD for each optical sensor circuit PAA.

[0049] The AFE circuit 48 is connected to the signal line SGL when the switch SSW is turned on during the readout period Pdet (see Figure 6). The detection signal amplification circuit 42 of the AFE circuit 48 converts the fluctuations in the current supplied from the signal line SGL into fluctuations in voltage and amplifies them. A reference potential (Vref) with a fixed potential is input to the non-inverting input (+) of the detection signal amplification circuit 42, and the signal line SGL is connected to the inverting input terminal (-). In this embodiment, the same signal as the reference signal COM is input as the reference potential (Vref) voltage. The detection signal amplification circuit 42 also has a capacitive element Cb and a reset switch RSW. During the reset period Prst (see Figure 6), the reset switch RSW is turned on, and the charge of the capacitive element Cb is reset.

[0050] Next, the configuration of the optical sensor PD will be described. Figure 5 is a schematic partial cross-sectional view of the optical sensor according to Embodiment 1. The sensor area 10 of the detection device 1 comprises a sensor substrate 21, a sensor structure 22, and a protective film 23. The sensor substrate 21 is, for example, an insulating substrate formed of a film-like resin.

[0051] The sensor structure 22 includes a TFT layer 221, an anode electrode (lower electrode) 222, a photosensor PD, and a cathode electrode (upper electrode) 226.

[0052] The TFT layer 221 is provided with various wirings such as gate lines GCL and signal lines SGL. The sensor substrate 21 and the TFT layer 221 are a drive circuit that drives the sensor and are also called a backplane.

[0053] The optical sensor PD comprises an active layer 224, an electron transport layer (lower buffer layer) 223 provided between the active layer 224 and the anode electrode (lower electrode) 222, and a hole transport layer (upper buffer layer) 225 provided between the active layer 224 and the cathode electrode (upper electrode) 226. In other words, the electron transport layer (lower buffer layer) 223, the active layer 224, and the hole transport layer (upper buffer layer) 225 of the optical sensor PD are stacked in this order in a direction perpendicular to the sensor substrate 21.

[0054] The active layer 224 changes its properties (e.g., voltage-current characteristics and resistance) depending on the light it is irradiated with. Organic materials are used as the material for the active layer 224. Specifically, the active layer 224 is a bulk heterostructure in which a p-type organic semiconductor and an n-type organic semiconductor, an n-type fullerene derivative (PCBM), are mixed. For example, C13 is a low-molecular-weight organic material used as the active layer 224. ６０ (Fullerene), PCBM (Phenyl C61-butyric acid methyl ester), CuPc (Copper Phthalocyanine), F １６ CuPc (fluorinated copper phthalocyanine), rubrene (5,6,11,12-tetraphenyltetracene), PDI (perylene derivative), etc. can be used.

[0055] The active layer 224 can be formed by vapor deposition (Dry Process) using these low-molecular-weight organic materials. In this case, the active layer 224 can be, for example, CuPc and F １６ A multilayer film with CuPc, or rubrene and C ６０ It may be a laminated film. The active layer 224 can also be formed by a wet process. In this case, the active layer 224 is made of a material that combines the low molecular weight organic material and the polymer organic material described above. As the polymer organic material, for example, P3HT (poly(3-hexylthiophene)), F8BT (F8-alt-benzothiadiazole), etc. can be used. The active layer 224 can be a film in which P3HT and PCBM are mixed, or a film in which F8BT and PDI are mixed.

[0056] The electron transport layer (lower buffer layer) 223 and the hole transport layer (upper buffer layer) 225 are provided to facilitate the arrival of electrons and holes generated in the active layer 224 at the anode electrode (lower electrode) 222 or the cathode electrode (upper electrode) 226. The electron transport layer (lower buffer layer) 223 is in direct contact with the anode electrode (lower electrode) 222. The active layer 224 is in direct contact with the electron transport layer (lower buffer layer) 223. The material used for the electron transport layer (lower buffer layer) 223 is ethoxylated polyethyleneimine (PEIE).

[0057] The hole transport layer (upper buffer layer) 225 is in direct contact with the active layer 224, and the cathode electrode (upper electrode) 226 is in direct contact with the hole transport layer (upper buffer layer) 225. The hole transport layer (upper buffer layer) 225 is a metal oxide layer. As the metal oxide layer, tungsten oxide (WO ３ ), molybdenum oxide, etc. are used.

[0058] Note that the materials and manufacturing methods for the electron transport layer (lower buffer layer) 223, the active layer 224, and the hole transport layer (upper buffer layer) 225 are merely examples, and other materials and manufacturing methods may be used.

[0059] The anode electrode (lower electrode) 222 and the cathode electrode (upper electrode) 226 face each other with the light sensor PD in between. The cathode electrode (upper electrode) 226 is made of a transparent conductive material such as ITO (Indium Tin Oxide). The anode electrode (lower electrode) 222 is made of a metallic material such as silver (Ag) or aluminum (Al). Alternatively, the anode electrode (lower electrode) 222 may be made of an alloy material containing at least one of these metallic materials.

[0060] By controlling the film thickness of the anode electrode (lower electrode) 222, the anode electrode (lower electrode) 222 can be formed as a translucent semi-transparent electrode. For example, by forming the anode electrode (lower electrode) 222 with a 10 nm thick Ag thin film, it can have approximately 60% translucency. In this case, the photosensor PD can detect the first light LD irradiated from, for example, the first surface FD side.

[0061] The protective film 23 is provided on the second surface FU, covering the cathode electrode (upper electrode) 226. The protective film 23 is a passivation film and is provided to protect the photosensor PD.

[0062] In Figure 4, a configuration is shown in which the sensor power supply signal VDDSNS is supplied to the anode of the optical sensor PD from the power supply circuit 123, and the signal line SGL and a reference signal COM, which is the initial potential of the capacitive element Ca, are supplied to the cathode of the optical sensor PD from the power supply circuit 123. However, for example, a configuration in which the sensor power supply signal VDDSNS is supplied to the cathode of the optical sensor PD from the power supply circuit 123, and the signal line SGL and a reference signal COM, which is the initial potential of the capacitive element Ca, are supplied to the anode of the optical sensor PD from the power supply circuit 123. In this case, unlike the configuration described above, the optical sensor PD has an active layer 224, a hole transport layer (lower buffer layer) 223 provided between the active layer 224 and the cathode electrode (lower electrode) 222, and an electron transport layer (upper buffer layer) 225 provided between the active layer 224 and the anode electrode (upper electrode) 226. In other words, the hole transport layer (lower buffer layer) 223, the active layer 224, and the electron transport layer (upper buffer layer) 225 of the optical sensor PD are stacked in this order in a direction perpendicular to the sensor substrate 21.

[0063] Furthermore, in this disclosure, the optical sensor PD is not limited to an organic photodiode (OPD). The optical sensor PD may be, for example, a silicon photodiode (SiPD).

[0064] Next, an example of the operation of the detection device 1 will be described. Figure 6 is a timing waveform diagram showing an example of the operation of the detection device according to Embodiment 1 during one frame period. In Figure 6, M is the number of columns in which the optical sensor circuits PAA (optical sensor PD) are arranged in the second direction Dy in the first region 10A (or second region 10B), and N is the number of rows in which the optical sensor circuits PAA (optical sensor PD) are arranged in the first direction Dx in the first region 10A (or second region 10B). In other words, the first region 10A (or second region 10B) is a region in which optical sensor circuits PAA (optical sensor PD) are arranged in M ​​columns and N rows, respectively.

[0065] As shown in Figure 6, the detection device 1 has a reset period Prst, an effective exposure period Pex, and a readout period Pdet.

[0066] During the reset period Prst, the gate line drive circuit 15 sequentially sets the gate drive signal Vgcl supplied to the gate line GCL to a high voltage level. As a result, the first switching element Tr of the optical sensor circuit PAA, which is aligned in the first direction Dx, conducts sequentially, and a reference signal COM is supplied to the optical sensor PD. Consequently, the charge accumulated in the capacitance of the capacitive element Ca is reset.

[0067] Each effective exposure period Pex(1), ..., Pex(N) begins when the gate drive signal Vgcl transitions from a high-level voltage to a low-level voltage during the reset period Prst. Each effective exposure period Pex(1), ..., Pex(N) ends when the gate drive signal Vgcl transitions from a low-level voltage to a high-level voltage during the readout period Pdet. The exposure time for each effective exposure period Pex(1), ..., Pex(N) is equal.

[0068] During the effective exposure period Pex, a current flows in accordance with the light irradiated onto the photosensor PD, and charge accumulates in each capacitive element Ca.

[0069] The control circuit 122 lowers the reset signal RST2 to a low voltage before the readout period Pdet begins. This stops the supply of the reference signal COM to the optical sensor circuit PAA.

[0070] During the readout period Pdet, the gate line drive circuit 15, similar to the reset period Prst, sequentially sets the gate drive signal Vgcl supplied to the gate line GCL to a high voltage level. As a result, the first switching elements Tr of the optical sensor circuits PAA, which are arranged in the first direction Dx, sequentially conduct, and the detection signal Vdet for each optical sensor circuit PAA is supplied to the AFE circuit 48 via the signal line selection circuit 16.

[0071] Figure 7 is a conceptual diagram showing the scanning directions in the first and second regions of the detection device 1 according to Embodiment 1. As shown in Figure 7, in Embodiment 1, the scanning direction in the first region 10A and the scanning direction in the second region 10B are opposite.

[0072] More specifically, in the example shown in Figure 7, the gate line drive circuit 15 sequentially scans from gate line GCL(N) to gate line GCL(1) in the first region 10A, and then sequentially scans from gate line GCL(N+1) to gate line GCL(2N) in the second region 10B, within one frame period.

[0073] Figures 8A, 8B, and 8C show the pulse wave waveforms acquired by the detection device according to Embodiment 1. In Figures 8A, 8B, and 8C, the propagation direction of the pulse wave is set to the descending direction of the gate line GCL (from bottom to top in the figures).

[0074] Figure 8A illustrates the pulse waves acquired by the first and nth rows of the optical sensor circuit PAA within the first region 10A. The detected value acquired by the first row of the optical sensor circuit PAA in the first region 10A is acquired with a delay compared to the detected value acquired by the nth row of the optical sensor circuit PAA. As a result, in the example shown in Figure 8A, the peak detection time T(N) of the pulse wave acquired by the nth row of the optical sensor circuit PAA in the first region 10A is the time obtained by adding the pulse wave propagation time (PTT) and the detection delay time (dT) to the peak detection time T(1) of the pulse wave acquired by the first row of the optical sensor circuit PAA in the first region 10A.

[0075] Figure 8B illustrates the pulse waves acquired by the optical sensor circuits PAA in the N+1th and 2Nth rows within the second region 10B. The detected value acquired by the optical sensor circuit PAA in the 2Nth row in the second region 10B is acquired with a delay compared to the detected value acquired by the optical sensor circuit PAA in the N+1th row. As a result, in the example shown in Figure 8B, the peak detection time T(2N) of the pulse wave acquired by the optical sensor circuit PAA in the 2Nth row in the second region 10B is the time obtained by adding the pulse wave propagation time (-PTT) and the detection delay time (dT) to the peak detection time T(N+1) of the pulse wave acquired by the optical sensor circuit PAA in the N+1th row in the second region 10B.

[0076] Figure 8C illustrates the pulse waves acquired by the optical sensor circuits PAA in the first row of the first region 10A and the 2Nth row of the second region 10B. The detected value acquired by the optical sensor circuit PAA in the first row of the first region 10A is acquired simultaneously with the detected value acquired by the optical sensor circuit PAA in the 2Nth row of the second region 10B. As a result, in the example shown in Figure 8C, the peak detection time T(1) of the pulse wave acquired by the optical sensor circuit PAA in the first row of the first region 10A is the time obtained by adding the pulse wave propagation time (PTT) to the peak detection time T(2N) of the pulse wave acquired by the optical sensor circuit PAA in the 2Nth row of the second region 10B.

[0077] In this disclosure, the detection circuit 40 (signal processing circuit 44) acquires the pulse wave propagation velocity based on the detection values ​​of the optical sensor circuit PAA in the first region 10A and the detection values ​​of the optical sensor circuit PAA in the second region 10B, which are acquired simultaneously within one frame period. Specifically, as shown in Figure 8C, for example, the pulse wave propagation velocity is calculated using the detection value acquired by the first row of the optical sensor circuit PAA in the first region 10A and the detection value acquired by the 2Nth row of the optical sensor circuit PAA in the second region 10B. This makes it possible to obtain a pulse wave propagation velocity that eliminates the effect of the detection delay time (dT).

[0078] The following describes a specific example of acquiring pulse wave velocity. Figure 9 is a flowchart showing an example of the detection process flow in the detection device according to Embodiment 1.

[0079] In the following explanation, the variable f represents the frame number for which the detected value was acquired, and the variable p represents the number for which the detected value was acquired within one frame period. Furthermore, the variable "X(f)[p]" represents the p-th variable acquired within the f-th frame period.

[0080] In the detection processing flow shown in Figure 9, first, the signal processing circuit 44 executes the detection value acquisition process shown in Figure 10 to acquire the detection values ​​Raw1(f)[p] for multiple frames in each optical sensor circuit PAA within the first region 10A, and the detection values ​​Raw2(f)[p] for multiple frames in each optical sensor circuit PAA within the second region 10B (Figure 9, step S100). Figure 10 is a subflowchart showing an example of the detection value acquisition process.

[0081] When acquiring detection values ​​Raw1(f)[p] and Raw2(f)[p] for multiple frames, the number of frames F to acquire is set to a number that allows for the acquisition of multiple pulse wave peaks (for example, about 10 times). The number of frames F to acquire is stored, for example, in the memory circuit 46. In addition, each detection value Raw1(f)[p] and Raw2(f)[p] is stored, for example, in the memory circuit 46.

[0082] Specifically, in the detection value acquisition process shown in Figure 10, the signal processing circuit 44 sets the detection value acquisition frame number f to 1 (f=1) (step S101), sets the detection value acquisition number p within one frame period to 1 (p=1) (step S102), and acquires the detection values ​​Raw1(f)[p] and Raw2(f)[p] (step S103). The signal processing circuit 44 stores the acquired detection values ​​Raw1(f)[p] and Raw2(f)[p] in the memory circuit 46.

[0083] Next, the signal processing circuit 44 increments the detected value acquisition number p (p = p + 1, step S104) and determines whether the detected value acquisition number p has reached the number of rows N in which the optical sensor circuits PAA (optical sensor PD) are aligned in the first direction Dx within the first region 10A and the second region 10B (step S105). If p[N] (step S105; No), the process returns to step S103.

[0084] If p = N (step S105; Yes), the signal processing circuit 44 then increments the detected value acquisition frame number f (f = f + 1, step S106) and determines whether the detected value acquisition frame number f has reached the number of acquired frames F (step S107). If f[F] (step S107; No), the process returns to step S102.

[0085] By repeating the process from step S102 to step S107 F times, the detected values ​​Raw1(f)[p] and Raw2(f)[p] for F frames are stored in the memory circuit 46.

[0086] When f = F (step S107; Yes), the process returns to the detection flow shown in Figure 9, and subsequently, the signal processing circuit 44 executes the pulse wave component extraction process shown in Figure 11 (Figure 11, step S200). Figure 11 is a subflowchart showing an example of the pulse wave component extraction process.

[0087] In the pulse wave component extraction process shown in Figure 11, the signal processing circuit 44 sets the detection value acquisition number p to 1 (p=1) (step S201), reads out the detection values ​​Raw1(f)[p] and Raw2(f)[p] for F frames from the memory circuit 46 (step S202), performs a Fourier transform (here, FFT (Fast Fourier Transform) process) on the readout detection values ​​Raw1(f)[p] and Raw2(f)[p] for F frames as time-domain data, generates frequency-domain data Sdet1[p] and Sdet2[p] (step S203), and extracts the peak values ​​Speak1[p] and Speak2[p] in the frequency band corresponding to the pulse wave (for example, 0.5 Hz to 3 Hz) (step S204). As a result, the pulse wave components of the signals acquired in the first region 10A and the second region 10B are extracted as peak values ​​Speak1[p] and Speak2[p]. The signal processing circuit 44 stores the extracted peak values ​​Speak1[p] and Speak2[p] in the memory circuit 46.

[0088] Then, the signal processing circuit 44 increments the detected value acquisition number p (p = p + 1, step S205) and determines whether the detected value acquisition number p has reached the number of rows N in which the optical sensor circuits PAA (optical sensor PD) are aligned in the first direction Dx within the first region 10A and the second region 10B (step S206). If p[N] (step S206; No), the process returns to step S202.

[0089] By repeating the process from step S202 to step S206 P times, the pulse wave components of the signals acquired in the first region 10A and the second region 10B, respectively, are stored in the memory circuit 46 as peak values ​​Speak1[p] and Speak2[p].

[0090] When p = N (step S206; Yes), the detection process flow shown in Figure 9 is returned, and subsequently, the signal processing circuit 44 executes the first pulse wave component maximum value extraction process shown in Figure 12 (Figure 12, step S300). Figure 12 is a subflowchart showing an example of the first pulse wave component maximum value extraction process.

[0091] In the first pulse wave component maximum value extraction process shown in Figure 12, the signal processing circuit 44 initializes the first maximum signal intensity, Speak1_max[P1], which is the maximum value of the pulse wave component of the signal acquired in the first region 10A, to "0" (Speak1_max[P1] = 0) (step S301) and stores it in the memory circuit 46.

[0092] Next, the signal processing circuit 44 sets the detected value acquisition number p to 1 (p=1) (step S302), reads the peak value Speak1[p] of the signal acquired in the first region 10A from the memory circuit 46 (step S303), and determines whether the read peak value Speak1[p] is greater than the first maximum signal intensity Speak1_max[P1] (Speak1[p]>Speak1_max[P1], step S304).

[0093] If the peak value Speak1[p] is less than or equal to the first maximum signal intensity Speak1_max[P1] (Speak1[p] ≤ Speak1_max[P1], step S304; No), the process proceeds to step S306.

[0094] If the peak value Speak1[p] is greater than the first maximum signal intensity Speak1_max[P1] (Speak1[p] > Speak1_max[P1], step S304; Yes), the signal processing circuit 44 replaces the first maximum signal intensity Speak1_max[P1] stored in the memory circuit 46 with the peak value Speak1[p] (Speak1_max[P1] = Speak1[p], step S305), and proceeds to the processing in step S306.

[0095] Next, the signal processing circuit 44 increments the detected value acquisition number p (p = p + 1, step S306) and determines whether the detected value acquisition number p has reached the number of rows N in which the optical sensor circuits PAA (optical sensor PD) are aligned in the first direction Dx within the first region 10A (step S307). If p[N] (step S307; No), the process returns to step S303.

[0096] By repeating the process from step S303 to step S307 N times, the maximum value of the pulse wave component of the signal acquired in the first region 10A is stored in the memory circuit 46 as the first maximum signal intensity Speak1_max[P1].

[0097] When p = N (step S307; Yes), the process returns to the detection flow shown in Figure 9, and subsequently, the signal processing circuit 44 executes the second pulse wave component maximum value extraction process shown in Figure 13 (Figure 13, step S400). Figure 13 is a subflowchart showing an example of the second pulse wave component maximum value extraction process.

[0098] In the second pulse wave component maximum value extraction process shown in Figure 13, the signal processing circuit 44 initializes the second maximum signal intensity, Speak2_max[P2], which is the maximum value of the pulse wave component of the signal acquired in the second region 10B, to "0" (Speak2_max[P2] = 0) (step S401) and stores it in the memory circuit 46.

[0099] Next, the signal processing circuit 44 sets the detected value acquisition number p to 1 (p=1) (step S402), reads the peak value Speak2[p] of the signal acquired in the second region 10B from the memory circuit 46 (step S403), and determines whether the read peak value Speak2[p] is greater than the second maximum signal intensity Speak2_max[P2] (Speak2[p]>Speak2_max[P2], step S404).

[0100] If the peak value Speak2[p] is less than or equal to the second maximum signal intensity Speak2_max[P2] (Speak2[p] ≤ Speak2_max[P2], step S404; No), the process proceeds to step S406.

[0101] If the peak value Speak2[p] is greater than the second maximum signal intensity Speak2_max[P2] (Speak2[p] > Speak2_max[P2], step S404; Yes), the signal processing circuit 44 replaces the second maximum signal intensity Speak2_max[P2] stored in the memory circuit 46 with the peak value Speak2[p] (Speak2_max[P2] = Speak2[p], step S405), and proceeds to the process in step S406.

[0102] Next, the signal processing circuit 44 increments the detected value acquisition number p (p = p + 1, step S406) and determines whether the detected value acquisition number p has reached the number of rows N in which the optical sensor circuits PAA (optical sensor PD) are aligned in the first direction Dx within the second region 10B (step S407). If p[N] (step S407; No), the process returns to step S403.

[0103] By repeating the process from step S403 to step S407 N times, the maximum value of the pulse wave component of the signal acquired in the second region 10B is stored in the memory circuit 46 as the second maximum signal intensity, Speak2_max[P2].

[0104] When p = N (step S407; Yes), the process returns to the detection flow shown in Figure 9, and subsequently, the signal processing circuit 44 executes the pulse wave propagation velocity acquisition process shown in Figure 14 (Figure 13, step S400). Figure 14 is a subflowchart showing an example of the pulse wave propagation velocity acquisition process.

[0105] In the pulse wave velocity acquisition process shown in Figure 14, the signal processing circuit 44 reads the first maximum signal intensity Speak1_max[P1] and the second maximum signal intensity Speak2_max[P2] from the memory circuit 46 (step S501), and determines whether the detected value acquisition number P1 of the first maximum signal intensity Speak1_max[P1] is greater than or equal to the detected value acquisition number P2 of the second maximum signal intensity Speak2_max[P2] (P1 ≥ P2, step S502).

[0106] If the detection value acquisition number P1 for the first maximum signal intensity Speak1_max[P1] is greater than or equal to the detection value acquisition number P2 for the second maximum signal intensity Speak2_max[P2] (P1 ≥ P2, step S502; Yes), the signal processing circuit 44 sets P = P1 (step S503), reads out the detection values ​​Raw1(f)[P] and Raw2(f)[P] for F frames acquired in the Pth position within one frame period from the memory circuit 46 (step S505), and calculates the pulse wave propagation velocity based on the time-series changes of the detection values ​​Raw1(f)[P] and Raw2(f)[P] (step S506).

[0107] If the detection value acquisition number P1 for the first maximum signal intensity Speak1_max[P1] is less than the detection value acquisition number P2 for the second maximum signal intensity Speak2_max[P2] (P1 < P2, step S502; No), the signal processing circuit 44 sets P = P2 (step S504), reads out the detection values ​​Raw1(f)[P] and Raw2(f)[P] for F frames acquired in the Pth position within one frame period from the memory circuit 46 (step S505), and calculates the pulse wave propagation velocity based on the time-series changes of the detection values ​​Raw1(f)[P] and Raw2(f)[P] (step S506).

[0108] Then, the process returns to the detection process flow shown in Figure 9 and terminates the detection process flow.

[0109] With the configuration and processing described above, the pulse wave velocity can be obtained using pulse waves acquired simultaneously at two different points.

[0110] (Modified Example) Figure 15 is a conceptual diagram showing the scanning directions in the first and second regions of the detection device 1 according to a modified example of Embodiment 1.

[0111] In Embodiment 1, an embodiment was described in which the scanning direction in the first region 10A and the scanning direction in the second region 10B are opposite. However, the scanning directions in the first region 10A and the second region 10B are not limited to this. For example, as shown in Figure 15, the scanning direction in the first region 10A and the scanning direction in the second region 10B may be the same.

[0112] More specifically, in the example shown in Figure 15, the gate line drive circuit 15 sequentially scans from gate line GCL(1) to gate line GCL(N) in the first region 10A, and then sequentially scans from gate line GCL(N+1) to gate line GCL(2N) in the second region 10B, within one frame period.

[0113] This makes it possible to keep the distance between lines at which detection values ​​are simultaneously acquired in the first region 10A and the second region 10B constant, regardless of the position where the pulse wave component is at its maximum.

[0114] In addition, in the modified example, as in Embodiment 1, the gate line GCL connected to the simultaneously selected optical sensor PD may be common to both the first region 10A and the second region 10B.

[0115] Figure 16 is a subflowchart showing an example of the pulse wave propagation velocity acquisition process according to a modified example.

[0116] In the pulse wave velocity acquisition process shown in Figure 16, the signal processing circuit 44 reads the first maximum signal intensity Speak1_max[P1] and the second maximum signal intensity Speak2_max[P2] from the memory circuit 46 (step S501), and determines whether the first maximum signal intensity Speak1_max[P1] is greater than or equal to the second maximum signal intensity Speak2_max[P2] (Speak1_max[P1] ≥ Speak2_max[P2], step S502a).

[0117] If the first maximum signal intensity Speak1_max[P1] is greater than or equal to the second maximum signal intensity Speak2_max[P2] (Speak1_max[P1] ≥ Speak2_max[P2], step S502a; Yes), in other words, if the maximum value of the pulse wave component of the signal acquired in the first region 10A is greater than or equal to the maximum value of the pulse wave component of the signal acquired in the second region 10B, then P = P1 (step S503), and the detected values ​​Raw1(f)[P] and Raw2(f)[P] for the F frames acquired as the Pth frame within one frame period are read from the memory circuit 46 (step S505), and the pulse wave propagation velocity is calculated based on the time-series change of the detected values ​​Raw1(f)[P] and Raw2(f)[P] (step S506).

[0118] If the first maximum signal intensity Speak1_max[P1] is less than the second maximum signal intensity Speak2_max[P2] (Speak1_max[P1] < Speak2_max[P2], step S502a; No), in other words, if the maximum value of the pulse wave component of the signal acquired in the first region 10A is less than the maximum value of the pulse wave component of the signal acquired in the second region 10B, then P = P2 (step S504), and the detected values ​​Raw1(f)[P] and Raw2(f)[P] for the F frames acquired as the Pth frame within one frame period are read from the memory circuit 46 (step S505), and the pulse wave propagation velocity is calculated based on the time-series change of the detected values ​​Raw1(f)[P] and Raw2(f)[P] (step S506).

[0119] Then, the process returns to the detection process flow shown in Figure 9 and terminates the detection process flow.

[0120] With the pulse wave propagation velocity acquisition process according to the modified example described above, the pulse wave propagation velocity can be acquired using pulse waves acquired simultaneously at two different points, similar to Embodiment 1.

[0121] (Embodiment 2) Figure 17 is a circuit diagram showing a detection device according to Embodiment 2.

[0122] In Embodiment 1, a configuration was described in which a plurality of optical sensor circuits PAA (optical sensor PDs) were arranged in a matrix in the first region 10A and the second region 10B, respectively. In Embodiment 2, however, as shown in Figure 17, the plurality of optical sensor circuits PAA (optical sensor PDs) are arranged in a checkerboard grid in the first region 10A and the second region 10B, respectively. As a result, the detection signal Vdet of the optical sensor circuit PAA (optical sensor PD) selected in the odd-numbered positions in the scanning direction of the first region 10A is output to the AFE circuit 48 from the signal line SGL of the odd-numbered rows, and the detection signal Vdet of the optical sensor circuit PAA (optical sensor PD) selected in the odd-numbered positions in the scanning direction of the second region 10B is output to the AFE circuit 48 from the signal line SGL of the even-numbered rows. Furthermore, the detection signal Vdet of the optical sensor circuit PAA (optical sensor PD) selected in the even-numbered position in the scanning direction of the first region 10A is output to the AFE circuit 48 from the signal line SGL of the even-numbered column, and the detection signal Vdet of the optical sensor circuit PAA (optical sensor PD) selected in the even-numbered position in the scanning direction of the second region 10B is output to the AFE circuit 48 from the signal line SGL of the odd-numbered column. For this reason, the signal line SGL of the first region 10A and the second region 10B can be made common.

[0123] (Modified Version) Figure 18 is a circuit diagram showing a detection device according to a modified version of Embodiment 2.

[0124] In Embodiment 2, as shown in Figure 18, by reversing the arrangement pattern of the multiple optical sensor circuits PAA (optical sensor PD) in the first region 10A and the second region 10B, the scanning direction in the first region 10A and the scanning direction in the second region 10B can be made the same, similar to Embodiment 1.

[0125] In the modified embodiment of the second embodiment, as shown in Figure 18, the multiple optical sensor circuits PAA (optical sensor PDs) are arranged in a checkerboard pattern in the first region 10A and the second region 10B, respectively. As a result, similar to the second embodiment, the detection signal Vdet of the optical sensor circuits PAA (optical sensor PDs) selected in the odd-numbered positions in the scanning direction of the first region 10A is output to the AFE circuit 48 from the odd-numbered signal lines SGL, and the detection signal Vdet of the optical sensor circuits PAA (optical sensor PDs) selected in the odd-numbered positions in the scanning direction of the second region 10B is output to the AFE circuit 48 from the even-numbered signal lines SGL. Furthermore, the detection signal Vdet of the optical sensor circuit PAA (optical sensor PD) selected in the even-numbered position in the scanning direction of the first region 10A is output to the AFE circuit 48 from the signal line SGL of the even-numbered column, and the detection signal Vdet of the optical sensor circuit PAA (optical sensor PD) selected in the even-numbered position in the scanning direction of the second region 10B is output to the AFE circuit 48 from the signal line SGL of the odd-numbered column. For this reason, the signal line SGL of the first region 10A and the second region 10B can be made common.

[0126] In Embodiment 2 and its modified form, as in Embodiment 1, the gate line GCL connected to the simultaneously selected optical sensor PD may be common to both the first region 10A and the second region 10B.

[0127] Although preferred embodiments of the present invention have been described above, the present invention is not limited to these embodiments. The contents disclosed in the embodiments are merely examples, and various modifications are possible without departing from the spirit of the present invention. Appropriate modifications made without departing from the spirit of the present invention naturally fall within the technical scope of the present invention. At least one of various omissions, substitutions, and modifications of components can be made without departing from the gist of each of the embodiments and modifications described above.

[0128] 1 Detection device 10 Sensor area 10A First area 10B Second area 11 Detection control circuit 15 Gate line drive circuit 16 Signal line selection circuit 17 Reset circuit 21 Sensor substrate 40, 40A, 40B Detection circuit 42 Detection signal amplification circuit 43 A / D conversion circuit 44 Signal processing circuit 46 Memory circuit 47 Detection timing control circuit 48 AFE circuit 61 First light source (light source) 62 Second light source (light source) 122 Control circuit 123 Power supply circuit 126 Output circuit AA Detection area GA Peripheral area GCL Gate line PAA Optical sensor circuit PD Optical sensor SGL Signal line

Claims

1. A detection device comprising: a sensor region in which a plurality of optical sensor circuits, each having an optical sensor, are arranged in a first direction and a second direction intersecting the first direction; a drive circuit that supplies drive signals to the plurality of optical sensor circuits; and a detection circuit that acquires detection values ​​output from the plurality of optical sensor circuits when the drive signals are supplied, and acquires vital data of the object to be detected, wherein the sensor region includes a first region and a second region provided side by side with the first region in the second direction; the drive circuit sequentially scans the optical sensor circuits arranged in the second direction in the first region and the optical sensor circuits arranged in the second direction in the second region, respectively, within one frame period, and simultaneously selects the optical sensor circuits arranged in the first direction in the first region and the optical sensor circuits arranged in the first direction in the second region and supplies the drive signals; and the detection circuit acquires pulse wave propagation velocity based on the detection values ​​of the optical sensor circuits in the first region and the detection values ​​of the optical sensor circuits in the second region acquired simultaneously within one frame period.

2. The detection device according to claim 1, wherein the optical sensor is an OPD.

3. The detection device according to claim 1, wherein the drive circuit has opposite scanning directions in the first region and in the second region.

4. The detection device according to claim 1, wherein the scanning direction in the first region and the scanning direction in the second region are the same direction for the drive circuit.

5. The detection device according to claim 1, wherein the plurality of optical sensor circuits are arranged in a matrix in the first region and the second region, respectively.

6. The detection device according to claim 1, wherein the plurality of optical sensor circuits are arranged in a checkerboard pattern in the first region and the second region, respectively.

7. The detection device according to any one of claims 1 to 6, wherein the detection circuit calculates the pulse wave propagation velocity using the detected value in which the pulse wave component is maximum in the first region.

8. The detection device according to any one of claims 1 to 6, wherein the detection circuit calculates the pulse wave propagation velocity using the detected value in which the pulse wave component is maximum in the second region.

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