Semiconductor apparatus

Abstract

This semiconductor apparatus includes: a chip having a main surface; a semiconductor region of a first conductivity type formed in a surface layer part of the main surface; an active region provided in an inner part of the main surface; an outer peripheral region provided in a peripheral part of the main surface and surrounding the active region; a device structure formed in the active region; and a temperature sensor structure which is formed on the main surface in the outer peripheral region and detects a temperature.

Description

Semiconductor equipment Related applications

[0001] This application corresponds to Japanese Patent Application No. 2024-161239, filed with the Japan Patent Office on 18 September 2024, and the full disclosure of this application is incorporated herein by reference.

[0002] This disclosure relates to semiconductor devices.

[0003] Patent document 1 (US2008 / 0277669A1) discloses a semiconductor device having a termination structure in the outer peripheral region of the drift layer.

[0004] U.S. Patent Application Publication No. 2008 / 0277669

[0005] [Summary] One embodiment of the present disclosure provides a semiconductor device comprising: a chip having a main surface; a semiconductor region of a first conductivity type formed on the surface layer of the main surface; an active region provided on the inner part of the main surface; an outer peripheral region provided on the periphery of the main surface and surrounding the active region; a device structure formed in the active region; and a temperature sensor structure formed on the main surface in the outer peripheral region for detecting temperature.

[0006] Figure 1 is a plan view showing a semiconductor device according to the first embodiment of this disclosure. Figure 2 is a cross-sectional view taken along the line II-II shown in Figure 1. Figure 3 is a plan view showing an example of the layout of the main surface electrode film. Figure 4 is a plan view showing an example of the layout of the first main surface of the chip. Figure 5 is an enlarged view of the portion enclosed by the dashed line V in Figure 4. Figure 6 is an enlarged plan view showing a key part of the first main surface shown in Figure 4. Figure 7 is an enlarged view of the portion enclosed by the dashed line VII in Figure 5. Figure 8 is a cross-sectional view taken along the line VIII-VIII shown in Figure 6. Figure 9 is a cross-sectional view taken along the line IX-IX shown in Figure 6. Figure 10 is a cross-sectional view taken along the line XX shown in Figure 7. Figure 11 is a cross-sectional view showing the cross-sectional structure of the outer peripheral region along the line XI-XI shown in Figure 1. Figure 12 is a graph showing an example of the concentration gradient of p-type impurities in the region along the line XII-XII shown in Figure 10. Figure 13A is a plan view of a temperature sensor element included in a temperature sensor structure. Figure 13B is a cross-sectional view of the temperature sensor structure taken along the line XIIIB-XIIIB shown in Figure 13A. Figure 13C is a cross-sectional view taken along the line XIIIC-XIIIC shown in Figure 3. Figure 14 is a plan view of the main part of a semiconductor device according to a second embodiment. Figure 15 is a cross-sectional view of the main part of a semiconductor device according to a second embodiment. Figure 16 is a plan view of the main part of a semiconductor device according to a third embodiment. Figure 17 is a plan view of the main part of a semiconductor device according to a second embodiment of this disclosure. Figure 18 is a cross-sectional view of the main part of a semiconductor device according to a second embodiment. Figure 19 is a plan view of the main part of a semiconductor device according to a fifth embodiment. Figure 20 is a plan view showing a semiconductor device according to a third embodiment of this disclosure. Figure 21 is a plan view showing the layout of the main surface electrode film. Figure 22 is a plan view showing an example of the layout of the first main surface of a chip. Figure 23 is an enlarged view of the portion enclosed by the dashed line XXIII in Figure 22. Figure 24 is a cross-sectional view taken along the line XXIV-XXIV shown in Figure 23. Figure 25 is a plan view of the main part of the seventh embodiment. Figure 26 is a cross-sectional view along the line XXVI-XXVI shown in Figure 25. Figure 27 is a plan view of the main part of the semiconductor device according to the eighth embodiment. Figure 28 is a plan view of the main part of the semiconductor device according to the ninth embodiment. Figure 29 is a plan view of the main part of the semiconductor device according to the tenth embodiment. Figure 30 is a plan view of the main part of the semiconductor device according to the fourth embodiment of this disclosure.Figure 31 is a cross-sectional view taken along the line XXXI-XXXI shown in Figure 30. Figure 32 is a plan view of the main part of a semiconductor device according to the twelfth embodiment. Figure 33 is a cross-sectional view of the main part of a semiconductor device according to the fifth embodiment of this disclosure.

[0007] [Detailed Description] Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0008] The attached drawings are all schematic diagrams and not strictly accurate; the scale, proportions, angles, etc., do not necessarily match. Corresponding structures in the attached drawings are given the same reference numerals, and redundant explanations are omitted or simplified. For structures whose explanations are omitted or simplified, the explanation given before the omission or simplification applies.

[0009] Where the word "substantially" is used in this specification, it includes not only numerical values ​​(forms) that are approximately equal to the numerical value (form) being compared, but also numerical errors (form errors) within a range of ±10% from the numerical value (form) being compared. In the following descriptions, words such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of explanation and are not intended to limit the names of each structure.

[0010] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "n-type" may be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." Of course, "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." "n-type" is the conductivity type due to pentavalent elements, and "p-type" is the conductivity type due to trivalent elements. Unless otherwise specified, trivalent elements are at least one of boron, aluminum, gallium, and indium. Unless otherwise specified, pentavalent elements are at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0011] Figure 1 is a plan view showing a semiconductor device 1A according to the first embodiment of the present disclosure. Figure 2 is a cross-sectional view taken along the line II-II shown in Figure 1. Figure 3 is a plan view showing the layout of the main surface electrode film 54. Figure 4 is a plan view showing an example of the layout of the first main surface 3 of the chip 2. Figure 5 is an enlarged view of the area enclosed by the dashed line V in Figure 4.

[0012] Semiconductor device 1A is a semiconductor switching device having an insulated gate type transistor structure Tr as an example of a device structure. The transistor structure Tr has a trench gate type vertical structure.

[0013] Referring to Figures 1 to 4, the semiconductor device 1A includes a chip 2 formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). In this embodiment, the chip 2 includes a single crystal of a wide-bandgap semiconductor. In other words, the semiconductor device 1A is a "wide-bandgap semiconductor device". The chip 2 may also be referred to as a "semiconductor chip," "wide-bandgap semiconductor chip," etc.

[0014] Wide-bandgap semiconductors are semiconductors that have a bandgap greater than that of silicon (Si). Examples of wide-bandgap semiconductors include gallium nitride (GaN), silicon carbide (SiC), and diamond (C). In this configuration, chip 2 is a "SiC chip" containing a hexagonal SiC single crystal as an example of a wide-bandgap semiconductor. In other words, semiconductor device 1A is a "SiC semiconductor device".

[0015] Hexagonal SiC single crystals have multiple polytypes, including 2H (Hexagonal)-SiC single crystals, 4H-SiC single crystals, and 6H-SiC single crystals. In this embodiment, an example is shown in which chip 2 contains a 4H-SiC single crystal, but chip 2 may also contain other polytypes.

[0016] The chip 2 has a first main surface (main surface) 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connected to the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a rectangular shape in a plan view from the vertical direction Z (hereinafter simply referred to as "plan view"). The vertical direction Z is also the thickness direction of the chip 2 and the normal direction of the first main surface 3 (second main surface 4). The first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape in a plan view.

[0017] The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, the first main surface 3 is preferably formed by the silicon plane ((0001) plane) of the SiC single crystal, and the second main surface 4 is preferably formed by the carbon plane ((000-1) plane) of the SiC single crystal. The first main surface 3 and the second main surface 4 may have an off-angle that is inclined at a predetermined angle in a predetermined off-direction with respect to the c-plane. The off-direction is preferably the a-axis direction ([11-20] direction) of the SiC single crystal. The off-angle may be greater than 0° and less than or equal to 10°. The off-angle is preferably 5° or less.

[0018] The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects the first direction X along the first main surface 3. Specifically, the second direction Y is perpendicular to the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0019] In this configuration, the first direction X is the a-axis direction ([11-20] direction) of the SiC single crystal, and the second direction Y is the m-axis direction ([1-100] direction) of the SiC single crystal. Alternatively, the first direction X may be the m-axis direction of the SiC single crystal, and the second direction Y may be the a-axis direction of the SiC single crystal.

[0020] The XY plane, which includes the first direction X and the second direction Y, forms a horizontal plane perpendicular to the vertical direction Z. Hereafter, the axis extending along the vertical direction Z may be referred to as the "vertical axis." Also below, the first direction X and the second direction Y may be referred to as the "horizontal direction." The horizontal direction is also the direction extending along the first principal plane 3.

[0021] The first to fourth sides 5A to 5D may have a length of 0.5 mm or more and 20 mm or less in a plan view. The length of the first to fourth sides 5A to 5D may be a value that falls within one of the following ranges: 0.5 mm or more and 1 mm or less, 1 mm or more and 2 mm or less, 2 mm or more and 5 mm or less, 5 mm or more and 10 mm or less, 10 mm or more and 15 mm or less, and 15 mm or more and 20 mm or less. The length of the first to fourth sides 5A to 5D may be 5 mm or more.

[0022] Referring to Figure 2, the semiconductor device 1A includes an n-type first semiconductor region 6 formed on the surface layer of the second main surface 4. A drain potential, which is a first potential (high potential), is applied to the first semiconductor region 6. The first semiconductor region 6 may also be referred to as the "base region (layer)", "semiconductor region (layer)", "drain region (layer)", etc.

[0023] The first semiconductor region 6 extends in layers along the second main surface 4 and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. In this embodiment, the first semiconductor region 6 consists of an n-type semiconductor layer. Specifically, the first semiconductor region 6 consists of a substrate (SiC substrate) containing a SiC single crystal (semiconductor single crystal), and forms the second main surface 4 and the first to fourth side surfaces 5A to 5D. The first semiconductor region 6 (substrate) has the aforementioned off-direction and off-angle. The first semiconductor region 6 may have a thickness T1 of 10 μm or more and 500 μm or less.

[0024] The semiconductor device 1A includes an n-type second semiconductor region 7 formed on the surface layer of the first main surface 3. The second semiconductor region 7 may also be referred to as a "semiconductor region (layer)," "drift region (layer)," etc. The second semiconductor region 7 has an n-type impurity concentration less than that of the first semiconductor region 6. In a cross-sectional view, the second semiconductor region 7 is formed in the region on the first main surface 3 side relative to the first semiconductor region 6 and is electrically connected to the first semiconductor region 6.

[0025] The second semiconductor region 7 extends in a layered manner along the first main surface 3 and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D. In this form, the second semiconductor region 7 is composed of an n-type semiconductor layer. Specifically, the second semiconductor region 7 is composed of an epitaxial layer (SiC epitaxial layer) containing a SiC single crystal (semiconductor single crystal), and forms the first main surface 3 and the first to fourth side surfaces 5A to 5D.

[0026] The second semiconductor region 7 (epitaxial layer) has the above-described off direction and off angle. The second semiconductor region 7 preferably has a thickness T2 that is less than the thickness T1 of the first semiconductor region 6. The thickness T2 of the second semiconductor region 7 may be greater than the thickness T1 of the first semiconductor region 6. The thickness T2 of the second semiconductor region 7 may be 5 μm or more and 15 μm or less.

[0027] Referring to FIG. 4, the semiconductor device 1A includes an active region 8 and an outer peripheral region 9 provided on the first main surface 3 of the chip 2. FIGS. 1, 3, and 4 are diagrams showing the layer structure formed on the active region 8 and the outer peripheral region 9 layer by layer. Among FIGS. 1, 3, and 4, FIG. 4 shows the lowermost layer, FIG. 3 shows a layer above FIG. 4, and FIG. 1 shows a layer above FIG. 2.

[0028] Referring to FIG. 4, the active region 8 includes a device structure (that is, a transistor structure Tr) and is a region where an output current (drain current) is generated. The active region 8 may be referred to as an element region. The active region 8 is set in the inner part of the chip 2 at an interval from the periphery (the first to fourth side surfaces 5A to 5D) of the chip 2 in a plan view. The active region 8 is formed in a polygonal shape having sides parallel to the periphery of the chip 2 in a plan view. In this form, the active region 8 is formed in a polygonal shape having a recess recessed along a gate pad electrode 57 described later in a plan view. The active region 8 may be formed in a rectangular shape in a plan view. The planar area of the active region 8 is preferably 50% or more and 90% or less of the planar area of the first main surface 3.

[0029] The outer peripheral region 9 is a region that does not include the device structure (transistor structure Tr). In a plan view, the outer peripheral region 9 is located in the region between the periphery of the chip 2 and the active region 8. In a plan view, the outer peripheral region 9 extends in a band shape along the active region 8 and is set up as a polygonal ring (a quadrilateral ring in this form) surrounding the active region 8.

[0030] The semiconductor device 1A includes a plurality of trench-type (trench electrode type) trench gate structures 15 formed on the first main surface 3 in the active region 8. A gate potential is applied to the plurality of trench gate structures 15 as a control potential. The trench gate structures 15 may also be referred to as "trench structures," "gate structures," etc.

[0031] In this embodiment, the multiple trench gate structures 15 are arranged at intervals in the second direction Y (m-axis direction) and are formed in a strip shape extending in the first direction X (a-axis direction). In other words, in this embodiment, the multiple trench gate structures 15 are arranged in a stripe shape extending in the a-axis direction (first direction X). The direction of extension of the multiple trench gate structures 15 coincides with the off-direction of the tip 2.

[0032] The semiconductor device 1A includes a p-type outer well region 40 formed in the outer peripheral region 9. The outer well region 40 includes a first outer well region 42 and a plurality of second outer well regions 43. The first outer well region 42 may be referred to as a "termination region," "termination well region," "JTE region (Junction Termination Extension region)," etc. The second outer well regions 43 may be referred to as a "field region," "guard region," "guard ring region," "field limit region," etc.

[0033] Referring to Figure 4, the first outer well region 42 is a rectangular ring-shaped region demarcated by thick solid lines and thick dashed lines. The first outer well region 42 has a portion extending in the first direction X and a portion extending in the second direction Y.

[0034] The first outer well region 42 is formed in the outer peripheral region 9 so as to extend along the outer peripheral boundary 19 (see Figure 10) between the active region 8 and the outer peripheral region 9. In this configuration, the first outer well region 42 is formed as a polygonal ring (a quadrilateral ring in this configuration) having four sides parallel to the periphery of the tip 2 in a plan view, and surrounds a plurality of trench gate structures 15.

[0035] The first outer well region 42 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape). In this embodiment, the first outer well region 42 is formed in the outer peripheral region 9 and surrounds the active region 8.

[0036] Each of the multiple second outer well regions 43 has a portion extending in a first direction X and a portion extending in a second direction Y. In this embodiment, each second outer well region 43 is formed as a polygonal ring (a quadrilateral ring in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the first outer well region 42.

[0037] Each second outer well region 43 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably in a quarter-circular arc shape). In this embodiment, the multiple second outer well regions 43 are formed in the outer peripheral region 9, spaced outward from the first outer well region 42.

[0038] Referring to Figures 4 and 5, the semiconductor device 1A has one or more dummy trench structures 61 formed on the first main surface 3 in the outer peripheral region 9. The dummy trench structure 61 is a trench structure in which no channels are formed around it.

[0039] The dummy formation region 62, in which one or more dummy trench structures 61 are formed, is not included in the active region 8, but is considered part of the outer peripheral region 9. The dummy formation region 62 is formed in the outer peripheral region 9 in the region adjacent to the active region 8 in the second direction Y (Figure 4).

[0040] In this configuration, one or more trench gate structures located on the outermost side in the second direction Y are not used as transistor structures Tr, but instead are designated as dummy trench structures 61. This allows only the trench gate structures 15 excluding the outermost ones in the second direction Y to be used as transistor structures Tr. Therefore, multiple trench gate structures 15 with good shape and dimensions can be used as transistor structures Tr.

[0041] Furthermore, as will be described later, dummy well regions 105 (Figure 10) are formed in the regions below each of the multiple dummy trench structures 61. By forming the dummy well regions 105 in the outer peripheral region 9, electric field concentration can be mitigated in the outer peripheral region 9 near the boundary with the active region 8.

[0042] The number of dummy trench structures 61 included in one dummy formation region 62 is arbitrary. The number of dummy trench structures 61 is the number of dummy trench structures 61 aligned in the second direction Y within one dummy formation region 62. The number of dummy trench structures 61 included in one dummy formation region 62 may be between 1 and 20. The number of dummy trench structures 61 may be 1, 2, 3, 4, 5, 6, 7, 8, 9, or 10. In this embodiment (as shown in Figure 5 and Figure 10 described later), the semiconductor device 1A includes, as an example, four dummy trench structures 61. The presence or absence of dummy trench structures 61 (dummy formation region 62) is arbitrary, and an embodiment without dummy trench structures 61 (dummy formation region 62) may be adopted.

[0043] Referring to Figure 5, in this embodiment, the semiconductor device 1A includes a temperature sensor structure 63 for detecting temperature, formed on the first main surface 3 in the outer peripheral region 9. The temperature sensor structure 63 includes a temperature sensor element 64. In this embodiment, the temperature sensor structure 63 overlaps the outer well region 40 in a plan view. More specifically, the temperature sensor structure 63 overlaps the first outer well region 42 in a plan view. The temperature sensor structure 63 is formed inwardly spaced relative to a plurality of second outer well regions 43 in a plan view.

[0044] In a plan view, the temperature sensor structure 63 is formed with an outer gap from the dummy formation region 62. The temperature sensor structure 63 is formed with an inner gap from the gate wiring 58. The temperature sensor structure 63 is formed with an inner gap from the source wiring 56.

[0045] Referring to Figure 3, the semiconductor device 1A includes an insulating interlayer insulating film 47 formed on the first main surface 3. The interlayer insulating film 47 may also be referred to as an "insulating film," "interlayer insulating film," or "intermediate insulating film." The interlayer insulating film 47 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. It is preferable that the interlayer insulating film 47 includes a silicon oxide film.

[0046] The semiconductor device 1A includes a main surface electrode film 54 disposed on an interlayer insulating film 47. In Figure 3, the interlayer insulating film 47 is shown as a white area, and the main surface electrode film 54 is shown as a hatched area. In this embodiment, the main surface electrode film 54 includes a source pad electrode 51, a source wiring 56, a gate pad electrode 57, and a gate wiring 58.

[0047] The source pad electrode 51 is positioned on the first main surface 3. The source pad electrode 51 is a terminal electrode to which a source potential is applied from the outside. The source pad electrode 51 may also be referred to as the "source electrode film," "first pad electrode," "first main surface electrode," "first terminal electrode," etc. The source pad electrode 51 is positioned on the portion of the interlayer insulating film 47 that covers the active region 8.

[0048] In this embodiment, the source pad electrode 51 has a first pad portion 51a, a second pad portion 51b, and a third pad portion 51c. The third pad portion 51c has a relatively large surface area and forms the main body of the source pad electrode 51. In this embodiment, the third pad portion 51c is formed in a polygonal shape (a quadrilateral shape in this embodiment) with four sides parallel to the periphery of the tip 2 in a plan view, and is offset towards the second side surface 5B with respect to the central part of the first main surface 3.

[0049] The first pad portion 51a has a flat area less than that of the third pad portion 51c and extends in a strip-like (square-shaped) manner from one end of the third pad portion 51c in the first direction X (the end on the third side surface 5C side) toward the first side surface 5A. The second pad portion 51b has a flat area less than that of the third pad portion 51c and extends in a strip-like (square-shaped) manner from the other end of the third pad portion 51c in the first direction X (the end on the fourth side surface 5D side) toward the first side surface 5A. The second pad portion 51b faces the first pad portion 51a in the first direction X.

[0050] The flat area of ​​the second pad portion 51b may be approximately equal to the flat area of ​​the first pad portion 51a. The flat area of ​​the second pad portion 51b may be larger than the flat area of ​​the first pad portion 51a, or smaller than the flat area of ​​the first pad portion 51a. Either the first pad portion 51a or the second pad portion 51b, or both, may be used as terminal portions for current monitoring.

[0051] The source pad electrode 51 does not necessarily have to have both the first pad portion 51a and the second pad portion 51b simultaneously. The source pad electrode 51 may have only one of the first pad portion 51a and the second pad portion 51b. The source pad electrode 51 may consist only of the third pad portion 51c and not have both the first pad portion 51a and the second pad portion 51b.

[0052] The source wiring 56 is arranged around the source pad electrode 51 on the interlayer insulating film 47. The source wiring 56 is supplied with the same potential (source potential) as the potential supplied to the source pad electrode 51. The source wiring 56 may also be referred to as "termination electrode (wiring)", "wiring", "first wiring", "finger electrode", "source finger", etc.

[0053] The source wiring 56 has a wiring width less than the electrode width of the source pad electrode 51 and is selectively routed on the interlayer insulating film 47. In this configuration, the source wiring 56 is led out from the source pad electrode 51 (first pad portion 51a) towards the second side surface 5C. The source wiring 56 is led out from the active region 8 to the outer peripheral region 9.

[0054] The source wiring 56 extends in a strip shape along the periphery of the first main surface 3 (the periphery of the active region 8). In this embodiment, the source wiring 56 is formed in a polygonal ring shape (a quadrilateral ring shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the inner part of the first main surface 3 (active region 8). The source wiring 56 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter-circular arc shape). The source wiring 56 may be ended or endless.

[0055] The gate pad electrode 57 is positioned on the first main surface 3. The gate pad electrode 57 is a terminal electrode to which a gate potential is applied from the outside. The gate pad electrode 57 may also be referred to as the "gate electrode film," "second pad electrode," "second main surface electrode," "second terminal electrode," etc.

[0056] The gate pad electrode 57 is positioned at a distance from the source pad electrode 51 on the portion of the interlayer insulating film 47 that covers the active region 8. In this configuration, the gate pad electrode 57 is positioned in the region on the first side surface 5A side with respect to the third pad portion 51c and faces the third pad portion 51c in the second direction Y. The gate pad electrode 57 is interposed in the region between the second pad portion 51b and the third pad portion 51c and faces both the second pad portion 51b and the third pad portion 51c in the first direction X.

[0057] The gate pad electrode 57 is formed in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the tip 2 in a plan view. The gate pad electrode 57 has a planar area less than that of the source pad electrode 51. The gate pad electrode 57 has a planar area less than that of the third pad portion 51c. The gate pad electrode 57 may also have a planar area less than that of the first pad portion 51a (second pad portion 51b).

[0058] The gate pad electrode 57 is located in a recess formed in the source pad electrode 51. The gate pad electrode 57 may be located in a region along the central part of any of the first to fourth side surfaces 5A to 5D. The gate pad electrode 57 may be located at any corner C of the tip 2 on the first main surface 3 in a plan view. The gate pad electrode 57 may be located in the central part of the first main surface 3 in a plan view. The gate pad electrode 57 may be located on the active region 8. In this embodiment, the gate pad electrode 57 is formed in a square shape in a plan view.

[0059] The gate wiring 58 is drawn out from the gate pad electrode 57 onto the first main surface 3. The gate wiring 58 may also be referred to as "wiring," "second wiring," "finger electrode," "gate finger," etc. The gate wiring 58 transmits the gate potential applied to the gate pad electrode 57 to other regions.

[0060] The gate wiring 58 is led out from the gate pad electrode 57 onto the portion of the interlayer insulating film 47 that covers the active region 8, and is routed in the region between the source pad electrode 51 and the source wiring 56, spaced apart from the source pad electrode 51 and the source wiring 56.

[0061] The gate wiring 58 of the semiconductor device 1A includes a plurality (e.g., two) of finger wirings 58a, 58b that extend in a strip-like manner from the outer edge of the gate pad electrode 57 in different directions from one another. The plurality of finger wirings 58a, 58b are arranged in a non-parallel relationship with respect to one another. The first finger wiring 58a and the second finger wiring 58b extend from the gate pad electrode 57 in opposite directions from one another along the periphery of the chip 2 and together surround the source pad electrode 51.

[0062] In this configuration, the first finger wiring 58a and the second finger wiring 58b are each formed in a substantially U shape in plan view and have a corner C1 at a position corresponding to the corner C of the chip 2.

[0063] The first finger wiring 58a extends from the gate pad electrode 57 in a first direction X along the first side surface 5A, the third side surface 5C, and the second side surface 5B in that order, and has a first tip portion 58c on the second side surface 5B. The first finger wiring 58a may also be referred to as, for example, "first outer peripheral wiring," "first outer peripheral electrode," "first outer peripheral finger wiring," "first outer peripheral finger electrode," etc.

[0064] The second finger wiring 58b extends from the gate pad electrode 57 in the first direction X along the first side surface 5A, the fourth side surface 5D, and the second side surface 5B in that order, and has a second tip portion 58d on the second side surface 5B. The second finger wiring 58b may also be referred to as, for example, "second outer peripheral wiring," "second outer peripheral electrode," "second outer peripheral finger wiring," or "second outer peripheral finger electrode."

[0065] The first tip portion 58c and the second tip portion 58d face each other in the first direction X with a space S1 between them. The first finger wiring 58a and the second finger wiring 58b may be collectively referred to as "outer peripheral wiring," "outer peripheral electrode," "outer peripheral finger wiring," "outer peripheral finger electrode," etc., surrounding the active region 8.

[0066] Referring to Figure 5, the semiconductor device 1A includes a first extraction electrode 65 and a second extraction electrode 66. A first connection wire 67 from a temperature sensor element 64 included in the temperature sensor structure 63 is connected to the first extraction electrode 65. A second connection wire 68 from the temperature sensor element 64 is connected to the second extraction electrode 66.

[0067] Referring to Figure 1, the semiconductor device 1A includes a surface insulating film 70 that selectively covers the main surface electrode film 54 (Figure 3) and the interlayer insulating film 47 (Figure 3) on the first main surface 3. The surface insulating film 70 includes a gate pad opening 72 that exposes a portion of the gate pad electrode 57 as a gate pad 71. The surface insulating film 70 covers the peripheral edge of the gate pad electrode 57 and the entire area of ​​the gate wiring 58. The gate pad opening 72 is formed in a rectangular shape in plan view.

[0068] The surface insulating film 70 includes a first source pad opening 74 that exposes a portion of the first pad portion 51a of the source pad electrode 51 as a first source pad 73, a second source pad opening 76 that exposes a portion of the second pad portion 51b as a second source pad 75, and a third source pad opening 78 that exposes a portion of the third pad portion 51c as a third source pad 77. The surface insulating film 70 covers the peripheral edges of the first pad portion 51a, the second pad portion 51b, and the third pad portion 51c.

[0069] The first source pad opening 74 is formed in a rectangular shape along the periphery of the first pad portion 51a in a plan view. Preferably, the planar area of ​​the first source pad opening 74 is smaller than the planar area of ​​the gate pad opening 72.

[0070] The second source pad opening 76 is formed in a rectangular shape along the periphery of the second pad portion 51b in a plan view. Preferably, the planar area of ​​the second source pad opening 76 is smaller than the planar area of ​​the gate pad opening 72.

[0071] The third source pad opening 78 is formed in a polygonal shape that follows the periphery of the third pad portion 51c in a plan view. Preferably, the planar area of ​​the third source pad opening 78 is larger than the planar area of ​​the gate pad opening 72.

[0072] The surface insulating film 70 includes a first extraction opening 80 (Figure 13C) that exposes a portion of the first extraction electrode 65 as a first extraction pad 79 (Figure 13C). The surface insulating film 70 covers the peripheral edge of the first extraction electrode 65.

[0073] The first extraction opening 80 is formed in a rectangular shape along the periphery of the first extraction electrode 65 in a plan view. Preferably, the planar area of ​​the first extraction opening 80 is smaller than the planar area of ​​the gate pad opening 72. Preferably, the planar area of ​​the first extraction opening 80 is smaller than the planar area of ​​the first source pad opening 74 (second source pad opening 76).

[0074] The surface insulating film 70 includes a second extraction opening 82 (Figure 13C) that exposes a portion of the second extraction electrode 66 as a second extraction pad 81 (Figure 13C). The surface insulating film 70 covers the peripheral edge of the second extraction electrode 66.

[0075] The second extraction opening 82 is formed in a rectangular shape along the periphery of the second extraction electrode 66 in a plan view. Preferably, the planar area of ​​the second extraction opening 82 is smaller than the planar area of ​​the gate pad opening 72. Preferably, the planar area of ​​the second extraction opening 82 is smaller than the planar area of ​​the first source pad opening 74 (second source pad opening 76).

[0076] The surface insulating film 70 may have a laminated structure including an inorganic insulating film and an organic insulating film stacked in this order from the chip 2 side. The surface insulating film 70 only needs to include at least one of the inorganic insulating film and the organic insulating film, and does not necessarily need to include both at the same time. The inorganic insulating film may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. It is preferable that the inorganic insulating film includes an insulating material different from the interlayer insulating film 47. The organic insulating film is preferably a polyimide film, a polyamide film, or a polybenzoxazole film. In this embodiment, the organic insulating film includes a polybenzoxazole film.

[0077] Referring to Figure 2, the semiconductor device 1A includes a drain electrode 59 that covers the second main surface 4. The drain electrode 59 is a terminal electrode to which a drain potential is applied from the outside. The drain electrode 59 may also be referred to as the "third pad electrode," "third main surface electrode," "third terminal electrode," etc.

[0078] The drain electrode 59 is electrically connected to the first semiconductor region 6. The drain electrode 59 may cover the entire area of ​​the second main surface 4 so as to be continuous with the periphery of the second main surface 4 (first to fourth side surfaces 5A to 5D). The drain electrode 59 may partially cover the second main surface 4 so as to expose the periphery of the second main surface 4.

[0079] The breakdown voltage that can be applied between the source pad electrode 51 and the drain electrode 59 (between the first main surface 3 and the second main surface 4) may be 500V or more and 3000V or less. The breakdown voltage may have a value that falls within at least one of the following ranges: 500V or more and 750V or less, 750V or more and 1000V or less, 1000V or more and 1250V or less, 1250V or more and 1500V or less, 1500V or more and 1750V or less, 1750V or more and 2000V or less, 2000V or more and 2250V or less, 2250V or more and 2500V or less, 2500V or more and 2750V or more and 3000V or less.

[0080] Figure 6 is an enlarged plan view showing a key part of the first main surface 3 shown in Figure 4. Figure 7 is an enlarged view of the area enclosed by the dashed line VII in Figure 5. Figure 8 is a cross-sectional view along the line VIII-VIII shown in Figure 6. Figure 9 is a cross-sectional view along the line IX-IX shown in Figure 6. Figure 10 is a cross-sectional view along the line XX shown in Figure 7. Figure 11 is a cross-sectional view showing the cross-sectional structure of the outer peripheral region 9 along the line XI-XI shown in Figure 1.

[0081] Referring to Figures 5 to 11, the transistor structure Tr formed in the active region 8 of the semiconductor device 1A and the configuration within the outer peripheral region 9 will be explained.

[0082] The semiconductor device 1A includes a p-type body region 10 formed on the surface layer of the first main surface 3 in the active region 8 (inner part of the first main surface 3). The body region 10 may also be called an "impurity region," "channel region," etc. A source potential may be applied to the body region 10. The source potential may be a reference potential that serves as a reference for circuit operation. The reference potential may be a ground potential. The body region 10 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7. The body region 10 has, for example, 1 × 10⁻¹⁶ １７ cm －３ The above 1 x 10 １８ cm －３ The following p-type impurity concentrations may be present as peak values.

[0083] Referring to Figures 6 and 7, the body region 10 is formed in the inner part of the first main surface 3, spaced apart from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. The body region 10 is formed on the surface layer of the second semiconductor region 7 and extends in layers along the first main surface 3. In this configuration, the body region 10 is formed over the entire area of ​​the active region 8. In this configuration, the body region 10 is not formed in the outer peripheral region 9.

[0084] Referring to Figures 8 and 9, the body region 10 is formed with a gap from the bottom of the second semiconductor region 7 (first semiconductor region 6) toward the first main surface 3, and faces the first semiconductor region 6 with a portion of the second semiconductor region 7 in between. The body region 10 is formed with a gap from the depth position of the middle part of the second semiconductor region 7 toward the first main surface 3.

[0085] The body region 10 is formed in the region on the first main surface 3 side relative to the second semiconductor region 7 in a cross-sectional view, and is electrically connected to the second semiconductor region 7. The body region 10 forms a pn junction (body diode) with the second semiconductor region 7. When a reverse bias voltage is applied, the body region 10 expands a depletion layer in the second semiconductor region 7. The depletion layer, starting from the body region 10, expands horizontally and in the thickness direction within the second semiconductor region 7.

[0086] Referring to Figures 6 to 8, the semiconductor device 1A includes an n-type source region 11 formed on the surface of the first main surface 3 in the active region 8. A source potential is applied to the source region 11. The source region 11 has a higher n-type impurity concentration than the n-type impurity concentration of the second semiconductor region 7. The n-type impurity concentration of the source region 11 is higher than the p-type impurity concentration of the body region 10.

[0087] The source region 11 is formed in the inner part of the first main surface 3, spaced apart from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. The source region 11 is formed on the surface layer of the body region 10 and extends in layers along the first main surface 3. In this configuration, the source region 11 is not formed in the outer peripheral region 9. The source region 11 may also be formed inward from the periphery of the body region 10, spaced apart.

[0088] The source region 11 is formed at a distance from the bottom of the body region 10 toward the first main surface 3, and faces the second semiconductor region 7 across a portion of the body region 10. In a cross-sectional view, the source region 11 is formed in the region toward the first main surface 3 relative to the body region 10 and is electrically connected to the body region 10.

[0089] Referring to Figures 6 to 9, the semiconductor device 1A includes a plurality of trench-type (trench electrode type) trench gate structures 15 formed in the inner part of the first main surface 3. The trench gate structure 15 is an example of a trench structure. The trench gate structure 15 may also be referred to as a "gate structure," etc. A gate potential (gate signal) as a control potential is applied to the plurality of trench gate structures 15. The plurality of trench gate structures 15 control the inversion and non-inversion of the channel within the body region 10 in response to the gate potential.

[0090] Multiple trench gate structures 15 are formed in the inner part of the first main surface 3, spaced apart from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. In this configuration, the multiple trench gate structures 15 are not formed in the outer peripheral region 9. In a plan view, the multiple trench gate structures 15 are arranged at intervals in the second direction Y (= m-axis direction) and each extends in a strip-like manner in the first direction X (= a-axis direction). In other words, in a plan view, the multiple trench gate structures 15 are arranged in a stripe-like manner extending in the first direction X.

[0091] The extension direction of the multiple trench gate structures 15 coincides with the off-direction of the SiC single crystal. With respect to the second direction Y, both ends of the multiple trench gate structures 15 may be located in the region between the periphery of the body region 10 and the periphery of the source region 11. The multiple trench gate structures 15 may be arranged at intervals in the second direction Y in a plan view and each may extend in a strip shape in the first direction X.

[0092] Multiple trench gate structures 15 penetrate the body region 10 and the source region 11 so as to reach the second semiconductor region 7. The multiple trench gate structures 15 are formed at intervals from the depth position at the bottom of the second semiconductor region 7 toward the first main surface 3, and face the first semiconductor region 6 with a portion of the second semiconductor region 7 in between.

[0093] The multiple trench gate structures 15 may be formed at intervals from the depth position of the middle part of the second semiconductor region 7 toward the first main surface 3, or they may be located toward the bottom of the second semiconductor region 7 relative to the depth position of the middle part of the second semiconductor region 7. The multiple trench gate structures 15 are formed substantially perpendicular to the first main surface 3. The multiple trench gate structures 15 may be formed in a tapered shape toward the bottom of the second semiconductor region 7.

[0094] The side walls (long sides) of the multiple trench gate structures 15 are formed by the m-plane ((1-100) plane) of the SiC single crystal. The side walls (long sides) of the multiple trench gate structures 15 may also be formed by the a-plane ((11-20) plane) of the SiC single crystal, depending on the direction of extension of the trench gate structure 15. The bottom walls of the multiple trench gate structures 15 are formed by the c-plane (Si plane) of the SiC single crystal. It is preferable that the bottom walls of the multiple trench gate structures 15 extend substantially flat along the horizontal direction. The bottom walls of the multiple trench gate structures 15 may be curved in an arc towards the second main surface 4.

[0095] Each of the multiple trench gate structures 15 includes a gate trench 16, a gate insulating film 17, and a gate electrode 18. The gate trench 16 is formed on the first main surface 3 and defines the wall surfaces (side walls and bottom walls) of the trench gate structure 15.

[0096] The gate insulating film 17 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the gate insulating film 17 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the gate insulating film 17 includes a silicon oxide film made of the oxide of the chip 2.

[0097] The gate insulating film 17 covers the walls of the gate trench 16. The gate insulating film 17 includes a first film portion and a second film portion. The first film portion covers the side walls of the gate trench 16 in a film-like manner. The second film portion covers the bottom wall of the gate trench 16 in a film-like manner and is connected to the first film portion. The second film portion has a thickness greater than that of the first film portion. The thickness of the second film portion may be approximately equal to that of the first film portion. The gate insulating film 17 may have a thickness of 10 nm or more and 150 nm or less.

[0098] The gate electrode 18 is embedded in the gate trench 16 with the gate insulating film 17 in between. The gate electrode 18 may contain either or both p-type conductive polysilicon and n-type conductive polysilicon. The gate electrode 18 faces the second semiconductor region 7, the body region 10, and the source region 11 with the gate insulating film 17 in between. The gate electrode 18 may also be referred to as the "embedded electrode".

[0099] The gate electrode 18 has an electrode surface exposed from the gate trench 16. The electrode surface is located on the bottom wall side of the gate trench 16 with respect to the height position of the first main surface 3. The electrode surface is located on the first main surface 3 side with respect to the depth position of the bottom of the source region 11. The electrode surface has a recess that tapers inward toward the bottom wall of the gate trench 16.

[0100] Referring to Figures 8 and 9, the semiconductor device 1A includes gate well regions 25 formed in the regions below each of the multiple trench gate structures 15 within the active region 8 chip 2 (second semiconductor region 7). The gate well regions 25 may also be referred to as the "first well region," "field relaxation region," "field relaxation layer," etc.

[0101] A source potential is applied to the gatewell region 25. The gatewell region 25 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7. The p-type impurity concentration of the gatewell region 25 may be higher than or lower than the p-type impurity concentration of the body region 10. The p-type impurity (trivalent element) in the gatewell region 25 is preferably aluminum.

[0102] Multiple gate well regions 25 are formed within the second semiconductor region 7, spaced apart from each other in the first direction X, in regions below (specifically, directly below) the multiple trench gate structures 15. The multiple gate well regions 25 are formed in the thickness range between the bottom of the second semiconductor region 7 and the bottom walls of the multiple trench gate structures 15, and overlap with the multiple trench gate structures 15 in a one-to-one correspondence in the thickness direction.

[0103] The multiple gatewell regions 25 each extend in a strip-like manner in the first direction X, following the extension direction of the corresponding trench gate structure 15 in a plan view. In other words, the multiple gatewell regions 25 are arranged in a stripe-like pattern extending in the first direction X in a plan view.

[0104] The extension direction of the multiple gatewell regions 25 coincides with the off-direction of the SiC single crystal. The multiple gatewell regions 25 may also extend in a second direction Y, depending on the extension direction of the multiple trench gate structures 15. In this case, the multiple gatewell regions 25 intersect (specifically, orthogonal) in the off-direction.

[0105] Multiple gate well regions 25 are formed at intervals from the bottom of the second semiconductor region 7 towards the bottom wall side of the multiple trench gate structures 15, and face the first semiconductor region 6 across a portion of the second semiconductor region 7. Each of the multiple gate well regions 25 has an upper end located on the bottom wall side of the corresponding trench gate structure 15, and a bottom located on the bottom side (second main surface 4 side) of the second semiconductor region 7.

[0106] The upper ends of the multiple gate well regions 25 are formed with a gap between them, extending from the bottom of the body region 10 towards the bottom wall of the corresponding trench gate structure 15. The upper ends of the multiple gate well regions 25 may be connected to the bottom wall of the corresponding trench gate structure 15. The upper ends of the multiple gate well regions 25 may have portions that run along the side walls of the corresponding trench gate structure 15. The upper ends of the multiple gate well regions 25 may be formed with a gap between them, extending from the bottom wall of the corresponding trench gate structure 15 towards the bottom of the second semiconductor region 7.

[0107] Each gatewell region 25 has a bulge 25a and a well bottom 25b. The bulge 25a extends horizontally in an arc shape from the region directly below the corresponding trench gate structure 15 to both sides of the corresponding trench gate structure 15. Multiple gatewell regions 25 are each formed in a tapering shape from the bulge 25a towards the bottom.

[0108] The well bottom 25b extends from the bulge 25a in a direction along the first main surface 3. The well bottom 25b may be located on the bottom wall side of the plurality of trench gate structures 15 with respect to the middle portion of the second semiconductor region 7, or it may be located on the bottom side (second main surface 4 side) of the second semiconductor region 7 with respect to the middle portion of the second semiconductor region 7.

[0109] The gatewell region 25 may have a width greater than the width of the trench gate structure 15, or a width less than the width of the trench gate structure 15. The width of the gatewell region 25 may be 0.1 μm or more and 2 μm or less.

[0110] The gatewell region 25 may have a depth less than the depth of the trench gate structure 15, or a depth greater than the depth of the trench gate structure 15. The depth of the gatewell region 25 is the depth of the gatewell region 25 when the bottom wall of the trench gate structure 15 is used as the reference point. The depth of the gatewell region 25 may be greater than 0 μm and 5 μm or less.

[0111] The gate well region 25 forms a pn junction with the second semiconductor region 7. When a reverse bias voltage is applied, the gate well region 25 expands a depletion layer in the second semiconductor region 7. The depletion layer, originating from the gate well region 25, expands in the horizontal and thickness directions, mitigating the electric field for the active region 8 (trench gate structure 15).

[0112] Referring to Figure 7, the semiconductor device 1A includes a plurality of p-type high-density regions 23, each positioned at the bottom of a plurality of trench gate structures 15. The plurality of high-density regions 23 are formed in a one-to-many correspondence with the corresponding trench gate structures 15. The plurality of high-density regions 23 are formed with spacing in the second direction Y.

[0113] Multiple high-concentration regions 23 face multiple gate contact regions 27 in the first direction X. One high-concentration region 23 is sandwiched in the first direction X by two gate contact regions 27. Two high-concentration regions 23 sandwich one gate contact region 27 in the first direction X. One high-concentration region 23 is in contact with each of the two gate contact regions 27 adjacent to it in the first direction X.

[0114] The following describes one high-concentration region 23. The high-concentration region 23 is sandwiched between the bottom of the gate trench 16 of the trench gate structure 15 and the gate well region 25. The high-concentration region 23 is in contact with the bottom surface of the gate trench 16.

[0115] The high-concentration region 23 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7 (for example, the base region 91 described later). The high-concentration region 23 may also have a p-type impurity concentration higher than the n-type impurity concentration of the high-concentration region 92 described later. The p-type impurity concentration of the high-concentration region 23 is higher than the p-type impurity concentration of the body region 10. The p-type impurity concentration of the high-concentration region 23 is higher than the p-type impurity concentration of the gate well region 25. The p-type impurity concentration of the high-concentration region 23 may be equivalent to the p-type impurity concentration of the gate contact region 27 described below.

[0116] The p-type impurity concentration in the high-concentration region 23 is 1 × 10⁻⁶ １８ cm －３ The above 1 x 10 ２１ cm －３ The following p-type impurity concentrations may be present as peak values. Preferably, the p-type impurity concentration in the high-concentration region 23 is adjusted by at least one trivalent element.

[0117] Referring to Figures 6, 7, and 9, the semiconductor device 1A includes a plurality of gate contact regions 27 formed within the chip 2 (second semiconductor region 7) in the active region 8. The gate contact regions 27 may also be referred to as "contact regions," etc. A source potential is applied to the gate contact regions 27.

[0118] The gate contact region 27 has a higher p-type impurity concentration than the n-type impurity concentration of the second semiconductor region 7. The p-type impurity concentration in the gate contact region 27 is higher than the p-type impurity concentration in the body region 10. The p-type impurity concentration in the gate contact region 27 is higher than the p-type impurity concentration in the gate well region 25.

[0119] Multiple gate contact regions 27 are formed in regions along multiple trench gate structures 15 at intervals from each other. The multiple gate contact regions 27 are formed in a one-to-many correspondence with the multiple trench gate structures 15. The multiple gate contact regions 27 are formed at intervals in the second direction Y, following the extending direction of the corresponding trench gate structure 15.

[0120] With respect to one trench gate structure 15 and the other, the multiple gate contact regions 27 along one trench gate structure 15 are opposite the multiple gate contact regions 27 along the other trench gate structure 15 in the first direction X when viewed from above. In other words, the multiple gate contact regions 27 are arranged in a matrix with spacing in the first direction X and the second direction Y when viewed from above.

[0121] In this embodiment, the multiple gate contact regions 27 extend in a strip-like manner along the multiple trench gate structures 15 in a plan view. The lengths of the multiple gate contact regions 27 in the second direction Y may be equal to or different from each other. The lengths of the multiple gate contact regions 27 in the second direction Y are adjusted according to the channel area to be formed.

[0122] The channel area is the total area of ​​the portion of the source region 11 exposed by the multiple gate contact regions 27. In other words, the channel area increases or decreases in proportion to the increase or decrease in the ratio of the total planar area of ​​the multiple gate contact regions 27. It is preferable that the total planar area of ​​the multiple gate contact regions 27 is less than the channel area.

[0123] In other words, in the region between a pair of adjacent trench gate structures 15, it is preferable that the total planar area of ​​the multiple gate contact regions 27 is less than the planar area of ​​the source region 11. With such a configuration, the increase in resistance (on-resistance) caused by short channels is suppressed.

[0124] Multiple gate contact regions 27 are interposed in the regions between the bottom walls of multiple trench gate structures 15 and the bottoms of multiple gate well regions 25. Each of the gate contact regions 27 is connected to the corresponding bottom wall of the trench gate structure 15 and the corresponding gate well region 25.

[0125] Multiple gate contact regions 27 increase the concentration of p-type impurities at the upper end of the corresponding gate well region 25. The gate contact regions 27 extend from the region directly below the trench gate structure 15 to both sides of the trench gate structure 15 and have extensions that extend along the side walls of the trench gate structure 15.

[0126] The horizontal (second direction Y) thickness of the portion of the gate contact region 27 that runs along the side wall of the trench gate structure 15 (extension) may be less than the vertical Z thickness of the portion of the gate contact region 27 that runs along the bottom wall of the trench gate structure 15.

[0127] The extension of the gate contact region 27 is electrically connected to the body region 10 at the surface layer of the first main surface 3, and the corresponding gate well region 25 is electrically connected to the body region 10. This suppresses the gate well region 25 from becoming electrically detached, and improves the electrical response characteristics of the gate well region 25.

[0128] The gate contact region 27 has an upper end exposed from the first main surface 3. In this embodiment, the upper end of the gate contact region 27 is exposed from the side wall of the gate trench 16 at the opening end of the gate trench 16. The upper end of the gate contact region 27 may extend horizontally in the surface layer of the body region 10.

[0129] Referring to FIGS. 8 and 9, the second semiconductor region 7 of the semiconductor device 1A includes a stacked structure of a base region 91 and a high-concentration region 92.

[0130] The base region 91 is formed farther from the body region 10 on the second main surface 4 side than the gate well region 25. The base region 91 is formed in a layer-like shape extending along the first main surface 3 at a position away from the body region 10 and the gate trench 16 on the second main surface 4 side. The base region 91 is formed over the entire surface layer portion on the second main surface 4 side of the second semiconductor region 7 and may be exposed from the first to fourth side surfaces 5A to 5D. The base region 91 forms a boundary surface with the first semiconductor region 6 in the second semiconductor region 7. The thickness of the base region 91 may be, for example, 0.5 μm or more and 20 μm or less. Preferably, the thickness of the base region 91 is 1 μm or more and 10 μm or less.

[0131] The n-type impurity concentration of the base region 91 is preferably less than the n-type impurity concentration of the first semiconductor region 6. The base region 91 may have a peak value of an n-type impurity concentration of 1×10 １６ cm －３ or more and 1×10 １７ cm －３ or less. The n-type impurity concentration of the base region 91 may be substantially constant in the thickness direction. Of course, the n-type impurity concentration of the base region 91 may have a concentration gradient that gradually increases and / or decreases in the thickness direction (crystal growth direction) of the chip 2.

[0132] The high-concentration region 92 is formed on the sides of the gate trench 16 and the gate well region 25 between the base region 91 and the body region 10. The high-concentration region 92 is in contact with the body region 10 and the gate well region 25 and is formed in a layer-like shape extending along the first main surface 3. The high-concentration region 92 is formed over the entire surface layer portion on the first main surface 3 side of the second semiconductor region 7 and may be exposed from the first to fourth side surfaces 5A to 5D. In this form, the high-concentration region 92 forms a boundary surface with the body region 10 in the second semiconductor region 7. The thickness of the high-concentration region 92 may be 0.1 μm or more and 0.5 μm or less. Preferably, the thickness of the high-concentration region 92 is 0.15 μm or more and 0.4 μm or less.

[0133] The concentration of n-type impurities in the high-concentration region 92 is preferably higher than the concentration of n-type impurities in the base region 91. The high-concentration region 92 is 1 × 10⁻⁶ １７ cm －３ The above 1 x 10 １８ cm －３ The following n-type impurity concentrations may be present as peak values. The n-type impurity concentration in the high-concentration region 92 may be approximately constant in the thickness direction. Of course, the n-type impurity concentration in the high-concentration region 92 may have a concentration gradient that gradually increases and / or decreases in the thickness direction (crystal growth direction) of the chip 2.

[0134] The concentration of n-type impurities in the high-concentration region 92 is preferably higher than the concentration of n-type impurities in the base region 91. The high-concentration region 92 is 1 × 10⁻⁶ １７ cm －３ The above 1 x 10 １８ cm －３ The following n-type impurity concentrations may be present as peak values. The n-type impurity concentration in the high-concentration region 92 may be approximately constant in the thickness direction. Of course, the n-type impurity concentration in the high-concentration region 92 may have a concentration gradient that gradually increases and / or decreases in the thickness direction (crystal growth direction) of the chip 2.

[0135] Referring to Figure 10, the semiconductor device 1A includes a p-type outer body region 60 formed on the surface layer of the first main surface 3 in the outer peripheral region 9. The outer body region 60 is not formed in the active region 8. Preferably, the outer body region 60 has a p-type impurity concentration that is approximately equal to the p-type impurity concentration of the body region 10. Of course, the p-type impurity concentration of the outer body region 60 may be less than the p-type impurity concentration of the body region 10, or it may be higher than the p-type impurity concentration of the body region 10.

[0136] The outer body region 60 is formed at a distance from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3 toward the active region 8, and extends in a band shape along the active region 8. In a plan view, the outer body region 60 has a portion that extends in a band shape in the first direction X and a portion that extends in a band shape in the second direction Y, and divides the active region 8 from multiple directions. The outer body region 60 forms the outer peripheral boundary portion 19 (Figure 10) of the active region 8 and the outer peripheral region 9. In this embodiment, the outer body region 60 may surround the active region 8 in a plan view and be divided into a polygonal ring (a quadrilateral ring in this embodiment) having four sides parallel to the periphery of the first main surface 3.

[0137] Referring to Figure 10, the outer body region 60 has an inner edge on the active region 8 side and an outer edge on the peripheral side of the first main surface 3. The inner edge of the outer body region 60 is connected to the body region 10 in the portion extending in the second direction Y. As a result, the outer body region 60 is fixed at the same potential as the multiple body regions 10. A clear boundary does not need to be formed between the body regions 10 and the outer body region 60. In Figure 10, for clarity, the boundary between the outermost body region 10 and the outer body region 60 in the second direction Y is shown by a solid line.

[0138] The outer body region 60 is formed with a gap from the bottom of the first semiconductor region 6 toward the first main surface 3, and faces the second semiconductor region 7 with a portion of the first semiconductor region 6 in between. Preferably, the outer body region 60 is formed with a gap from the middle of the first semiconductor region 6 toward the first main surface 3. The outer body region 60 is exposed from the first main surface 3.

[0139] Preferably, the outer body region 60 has a thickness (depth) approximately equal to the thickness (depth) of the body region 10. Of course, the thickness of the outer body region 60 may be less than the thickness of the body region 10, or it may be greater than the thickness of the body region 10.

[0140] As described above, the semiconductor device 1A has one or more dummy trench structures 61 formed on the first main surface 3 in the outer peripheral region 9. The dummy trench structures 61 are not in contact with the source region 11. Therefore, no channels are formed around the dummy trench structures 61. In other words, the dummy trench structures 61 are trench structures in which no channels are formed.

[0141] The dummy formation region 62 is the region where the dummy trench structure 61 is formed. The dummy formation region 62 is located in the peripheral region 9, near the peripheral boundary 19 with the active region 8.

[0142] In this configuration, the dummy formation region 62 is provided spanning the outer body region 60 and the first outer well region 42. The dummy formation region 62 overlaps with the outer body region 60. The dummy formation region 62 overlaps with the first outer well region 42.

[0143] In other words, in this configuration, at least one dummy trench structure 61 is formed in the outer body region 60. This dummy trench structure 61 penetrates the outer body region 60 and reaches the high-concentration region 92.

[0144] Furthermore, at least one dummy trench structure 61 is formed in the first outer well region 42. The bottom of this dummy trench structure 61 is also located in the first outer well region 42.

[0145] One dummy trench structure 61 includes a dummy trench 101, a dummy insulating film 102, and a dummy electrode 103. The dummy trench 101 is formed on the first main surface 3 and defines the walls (side walls and bottom walls) of the dummy trench structure 61.

[0146] The dummy insulating film 102 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the dummy insulating film 102 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the dummy insulating film 102 includes a silicon oxide film made of the oxide of the chip 2.

[0147] The dummy insulating film 102 covers the walls of the dummy trench 101. The dummy insulating film 102 includes a third film portion and a fourth film portion. The third film portion covers the side walls of the dummy trench 101 in a film-like manner. The fourth film portion covers the bottom wall of the dummy trench 101 in a film-like manner and is connected to the third film portion. The fourth film portion has a greater thickness than the third film portion. The thickness of the fourth film portion may be approximately equal to the thickness of the third film portion. The thickness of the dummy insulating film 102 may be the same as the thickness of the gate insulating film 17. The dummy insulating film 102 may have a thickness of 10 nm or more and 150 nm or less.

[0148] The dummy electrode 103 is embedded in the dummy trench 101 with a dummy insulating film 102 in between. The dummy electrode 103 may contain either or both p-type conductive polysilicon and n-type conductive polysilicon. The dummy electrode 103 faces the second semiconductor region 7 and the outer body region 60 (first outer well region 42) with the dummy insulating film 102 in between. The dummy electrode 103 may also be referred to as a "dummy embedded electrode".

[0149] The dummy electrode 103 has an electrode surface exposed from the dummy trench 101. The electrode surface is located on the bottom wall side of the dummy trench 101 with respect to the height position of the first main surface 3. The electrode surface has a recess that tapers inward toward the bottom wall of the dummy trench 101. The electrode surface may be at the same height as the gate electrode 18.

[0150] The depth position of the bottom of one dummy trench structure 61 may be the same as the depth position of the bottom of the dummy trench structure 61. The width in the second direction Y of the dummy trench structure 61 may be the same as the width in the second direction Y of the dummy trench structure 61.

[0151] In this configuration, the source region 11 is not formed in the outer peripheral region 9. On the other hand, the dummy trench structure 61 is provided only in the outer peripheral region 9. Therefore, the source region 11 is not exposed on the side wall of the dummy trench 101. In other words, the side wall of the dummy trench 101 is not in contact with the source region 11. Therefore, no channel is formed around the dummy trench structure 61.

[0152] Since no channels are formed around the dummy trench structure 61, the dummy trench structure 61 does not function as a trench gate structure 15. To more reliably prevent the dummy trench structure 61 from functioning as a trench gate structure 15, a structure that applies a gate potential to the dummy trench structure 61 may be provided.

[0153] The semiconductor device 1A includes dummy well regions 105 formed in the regions below each of the multiple dummy trench structures 61 within the chip 2 (second semiconductor region 7) of the outer peripheral region 9. The dummy well regions 105 may also be referred to as "dummy field relaxation regions," "dummy field relaxation layers," etc.

[0154] The dummy well region 105 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7. The p-type impurity concentration of the dummy well region 105 may be higher than or lower than the p-type impurity concentration of the outer body region 60. The p-type impurity (trivalent element) in the dummy well region 105 is preferably aluminum.

[0155] No source potential (the potential applied to the gate well region 25) is applied to the dummy well region 105. If a structure is provided to apply a gate potential to the dummy trench structure 61, then a gate potential is applied to the dummy well region 105.

[0156] Multiple dummy well regions 105 are formed within the second semiconductor region 7, spaced apart from each other in the first direction X, in regions below (specifically directly below) the multiple dummy trench structures 61. The multiple dummy well regions 105 are formed in the thickness range between the bottom of the second semiconductor region 7 and the bottom walls of the multiple dummy trench structures 61, and overlap with the multiple dummy trench structures 61 in a one-to-one correspondence in the thickness direction.

[0157] The multiple dummy well regions 105 each extend in a strip-like manner in the first direction X, following the direction of extension of the corresponding dummy trench structure 61 in a plan view. In other words, the multiple dummy well regions 105 are arranged in a stripe-like pattern extending in the first direction X in a plan view.

[0158] The extension directions of the multiple dummy well regions 105 coincide with the off-direction of the SiC single crystal. The multiple dummy well regions 105 may also extend in a second direction Y, depending on the extension direction of the multiple dummy trench structures 61. In this case, the multiple dummy well regions 105 intersect (specifically, orthogonal to) the off-direction.

[0159] Multiple dummy well regions 105 are formed at intervals from the bottom of the second semiconductor region 7 towards the bottom wall side of the multiple dummy trench structures 61, and face the first semiconductor region 6 across a portion of the second semiconductor region 7. Each of the multiple dummy well regions 105 has an upper end located on the bottom wall side of the corresponding dummy trench structure 61, and a bottom located on the bottom side (second main surface 4 side) of the second semiconductor region 7.

[0160] The upper ends of the multiple dummy well regions 105 are formed with a gap between them and the bottom wall of the corresponding dummy trench structure 61, extending from the bottom of the outer body region 60. The upper ends of the multiple dummy well regions 105 may be connected to the bottom wall of the corresponding dummy trench structure 61. The upper ends of the multiple dummy well regions 105 may have portions that run along the side walls of the corresponding dummy trench structure 61. The upper ends of the multiple dummy well regions 105 may be formed with a gap between them and the bottom of the second semiconductor region 7, extending from the bottom wall of the corresponding dummy trench structure 61.

[0161] Each dummy well region 105 has a dummy bulge 105a and a dummy well bottom 105b. The dummy bulge 105a extends horizontally in an arc shape from the region directly below the corresponding dummy trench structure 61 to both sides of the corresponding dummy trench structure 61. Multiple dummy well regions 105 are each formed in a tapering shape from the dummy bulge 105a towards the bottom.

[0162] The dummy well bottom 105b extends from the dummy bulge 105a in a direction along the first main surface 3. The dummy well bottom 105b may be located on the bottom wall side of the plurality of dummy trench structures 61 relative to the middle portion of the second semiconductor region 7, or it may be located on the bottom side (second main surface 4 side) of the second semiconductor region 7 relative to the middle portion of the second semiconductor region 7. The depth position of the dummy well bottom 105b may be the same as the depth position of the well bottom 25b.

[0163] The dummy well region 105 may have a width greater than the width of the dummy trench structure 61, or a width less than the width of the dummy trench structure 61. The dummy well region 105 may have the same width as the gate well region 25. The width of the dummy well region 105 may be 0.1 μm or more and 2 μm or less.

[0164] The dummy well region 105 may have a depth less than the depth of the dummy trench structure 61, or a depth greater than the depth of the dummy trench structure 61. The depth of the dummy well region 105 is the depth of the dummy well region 105 when the bottom wall of the dummy trench structure 61 is used as the reference point. The dummy well region 105 may have the same depth as the gate well region 25. The depth of the dummy well region 105 may be greater than 0 μm and 5 μm or less.

[0165] The dummy well region 105 forms a pn junction with the second semiconductor region 7. When a reverse bias voltage is applied, the dummy well region 105 expands a depletion layer in the second semiconductor region 7. The depletion layer, starting from the dummy well region 105, expands in the horizontal and thickness directions, mitigating the electric field in the outer peripheral region 9 (dummy trench structure 61).

[0166] The semiconductor device 1A includes a plurality of p-type high-density regions 123, each located at the bottom of a plurality of dummy trench structures 61.

[0167] The following describes one high-concentration region 123. The high-concentration region 123 is sandwiched between the bottom of the dummy trench 101 of the dummy trench structure 61 and the dummy well region 105. The high-concentration region 123 is in contact with the bottom surface of the dummy trench 101.

[0168] The high-concentration region 123 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7 (for example, the base region 91). The high-concentration region 123 may also have a p-type impurity concentration higher than the n-type impurity concentration of the high-concentration region 92, which will be described later. The p-type impurity concentration of the high-concentration region 123 is higher than the p-type impurity concentration of the outer body region 60. The p-type impurity concentration of the high-concentration region 123 is higher than the p-type impurity concentration of the outer well region 40. The p-type impurity concentration of the high-concentration region 123 is higher than the p-type impurity concentration of the dummy well region 105. The p-type impurity concentration of the high-concentration region 123 may also be the same as the p-type impurity concentration of the high-concentration region 23.

[0169] The p-type impurity concentration in the high-concentration region 123 is 1 × 10⁻⁶ １８ cm －３ The above 1 x 10 ２１ cm －３ The following p-type impurity concentrations may be present as peak values. Preferably, the p-type impurity concentration in the high-concentration region 123 is adjusted by at least one trivalent element.

[0170] Of the multiple dummy trench structures 61, the outermost dummy trench structure 61 is the terminal dummy trench structure 61A (Figure 10). The terminal dummy trench structure 61A has the same structure as the remaining dummy trench structures 61, except for its arrangement in the stripe pattern.

[0171] Referring to Figures 7, 10, and 11, the semiconductor device 1A includes a p-type outer well region 40 formed on the surface layer of the first main surface 3 in the outer peripheral region 9. A source potential is applied to the outer well region 40. The outer well region 40 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7.

[0172] The p-type impurity concentration in the outer well region 40 is less than the p-type impurity concentration in the dummy well region 105. The p-type impurity concentration in the outer well region 40 is less than the p-type impurity concentration in the gate contact region 27.

[0173] The p-type impurity concentration in the outer well region 40 may be approximately equal to the p-type impurity concentration in the dummy well region 105. The p-type impurity concentration in the outer well region 40 may be higher than the p-type impurity concentration in the dummy well region 105, or it may be lower than the p-type impurity concentration in the dummy well region 105.

[0174] The p-type impurity concentration in the outer well region 40 may be approximately equal to the p-type impurity concentration in the body region 10. It may also be higher than the p-type impurity concentration in the outer body region 60, or lower than the p-type impurity concentration in the body region 10.

[0175] As described above, the outer well region 40 includes a first outer well region 42 and a plurality of second outer well regions 43.

[0176] A source potential is applied to the first outer well region 42. The first outer well region 42 has a p-type impurity concentration that is higher than the n-type impurity concentration of the second semiconductor region 7.

[0177] Referring mainly to Figures 10 and 11, the first outer well region 42 is formed on the surface of the second semiconductor region 7 and is electrically connected to the second semiconductor region 7. The first outer well region 42 is formed with a gap from the bottom of the second semiconductor region 7 toward the first main surface 3 and faces the first semiconductor region 6 with a part of the second semiconductor region 7 in between. Preferably, the first outer well region 42 is formed with a gap from the depth position of the middle part of the second semiconductor region 7 toward the first main surface 3.

[0178] The first outer well region 42 extends along the outer peripheral boundary 19. The first outer well region 42 is formed deeper than the dummy well region 105. The depth D1 of the first outer well region 42 (Figure 10) may be, for example, greater than 0 μm and 4 μm or less. The depth D1 of the first outer well region 42 may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, 1.75 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, and 3.5 μm or more and 4 μm or less.

[0179] The depth D1 of the first outer well region 42 (Figure 10) is deeper than the bottom wall (bottom) of the dummy trench structure 61. The depth D1 is deeper than the bottom wall (bottom) of the dummy trench structure 61. The depth D1 is deeper than the bottom 105b of the dummy well (bottom of the dummy well region 105).

[0180] In the horizontal direction along the first main surface 3, the first outer well region 42 partially covers at least the dummy well region 105 of the terminal dummy trench structure 61A.

[0181] In the horizontal direction along the first main surface 3, the first outer well region 42 extends its outer peripheral region 9 toward the active region 8 and overlaps at least the dummy well region 105 of the terminal dummy trench structure 61A.

[0182] More specifically, the first outer well region 42 integrally contacts and covers the dummy well region 105 with the dummy bulge 105a and the dummy well bottom 105b. As a result, the first outer well region 42 surrounds the dummy well region 105 from the side wall of the terminal dummy trench structure 61A.

[0183] The first outer well region 42 covers the entire dummy well region 105 of the terminal dummy trench structure 61A. In this configuration, the first outer well region 42 covers the gate well region 25 of the terminal dummy trench structure 61A, and the gate well regions 25 of one to ten dummy trench structures 61 extending from the terminal dummy trench structure 61A.

[0184] In the example shown in Figure 10, the entire dummy well region 105 of the terminal dummy trench structure 61A and the adjacent dummy trench structure 61 is covered by the first outer well region 42, and a portion of the dummy well region 105 of the second dummy trench structure 61 from the terminal dummy trench structure 61A is covered by the first outer well region 42. These dummy well regions 105 are covered by the first outer well region 42 over their entire longitudinal length from one end to the other in the stripe direction (first direction X in this embodiment) of the dummy trench structure 61.

[0185] The first outer well region 42 has an upper end portion 42a on the first main surface 3 side, a lower end portion 42b on the opposite side, and a main body portion 42c between the lower end portion 42b and the upper end portion 42a.

[0186] The upper end portion 42a extends horizontally along the first main surface 3 and is exposed from the first main surface 3. The upper end portion 42a is located on the first main surface 3 side with respect to the depth position of the bottom of the dummy trench structure 61. The upper end portion 42a is located on the first main surface 3 side with respect to the depth position of the bottom of the dummy well region 105. The upper end portion 42a is located on the first main surface 3 side with respect to the depth position of the bottom of the body region 10. The upper end portion 42a is located on the first main surface 3 side with respect to the depth position of the boundary between the high-concentration region 92 and the base region 91.

[0187] The upper end portion 42a is formed in a shape that extends in an arc from the main body portion 42c toward the first main surface 3. The upper end portion 42a includes a central portion exposed from the first main surface 3 and an end portion positioned at a distance from the first main surface 3 toward the bottom of the second semiconductor region 7.

[0188] The lower end portion 42b extends horizontally along the first main surface 3 and forms a pn junction with the second semiconductor region 7. In this configuration, the lower end portion 42b forms a pn junction with the base region 91. The lower end portion 42b is located on the bottom side of the second semiconductor region 7 with respect to the depth position of the bottom of the dummy trench structure 61. The lower end portion 42b is located on the bottom side of the second semiconductor region 7 with respect to the depth position of the bottom of the dummy well region 105. The lower end portion 42b is located on the bottom side of the second semiconductor region 7 with respect to the depth position of the bottom of the outer body region 60.

[0189] The lower end portion 42b is formed in a flat shape that is substantially parallel to the first main surface 3. The lower end portion 42b may also be formed in a flat shape that extends in a direction perpendicular to the thickness direction of the second semiconductor region 7.

[0190] The main body portion 42c is sandwiched between the upper end portion 42a and the lower end portion 42b. The main body portion 42c may be a part of the first outer well region 42 that covers the dummy trench structure 61 and the dummy well region 105.

[0191] The main body portion 42c includes a side portion 42d (Figure 11) connecting the upper end portion 42a and the lower end portion 42b. In this embodiment, the side portion 42d is inclined toward the active region 8 from the upper end portion 42a toward the lower end portion 42b. For example, the first outer well region 42 may be formed in a mesa shape in cross-section, having a side portion 42d that is inclined such that the width W1 narrows from the upper end portion 42a toward the lower end portion 42b.

[0192] The first outer well region 42 has a width W1 that is greater than the width of the dummy trench structure 61 (for example, the width of the lower end portion 42b, Figure 11). The width W1 of the first outer well region 42 is greater than the width of the end dummy trench structure 61A. The width W1 of the first outer well region 42 may be greater than the total width of the multiple end dummy trench structures 61A. The width W1 of the first outer well region 42 may be greater than the total width of the multiple dummy well regions 105.

[0193] The width W1 of the first outer well region 42 may be greater than 0 μm and 300 μm or less. The width W1 of the first outer well region 42 may have a value that falls within at least one of the following ranges: greater than 0 μm and 25 μm or less, 25 μm or more and 50 μm or less, 50 μm or more and 75 μm or less, 75 μm or more and 100 μm or less, 100 μm or more and 125 μm or less, 125 μm or more and 150 μm or less, 150 μm or more and 175 μm or less, 175 μm or more and 200 μm or less, 200 μm or more and 225 μm or less, 225 μm or more and 250 μm or less, 250 μm or more and 275 μm or more and 300 μm or less.

[0194] The first outer well region 42 expands a depletion layer into the second semiconductor region 7 when a reverse bias voltage is applied. The depletion layer, originating from the first outer well region 42, expands in the horizontal and thickness directions, mitigating the electric field near the outer peripheral boundary 19 between the active region 8 and the outer peripheral region 9.

[0195] Referring to Figure 11, the semiconductor device 1A includes a p-type outer contact region 41 formed on the surface layer of the first main surface 3 in the outer peripheral region 9. A source potential is applied to the outer contact region 41. The outer contact region 41 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7 (high-concentration region 92).

[0196] The p-type impurity concentration in the outer contact region 41 is higher than the p-type impurity concentration in the dummy well region 105. The p-type impurity concentration in the outer contact region 41 may be approximately equal to the p-type impurity concentration in the dummy well region 105. The p-type impurity concentration in the outer contact region 41 may be lower than the p-type impurity concentration in the dummy well region 105.

[0197] The p-type impurity concentration in the outer contact region 41 may be approximately equal to the p-type impurity concentration in the gate contact region 27. The p-type impurity concentration in the outer contact region 41 may be higher than or lower than the p-type impurity concentration in the gate contact region 27.

[0198] The outer contact region 41 is formed on the surface of the first outer well region 42. In other words, the outer contact region 41 is formed in the thickness range between the first main surface 3 and the bottom of the first outer well region 42. The outer contact region 41 increases the p-type impurity concentration of the first outer well region 42 and improves the electrical response speed of the first outer well region 42.

[0199] The outer contact region 41 has a width less than the width of the first outer well region 42 and is formed within the first outer well region 42. The outer contact region 41 has an inner edge on the inner side (active region 8 side) of the first main surface 3 and an outer edge on the peripheral side of the first main surface 3.

[0200] The width of the outer contact region 41 may be greater than 0 μm and 300 μm or less. The width of the outer contact region 41 may have a value that falls within at least one of the following ranges: greater than 0 μm and 25 μm or less, 25 μm or more and 50 μm or less, 50 μm or more and 75 μm or less, 75 μm or more and 100 μm or less, 100 μm or more and 125 μm or less, 125 μm or more and 150 μm or less, 150 μm or more and 175 μm or less, 175 μm or more and 200 μm or less, 200 μm or more and 225 μm or less, 225 μm or more and 250 μm or less, 250 μm or more and 275 μm or more and 300 μm or less.

[0201] The outer contact region 41 has an upper end located on the first main surface 3 side and a bottom located on the bottom side of the first outer well region 42. The upper end of the outer contact region 41 is exposed from the first main surface 3. The bottom of the outer contact region 41 is located on the first main surface 3 side with respect to the depth position of the bottom of the dummy well region 105.

[0202] The bottom of the outer contact region 41 is located on the first main surface 3 side with respect to the depth position of the bottom of the first outer well region 42. The bottom of the outer contact region 41 may be located on the first main surface 3 side with respect to the depth position of the bottom of the body region 10, or it may be located on the bottom side of the first outer well region 42.

[0203] The depth (thickness) of the outer contact region 41 may be greater than 0 μm and 1 μm or less. The depth of the outer contact region 41 may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.3 μm or less, 0.3 μm or more and 0.4 μm or less, 0.4 μm or more and 0.5 μm or less, 0.5 μm or more and 0.6 μm or less, 0.6 μm or more and 0.7 μm or less, 0.7 μm or more and 0.8 μm or less, 0.8 μm or more and 0.9 μm or less, and 0.9 μm or more and 1 μm or less.

[0204] Figure 12 is a graph showing an example of the concentration gradient of p-type impurities in the region along the XII-XII line shown in Figure 10. In Figure 12, the p-type impurity concentration in the first outer well region 42 is shown, and the horizontal axis represents the depth in the thickness direction of the second semiconductor region 7, with the upper end of the second semiconductor region 7 (first main surface 3) as the reference point (zero point).

[0205] Referring to Figure 12, the p-type impurity concentration in the first outer well region 42 and the concentration gradient in the second semiconductor region 7 are explained. The numerical values ​​for impurity concentration, thickness, etc. shown below are not intended to uniquely limit the configuration of the first outer well region 42. The impurity concentration, thickness, etc., are adjusted to various values ​​depending on the injection conditions (dose amount, injection temperature, injection energy, etc.) of trivalent or pentavalent elements. Also, the term "concentration gradient" may be completely replaced with the term "concentration profile."

[0206] The upper portion 422 of the first outer well region 42 has a concentration gradient characteristic of the impurity region formed by the random injection method. Figure 12 shows the concentration gradient of the upper portion 422 when a predetermined trivalent element (aluminum in this case) is introduced into the second semiconductor region 7 in a random direction with an injection energy of 650 KeV. The random direction is a direction that is not parallel (or nearly parallel) to the axial channel of the second semiconductor region 7 (for example, the vertical direction Z). The depth (thickness) of the upper portion 422 is about 0.5 μm, and the dose of the trivalent element is 1 × 10⁻¹⁶ １３ cm －２ That is the case.

[0207] The upper portion 422 has a rapidly increasing portion 86, a peak portion 87 (peak value P1), and a rapidly decreasing portion 88 in the range of 0.5 μm.

[0208] The rapid increase section 86 is the portion where the impurity concentration rapidly increases from the first main surface 3 toward the peak section 87. The sharp decrease section 88 is the portion where the impurity concentration sharply decreases from the peak section 87 toward the lower end 42b of the first outer well region 42. For example, the depth position of the peak section 87 is 0.2 μm or more and 0.3 μm or less from the boundary with the outer contact region 41. The upper portion 422 may have the rapid increase section 86 and the sharp decrease section 88 in the range of 0.1 μm or more and 0.2 μm or less on the shallower and deeper sides of the peak section 87, respectively.

[0209] The rapid increase section 86 has a thickness of 0.1 μm or more and 0.2 μm or less, and has a concentration change rate of 100% or more within that thickness range. Similarly, the rapid decrease section 88 has a thickness of 0.1 μm or more and 0.2 μm or less, and has a concentration change rate of 100% or more within that thickness range.

[0210] The lower portion 421 of the first outer well region 42 has a concentration gradient characteristic of the impurity region formed by the channeling injection method. Figure 12 shows the concentration gradient of the lower portion 421 when a predetermined trivalent element (in this case, aluminum) is introduced into the second semiconductor region 7 parallel or nearly parallel to the axial channel of the second semiconductor region 7 with an injection energy of 650 KeV. The depth (thickness) of the lower portion 421 from the boundary between the high-concentration region 92 and the base region 91 is about 2.5 μm, and the dose of the trivalent element is 1 × 10⁻¹⁶ １３ cm －２ That is the case.

[0211] The p-type impurity concentration in the lower portion 421 has a concentration gradient that includes a gradually increasing portion 95, a peak portion 96, a slow-growing portion 97, and a gradually decreasing portion 98, from the upper end portion 42a to the lower end portion 42b. The gradually increasing portion 95 is the portion that forms the boundary portion 432 of the lower portion 421, and is the portion in which the p-type impurity concentration gradually increases at a relatively steep rate from the upper end portion 42a to the lower end portion 42b up to the peak portion 96.

[0212] The peak portion 96 is the portion having the peak value P2 (maximum value) of the p-type impurity concentration. The peak portion 96 is also a convex main concentration transition portion that includes a series of concentration changes (inflection points) where the p-type impurity concentration changes from increasing (increasing trend) to decreasing (decreasing trend). The depth position of the peak portion 96 from the boundary between the high-concentration region 92 and the base region 91 is between 0.5 μm and 1 μm.

[0213] The slow-reducing portion 97 is formed in the region below the peak portion 96, on the lower end 42b side, and is a portion where the impurity concentration gradually decreases at a relatively slow rate. In other words, the slow-reducing portion 97 is a portion that maintains a constant p-type impurity concentration within a certain depth range, and forms the main body of the lower portion 421. The p-type impurity concentration in the slow-reducing portion 97 gradually decreases within a concentration range lower than the p-type impurity concentration in the peak portion 96.

[0214] The slow-down portion 97 is defined by a portion having a concentration reduction rate of 50% or less in a thickness range of at least 1 μm. In this example, the slow-down portion 97 has a thickness of 0.7 μm to 1.5 μm and has a concentration reduction rate of 50% or less in that thickness range. In this example, the p-type impurity concentration of the slow-down portion 97 is 4.5 × 10⁻⁶. １６ cm －３ The above 9 x 10 １６ cm －３ The concentrations fall within the following range.

[0215] The gradually decreasing section 98 is the portion that forms the lower end portion 42b of the first outer well region 42. The gradually decreasing section 98 has a higher concentration reduction rate than the concentration reduction rate in the slow section 97, and is the portion where the p-type impurity concentration gradually decreases from the slow section 97 toward the lower end portion 42b. The concentration reduction rate per unit thickness in the gradually decreasing section 98 is greater than the concentration reduction rate per unit thickness in the slow section 97. The p-type impurity concentration in the gradually decreasing section 98 is 1 × 10⁻⁶ from the slow section 97. １５ cm －３ It is gradually decreasing to that point.

[0216] Referring to Figure 11, the second outer well region 43 is formed in an electrically floating state. A source potential may be applied to the second outer well region 43.

[0217] The number of second outer well regions 43 is arbitrary. The number of second outer well regions 43 may be between 1 and 15. The number of second outer well regions 43 may be 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, or 15. Typically, the number of second outer well regions 43 is between 1 and 10. In this embodiment, semiconductor device 1A includes, as an example, three second outer well regions 43.

[0218] The second outer well region 43 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7. The p-type impurity concentration of the second outer well region 43 may be approximately equal to the p-type impurity concentration of the first outer well region 42. The p-type impurity concentration of the second outer well region 43 may be higher than the p-type impurity concentration of the first outer well region 42, or lower than the p-type impurity concentration of the first outer well region 42.

[0219] The p-type impurity concentration in the second outer well region 43 may be lower than the p-type impurity concentration in the gate contact region 27. The p-type impurity concentration in the second outer well region 43 may be higher than the p-type impurity concentration in the dummy well region 105, or lower than the p-type impurity concentration in the dummy well region 105. The p-type impurity concentration in the second outer well region 43 may be higher than the p-type impurity concentration in the body region 10, or lower than the p-type impurity concentration in the outer body region 60.

[0220] In this configuration, the p-type impurity concentrations in the multiple second outer well regions 43 are approximately equal to each other. The p-type impurity concentrations in the multiple second outer well regions 43 are arbitrary and can take various values ​​depending on the electric field to be relaxed. The p-type impurity concentrations in the multiple second outer well regions 43 may also be different from each other.

[0221] Multiple second outer well regions 43 are formed on the surface of the second semiconductor region 7 and are electrically connected to the second semiconductor region 7. Multiple second outer well regions 43 are formed at intervals from the bottom of the second semiconductor region 7 toward the first main surface 3 and face the first semiconductor region 6 across a portion of the second semiconductor region 7. Preferably, multiple second outer well regions 43 are formed at intervals from the depth position of the middle part of the second semiconductor region 7 toward the first main surface 3.

[0222] The depth D2 of the second outer well region 43 may be approximately equal to the depth D1 of the first outer well region 42 (Figure 10). The depth D2 of the second outer well region 43 may be deeper than the depth D1 of the first outer well region 42, or it may be shallower than the depth D1 of the first outer well region 42.

[0223] The depth D2 of the second outer well region 43 may be deeper than the bottom wall (bottom) of the dummy trench structure 61. The depth D2 of the second outer well region 43 may be deeper than the dummy well bottom 105b (bottom of the dummy well region 105). The depth D2 of the second outer well region 43 may be, for example, greater than 0 μm and 4 μm or less.

[0224] In this configuration, the depths D2 of the multiple second outer well regions 43 are approximately equal to each other. The depths D2 of the multiple second outer well regions 43 are arbitrary and can take various values ​​depending on the electric field to be relaxed. The depths D2 of the multiple second outer well regions 43 may be different from each other.

[0225] Multiple second outer well regions 43 are formed at intervals in the region between the periphery of the first main surface 3 and the outer peripheral boundary portion 19 (Figure 10). Multiple second outer well regions 43 are formed at intervals in the region between the periphery of the first main surface 3 and the first outer well region 42.

[0226] The multiple second outer well regions 43 may have a width W2 less than the width W1 of the first outer well region 42. The width W2 of the multiple second outer well regions 43 (for example, the width of the second outer well region 43) may be smaller than the width of the trench gate structure 15, or larger than the width of the trench gate structure 15. The width W2 of the second outer well region 43 may be smaller than the width of the dummy well region 105, or larger than the width of the dummy well region 105.

[0227] In this configuration, the widths W2 of the multiple second outer well regions 43 are approximately equal to each other. The widths W2 of the multiple second outer well regions 43 are arbitrary and can take various values ​​depending on the electric field to be relaxed. The widths W2 of the multiple second outer well regions 43 may be different from each other.

[0228] The spacing between the multiple second outer well regions 43 may be less than or equal to the width W2 of the second outer well region 43. Preferably, the spacing between the multiple second outer well regions 43 is less than the width W2 of the second outer well region 43. The spacing between the multiple second outer well regions 43 may be greater than the width W2 of the second outer well region 43.

[0229] In this configuration, the spacing between the multiple second outer well regions 43 is approximately equal to that of the other. The spacing between the multiple second outer well regions 43 is arbitrary and can take various values ​​depending on the electric field to be relaxed. The spacing between the multiple second outer well regions 43 may also be different from that of the other.

[0230] The multiple second outer well regions 43 expand a depletion layer in the second semiconductor region 7 when a reverse bias voltage is applied. The depletion layer originating from the multiple second outer well regions 43 expands in the horizontal and thickness directions and integrates with the depletion layer originating from the first outer well region 42. The multiple second outer well regions 43 extend the depletion layer originating from the first outer well region 42 toward the periphery of the first main surface 3, thereby mitigating the electric field at the periphery (outer peripheral region 9) of the first main surface 3.

[0231] Referring to Figures 8 to 11, the semiconductor device 1A includes a main surface insulating film 45 that selectively covers the first main surface 3. The main surface insulating film 45 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. It is preferable that the main surface insulating film 45 contains the same insulating material as the gate insulating film 17. In this embodiment, the main surface insulating film 45 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the main surface insulating film 45 includes a silicon oxide film made of the oxide of the chip 2.

[0232] The main surface insulating film 45 is connected to the gate insulating films 17 of the multiple trench gate structures 15 in the active region 8, exposing the gate electrodes 18 of the multiple trench gate structures 15.

[0233] The main surface insulating film 45 covers the second semiconductor region 7, the first outer well region 42, the outer contact region 41, and the second outer well region 43 in the outer peripheral region 9. In this embodiment, the main surface insulating film 45 is continuous with the first to fourth side surfaces 5A to 5D at the peripheral edge of the first main surface 3. The main surface insulating film 45 may be formed with a gap inward from the peripheral edge of the first main surface 3, exposing the peripheral edge of the first main surface 3 (the second semiconductor region 7).

[0234] Referring to Figures 8 to 10, as described above, the semiconductor device 1A includes an insulating interlayer insulating film 47. The interlayer insulating film 47 selectively covers the first main surface 3 with the main surface insulating film 45 in between.

[0235] The interlayer insulating film 47 covers a plurality of trench gate structures 15 (gate electrodes 18) on the active region 8 side. On the outer peripheral region 9 side, the interlayer insulating film 47 covers the second semiconductor region 7, the first outer well region 42, the outer contact region 41, and the second outer well region 43, sandwiching the main surface insulating film 45.

[0236] In this embodiment, the interlayer insulating film 47 is continuous with the first to fourth side surfaces 5A to 5D at the peripheral edge of the first main surface 3. The interlayer insulating film 47 may be formed with a gap inward from the peripheral edge of the first main surface 3, exposing the peripheral edge of the first main surface 3 (second semiconductor region 7).

[0237] The interlayer insulating film 47 may have a thickness of 0.5 μm or more and 3 μm or less. The thickness of the interlayer insulating film 47 may have a value that falls within at least one of the following ranges: 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less.

[0238] The semiconductor device 1A includes a plurality of gate openings (not shown) formed in the interlayer insulating film 47 in the active region 8. The plurality of gate openings are formed in a one-to-many correspondence with a corresponding trench gate structure 15. In this configuration, the plurality of gate openings penetrate the interlayer insulating film 47, exposing one end or the other end of each of the plurality of trench gate structures 15 (gate electrodes 18).

[0239] Multiple gate openings may each have an opening end that is curved in an arc shape. Multiple gate openings may be formed in a square shape, a rectangular shape (strip shape) extending in a first direction X, a rectangular shape (strip shape) extending in a second direction Y, a circular shape, etc., in a plan view. Multiple gate openings may each have an opening end that is curved in an arc shape.

[0240] Referring to Figures 6 to 10, the semiconductor device 1A includes a plurality of source openings 49 formed in the interlayer insulating film 47 in the active region 8. The plurality of source openings 49 are formed in the portion of the interlayer insulating film 47 that covers the active region 8. In this configuration, the plurality of source openings 49 are each formed in regions between a plurality of adjacent trench gate structures 15, exposing a plurality of source regions 11 and a plurality of gate contact regions 27, respectively.

[0241] Multiple source openings 49 penetrate the main surface insulating film 45 and the interlayer insulating film 47, exposing corresponding multiple source regions 11 and multiple gate contact regions 27, respectively. Each of the multiple source openings 49 may have an arc-shaped curved opening end.

[0242] Multiple source openings 49 may be formed in a one-to-many correspondence with respect to the region between adjacent trench gate structures 15. In this case, the multiple source openings 49 may be formed at intervals along the region between the corresponding trench gate structures 15. Also in this case, the multiple source openings 49 may be formed in a square, rectangular (strip-shaped), circular, or the like in a plan view.

[0243] Referring to Figure 11, the semiconductor device 1A includes at least one (one in this embodiment) outer opening 50 formed in the interlayer insulating film 47 in the outer peripheral region 9. The outer opening 50 penetrates the main surface insulating film 45 and the interlayer insulating film 47, exposing the outer contact region 41. In a plan view, the outer opening 50 extends in a strip shape along the outer contact region 41.

[0244] In this configuration, the outer opening 50 is formed in a polygonal ring shape (specifically, a quadrilateral ring shape) that surrounds the inner portion (active region 8) of the first main surface 3 along the outer contact region 41 in a plan view. The outer opening 50 may have an opening end that is curved in an arc shape.

[0245] The semiconductor device 1A may have a plurality of outer openings 50. In this case, the plurality of outer openings 50 may be formed at intervals along the outer contact region 41 so as to surround the inner portion (active region 8) of the first main surface 3. In this case, the plurality of outer openings 50 may be formed in a square shape, rectangular shape, hexagonal shape, circular shape, etc., when viewed from above.

[0246] Referring to Figures 8 to 10, in this embodiment, the source pad electrode 51 has a laminated structure including a lower electrode film 52 and a main electrode film 53 stacked in this order from the tip 2 side. In this embodiment, the lower electrode film 52 has a laminated structure including a first electrode film and a second electrode film. In this embodiment, the first electrode film includes a Ti film, and the second electrode film includes a TiN film. The lower electrode film 52 does not necessarily have to have a laminated structure, and may have a single-layer structure consisting of either the first electrode film (Ti film) or the second electrode film (TiN film).

[0247] The lower electrode film 52 comprehensively covers the region of the interlayer insulating film 47 where multiple source openings 49 are formed, and extends from above the interlayer insulating film 47 into the multiple source openings 49. The lower electrode film 52 has a portion that covers the insulating main surface of the interlayer insulating film 47 in a film-like manner, a portion that covers the wall surfaces of the multiple source openings 49 in a film-like manner, and a portion that covers the first main surface 3 within the multiple source openings 49 in a film-like manner. The lower electrode film 52 is mechanically and electrically connected to the multiple source regions 11 and the multiple gate contact regions 27 within the source openings 49.

[0248] The main electrode film 53 contains a different conductive material than the lower electrode film 52. The main electrode film 53 may contain at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The Al alloy film may contain at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film. The main electrode film 53 has a thickness greater than the thickness (total thickness) of the lower electrode film 52. Preferably, the thickness of the main electrode film 53 is greater than the thickness of the interlayer insulating film 47.

[0249] The thickness of the main electrode film 53 may be 0.5 μm or more and 5 μm or less. The thickness of the main electrode film 53 may have a value that falls within at least one of the following ranges: 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or more and 5 μm or less.

[0250] The main electrode film 53 directly covers the lower electrode film 52. The main electrode film 53 collectively covers the region of the interlayer insulating film 47 where multiple source openings 49 are formed, and backfills the multiple source openings 49.

[0251] The main electrode film 53 has a portion that covers the insulating main surface of the interlayer insulating film 47 with the lower electrode film 52 in between, a portion that covers the wall surfaces of the plurality of source openings 49 with the lower electrode film 52 in between, and a portion that covers the first main surface 3 with the lower electrode film 52 in between. The main electrode film 53 is electrically connected to the plurality of source regions 11 and the plurality of gate contact regions 27 within the plurality of source openings 49 via the lower electrode film 52.

[0252] Referring to Figure 11, in semiconductor device 1A, the source wiring 56 is arranged around the source pad electrode 51 on the interlayer insulating film 47. The source wiring 56 is drawn out from the active region 8 to the outer peripheral region 9 and has a portion that faces the outer contact region 41 across the interlayer insulating film 47. The source wiring 56 enters the outer opening 50 from above the interlayer insulating film 47 and is electrically connected to the outer contact region 41 within the outer opening 50. In other words, the source wiring 56 is electrically connected to the first outer well region 42 via the outer contact region 41.

[0253] The source wiring 56 has an inner edge on the inner side (active region 8 side) of the first main surface 3, and an outer edge on the peripheral side of the first main surface 3. The inner edge of the source wiring 56 is located within the active region 8 and faces one or more (multiple in this embodiment) trench gate structures 15 across the interlayer insulating film 47.

[0254] The outer edge of the source wiring 56 is formed with a gap extending inward (towards the active region 8) from the periphery of the first main surface 3. The outer edge of the source wiring 56 is formed with a gap extending inward from the innermost of the multiple second outer well regions 43. In other words, the source wiring 56 does not face any of the multiple second outer well regions 43 across the interlayer insulating film 47.

[0255] With this configuration, the shielding of the electric field dispersion path by the source wiring 56 in the region above the multiple second outer well regions 43 is suppressed, and the electric field (electric field lines) is appropriately dispersed by the multiple second outer well regions 43.

[0256] Although the cross-sectional structure is omitted, the source wiring 56 may have a laminated structure including a lower electrode film 52 and a main electrode film 53 stacked in this order from the chip 2 side, similar to the source pad electrode 51.

[0257] Although the cross-sectional structure is omitted, the gate pad electrode 57 and gate wiring 58 (see Figure 1) may also have a laminated structure including a lower electrode film 52 and a main electrode film 53 stacked in this order from the chip 2 side, similar to the source pad electrode 51 and source wiring 56.

[0258] As described above, the semiconductor device 1A includes a temperature sensor structure 63 formed on the first main surface 3 in the outer peripheral region 9 for detecting temperature.

[0259] Figure 13A is a plan view of the temperature sensor element 64 included in the temperature sensor structure 63. Figure 13B is a cross-sectional view of the temperature sensor structure 63 cut along the line XIIIB-XIIIB shown in Figure 13A. Figure 13B shows the temperature sensor structure 63 cut along a different cross-sectional line than that in Figure 10.

[0260] The temperature sensor structure 63 will now be described. The temperature sensor structure 63 includes a temperature sensor element 64 and an insulating film 109 that insulates the temperature sensor element 64 from at least the first main surface 3.

[0261] Referring to Figures 13A and 13B, the temperature sensor element 64 includes a temperature-sensitive diode sensor. This temperature-sensitive diode sensor includes a polysilicon diode. This polysilicon diode includes a polysilicon layer 110, an anode region 112, and a cathode region 113. The anode region 112 and the cathode region 113 are formed in the polysilicon layer 110. The temperature sensor element 64 is a diode element with the anode region 112 as the anode and the cathode region 113 as the cathode.

[0262] The polysilicon layer 110 is formed on the first main surface 3 in the outer peripheral region 9. In this embodiment, the polysilicon layer 110 has a rectangular shape in plan view. The thickness of the polysilicon layer 110 may be 0.2 μm or more and 1.0 μm or less.

[0263] More specifically, the polysilicon layer 110 is formed on the field insulating film 106 contained in the insulating film 109 in the outer peripheral region 9. The polysilicon layer 110 is electrically insulated from the first main surface 3 (chip 2) by the field insulating film 106.

[0264] The anode region 112 is a region formed by selectively introducing p-type impurities into the polysilicon layer 110. In this embodiment, the anode region 112 is formed in the central part of the polysilicon layer 110. The anode region 112 is exposed from the first surface 110a and the second surface 110b of the polysilicon layer 110.

[0265] In this embodiment, the anode region 112 is formed in a quadrilateral shape in plan view. The planar shape of the anode region 112 is arbitrary. In plan view, the anode region 112 may be formed in a polygonal shape such as a triangle or hexagon, a circular shape, or an ellipse shape.

[0266] The cathode region 113 is a region formed by selectively introducing n-type impurities into the polysilicon layer 110. In this embodiment, the cathode region 113 is formed along the periphery of the anode region 112. In this embodiment, the cathode region 113 is formed in a C-shape or U-shape surrounding the anode region 112 in a plan view. The cathode region 113 may also be formed in an annular shape surrounding the entire circumference of the anode region 112. The cathode region 113 is electrically connected to the anode region 112.

[0267] In this configuration, the cathode region 113 is exposed from the first surface 110a and the second surface 110b of the polysilicon layer 110. The cathode region 113 is connected to the anode region 112 across the entire thickness direction of the polysilicon layer 110.

[0268] The cathode region 113 forms a pn joint 111 at its interface with the anode region 112. In this embodiment, since the cathode region 113 surrounds the anode region 112 in a C-shape or U-shape, the pn joint 111 is C-shaped or U-shaped in plan view. If the cathode region 113 surrounds the anode region 112 in an annular manner and is in contact with the entire circumference of the anode region 112, the pn joint 111 will have an annular shape in plan view accordingly.

[0269] Referring to Figure 13B, the insulating film 109 includes a field insulating film 106, a cover insulating film 107, and a sensor insulating film 108.

[0270] The field insulating film 106 selectively covers the first main surface 3 in the peripheral region 9. The thickness T3 of the field insulating film 106 is greater than that of the main surface insulating film 45. The field insulating film 106 is also greater than that of the interlayer insulating film 47. The field insulating film 106 may contain a silicon oxide film. The field insulating film 106 may contain a silicon oxide film formed by the CVD method. The lower surface of the field insulating film 106 is in contact with the first main surface 3 in the peripheral region 9.

[0271] The field insulating film 106 has an upper surface parallel to the first main surface 3. A temperature sensor element 64 is positioned on the upper surface of the field insulating film 106. In other words, the temperature sensor element 64 is formed on the first main surface 3 in the outer peripheral region 9, with the field insulating film 106 in between. Because the field insulating film 106 is sufficiently thick, the temperature sensor element 64 is electrically insulated from the first main surface 3 (chip 2) by the field insulating film 106. Furthermore, because the field insulating film 106 is sufficiently thick, the temperature sensor element 64 is not affected by the heat from the first main surface 3.

[0272] The cover insulating film 107 constitutes the upper and side walls of the temperature sensor structure 63. The cover insulating film 107 covers the upper and side portions of the temperature sensor element 64. The cover insulating film 107 accommodates a portion of the anode wiring 116 and cathode wiring 117 described below.

[0273] The cover insulating film 107 may have the same thickness as the interlayer insulating film 47. The cover insulating film 107 may be the same type of insulating film as the interlayer insulating film 47. The cover insulating film 107 may be formed at the same time as the interlayer insulating film 47.

[0274] The sensor insulating film 108 includes a first sensor insulating film 108a and a second sensor insulating film 108b. The first sensor insulating film 108a is formed on the upper and side surfaces of the field insulating film 106. The first sensor insulating film 108a covers the upper and side surfaces of the field insulating film 106. In this embodiment, the polysilicon layer 110 (temperature sensor element 64) is placed on the upper surface of the field insulating film 106 via the first sensor insulating film 108a.

[0275] The second sensor insulating film 108b is formed on the upper and side surfaces of the polysilicon layer 110 (temperature sensor element 64). The second sensor insulating film 108b selectively covers the upper surface of the polysilicon layer 110 (temperature sensor element 64). The second sensor insulating film 108b covers the side surfaces of the polysilicon layer 110 (temperature sensor element 64).

[0276] The periphery of the sensor insulating film 108 (the periphery of the first sensor insulating film 108a) is connected to the main surface insulating film 45. The sensor insulating film 108 may have the same thickness as the main surface insulating film 45. The sensor insulating film 108 may be the same insulating film as the main surface insulating film 45. The sensor insulating film 108 may be formed at the same time as the main surface insulating film 45.

[0277] In the second sensor insulating film 108b, an anode opening 114 and a cathode opening 115 are formed in the portion covering the polysilicon layer 110. The anode opening 114 exposes the anode region 112. The anode opening 114 is formed penetrating the second sensor insulating film 108b. In this embodiment, the anode opening 114 is formed in a substantially rectangular shape in plan view. Of course, the planar shape of the anode opening 114 is arbitrary and not limited to a rectangle; it may be any polygonal shape, or it may be circular or elliptical. Also, in plan view, the anode opening 114 may extend in a band shape along the periphery of the anode region 112. In this case, in plan view, the anode opening 114 may be an annular shape such as a circular annular shape, an elliptical annular shape, or a polygonal annular shape.

[0278] The cathode opening 115 exposes the cathode region 113. The cathode opening 115 is formed by penetrating the second sensor insulating film 108b. In a plan view, the cathode opening 115 extends in a band shape along the periphery of the anode region 112. In a plan view, the cathode opening 115 is formed in a C-shape or U-shape. The planar shape of the cathode opening 115 is arbitrary and is not limited to a C-shape or U-shape. In a plan view, the cathode opening 115 may be formed in a polygonal shape such as a triangle, square, or hexagon, or in an elliptical shape.

[0279] The temperature sensor structure 63 includes an anode wiring 116 and a cathode wiring 117. The anode wiring 116 is formed on the second sensor insulating film 108b.

[0280] One end of the anode wiring 116 is in contact with the upper surface of the anode region 112 through the anode opening 114. The anode wiring 116 may contain at least one of aluminum, copper, Al-Si-Cu (aluminum-silicon-copper) alloy, Al-Si (aluminum-silicon) alloy, or Al-Cu (aluminum-copper) alloy.

[0281] The other end of the anode wiring 116 penetrates the cover insulating film 107 and is exposed to the outside of the temperature sensor structure 63. The other end of the anode wiring 116 is connected to the first connecting wiring 67 (Figure 5). As a result, the anode region 112 is electrically connected to the first extraction electrode 65 via the anode wiring 116 and the first connecting wiring 67.

[0282] The cathode wiring 117 is formed on the second sensor insulating film 108b.

[0283] One end of the cathode wiring 117 is in contact with the upper surface of the cathode region 113 via the cathode opening 115. The cathode wiring 117 may contain at least one of the following materials: aluminum, copper, Al-Si-Cu (aluminum-silicon-copper) alloy, Al-Si (aluminum-silicon) alloy, or Al-Cu (aluminum-copper) alloy.

[0284] The other end of the cathode wiring 117 penetrates the cover insulating film 107 and is exposed to the outside of the temperature sensor structure 63. The other end of the cathode wiring 117 is connected to the second connecting wiring 68 (Figure 5). As a result, the cathode region 113 is electrically connected to the second extraction electrode 66 via the cathode wiring 117 and the second connecting wiring 68.

[0285] The sensor insulating film 108 may be omitted. In this case, the top and side surfaces of the polysilicon layer 110 (temperature sensor element 64) are directly covered by the cover insulating film 107. Alternatively, the polysilicon layer 110 (temperature sensor element 64) is placed directly on the top surface of the field insulating film 106.

[0286] In the temperature sensor element 64, the cathode region 113 may be formed in the central part of the polysilicon layer 110, and the anode region 112 may be formed in the peripheral part of the polysilicon layer 110. In this case, the anode region 112 may surround the cathode region 113 in a C-shape or a U-shape. The anode region 112 may surround the cathode region 113 in a ring shape.

[0287] Referring to Figure 3, as described above, the semiconductor device 1A includes a first extraction electrode 65 and a second extraction electrode 66. The first extraction electrode 65 and the second extraction electrode 66 are sandwiched in the first direction X by a source pad electrode 51 and a gate pad electrode 57. The first extraction electrode 65 and the second extraction electrode 66 are sandwiched in the first direction X by a source pad electrode 51 and a gate wiring 58.

[0288] Referring to Figures 5 and 10, the temperature sensor structure 63 is formed on the first outer well region 42. In this configuration, the temperature sensor structure 63 overlaps the p-shaped first outer well region 42 in a plan view. The temperature sensor structure 63 does not overlap the outer body region 60 in a plan view.

[0289] The first outer well region 42 is exposed to the first main surface 3 in the outer peripheral region 9. The field insulating film 106 included in the temperature sensor structure 63 is in contact with the first outer well region 42 on the first main surface 3 of the outer peripheral region 9. The entire area of ​​the field insulating film 106 is in contact with the first outer well region 42.

[0290] Referring to Figure 10, the temperature sensor structure 63 (temperature sensor element 64) is formed with a gap in the second direction Y from the periphery 51d of the source pad electrode 51. The temperature sensor structure 63 (temperature sensor element 64) faces the periphery 51d of the source pad electrode 51 in the second direction Y, with a portion of the surface insulating film 70 in between. In other words, in a plan view, the temperature sensor structure 63 (temperature sensor element 64) is positioned with a gap on the outside from the periphery 51d of the source pad electrode 51.

[0291] Referring to Figures 5 and 11, the temperature sensor structure 63 is sandwiched in the second direction Y by the source pad electrode 51 and the gate wiring 58. The temperature sensor structure 63 is formed with a gap between it and both the source pad electrode 51 and the gate wiring 58. In other words, in the outer peripheral region 9, the temperature sensor structure 63 is formed with an inward gap between it and the gate wiring 58.

[0292] The temperature sensor structure 63 is sandwiched in the second direction Y by the source pad electrode 51 and the source wiring 56. In other words, in the outer peripheral region 9, the temperature sensor structure 63 is formed with an inward gap from the source wiring 56.

[0293] Figure 13C is a cross-sectional view along the line XIIIC-XIIIC shown in Figure 3. The first extraction electrode 65 and the second extraction electrode 66 will be described below with reference to Figures 3 and 13C.

[0294] Referring to Figures 3 and 13C, the first extraction electrode 65 is formed on the active region 8. In other words, the first extraction electrode 65 faces the first main surface 3 in the active region 8, with the main surface insulating film 45 in between. In yet another word, the first extraction electrode 65 overlaps the active region 8 in a plan view. The first extraction electrode 65, like the source pad electrode 51, has a laminated structure including a lower electrode film 52 and a main electrode film 53 stacked in this order from the chip 2 side.

[0295] Referring to Figure 3, the first extraction electrode 65 is, for example, rectangular in shape in a plan view. The peripheral edge of the first extraction electrode 65 is aligned with the first direction X and the second direction Y.

[0296] The first extraction electrode 65 is positioned with a gap between it and the source pad electrode 51 in both the first direction X and the second direction Y (with a gap along the first main surface 3). The first extraction electrode 65 is positioned with a gap between it and the gate pad electrode 57 in the first direction X. The first extraction electrode 65 is positioned with a gap between it and the gate wiring 58 in the second direction Y. The first extraction electrode 65 is electrically insulated from the source pad electrode 51, the gate pad electrode 57, and the gate wiring 58.

[0297] Referring to Figures 3 and 13C, the second extraction electrode 66 is formed on the active region 8, as described above. In other words, the second extraction electrode 66 faces the first main surface 3 in the active region 8, with the main surface insulating film 45 in between. In yet another way, the second extraction electrode 66 overlaps the active region 8 in a plan view. The second extraction electrode 66, like the source pad electrode 51, has a laminated structure including a lower electrode film 52 and a main electrode film 53 stacked in this order from the chip 2 side.

[0298] Referring to Figure 3, the second extraction electrode 66 is, for example, rectangular in shape in a plan view. The peripheral edge of the second extraction electrode 66 is aligned with the first direction X and the second direction Y.

[0299] The second extraction electrode 66 is positioned with a gap between it and the source pad electrode 51 in both the first direction X and the second direction Y. The second extraction electrode 66 is positioned with a gap between it and the gate pad electrode 57 in the first direction X. The second extraction electrode 66 is positioned with a gap between it and the gate wiring 58 in the second direction Y. The second extraction electrode 66 is electrically insulated from the source pad electrode 51, the gate pad electrode 57, and the gate wiring 58.

[0300] In this configuration, the first extraction electrode 65 and the second extraction electrode 66 are aligned in the second direction Y. The first extraction electrode 65 is positioned closer to the outside of the active region 8 (i.e., towards the outer peripheral region 9) relative to the second extraction electrode 66. The second extraction electrode 66 is positioned closer to the inside of the active region 8 relative to the second extraction electrode 66.

[0301] In other words, the first extraction electrode 65 and the second extraction electrode 66 are spaced apart in the second direction Y. The first extraction electrode 65 and the second extraction electrode 66 are electrically insulated from each other.

[0302] The first extraction electrode 65 may be positioned closer to the inside of the active region 8 relative to the second extraction electrode 66. The second extraction electrode 66 may be positioned closer to the outside of the active region 8 (i.e., towards the outer peripheral region 9) relative to the second extraction electrode 66. The first extraction electrode 65 and the second extraction electrode 66 may be aligned in the first direction X.

[0303] Conventionally, no MOSFETs with a built-in temperature sensor element are known. If a temperature sensor element were to be integrated into a MOSFET, it would be conceivable to form the temperature sensor element in a portion of the active region.

[0304] However, in this case, the area of ​​the active region may be reduced by the area of ​​the temperature sensor element. Therefore, it is desirable to incorporate a temperature sensor structure (temperature sensor element) without reducing the area of ​​the active region. In other words, it is desirable to provide a semiconductor device that can realize a configuration that incorporates a temperature sensor structure (temperature sensor element) while effectively utilizing the active region.

[0305] As described above, in semiconductor device 1A, the temperature sensor structure 63 is formed on the first main surface 3 in the outer peripheral region 9. Specifically, in a plan view, the temperature sensor structure 63 overlaps with the p-shaped outer well region 40. More specifically, in a plan view, the temperature sensor structure 63 overlaps with the first outer well region 42.

[0306] Since the temperature sensor structure 63 is not formed in the active region 8, the temperature sensor structure 63 can be incorporated into the semiconductor device 1A without reducing the area of ​​the active region. This makes it possible to realize a configuration that incorporates the temperature sensor structure 63 while effectively utilizing the active region 8.

[0307] Furthermore, the temperature sensor structure 63 includes a temperature sensor element 64 and an insulating film 109 that insulates the temperature sensor element 64 from at least the first main surface 3. Specifically, the insulating film 109 includes a field insulating film 106, and the temperature sensor element 64 is formed on the upper surface of the field insulating film 106 via the first sensor insulating film 108a. Since it is insulated from the first main surface 3 via the field insulating film 106, the temperature sensor element 64 can be formed on the first main surface 3 (outer peripheral region 9) while reliably avoiding electrical influence from the first main surface 3.

[0308] Furthermore, because the field insulating film 106 is sufficiently thick, the temperature sensor element 64 can reliably avoid thermal influence from the first main surface 3.

[0309] Furthermore, the insulating film 109 further includes a cover insulating film 107 that covers the upper and side portions of the temperature sensor element 64. Therefore, the temperature sensor element 64 can be insulated from surrounding structures. This further helps to avoid electrical influences on the temperature sensor element 64.

[0310] Furthermore, the cover insulating film 107 further prevents the temperature sensor element 64 from being affected by heat from the surroundings.

[0311] Furthermore, the temperature sensor structure 63 is covered with a surface insulating film 70. This further helps to avoid electrical influences on the temperature sensor element 64.

[0312] Furthermore, the temperature sensor structure 63 is formed with an outer gap from the peripheral edge 51d of the source pad electrode 51. Also, the temperature sensor structure 63 is formed with an inward gap from the source wiring 56. Therefore, the temperature sensor structure 63 can be formed on the first main surface 3 (outer peripheral region 9) while avoiding interference with the source pad electrode 51 and the source wiring 56.

[0313] Furthermore, the first extraction electrode 65 is formed with a gap between it and the source pad electrode 51 in a direction along the first main surface 3. The second extraction electrode 66 is also formed with a gap between it and the source pad electrode 51 in a direction along the first main surface 3. The first extraction electrode 65 and the second extraction electrode 66 are formed with a gap between them in a direction along the first main surface 3. Therefore, the detection output from the temperature sensor element 64 can be efficiently extracted via the first extraction electrode 65 and the second extraction electrode 66.

[0314] Furthermore, the first extraction electrode 65 and the second extraction electrode 66 overlap the active region 8 in a plan view. Therefore, the first extraction pad 79 and the second extraction pad 81 can be formed at positions not far from the other pads (first pad portion 51a, second pad portion 51b, and third pad portion 51c). This makes wire bonding to the first extraction pad 79 and the second extraction pad 81 relatively easy.

[0315] Figure 14 is a plan view of the main part of a semiconductor device 1A according to a second embodiment of the first embodiment of the present disclosure. Figure 14 shows a plan view at the same position as Figure 5. Figure 15 is a cross-sectional view of the main part of a semiconductor device 1A according to a second embodiment. Figure 15 shows a cross-section at the same position as Figure 10.

[0316] The difference between the second embodiment (embodiment examples in Figures 14 and 15) and the first embodiment of the first embodiment (embodiment examples in Figures 1 to 13C) is that the temperature sensor structure 63 overlaps with the dummy formation region 62 in a plan view.

[0317] In a plan view, the temperature sensor structure 63 overlaps with one or more dummy trench structures 61, which are included in a plurality of dummy trench structures 61.

[0318] In a plan view, the temperature sensor structure 63 overlaps with the end dummy trench structure 61A and one to fifteen dummy trench structures 61 extending from the end dummy trench structure 61A. In the examples of Figures 14 and 15, the temperature sensor structure 63 overlaps with two dummy trench structures 61 in a plan view. Specifically, in a plan view, the temperature sensor structure 63 overlaps with the end dummy trench structure 61A and an adjacent dummy trench structure 61.

[0319] These dummy trenches 101 are covered by a field insulating film 106 included in the temperature sensor element 64. In this configuration, the interlayer insulating film 47 corresponding to these dummy trenches 101 is integrated with the field insulating film 106.

[0320] In the example shown in Figure 15, the entire dummy well region 105 of the terminal dummy trench structure 61A and the adjacent dummy trench structure 61 is covered by the first outer well region 42, and a portion of the dummy well region 105 of the second dummy trench structure 61 from the terminal dummy trench structure 61A is covered by the first outer well region 42.

[0321] In other words, in the second embodiment, the temperature sensor structure 63 overlaps with the first outer well region 42. To put it another way, in a plan view, the temperature sensor structure 63 overlaps with both the dummy formation region 62 and the first outer well region 42. To put it yet another way, in a plan view, the temperature sensor structure 63 overlaps with both the dummy formation region 62 and the outer well region 40. In a plan view, the temperature sensor structure 63 does not overlap with the outer body region 60.

[0322] On the other hand, the temperature sensor structure 63 does not overlap with one or more dummy trench structures 61 in a plan view. The temperature sensor structure 63 does not overlap with one to ten dummy trench structures 61 from the innermost side (the side closest to the outer peripheral boundary 19). In the examples of Figures 14 and 15, the temperature sensor structure 63 does not overlap with two dummy trench structures 61 from the innermost side (the side closest to the outer peripheral boundary 19).

[0323] In other words, the number of dummy trench structures 61 that overlap the temperature sensor structure 63 in a plan view (the number of dummy trench structures 61 aligned in the second direction Y) is less than the number of dummy trench structures 61 formed in one dummy formation region 62.

[0324] As described above, in the semiconductor device 1A according to the second embodiment, the temperature sensor structure 63 overlaps with the dummy formation region 62 in a plan view. Therefore, the temperature sensor structure 63 can be incorporated into the semiconductor device 1A without reducing the area of ​​the active region 8. This makes it possible to realize a configuration that incorporates the temperature sensor structure 63 while effectively utilizing the active region 8.

[0325] Furthermore, the second form exhibits effects equivalent to those described in relation to the first form.

[0326] Figure 16 is a plan view of the main part of a semiconductor device 1A according to a third embodiment of the first embodiment of the present disclosure. Figure 16 shows a plan view at the same position as in Figures 5 and 14.

[0327] The third embodiment (the embodiment shown in Figure 16) is similar to the second embodiment (the embodiments shown in Figures 14 and 15) in that the temperature sensor structure 63 overlaps with the dummy formation region 62 in a plan view. The difference between the third embodiment and the second embodiment is that the temperature sensor structure 63 overlaps with the innermost (closest to the active region 8) dummy trench structure 61.

[0328] The temperature sensor structure 63 overlaps in plan view with both the innermost (closest to the active region 8) dummy trench structure 61 and the terminal dummy trench structure 61A. In other words, in plan view, the temperature sensor structure 63 overlaps with all the dummy trench structures 61 contained within a single dummy formation region 62.

[0329] Figure 17 is a plan view of the main part of the semiconductor device 1B according to the second embodiment of this disclosure. Figure 17 shows a plan view at the same position as in Figure 5. Figure 18 is a cross-sectional view of the main part of the semiconductor device 1B according to the second embodiment. Figure 18 shows a cross-section at the same position as in Figure 10. In Figures 17 and 18, components that are the same as those already described are denoted by the same reference numerals and their descriptions are omitted.

[0330] The second embodiment (fourth embodiment example; embodiment example in Figures 17 and 18) is similar to the second embodiment example of the first embodiment (embodiment example in Figures 14 and 15) in that the temperature sensor structure 63 overlaps with the dummy formation region 62 in a plan view. The difference between the second embodiment and the second embodiment example of the first embodiment is that the temperature sensor structure 63 does not overlap with the first outer well region 42 in a plan view. In this embodiment, the temperature sensor structure 63 overlaps with the outer body region 60 in a plan view.

[0331] In the second embodiment, the first outer well region 42 is formed with a gap extending outward from the outer peripheral boundary 19 (Figure 18). The first outer well region 42 is formed with a gap extending outward from the gate wiring 58. In a plan view, the temperature sensor structure 63 does not overlap with the first outer well region 42.

[0332] In the second embodiment, the multiple dummy trench structures 61 formed in the dummy formation region 62 penetrate the outer body region 60 and reach the high-concentration region 92. The multiple dummy trench structures 61 are not formed in the first outer well region 42.

[0333] The terminal dummy trench structure 61A penetrates the outer body region 60 and reaches the high-concentration region 92. The terminal dummy trench structure 61A is not formed in the first outer well region 42. The dummy well region 105 of the terminal dummy trench structure 61A is not covered by the first outer well region 42.

[0334] The dummy formation region 62 does not overlap with the first outer well region 42. The dummy formation region 62 is provided with a gap inward relative to the first outer well region 42.

[0335] The semiconductor device 1B according to the second embodiment provides the same effects and benefits as those described in relation to the first embodiment (first example).

[0336] Figure 19 is a plan view of the main part of semiconductor device 1B according to the fifth embodiment. Figure 19 shows a plan view at the same position as in Figures 5 and 17.

[0337] The fifth embodiment (the embodiment shown in Figure 19) is similar to the fourth embodiment of the second embodiment (the embodiments shown in Figures 17 and 18) in that the temperature sensor structure 63 overlaps with the dummy formation region 62 in a plan view. The difference between the fifth embodiment and the fourth embodiment is that the temperature sensor structure 63 overlaps with the innermost (closest to the active region 8) dummy trench structure 61.

[0338] The temperature sensor structure 63 overlaps in plan view with both the innermost (closest to the active region 8) dummy trench structure 61 and the terminal dummy trench structure 61A. In other words, in plan view, the temperature sensor structure 63 overlaps with all the dummy trench structures 61 contained within a single dummy formation region 62.

[0339] Figure 20 is a plan view showing a semiconductor device 1C according to a third embodiment of the present disclosure. Figure 21 is a plan view showing the layout of the main surface electrode film 54 in the semiconductor device 1C. Figure 22 is a plan view showing an example of the layout of the first main surface 3 of the chip 2 in the semiconductor device 1C. Figure 23 is an enlarged view of the portion enclosed by the dashed line XXIII in Figure 22. Figure 24 is a cross-sectional view along the line XXIV-XXIV shown in Figure 23. In Figures 20 to 24, components that are the same as those already described are denoted by the same reference numerals and their descriptions are omitted.

[0340] The third embodiment (examples shown in Figures 20 to 24) differs from the first embodiment (examples shown in Figures 1 to 13C) in that the temperature sensor structure 63 is formed in a region opposite to the gate pad electrode 57 in a plan view, with the active region 8 (source pad electrode 51) in between. More specifically, the temperature sensor structure 63 is formed in a region sandwiched in the first direction X by the tip portions 58c and 58d (Figure 21) of a pair of finger wirings 58a and 58b in a plan view.

[0341] Referring to Figure 21, the third pad portion 51c of the source pad electrode 51 has a notch (recess) 51e that recedes from the edge facing the second side surface 5B toward the first side surface 5A. In plan view, the first extraction electrode 65 and the second extraction electrode 66 are arranged inside the notch 51e. The first extraction electrode 65 and the second extraction electrode 66 are surrounded by the third pad portion 51c of the source pad electrode 51. The first extraction electrode 65 and the second extraction electrode 66 are aligned in the second direction Y. The first extraction electrode 65 and the second extraction electrode 66 may also be aligned in the first direction X.

[0342] Referring to Figures 23 and 24, the temperature sensor structure 63 is formed on the first outer well region 42. In this configuration, the temperature sensor structure 63 overlaps the p-shaped first outer well region 42 in a plan view. The temperature sensor structure 63 does not overlap the outer body region 60 in a plan view.

[0343] The first outer well region 42 is exposed to the first main surface 3 in the outer peripheral region 9. The field insulating film 106 included in the temperature sensor structure 63 is in contact with the first outer well region 42 on the first main surface 3 of the outer peripheral region 9. The entire area of ​​the field insulating film 106 is in contact with the first outer well region 42.

[0344] Referring to Figure 24, the temperature sensor structure 63 (temperature sensor element 64) is formed with a gap in the second direction Y from the periphery 51d of the source pad electrode 51. The temperature sensor structure 63 (temperature sensor element 64) faces the periphery 51d of the source pad electrode 51 in the second direction Y, with a portion of the surface insulating film 70 in between. In other words, in a plan view, the temperature sensor structure 63 (temperature sensor element 64) is formed with a gap outward from the periphery 51d of the source pad electrode 51.

[0345] The semiconductor device 1C according to the third embodiment provides the same effects and benefits as those described in relation to the first embodiment (first example).

[0346] Figure 25 is a plan view of the main part of a semiconductor device 1C according to a seventh embodiment of the third embodiment of the present disclosure. Figure 25 shows a plan view at the same position as Figure 23. Figure 26 is a cross-sectional view along the line XXVI-XXVI shown in Figure 25.

[0347] The seventh embodiment (the embodiment shown in Figures 25 and 26) differs from the sixth embodiment of the third embodiment (the embodiment shown in Figures 20 to 24) in that the temperature sensor structure 63 overlaps with the dummy formation region 62 in a plan view.

[0348] In a plan view, the temperature sensor structure 63 overlaps with one or more dummy trench structures 61, which are included in a plurality of dummy trench structures 61.

[0349] In a plan view, the temperature sensor structure 63 overlaps with the end dummy trench structure 61A and one to fifteen dummy trench structures 61 extending from the end dummy trench structure 61A. In the examples of Figures 25 and 26, the temperature sensor structure 63 overlaps with two dummy trench structures 61 in a plan view. Specifically, in a plan view, the temperature sensor structure 63 overlaps with the end dummy trench structure 61A and an adjacent dummy trench structure 61.

[0350] These dummy trenches 101 are covered by a field insulating film 106 included in the temperature sensor element 64. Specifically, the interlayer insulating film 47 corresponding to these dummy trenches 101 is integrated with the field insulating film 106.

[0351] In the example shown in Figure 26, the entire dummy well region 105 of the terminal dummy trench structure 61A and the adjacent dummy trench structure 61 is covered by the first outer well region 42, and a portion of the dummy well region 105 of the second dummy trench structure 61 from the terminal dummy trench structure 61A is covered by the first outer well region 42.

[0352] In other words, in the seventh embodiment, the temperature sensor structure 63 overlaps with the first outer well region 42. To put it another way, in a plan view, the temperature sensor structure 63 overlaps with both the dummy formation region 62 and the first outer well region 42. To put it yet another way, in a plan view, the temperature sensor structure 63 overlaps with both the dummy formation region 62 and the outer well region 40. In a plan view, the temperature sensor structure 63 does not overlap with the outer body region 60.

[0353] On the other hand, the temperature sensor structure 63 does not overlap with one or more dummy trench structures 61 in a plan view. The temperature sensor structure 63 does not overlap with one to ten dummy trench structures 61 from the innermost side (the side closest to the outer peripheral boundary 19). In the examples of Figures 25 and 26, the temperature sensor structure 63 does not overlap with two dummy trench structures 61 from the innermost side (the side closest to the outer peripheral boundary 19).

[0354] In other words, the number of dummy trench structures 61 that overlap the temperature sensor structure 63 in a plan view (the number of dummy trench structures 61 aligned in the second direction Y) is less than the number of dummy trench structures 61 formed in one dummy formation region 62.

[0355] As described above, in the semiconductor device 1C according to the seventh embodiment, the temperature sensor structure 63 overlaps with the dummy formation region 62 in a plan view. Therefore, the temperature sensor structure 63 can be incorporated into the semiconductor device 1C without reducing the area of ​​the active region 8. This makes it possible to realize a configuration that incorporates the temperature sensor structure 63 while effectively utilizing the active region 8.

[0356] Furthermore, the seventh embodiment exhibits effects equivalent to those described in relation to the first embodiment of the first embodiment.

[0357] Figure 27 is a plan view of the main part of a semiconductor device 1C according to the eighth embodiment of the third embodiment of the present disclosure. Figure 27 shows a plan view at the same position as in Figures 23 and 25.

[0358] The eighth embodiment (the embodiment shown in Figure 27) is similar to the seventh embodiment (the embodiments shown in Figures 25 and 26) in that the temperature sensor structure 63 overlaps with the dummy formation region 62 in a plan view. The difference between the eighth embodiment and the seventh embodiment is that the temperature sensor structure 63 overlaps with the innermost (closest to the active region 8) dummy trench structure 61.

[0359] The temperature sensor structure 63 overlaps in plan view with both the innermost (closest to the active region 8) dummy trench structure 61 and the terminal dummy trench structure 61A. In other words, in plan view, the temperature sensor structure 63 overlaps with all the dummy trench structures 61 contained within a single dummy formation region 62.

[0360] Figure 28 is a plan view of the main part of a semiconductor device 1C according to the ninth embodiment of the third embodiment of the present disclosure. Figure 29 is a plan view of the main part of a semiconductor device 1C according to the tenth embodiment of the third embodiment of the present disclosure. In Figures 28 and 29, the temperature sensor structure 63 overlaps with the second outer well region 43.

[0361] As shown in Figure 28, the temperature sensor structure 63 may overlap both the first outer well region 42 and the second outer well region 43 in a plan view. As shown in Figure 29, the temperature sensor structure 63 may overlap multiple second outer well regions 43 in a plan view.

[0362] Figure 30 is a plan view of the main part of the semiconductor device 1D according to the fourth embodiment of the present disclosure. Figure 30 shows a plan view at the same position as in Figure 23. Figure 31 is a cross-sectional view along the line XXXI-XXXI shown in Figure 30. In Figures 30 and 31, components that are the same as those already described are denoted by the same reference numerals and their descriptions are omitted.

[0363] The fourth embodiment (fourth embodiment example; embodiment example in Figures 30 and 31) is similar to the seventh embodiment example of the third embodiment (embodiment example in Figures 25 and 26) in that the temperature sensor structure 63 overlaps with the dummy formation region 62 in a plan view. The difference between the fourth embodiment and the seventh embodiment example of the third embodiment is that the temperature sensor structure 63 does not overlap with the first outer well region 42 in a plan view. In this embodiment, the temperature sensor structure 63 overlaps with the outer body region 60 in a plan view.

[0364] In the fourth embodiment, the first outer well region 42 is formed with a gap extending outward from the outer peripheral boundary 19 (Figure 31). The first outer well region 42 is formed with a gap extending outward from the gate wiring 58. In a plan view, the temperature sensor structure 63 does not overlap with the first outer well region 42.

[0365] In the fourth embodiment, the multiple dummy trench structures 61 formed in the dummy formation region 62 penetrate the outer body region 60 and reach the high-concentration region 92. The multiple dummy trench structures 61 are not formed in the first outer well region 42.

[0366] The terminal dummy trench structure 61A penetrates the outer body region 60 and reaches the high-concentration region 92. The terminal dummy trench structure 61A is not formed in the first outer well region 42. The dummy well region 105 of the terminal dummy trench structure 61A is not covered by the first outer well region 42.

[0367] The dummy formation region 62 does not overlap with the first outer well region 42. The dummy formation region 62 is provided with a gap inward relative to the first outer well region 42.

[0368] The semiconductor device 1D according to the fourth embodiment provides the same effects and benefits as those described in relation to the first embodiment (first example).

[0369] Figure 32 is a plan view of the main part of the semiconductor device 1D according to the twelfth embodiment. Figure 32 shows a plan view at the same position as in Figures 23 and 30.

[0370] The twelfth embodiment (the embodiment shown in Figure 32) is similar to the eleventh embodiment of the fourth embodiment (the embodiments shown in Figures 30 and 31) in that the temperature sensor structure 63 overlaps with the dummy formation region 62 in a plan view. The difference between the twelfth embodiment and the eleventh embodiment is that the temperature sensor structure 63 overlaps with the innermost (closest to the active region 8) dummy trench structure 61.

[0371] The temperature sensor structure 63 overlaps in plan view with both the innermost (closest to the active region 8) dummy trench structure 61 and the terminal dummy trench structure 61A. In other words, in plan view, the temperature sensor structure 63 overlaps with all the dummy trench structures 61 contained within a single dummy formation region 62.

[0372] Figure 33 is a cross-sectional view of a main part of the semiconductor device 1E according to the fifth embodiment of this disclosure. Figure 33 shows a cross-section at the same position as in Figure 10.

[0373] Referring to Figure 33, semiconductor device 1E has a configuration in which the configuration of the multiple gate structures related to semiconductor devices 1A to 1D has been changed. More specifically, semiconductor device 1E includes a planar gate structure 200 instead of a trench gate structure 15 as a gate structure.

[0374] Prior to describing the planar gate structure 200, the semiconductor device 1E includes a plurality of p-type body regions 201 formed on the surface layer of the first main surface 3 in the active region 8. The plurality of body regions 201 are arranged with spacing in the first direction X and are each formed in a strip shape extending in the second direction Y. In other words, the plurality of body regions 201 are arranged in a stripe shape extending in the second direction Y.

[0375] Multiple body regions 201 are formed at intervals from the bottom of the second semiconductor region 7 toward the first main surface 3, and face the first semiconductor region 6 with a portion of the second semiconductor region 7 in between. Preferably, multiple body regions 201 are formed at intervals from the middle of the second semiconductor region 7 toward the first main surface 3. Multiple body regions 201 are exposed from the first main surface 3. In this embodiment, multiple body regions 201 are formed at intervals from the bottom of the high-density region 92 toward the first main surface 3, and face the base region 91 with a portion of the high-density region 92 in between.

[0376] Multiple body regions 201 are formed to be shallower than the outer well region 40. Multiple body regions 201 are formed to be shallower than the first outer well region 42.

[0377] The semiconductor device 1E includes n-type source regions 202 formed on the surface of each of the multiple body regions 201. The source regions 202 have a higher n-type impurity concentration than the n-type impurity concentration of the first semiconductor region 6. A source potential is applied to the source regions 202.

[0378] The semiconductor device 1E includes a plurality of p-type channel regions 203 formed on the surface layer of the first main surface 3. The plurality of channel regions 203 are each partitioned in the surface layer of the plurality of body regions 201 in the region between the ends of the plurality of body regions 201 and the periphery of the source region 202. In this embodiment, the plurality of channel regions 203 are arranged with spacing in the second direction Y and are each formed in a strip shape extending in the first direction X. In other words, the plurality of channel regions 203 are arranged in a stripe shape extending in the first direction X.

[0379] Each planar gate structure 200 is positioned on at least one channel region 203. In this embodiment, each planar gate structure 200 is positioned across the region between two adjacent body regions 201 and straddles the two body regions 201, covering a plurality of channel regions 203. Specifically, each planar gate structure 200 is positioned across the source region 202 on one body region 201 and the source region 202 on the other body region 201, covering a portion of the source region 202 and the channel regions 203.

[0380] The planar gate structure 200 has a multilayer structure including an insulating film 204 and a gate electrode 205. The insulating film 204 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the insulating film 204 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the insulating film 204 includes a silicon oxide film made of the oxide of the chip 2.

[0381] The insulating film 204 coats the first main surface 3 in a film-like manner and is positioned on at least one channel region 203. In this embodiment, the insulating film 204 is positioned to span two adjacent body regions 201 and covers multiple channel regions 203.

[0382] Specifically, the insulating film 204 is arranged to span the source region 202 on one body region 201 side and the source region 202 on the other body region 201 side, covering a portion of the source region 202 and the channel region 203.

[0383] The gate electrode 205 is positioned on the insulating film 204 and faces at least one channel region 203 across the insulating film 204. A gate potential is applied to the gate electrode 205 as a control potential. The gate electrode 205 controls the inversion and non-inversion of at least one channel region 203 in response to the gate potential.

[0384] The gate electrode 205 comprises a conductive semiconductor polycrystal. The gate electrode 205 may contain either or both of p-type conductive polysilicon and n-type conductive polysilicon. The conductivity type of the gate electrode 205 is adjusted according to the gate threshold voltage to be achieved. The gate electrode 205 may be referred to as a "polysilicon gate," "polygate," etc.

[0385] The semiconductor device 1E includes a low-concentration region 206 stacked on a high-concentration region 92. The low-concentration region 206 is part of the second semiconductor region 7. In other words, the second semiconductor region 7 of the semiconductor device 1E includes a stacked structure of a base region 91, a high-concentration region 92, and a low-concentration region 206.

[0386] The low-concentration region 206 is formed on the side of the body region 201 between the high-concentration region 92 and the first main surface 3. The low-concentration region 206 is in contact with the body region 201 and is formed in a layered manner extending along the first main surface 3. The body region 201 crosses the boundary between the high-concentration region 92 and the low-concentration region 206 in the thickness direction of the second semiconductor region 7 and is in contact with both sides of the high-concentration region 92 and the low-concentration region 206.

[0387] The n-type impurity concentration in the low-concentration region 206 is preferably lower than the n-type impurity concentration in the high-concentration region 92. The n-type impurity concentration in the low-concentration region 206 may be the same as the n-type impurity concentration in the base region 91. The low-concentration region 206 is 1 × 10⁻⁶ １５ cm －３ The above 5 x 10 １６ cm －３ The following n-type impurity concentrations may be present as peak values. The n-type impurity concentration in the low-concentration region 206 may be approximately constant in the thickness direction. Of course, the n-type impurity concentration in the low-concentration region 206 may have a concentration gradient that gradually increases and / or decreases toward the thickness direction (crystal growth direction) of the chip 2.

[0388] The first outer well region 42 is formed deeper than the multiple body regions 201 along the outer peripheral boundary 19 between the active region 8 and the outer peripheral region 9. The outer well region 40 may be approximately the same depth as the multiple body regions 201.

[0389] More specifically, the body region 201 includes a well side portion 201a extending in the thickness direction of the second semiconductor region 7 and a well bottom portion 201b extending from the well side portion 201a in a direction along the first main surface 3. The outer well region 40 is in contact with the well side portion 201a.

[0390] The semiconductor device 1E includes a temperature sensor structure 63 formed on the first main surface 3 in the outer peripheral region 9 for detecting temperature. The temperature sensor structure 63 includes a temperature sensor element 64. In this embodiment, the temperature sensor structure 63 overlaps with the outer well region 40 in a plan view. More specifically, the temperature sensor structure 63 overlaps with the first outer well region 42 in a plan view. In this embodiment, the entire area of ​​the temperature sensor structure 63 overlaps with the p-shaped first outer well region 42 in a plan view.

[0391] The first outer well region 42 is exposed to the first main surface 3 in the outer peripheral region 9. The field insulating film 106 included in the temperature sensor structure 63 is in contact with the first outer well region 42 on the first main surface 3 of the outer peripheral region 9.

[0392] The semiconductor device 1E provides the same effects and benefits as those described in relation to the semiconductor device 1A according to the first embodiment.

[0393] Semiconductor device 1E is an example of a configuration in which a planar gate structure 200 is used as the gate structure in semiconductor device 1A. The planar gate structure 200 may also be used as the gate structure in semiconductor devices 1B to 1D. In other words, semiconductor device 1E may be combined with semiconductor devices 1B to 1D.

[0394] The embodiments described above (including variations) can be implemented in other forms. For example, in each of the embodiments described above, a chip 2 containing a SiC single crystal was used. However, the chip 2 may also contain a silicon single crystal. Similarly, the first semiconductor region 6 may contain a silicon single crystal. Similarly, the second semiconductor region 7 may contain a silicon single crystal.

[0395] In each of the above-described embodiments, a structure may be adopted in which the conductivity type of the "n-type" semiconductor region is inverted to "p-type," and the conductivity type of the "p-type" semiconductor region is inverted to "n-type." The specific configuration in this case can be obtained by replacing "n-type" with "p-type" and simultaneously replacing "p-type" with "n-type" in the above description and attached drawings.

[0396] In the first to fifth embodiments, a p-type collector region may be formed on the surface layer of the second main surface 4 of the chip 2. In this case, the transistor structure Tr includes an IGBT (Insulated Gate Bipolar Transistor) structure instead of a MISFET structure. The specific configuration in this case is obtained by replacing the "source" of the MISFET structure with the "emitter" of the IGBT structure and the "drain" of the MISFET structure with the "collector" of the IGBT structure, as described above. In this case, the chip 2 may have a single-layer structure made of an n-type semiconductor substrate.

[0397] The following are examples of features extracted from this specification and drawings. The alphanumeric characters in parentheses below represent the corresponding components in each of the embodiments described above, but this is not intended to limit the scope of each Clause to the embodiments. The term "semiconductor device" in the following items may be replaced with "semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "semiconductor rectifier," "MISFET device," "IGBT device," "diode device," etc., as needed.

[0398] [Note 1-1] A semiconductor device (1A, 1B, 1C, 1D, 1E) comprising: a chip (2) having a main surface (3); a first conductivity type semiconductor region (7) formed on the surface layer of the main surface (3); an active region (8) provided on the inner part of the main surface (3); an outer peripheral region (9) provided on the periphery of the main surface (3) and surrounding the active region (8); a device structure (Tr) formed on the active region (8); and a temperature sensor structure (63) formed on the main surface (3) in the outer peripheral region (9) for detecting temperature.

[0399] [Appendix 1-2] The semiconductor device (1A, 1C, 1E) according to Appendix 1-1, further comprising a second conductivity type outer well region (40) formed on the surface layer of the semiconductor region (7) in the outer peripheral region (9), wherein the temperature sensor structure (63) overlaps with the outer well region (40) in a plan view.

[0400] [Appendix 1-3] The semiconductor device (1A, 1C, 1E) according to Appendix 1-2, wherein the outer well region (40) includes a first outer well region (42) formed to extend along the outer peripheral boundary (19) between the active region (8) and the outer peripheral region (9), and the temperature sensor structure (63) overlaps the first outer well region (42) in a plan view.

[0401] [Appendix 1-4] The semiconductor device (1C, 1E) according to Appendix 1-2 or Appendix 1-3, wherein the outer well region (40) is formed at intervals on the surface of the semiconductor region (7) and includes a plurality of annular second outer well regions (43) of a second conductivity type surrounding the active region (8), and the temperature sensor structure (63) overlaps the second outer well region (43).

[0402] [Appendix 1-5] The semiconductor device (1A, 1C, 1E) according to any one of Appendix 1-2 to 1-4, further comprising a trench structure (15) in the active region (8) extending from the main surface (3) toward the semiconductor region (7), wherein the outer well region (40) has a bottom at a depth greater than the bottom of the trench structure (15).

[0403] [Appendix 1-6] The semiconductor device (1A, 1C) according to Appendix 1-5, further comprising a dummy trench structure (61) extending in the outer peripheral region (9) from the main surface (3) toward the semiconductor region (7), wherein the dummy trench structure (61) is formed in the main surface (3), and the temperature sensor structure (63) is formed in a plan view at an external distance from the dummy formation region (62).

[0404] [Appendix 1-7] The semiconductor device (1A, 1B, 1C, 1D) according to Appendix 1-5 or Appendix 1-6, wherein the device structure (Tr) further includes a second conductivity type body region (10) formed on the surface of the semiconductor region (7), a first conductivity type source region (11) formed on the surface of the body region (10), and a plurality of trench gate structures (15) including a plurality of gate trenches (16) arranged in a stripe pattern that penetrate the source region (11) and the body region (10) and reach the semiconductor region (7), a gate insulating film (17) formed on the inner surface of the plurality of gate trenches (16), and gate electrodes (18) embedded in the plurality of gate trenches (16) via the gate insulating film (17), and the plurality of trench gate structures (15) are formed as a plurality of trench structures (15).

[0405] [Appendix 1-8] The semiconductor device (1A, 1B, 1C, 1D, 1E) according to any one of Appendix 1-1 to 1-7, wherein the temperature sensor structure (63) includes a temperature sensor element (64) for detecting temperature and an insulating film (109) formed on the main surface (3) so as to cover the temperature sensor element (64) in the outer peripheral region (9) and insulates the temperature sensor element (64) from at least the main surface (3).

[0406] [Appendix 1-9] The semiconductor device (1A, 1B, 1C, 1D, 1E) according to Appendix 1-8, wherein the temperature sensor element (64) includes a polysilicon layer (110), an anode region (102) formed on the polysilicon layer (110), and a cathode region (103) formed on the polysilicon layer (110).

[0407] [Appendix 1-10] The semiconductor device (1A, 1B, 1C, 1D, 1E) according to Appendix 1-8 or Appendix 1-9, wherein the insulating film (109) includes a field insulating film (106) formed on the main surface (3) in the outer peripheral region (9), and the temperature sensor element (64) is formed on the main surface (3) in the outer peripheral region (9) with the field insulating film (106) in between.

[0408] [Appendix 1-11] The semiconductor device (1A, 1B, 1C, 1D, 1E) according to Appendix 1-10, wherein the insulating film (109) further includes a cover insulating film (107) that covers the upper and side portions of the temperature sensor element (64).

[0409] [Appendix 1-12] The semiconductor device (1A, 1B, 1C, 1D, 1E) according to any one of Appendix 1-1 to 1-6, wherein the device structure (Tr) includes a second conductivity type body region (10) formed on the surface of the semiconductor region (7) and a first conductivity type source region (11) formed on the surface of the body region (10), and further includes an interlayer insulating film (47) formed on the main surface (3) so as to cover the device structure (Tr).

[0410] [Appendix 1-13] The semiconductor device (1A, 1B, 1C, 1D, 1E) according to Appendix 1-12, further comprising a source pad electrode (51) formed on the main surface (3) so as to cover the interlayer insulating film (47) and electrically connected to the source region (11), wherein the temperature sensor structure (63) is formed outside the periphery (51d) of the source pad electrode (51).

[0411] [Appendix 1-14] The semiconductor device (1A, 1B, 1C, 1D, 1E) according to Appendix 1-13, further comprising: a first extraction electrode (65) formed on the source pad electrode (51) at a distance along the main surface (3) and electrically connected to the temperature sensor structure (63); and a second extraction electrode (66) formed on the source pad electrode (51) and the first extraction electrode (65) at a distance along the main surface (3) and electrically connected to the temperature sensor structure (63).

[0412] [Appendix 1-15] The semiconductor device (1A, 1B, 1C, 1D, 1E) described in Appendix 1-14, wherein the first extraction electrode (65) and the second extraction electrode (66) overlap the active region (8) in a plan view.

[0413] [Appendix 1-16] The semiconductor device (1A, 1B, 1C, 1D, 1E) according to Appendix 1-14 or Appendix 1-15, further comprising a surface insulating film (70) that covers the temperature sensor structure (63) and selectively covers the source pad electrode (51), the first extraction electrode (65), and the second extraction electrode (66).

[0414] [Appendix 1-17] The semiconductor device (1A, 1B, 1E) according to any one of Appendix 1-13 to 1-16, further including a source wiring (56) extending over the outer peripheral region (9) along the periphery of the chip (2), wherein the temperature sensor structure (63) is formed inward relative to the source wiring (56).

[0415] [Appendix 1-18] The semiconductor device (1C, 1D, 1E) according to any one of Appendix 1-13 to 1-17, wherein the chip (2) has a rectangular shape in plan view, and further includes a gate pad electrode (57) formed on the interlayer insulating film (47) at the peripheral edge of the main surface (3) of the chip (2), and the temperature sensor structure (63) is formed in a region opposite to the gate pad electrode (57) in plan view, with the source pad electrode (51) in between.

[0416] [Appendix 1-19] A pair of gate wirings (58a, 58b) formed on the interlayer insulating film (47), electrically connected to the gate pad electrode (57), and extending in opposite directions from the gate pad along the periphery of the chip (2), further comprising a pair of gate wirings (58a, 58b) that collectively surround the source pad electrode (51), wherein the temperature sensor structure (63) is formed in a region sandwiched between the tip portions (58c, 58d) of the pair of gate wirings (58a, 58b) in a plan view, as described in Appendix 1-18 (1C, 1D, 1E).

[0417] [Appendix 1-20] The semiconductor device (1A, 1B, 1C, 1D, 1E) described in any one of the appendices 1-1 to 1-19, wherein the chip (2) includes a SiC chip (2).

[0418] [Appendix 1-21] The semiconductor device (1A, 1B, 1C, 1D) according to Appendix 1-3, further comprising: a trench structure (15) in the active region (8) extending from the main surface (3) toward the semiconductor region (7); and a dummy trench structure (61) in the outer peripheral region (9) extending from the main surface (3) toward the semiconductor region (7), wherein the dummy trench structure (61) extends parallel to the trench structure (15); the first outer well region (42) overlaps with a dummy formation region (62) on the main surface (3) where the dummy trench structure (61) is formed; and the temperature sensor structure (63) overlaps with the dummy formation region (62) in a plan view.

[0419] [Appendix 1-22] The semiconductor device (1E) according to any one of Appendix 1-1 to 1-6, wherein the device structure (Tr) includes a plurality of planar gate structures (200) having a plurality of gate electrodes (18) arranged in a stripe pattern on the main surface (3), and a gate insulating film (17) formed between the plurality of gate electrodes (18) and the main surface (3).

[0420] [Note 2-1] A chip (2) having a main surface (3), a first conductivity type semiconductor region (7) formed on the surface layer of the main surface (3), an active region (8) provided on the inner part of the main surface (3), an outer peripheral region (9) provided on the periphery of the main surface (3) and surrounding the active region (8), a device structure (Tr) formed on the active region (8) including a trench structure (15) in the active region (8) extending from the main surface (3) into the semiconductor region (7), a dummy formation region (62) in the outer peripheral region (9) which is a region on the main surface (3) where a dummy trench structure (61) is formed, and a temperature sensor structure (63) formed on the main surface (3) in the outer peripheral region (9) for detecting temperature. The semiconductor device (1A, 1B, 1C, 1D) has a temperature sensor structure (63) that overlaps with the dummy formation region (62) in a plan view.

[0421] [Appendix 2-2] The semiconductor device (1A, 1C) according to Appendix 2-1, further comprising a second conductivity type outer well region (40) formed on the surface layer of the semiconductor region (7) in the outer peripheral region (9), wherein the temperature sensor structure (63) overlaps with both the dummy formation region (62) and the outer well region (40) in a plan view.

[0422] [Note 2-3] The semiconductor device (1A, 1C) according to Note 2-2, wherein the outer well region (40) includes a first outer well region (42) formed to extend along the outer peripheral boundary (19) between the active region (8) and the outer peripheral region (9), and the temperature sensor structure (63) overlaps with both the dummy formation region (62) and the first outer well region (42) in a plan view.

[0423] [Note 2-4] The semiconductor device (1A, 1C) according to Note 2-3, wherein the dummy trench structure (61) is formed in the first outer well region (42).

[0424] [Note 2-5] The semiconductor device (1B, 1D) according to Note 2-2, wherein the outer well region (40) includes a first outer well region (42) formed to extend along the outer peripheral boundary (19) between the active region (8) and the outer peripheral region (9), and the temperature sensor structure (63) does not overlap with the first outer well region (42) in a plan view.

[0425] [Appendix 2-6] The semiconductor device (1B, 1D) according to Appendix 2-5, further comprising a second conductivity type outer body region (60) formed on the surface layer of the semiconductor region (7) in the outer peripheral region (9), wherein the dummy trench structure (61) is formed in the outer body region (60).

[0426] [Appendix 2-7] The semiconductor device (1A, 1B, 1C, 1D) according to any one of Appendix 2-1 to 2-6, wherein the device structure (Tr) further includes a second conductivity type body region (10) formed on the surface of the semiconductor region (7), a first conductivity type source region (11) formed on the surface of the body region (10), and a plurality of trench gate structures (15) including a plurality of gate trenches (16) arranged in a stripe pattern that penetrate the source region (11) and the body region (10) and reach the semiconductor region (7), a gate insulating film (17) formed on the inner surface of the plurality of gate trenches (16), and gate electrodes (18) embedded in the plurality of gate trenches (16) via the gate insulating film (17), and the plurality of trench gate structures (15) are formed as a plurality of trench structures (15).

[0427] [Appendix 2-8] The semiconductor device (1A, 1B, 1C, 1D) according to any one of Appendix 2-1 to 2-7, wherein the temperature sensor structure (63) includes a temperature sensor element (64) for detecting temperature and an insulating film (109) formed on the main surface (3) so as to cover the temperature sensor element (64) in the outer peripheral region (9) and insulates the temperature sensor element (64) from at least the main surface (3).

[0428] [Note 2-9] The semiconductor device (1A, 1B, 1C, 1D) according to Note 2-8, wherein the temperature sensor element (64) includes a polysilicon layer (110), an anode region (102) formed on the polysilicon layer (110), and a cathode region (103) formed on the polysilicon layer (110).

[0429] [Appendix 2-10] The semiconductor device (1A, 1B, 1C, 1D) according to Appendix 2-8 or Appendix 2-9, wherein the insulating film (109) includes a field insulating film (106) formed on the main surface (3) in the outer peripheral region (9), and the temperature sensor element (64) is formed on the main surface (3) in the outer peripheral region (9) with the field insulating film (106) in between.

[0430] [Supplementary Note 2-11] The semiconductor device (1A, 1B, 1C, 1D) according to Supplementary Note 2-10, wherein the insulating film (109) further includes a cover insulating film (107) that covers the upper and side portions of the temperature sensor element (64).

[0431] [Supplementary Note 2-12] The semiconductor device (1A, 1B, 1C, 1D) according to any one of Supplementary Notes 2-1 to 2-6, wherein the device structure (Tr) includes a body region (10) of the second conductivity type formed in the surface layer portion of the semiconductor region (7), and a source region (11) of the first conductivity type formed in the surface layer portion of the body region (10), and further includes an interlayer insulating film (47) formed on the main surface (3) so as to cover the device structure (Tr).

[0432] [Supplementary Note 2-13] The semiconductor device (1A, 1B, 1C, 1D) according to Supplementary Note 2-12, further including a source pad electrode (51) formed on the main surface (3) so as to cover the interlayer insulating film (47) and electrically connected to the source region (11), and wherein the temperature sensor structure (63) is formed outside the peripheral edge (51d) of the source pad electrode (51).

[0433] [Supplementary Note 2-14] The semiconductor device (1A, 1B, 1C, 1D) according to Supplementary Note 2-13, further including a first extraction electrode (65) formed at intervals in a direction along the main surface (3) on the source pad electrode (51) and electrically connected to the temperature sensor structure (63), and a second extraction electrode (66) formed at intervals in a direction along the main surface (3) on the source pad electrode (51) and the first extraction electrode (65) and electrically connected to the temperature sensor structure (63).

[0434] [Supplementary Note 2-15] The semiconductor device (1A, 1B, 1C, 1D) according to Supplementary Note 2-14, wherein the first extraction electrode (65) and the second extraction electrode (66) overlap the active region (8) in a plan view.

[0435] [Appendix 2-16] The semiconductor device (1A, 1B, 1C, 1D) according to Appendix 2-14 or Appendix 2-15, further comprising a surface insulating film (70) that covers the temperature sensor structure (63) and selectively covers the source pad electrode (51), the first extraction electrode (65), and the second extraction electrode (66).

[0436] [Appendix 2-17] The semiconductor device (1A, 1B) according to any one of Appendix 2-13 to 2-16, further including a source wiring (56) extending along the periphery of the chip (2) over the outer peripheral region (9), wherein the temperature sensor structure (63) is formed inward relative to the source wiring (56).

[0437] [Appendix 2-18] The semiconductor device (1A, 1B) according to any one of Appendix 2-13 to 2-17, wherein the chip (2) has a rectangular shape in plan view, and further includes a gate pad electrode (57) formed on the interlayer insulating film (47) at the peripheral edge of the main surface (3) of the chip (2), and the temperature sensor structure (63) is formed in a region opposite to the gate pad electrode (57) in plan view, with the source pad electrode (51) in between.

[0438] [Appendix 2-19] A pair of gate wirings (58a, 58b) formed on the interlayer insulating film (47), electrically connected to the gate pad electrode (57), and extending in opposite directions from the gate pad along the periphery of the chip (2), further comprising a pair of gate wirings (58a, 58b) that collectively surround the source pad electrode (51), wherein the temperature sensor structure (63) is formed in a region sandwiched between the tip portions (58c, 58d) of the pair of gate wirings (58a, 58b) in a plan view, as described in Appendix 1-18 (1C, 1D).

[0439] [Appendix 2-20] The semiconductor device (1A, 1B, 1C, 1D) described in any one of the appendices 1-1 to 1-19, wherein the chip (2) includes a SiC chip (2).

[0440] 1A...Semiconductor device, 1B...Semiconductor device, 1C...Semiconductor device, 1D...Semiconductor device, 1E...Semiconductor device, 2...Chip, 3...First main surface, 4...Second main surface, 5A...First side surface, 5B...Second side surface, 5C...Third side surface, 5D...Fourth side surface, 6...First semiconductor region, 7...Second semiconductor region (semiconductor region), 8...Active region, 9...Peripheral region, 10...Body region, 11...Source region, 15...Trench gate structure (trench structure), 16...Gate trench, 17...Gate insulating film, 18...Gate gate, 19...Peripheral boundary, 23...High-concentration region, 25...Gate well region, 25a...Bulge, 25b ...well bottom, 27...gate contact region, 40...outer well region, 41...outer contact region, 42...first outer well region, 42a...upper end, 42b...lower end, 42c...main body, 42d...first side, 43...second outer well region, 45...main surface insulating film, 47...interlayer insulating film, 49...source opening, 50...outer opening, 51...source pad electrode, 51a...first pad portion, 51b...second pad portion, 51c...third pad portion, 51d...periphery, 52...lower electrode film, 53...main electrode film, 54...main surface electrode film, 56...source wiring, 57...gate pad electrode, 58 …gate wiring, 58a…first finger wiring, 58b…second finger wiring, 58c…first tip, 58d…second tip, 59…drain electrode, 60…outer body region, 61…dummy trench structure, 61A…end dummy trench structure, 62…dummy formation region, 63…temperature sensor structure, 64…temperature sensor element, 65…first extraction electrode, 66…second extraction electrode, 67…first connection wiring, 68…second connection wiring, 70…surface insulating film, 71…gate pad, 72…gate pad opening, 73…first source pad, 74…first source pad opening, 75…second source Spud, 76...Second source pad opening, 77...Third source pad, 78...Third source pad opening, 79...First extraction pad, 80...First extraction opening, 81...Second extraction pad, 82...Second extraction opening, 86...Increase intensity section, 87...Peak section, 88...Sudden decrease section, 91...Base region, 92...High concentration region, 95...Gradual increase section, 96...Peak section, 97...Slow decrease section, 98...Gradual decrease section, 101...Dummy trench, 102...Dummy insulating film, 103...Dummy electrode, 105...Dummy well region, 105a...Dummy bulge section, 105b...Dummy well bottom, 106...Field insulating film,107...Cover insulating film, 108...Sensor insulating film, 108a...First sensor insulating film, 108b...Second sensor insulating film, 109...Insulating film, 110...Polysilicon layer, 110a...First surface, 110b...Second surface, 111...pn junction, 112...Anode region, 113...Cathode region, 114...Anode opening, 115...Cathode opening, 116...Anode wiring, 117...Cathode wiring, 123...High-density region, 200...Planar gate structure, 201...Body region, 20 1a... Well side, 201b... Well bottom, 202... Source region, 203... Channel region, 204... Insulating film, 205... Gate electrode, 206... Low concentration region, 421... Upper part, 422... Lower part, 423... Boundary, C... Corner, C1... Corner, D1... Depth, D2... Depth, P1... Peak value, P2... Peak value, S1... Space, T1... Thickness, T2... Thickness, T3... Thickness, Tr... Transistor structure (device structure), X... First direction, Y... Second direction, Z... Vertical direction

Claims

1. A semiconductor device comprising: a chip having a main surface; a semiconductor region of a first conductivity type formed on the surface layer of the main surface; an active region provided on the inner part of the main surface; an outer peripheral region provided on the periphery of the main surface and surrounding the active region; a device structure formed in the active region; and a temperature sensor structure formed on the main surface in the outer peripheral region for detecting temperature.

2. The semiconductor device according to claim 1, further comprising a second conductivity type outer well region formed on the surface layer of the semiconductor region in the outer peripheral region, wherein the temperature sensor structure overlaps the outer well region in a plan view.

3. The semiconductor device according to claim 2, wherein the outer well region includes a first outer well region formed to extend along the outer peripheral boundary between the active region and the outer peripheral region, and the temperature sensor structure overlaps the first outer well region in a plan view.

4. The semiconductor device according to claim 2 or 3, wherein the outer well region is formed at intervals in the surface layer of the semiconductor region and includes a plurality of annular second outer well regions of a second conductivity type surrounding the active region, and the temperature sensor structure overlaps the second outer well region.

5. The semiconductor device according to any one of claims 2 to 4, further comprising a trench structure in the active region extending from the main surface toward the semiconductor region, wherein the outer well region has a bottom at a depth greater than the bottom of the trench structure.

6. The semiconductor device according to claim 5, further comprising a dummy trench structure extending in the outer peripheral region from the main surface toward the semiconductor region, wherein the outer peripheral region includes a dummy forming region on the main surface in which the dummy trench structure is formed, and the temperature sensor structure is formed in a plan view at an outward spacing from the dummy forming region.

7. The semiconductor device according to claim 5 or 6, wherein the device structure further includes a body region of a second conductivity type formed on the surface of the semiconductor region, a source region of a first conductivity type formed on the surface of the body region, and a plurality of trench gate structures including a plurality of gate trenches arranged in a stripe pattern that penetrate the source region and the body region and reach the semiconductor region, a gate insulating film formed on the inner surface of the plurality of gate trenches, and gate electrodes embedded in the plurality of gate trenches via the gate insulating film, the plurality of trench gate structures being formed as a plurality of trench structures.

8. The semiconductor device according to any one of claims 1 to 7, wherein the temperature sensor structure includes a temperature sensor element for detecting temperature and an insulating film formed on the main surface so as to cover the temperature sensor element in the outer peripheral region and insulating the temperature sensor element from at least the main surface.

9. The semiconductor device according to claim 8, wherein the temperature sensor element includes a polysilicon layer, an anode region formed on the polysilicon layer, and a cathode region formed on the polysilicon layer.

10. The semiconductor device according to claim 8 or 9, wherein the insulating film includes a field insulating film formed on the main surface in the peripheral region, and the temperature sensor element is formed on the main surface in the peripheral region, sandwiching the field insulating film.

11. The semiconductor device according to claim 10, wherein the insulating film further comprises a cover insulating film that covers the upper and side portions of the temperature sensor element.

12. The semiconductor device according to any one of claims 1 to 6, wherein the device structure includes a body region of a second conductivity type formed on the surface of the semiconductor region and a source region of a first conductivity type formed on the surface of the body region, and further includes an interlayer insulating film formed on the main surface so as to cover the device structure.

13. The semiconductor device according to claim 12, further comprising a source pad electrode formed on the main surface so as to cover the interlayer insulating film and electrically connected to the source region, wherein the temperature sensor structure is formed outward with respect to the periphery of the source pad electrode.

14. The semiconductor device according to claim 13, further comprising: a first extraction electrode formed on the source pad electrode at a distance from the main surface and to which a first connecting wire extending from the temperature sensor structure is connected; and a second extraction electrode formed on the source pad electrode and the first extraction electrode at a distance from the main surface and to which a second connecting wire extending from the temperature sensor structure is connected.

15. The semiconductor device according to claim 14, wherein the first extraction electrode and the second extraction electrode overlap the active region in a plan view.

16. The semiconductor device according to claim 14 or 15, further comprising a surface insulating film that covers the temperature sensor structure and selectively covers the source pad electrode, the first extraction electrode, and the second extraction electrode.

17. The semiconductor device according to any one of claims 13 to 16, further comprising a source wiring extending over the outer peripheral region along the periphery of the chip, wherein the temperature sensor structure is formed inward with respect to the source wiring.

18. The semiconductor device according to any one of claims 13 to 17, wherein the chip has a rectangular shape in plan view, and further includes a gate pad electrode formed on the interlayer insulating film at the peripheral edge of the main surface of the chip, and the temperature sensor structure is formed in a region opposite to the gate pad electrode in plan view, with the source pad electrode in between.

19. The semiconductor device according to claim 18, further comprising a pair of gate wirings formed on the interlayer insulating film, electrically connected to the gate pad electrode, and extending in opposite directions from the gate pad electrode along the periphery of the chip, the pair of gate wirings as a whole surrounding the source pad electrode, wherein the temperature sensor structure is formed in a region sandwiched between the tips of the pair of gate wirings in a plan view.

20. The semiconductor device according to any one of claims 1 to 19, wherein the chip includes a SiC chip.

Images