Circuit board and semiconductor package

Abstract

This circuit board comprises: a core layer; a first build-up layer disposed on one surface of the core layer and including at least one insulating layer; and a second build-up layer disposed on the other surface of the core layer and including at least one insulating layer, wherein the core layer includes a first core layer, a second core layer disposed on one surface of the first core layer, and a third core layer disposed on the other surface of the first core layer, and the material of fibers constituting the first core layer is different from that of fibers constituting the second core layer or the third core layer.

Description

Circuit boards and semiconductor packages

[0001] The present embodiment relates to a circuit board and a semiconductor package.

[0002]

[0003] Recently, technologies related to electronic products, such as AI and servers, are progressing toward multifunctionality and high speed, and to respond to this trend, semiconductor chip manufacturing technology is also developing rapidly.

[0004] In particular, as the density of transistors and wiring within semiconductor chips increases, the number of I / O terminals on the chips is growing. To meet this trend, not only are the wiring densities, lengths, and widths of circuit boards becoming finer, but there is also a trend toward high-layer, large-area designs.

[0005] Furthermore, from the perspective of miniaturizing finished electronic products, the thickness of the applied circuit boards is also decreasing, and technologies related to multilayer circuit boards, which configure more circuit layers within a circuit board of the same thickness, are being actively researched. In addition, as the pitch of semiconductor chips narrows and the size of chips increases, chiplet technology for separating semiconductor chips by function is being researched. Moreover, technologies for connecting separated chiplets on circuit boards are being actively researched. Furthermore, by connecting semiconductor chips with different functions on circuit boards, technologies regarding the connection relationship between circuit boards and semiconductor chips are being actively researched, such as the circuit board connecting semiconductor chips to each other, which was previously considered only from the perspective of conventional semiconductor packaging.

[0006] A circuit board is a device in which circuit line patterns are arranged using a conductive material, such as copper, on an electrically insulating substrate; it is a general term for the package board immediately before mounting electronic components. To densely mount many different types of electronic components on a flat surface, the mounting positions of each component are determined, and circuit patterns connecting the components are printed and fixed onto the surface.

[0007] A circuit board is formed by printing circuit line patterns using a conductive material, such as copper, onto an electrically insulating substrate; it is a general term for a board immediately before electronic components are mounted. To densely mount many different types of electronic components on a flat surface, the mounting positions of each component are determined, and circuit patterns connecting the components are printed on the surface of the flat plate to secure them.

[0008] The circuit board includes a core layer and a build-up layer disposed on the surface of the core layer. The core layer and the build-up layer may each include one or more insulating layers, and each insulating layer may have a wiring layer and via electrodes that connect different wiring layers in a vertical direction disposed therein.

[0009] According to the above structure, warpage may occur within the circuit board due to differences in physical properties, such as the coefficient of thermal expansion between the material constituting the core layer and the material constituting the build-up layer.

[0010]

[0011] The present invention provides a circuit board and a semiconductor package that enable high multilayer and large area, and improve reliability by minimizing warpage.

[0012]

[0013] A circuit board according to the present embodiment comprises a core layer; a first build-up layer disposed on one side of the core layer and including at least one insulating layer; and a second build-up layer disposed on the other side of the core layer and including at least one insulating layer, wherein the core layer comprises a first core layer, a second core layer disposed on one side of the first core layer, and a third core layer disposed on the other side of the first core layer, and the material of the fiber constituting the first core layer is different from the material of the fiber constituting the second core layer or the third core layer.

[0014] The first core layer comprises a resin and fibers disposed within the resin, and the fibers of the first core layer may be quartz fibers.

[0015] The second core layer and the third core layer may each be a prepreg (PPG) comprising a resin and glass fibers disposed within the resin.

[0016] The material of the insulating layer constituting the first build-up layer and the second build-up layer may be different from the material of the core layer.

[0017] The insulating layer constituting the first build-up layer and the second build-up layer may be ABF (Ajinomoto Build-up Film).

[0018] The second core layer and the third core layer each include a second layer, and the vertical thickness of the first core layer may be greater than the vertical thickness of the second layer.

[0019] The vertical thickness of the first core layer may be thinner than the vertical thickness of the second core layer or the third core layer.

[0020] The core layer includes a via hole penetrating from one side to the other side, and the quartz fiber and the glass fiber may each have a region separated from the region where the via hole is formed.

[0021] The above quartz fibers may be arranged to form multiple layers in a vertical direction within the resin constituting the first core layer.

[0022] A semiconductor package according to the present embodiment comprises: a core layer; a first build-up layer disposed on one side of the core layer and including at least one insulating layer; a second build-up layer disposed on the other side of the core layer and including at least one insulating layer; and a semiconductor chip disposed on the surface of the first build-up layer or the second build-up layer, wherein the core layer comprises a first core layer, a second core layer disposed on one side of the first core layer, and a third core layer disposed on the other side of the first core layer, and the material of the fiber constituting the first core layer is different from the material of the fiber constituting the second core layer or the third core layer.

[0023]

[0024] Through this embodiment, the core layer is composed of multiple fibers of different materials, which has the advantage of minimizing the warping phenomenon of the circuit board by considering productivity and lowering the coefficient of thermal expansion.

[0025]

[0026] FIG. 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention.

[0027] FIG. 2 is a drawing reflecting the specific structure of the core layer in FIG. 1.

[0028] FIG. 3 is a drawing for explaining the structure of a core layer within a circuit board according to an embodiment of the present invention.

[0029] FIG. 4 is a cross-sectional view of a circuit board according to an embodiment of the present invention.

[0030] FIG. 5 is a table comparing the degree of bending of a circuit board according to an embodiment of the present invention and a circuit board according to a comparative example according to temperature.

[0031] FIG. 6 is a drawing illustrating a semiconductor package according to an embodiment of the present invention.

[0032] FIG. 7 is a drawing reflecting the specific structure of the core layer in FIG. 6.

[0033]

[0034] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

[0035] However, the technical concept of the present invention is not limited to some of the described embodiments but can be implemented in various different forms, and within the scope of the technical concept of the present invention, one or more of the components among the embodiments may be selectively combined or substituted.

[0036] In addition, terms used in the embodiments of the present invention (including technical and scientific terms) may be interpreted in a sense that is generally understood by those skilled in the art to which the present invention belongs, unless explicitly and specifically defined otherwise. Terms that are commonly used, such as terms defined in advance, may be interpreted in consideration of their meaning in the context of the relevant technology.

[0037] Additionally, the terms used in the embodiments of the present invention are for describing the embodiments and are not intended to limit the present invention. In this specification, the singular form may include the plural form unless specifically stated otherwise in the text, and when described as “at least one of A and B and C (or more than one),” it may include one or more of all combinations that can be combined with A, B, and C.

[0038] In addition, terms such as first, second, A, B, (a), (b), etc. may be used when describing the components of the embodiments of the present invention.

[0039] These terms are intended merely to distinguish a component from other components and are not limited by the nature, order, sequence, etc., of the said component.

[0040] And, where it is stated that a component is 'connected', 'combined', or 'joined' to another component, this may include not only cases where the component is directly connected, combined, or joined to the other component, but also cases where it is 'connected', 'combined', or 'joined' due to another component located between the component and the other component.

[0041] Furthermore, when described as being formed or placed "above or below" each component, "above" or "below" includes not only cases where two components are in direct contact with each other, but also cases where one or more other components are formed or placed between the two components. Additionally, when expressed as "above or below," it may include the meaning of a downward direction as well as an upward direction relative to a single component.

[0042] In addition, the expression that configuration A is positioned between configuration B and configuration C must include the meaning that configuration A is positioned such that at least a portion of it overlaps with configurations B and C in the horizontal and / or vertical directions.

[0043] Expressions referring to directions include horizontal and vertical directions, and the horizontal direction includes a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction. These are referred to as the first horizontal direction (X-axis), the second horizontal direction (Y-axis), and the vertical direction (Z-axis) according to the Cartesian coordinate system, and the meaning of being superimposed along the horizontal direction must include the meaning of being superimposed along the first horizontal direction and / or superimposed along the second horizontal direction.

[0044] Furthermore, the statement that Configuration A is exposed from Configuration B should be understood as meaning that Configuration A is exposed from Configuration B, not that Configuration A is exposed from the entire product. In other words, when Configuration A is stated to be exposed from Configuration B, it should be understood to mean that Configuration A is covered by at least a portion of Configuration C.

[0045] Furthermore, when it is stated that Component A 'contacts' Component B, this may include not only cases where the component 'contacts' the other component directly, but also cases where it 'contacts' due to another component located between the component and the other component. Therefore, if Component A is to be understood only as 'directly contacting' Component B, it is described as 'directly contacting'.

[0046] In addition, when it is stated that configuration A is 'covered' by configuration B, it should be understood that configuration A is covered by configuration B, and that the part intended for the function and purpose to be resolved is covered, and unless there are special circumstances, it should not be understood that the entire configuration A is covered by configuration B.

[0047] FIG. 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention, FIG. 2 is a drawing reflecting the specific structure of the core layer in FIG. 1, FIG. 3 is a drawing for explaining the structure of the core layer within the circuit board according to an embodiment of the present invention, FIG. 4 is a cross-sectional view of a circuit board according to an embodiment of the present invention, and FIG. 5 is a table comparing the degree of bending of a circuit board according to an embodiment of the present invention and a circuit board according to a comparative example by temperature.

[0048] Referring to FIGS. 1 to 5, a circuit board (10) according to an embodiment of the present invention may include a core layer (100), a first build-up layer (200), a second build-up layer (300), a plurality of wiring portions, a plurality of via portions, and a protective layer.

[0049] The circuit board (10) may include a core layer (100). The core layer (100) may be a component forming the basis of the circuit board (10). Based on the vertical direction of the circuit board (10), the core layer (100) may be positioned in the center. The material of the core layer (100) may include at least one selected from the group consisting of glass, resin, plastic, and metal.

[0050] The core layer (100) may include a plurality of insulating layers stacked in a vertical direction. When the core layer (100) is implemented with a plurality of insulating layers, compared to a structure in which the core layer is implemented with a single layer, via holes in each insulating layer constituting the core layer (100) can be formed using a laser as well as a mechanical drill, thereby lowering the manufacturing cost and making it easy to fill the entire interior of the via holes of the core layer (100) with metal. In addition, according to the structure in which a plurality of insulating layers are stacked vertically, the degree of design freedom regarding the formation of pads and via electrodes is increased, and accordingly, there is an advantage that production efficiency can be improved. In addition, the core layer (100) may have a structure in which a plurality of reinforcing members are stacked along the vertical direction within the insulating layer. In addition, at least two of the reinforcing members may be provided with different materials.

[0051] The specific structure of the core layer (100) will be described later.

[0052] For example, to suppress warpage of the circuit board (10), the vertical thickness of the core layer (100) may differ from the vertical thickness of the first build-up layer (200) or the second build-up layer (300) described later. In the circuit board (10) according to the present embodiment, the vertical thickness of the core layer (100) is depicted as being thicker than the vertical thickness of the first build-up layer (200) and / or the vertical thickness of the second build-up layer (200), but it may be freely provided without being limited thereto depending on the area of ​​the circuit board (10) and the design of the circuit.

[0053] The first build-up layer (200) may be disposed on one side of the core layer (100). The first build-up layer (200) may be disposed on the upper surface of the core layer (100). The second build-up layer (300) may be disposed on the other side of the core layer (100). The second build-up layer (300) may be disposed on the lower surface of the core layer (100). The first build-up layer (100) and the second build-up layer (300) may be disposed facing each other with respect to the core layer (100). The first build-up layer (200) and the second build-up layer (300) may each include a plurality of insulating layers disposed in a vertical direction. The number of insulating layers of the first build-up layer (200) and the number of insulating layers of the second build-up layer (300) may be the same. Accordingly, the occurrence of bending of the circuit board (10) based on the core layer (100) can be minimized. However, this is not limited to the number of insulating layers in the first build-up layer (200) and the number of insulating layers in the second build-up layer (300) may differ from each other.

[0054] For example, the first build-up layer (200) may include a first insulating layer (210), a second insulating layer (220), and a third insulating layer (230) arranged in a vertical direction. The first insulating layer (210) may be placed on the upper surface of the core layer (100). The second insulating layer (220) may be placed on the upper surface of the first insulating layer (210). The third insulating layer (230) may be placed on the upper surface of the second insulating layer (220).

[0055] The second build-up layer (300) may include a fourth insulating layer (310), a fifth insulating layer (320), and a sixth insulating layer (330) arranged in a vertical direction. The fourth insulating layer (310) may be placed on the lower surface of the core layer (100). The fifth insulating layer (320) may be placed on the lower surface of the fourth insulating layer (310). The sixth insulating layer (330) may be placed on the lower surface of the fifth insulating layer (320).

[0056] The number of insulating layers constituting the first build-up layer (200) and the number of insulating layers constituting the second build-up layer (300) shown in FIG. 1 are exemplary, and as shown in FIG. 4, the circuit board (10) may have a greater number of insulating layers stacked vertically to form the first build-up layer (200) and the second build-up layer (300), respectively.

[0057] The first to sixth insulating layers (210, 220, 230, 310, 320, 330) may each be any insulating material, such as photocurable and / or thermosetting materials. As thermosetting insulating materials, an insulating material in which inorganic and / or organic fillers are dispersed within a resin, such as ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Corporation, may be used, and a prepreg (PPG) containing glass fibers within a resin may be used. In addition, the resins described above may be, for example, epoxy resin, bismaleimide triazine resin (BT resin), phenolic resin, etc., and the inorganic and / or organic fillers may be provided with materials such as silica or plastic. When an insulating resin is used as a core, it may include a reinforcing material provided with glass fibers or aramid fibers. If the first to sixth insulating layers (210, 220, 230, 310, 320, 330) are photocurable insulators, the first to sixth insulating layers (210, 220, 230, 310, 320, 330) may each be a PID (Photo Imageable Dielectric).

[0058] The vertical thickness of each of the first to sixth insulating layers (210, 220, 230, 310, 320, 330) may be thinner than the vertical thickness of each layer constituting the core layer (100).

[0059] The circuit board (10) may include a protective layer. The protective layer may include a first protective layer (510) disposed on the surface of the first build-up layer (200) and a second protective layer (520) disposed on the surface of the second build-up layer (200). When a semiconductor device is disposed on the surface of the circuit board (10) using a material such as solder, the first protective layer (510) and the second protective layer (520) can perform the function of preventing short circuits between solders due to low wettability with the solder, and can prevent the problem of external contaminants penetrating into the build-up structure and reducing reliability. The first protective layer (510) and the second protective layer (520) may each utilize a photocurable insulating material. Accordingly, the first protective layer (510) and the second protective layer (520) are provided with a solder resist rather than the aforementioned ABF, PPG, BT resin, or PID. However, it is not limited to this, and can be provided with various materials capable of performing low wettability with solder and the resulting short-circuit prevention function between solders as described above.

[0060] The first protective layer (510) may include a hole (512) for exposing the fifth wiring section (415), which will be described later, to the upper side of the circuit board (10). The second protective layer (520) may include a hole (522) for exposing the eighth wiring section (418), which will be described later, to the lower side of the circuit board (10).

[0061] The circuit board (10) may include a circuit pattern for transmitting electrical signals and / or power to an electronic device such as a semiconductor chip. The circuit pattern may include a plurality of wiring portions and a plurality of via portions.

[0062] A plurality of wiring sections may each be disposed on the surface of a plurality of insulating layers. Here, the meaning of being disposed on the surface may also include the meaning that at least a portion of the plurality of wiring sections is embedded within a plurality of insulating layers or protective layers and exposed to the outside from the surface. A wiring section may also be referred to as a metal layer. Furthermore, the surface of the plurality of insulating layers includes a first surface, a second surface, and a side between the first surface and the second surface. Here, the first surface of the insulating layer may be understood as the upper surface, and the second surface of the insulating layer may be understood as the lower surface. The meaning of a wiring section being disposed on the surface is that it is disposed on at least one of the first surface, the second surface, or the side between the plurality of insulating layers. A structure may be formed in which wiring sections are disposed on the first surface and the second surface of some of the insulating layers, respectively, and wiring sections are disposed on only the first surface or the second surface of other parts of the plurality of insulating layers.

[0063] A plurality of wiring sections may include a first wiring section (411) disposed on the upper surface of the core layer (100), a second wiring section (412) disposed on the lower surface of the core layer (100), a third wiring section (413) disposed on the upper surface of the first insulating layer (210), a fourth wiring section (414) disposed on the upper surface of the second insulating layer (220), a fifth wiring section (415) disposed on the upper surface of the third insulating layer (230), a sixth wiring section (416) disposed on the lower surface of the fourth insulating layer (310), a seventh wiring section (417) disposed on the lower surface of the fifth insulating layer (320), and an eighth wiring section (418) disposed on the lower surface of the sixth insulating layer (330). Here, the fifth wiring section (415) and the eighth wiring section (418), which are covered by at least a portion of the protective layer (510, 520), can be named the first pad section and the second pad section, respectively. Additionally, the wiring section may include a pad section for connecting to a via section.

[0064] The via portion may be a metallic material disposed in a via hole formed in each of a plurality of insulating layers to connect a plurality of wiring portions facing each other in a vertical direction. Here, the via hole penetrates at least a portion of each of the plurality of insulating layers in a vertical direction, and a via portion may be disposed within the via hole.

[0065] The via section may include a first via section (421) penetrating at least a portion of the core layer (100), a second via section (422) penetrating at least a portion of the first insulating layer (210), a third via section (423) penetrating at least a portion of the second insulating layer (220), a fourth via section (424) penetrating at least a portion of the third insulating layer (230), a fifth via section (425) penetrating at least a portion of the fourth insulating layer (310), a sixth via section (426) penetrating at least a portion of the fifth insulating layer (320), and a seventh via section (427) penetrating at least a portion of the sixth insulating layer (330).

[0066] The first via section (421) can electrically connect the first wiring section (411) and the second wiring section (412). A filling member (460) may be disposed within the via hole (190) in which the first via section (421) is formed within the core layer (100). The first via section (421) is disposed along the wall of the via hole (190) of the core layer (100), and the filling member (460) is filled into the space formed inside the first via section (421) to bury the via hole (190) of the core layer (100).

[0067] The second via (422) can electrically connect the first wiring section (411) and the third wiring section (413). The third via (423) can electrically connect the third wiring section (413) and the fourth wiring section (414). The fourth via (424) can electrically connect the fourth wiring section (414) and the fifth wiring section (415). The fifth via (425) can electrically connect the second wiring section (412) and the sixth wiring section (416). The sixth via (426) can electrically connect the sixth wiring section (416) and the seventh wiring section (417). The seventh via (477) can electrically connect the seventh wiring section (417) and the eighth wiring section (418).

[0068] The second to fourth via portions (422, 423, 424) disposed in the first build-up layer (200) may each have a shape in which the horizontal width gradually decreases as it faces the core layer (100). The fifth to seventh via portions (425, 426, 427) disposed in the second build-up layer (300) may each have a shape in which the horizontal width gradually decreases as it faces the core layer (100). Accordingly, with respect to the core layer (100), the shapes of the via portions within the first build-up layer (200) and the via portions within the second build-up layer (300) may be formed to be symmetrical to each other.

[0069] Referring to FIGS. 3 and 4, the core layer (100) may include a plurality of layers arranged in a vertical direction. The core layer (100) may include a first core layer (110), a second core layer (130) disposed on the upper surface of the first core layer (110), and a third core layer (140) disposed on the lower surface of the first core layer (110). The second core layer (130) may be disposed between the first core layer (110) and the first build-up layer (200). The third core layer (140) may be disposed between the first core layer (110) and the second build-up layer (300).

[0070] The first core layer (110), the second core layer (130), and the third core layer (140) may each include at least one insulating layer. For example, the first core layer (110) may include one insulating layer, and the second core layer (130) and the third core layer (140) may each include a plurality of insulating layers. The number of insulating layers of the second core layer (130) and the number of insulating layers of the third core layer (140) may be the same.

[0071] For convenience of explanation, the insulating layer constituting the second core layer (130) and the third core layer (140) will be described below as the second layer.

[0072] The vertical thickness of the first core layer (110) may be thinner than the vertical thickness of the second core layer (130) or the vertical thickness of the third core layer (140). However, the vertical thickness of the first core layer (110) may be thicker than the vertical thickness of each insulating layer constituting the second core layer (130) or the third core layer (140). That is, the vertical thickness of the first core layer (110) may be thicker than the vertical thickness of the second layer.

[0073] The first core layer (110), the second core layer (130), and the third core layer (140) may each include a reinforcing material within the resin, i.e., fibers. In this case, the material of the fibers constituting the first core layer (110) and the material of the fibers constituting the second core layer (130) or the third core layer (140) may be different from each other. That is, the material of the fibers of the first core layer (110) and the material of the fibers of the second layer may be different from each other.

[0074] The first core layer (110) may include a resin (112) and quartz fibers (114) disposed within the resin (112). That is, the material of the fibers of the first core layer (110) may be quartz fibers. Quartz material is a material with excellent high-temperature stability, chemical resistance, and corrosion resistance, and is a high-purity quartz glass material. Accordingly, the content of SiO2 in the material constituting the first core layer (110) may be higher than the content of SiO2 in the material constituting the second core layer (130). Accordingly, it may have high thermal and chemical stability.

[0075] As illustrated in FIG. 3, the quartz fiber (114) may be arranged horizontally within the resin (112) of the first core layer (110). The quartz fiber (114) may be a single layer within the resin (112), but is not limited thereto, and may be implemented in multiple layers and arranged vertically within the resin (112).

[0076] The vertical thickness of the quartz fiber (114) may be 10% or more and less than 20% of the vertical thickness of the resin (112) of the first core layer (110). If the vertical thickness of the quartz fiber (114) is less than 10% of the thickness of the resin (112) of the first core layer (110), the effect of preventing bending of the circuit board (10) may be negligible. If the vertical thickness of the quartz fiber (114) exceeds 20% of the thickness of the resin (112) of the first core layer (110), the rigidity of the core layer itself increases, but the manufacturing cost becomes very high relative to the durability, and the efficiency of production processes such as the formation of via holes within the core layer may decrease.

[0077] As shown in FIG. 4, the quartz fiber (114) of the first core layer (110) may have a separated region in the formation area of ​​the via hole (190).

[0078] In FIG. 4, the quartz fiber (114) is illustrated as a single layer within the resin (112) of the first core layer (110), but this is not limited thereto, and the quartz fiber (114) may be provided in multiple layers and arranged along the vertical direction within the resin (112) of the first core layer (110).

[0079] The resin (112) of the first core layer (110) may include one or more of epoxy, BT, and acrylic.

[0080] The second core layer (130) and the third core layer (140) may each be a prepreg (PPG) containing a resin and glass fibers disposed within the resin. That is, the material of the fibers of the second core layer (130) and the third core layer (140) may be glass fibers. The glass fibers may be arranged horizontally within the resin of the second core layer (130) and the third core layer (140). Likewise, the glass fibers may be a single layer within the resin of the second core layer (130) and the third core layer (140), but may be implemented as multiple layers and arranged vertically within the resin.

[0081] The glass fibers in the material constituting the second core layer (130) and the third core layer (140) may include various metal oxides in addition to SiO2. For example, the glass fibers in the material constituting the second core layer (130) and the third core layer (140) may be soda-lime glass with added Na2O or CaO, or borosilicate glass with improved heat resistance through the addition of B2O3. Accordingly, processability for forming circuit layers in the second core layer (130) and the third core layer (140) may be improved.

[0082] As a variation example, the second core layer (130) and the third core layer (140) may each include fibers arranged in multiple layers within the resin. In this case, some of the fibers in the multiple layers may be quartz fibers, and others may be glass fibers. Accordingly, the durability of the second core layer (130) and the third core layer (140) can be improved. When quartz fibers are arranged in the resin within the second core layer (130) and the third core layer (140), the quartz fibers may be arranged closer to the first core layer (110) than the glass fibers.

[0083] The glass fibers of the second core layer (130) and the third core layer (140) may have a horizontally separated region in the formation area of ​​the via hole (190). The separated region of the glass fibers of the second core layer (130) and the third core layer (140) may overlap vertically with the separated region of the quartz fiber (114) of the first core layer (110).

[0084] Quartz fibers have a relatively low coefficient of thermal expansion compared to glass fibers. The coefficient of thermal expansion of glass fibers is 5 to 7 ppm / °C, and the coefficient of thermal expansion of quartz fibers is 0.5 ppm / °C. Accordingly, by implementing the core layer (100) as a core layer of quartz fibers together with a core layer of glass fibers, the coefficient of thermal expansion of the entire core layer (100) is reduced, thereby minimizing deformation such as warpage due to temperature changes of the circuit board (10).

[0085] Meanwhile, considering that quartz fibers are more expensive than glass fibers, by placing the first core layer (110) in which the quartz fibers are arranged at the center of the vertical direction of the core layer (100), the coefficient of thermal expansion of the entire core layer (100) can be efficiently reduced, and productivity can also be satisfied.

[0086] FIG. 5 is a table comparing the degree of warping occurrence by temperature between a circuit board containing quartz fibers in a core layer (100) according to an embodiment of the present invention and a circuit board not containing quartz fibers in a core layer according to a comparative example.

[0087] In Fig. 5, Cry is a term describing a curved shape in which the central region of the circuit board protrudes upward above the edge region due to heat, and smile is a term describing a curved shape in which the central region of the circuit board protrudes downward above the edge region due to heat.

[0088] Referring to FIG. 5, it can be seen that the circuit board (10) according to an embodiment of the present invention has a lower degree of bending compared to the circuit board according to a comparative example at various temperatures. In particular, in the 22°C range, which is a room temperature state, it can be seen that the circuit board (10) has a bending improvement effect of 41 µm or more compared to the circuit board according to a comparative example.

[0089] FIG. 6 is a drawing illustrating a semiconductor package according to an embodiment of the present invention, and FIG. 7 is a drawing reflecting the specific structure of the core layer in FIG. 6.

[0090] Referring to FIGS. 6 and 7, a semiconductor package according to an embodiment of the present invention may include a semiconductor chip (1000, 2000) disposed on the surface of a circuit board (10). For example, the semiconductor chip (1000, 2000) may include a first semiconductor chip (1000) disposed on a first build-up layer (200) and a second semiconductor chip (2000) disposed on the lower surface of a second build-up layer (300). The first semiconductor chip (1000) may be electrically connected through a connecting member to a fifth wiring portion (415) disposed on the first build-up layer (200). The second semiconductor chip (2000) may be electrically connected through a connecting member to an eighth wiring portion (418) disposed on the lower surface of the second build-up layer (300).

[0091] In the foregoing, although all components constituting an embodiment of the present invention have been described as being combined or operating in combination, the present invention is not necessarily limited to such embodiments. That is, within the scope of the purpose of the present invention, all components may be selectively combined in one or more ways to operate. Furthermore, terms such as "include," "constitute," or "have" described above, unless specifically stated otherwise, mean that the relevant component may be inherent; thus, they should be interpreted as allowing for the inclusion of additional components rather than excluding other components. All terms, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which the present invention pertains, unless otherwise defined. Terms commonly used, such as those defined in advance, should be interpreted in accordance with their meaning in the context of the relevant technology and should not be interpreted in an ideal or overly formal sense unless explicitly defined in the present invention.

[0092] The foregoing description is merely an illustrative explanation of the technical concept of the present invention, and those skilled in the art to which the present invention pertains will be able to make various modifications and variations within the scope of the essential characteristics of the present invention. Accordingly, the embodiments disclosed in the present invention are intended to explain, not limit, the technical concept of the present invention, and the scope of the technical concept of the present invention is not limited by such embodiments. The scope of protection of the present invention shall be interpreted by the claims below, and all technical concepts within an equivalent scope shall be interpreted as being included within the scope of rights of the present invention.

[0093] Meanwhile, when a circuit board having the features of the invention described above is used in IT devices or home appliances such as smartphones, server computers, and TVs, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the features of the invention performs a semiconductor package function, it can safely protect the semiconductor chip from external moisture or contaminants, and can resolve issues such as leakage current, electrical short circuits between terminals, or electrical open circuits of terminals supplying power to the semiconductor chip. In addition, when it is responsible for signal transmission, it can resolve noise issues. Through this, the circuit board having the features of the invention described above enables the stable operation of IT devices or home appliances, thereby allowing the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability.

[0094] When a circuit board having the features of the invention described above is used in a transportation device such as a vehicle, it can resolve the problem of signal distortion transmitted to the transportation device, or safely protect a semiconductor chip controlling the transportation device from the outside, and further improve the stability of the transportation device by resolving problems such as leakage current, electrical short circuits between terminals, or electrical open circuits of terminals supplying power to the semiconductor chip. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

Claims

1. Core layer; A first build-up layer disposed on one side of the core layer and comprising at least one insulating layer; and A second build-up layer disposed on the other side of the core layer and comprising at least one insulating layer, and The core layer comprises a first core layer, a second core layer disposed on one side of the first core layer, and a third core layer disposed on the other side of the first core layer. A circuit board in which the material of the fiber constituting the first core layer is different from the material of the fiber constituting the second core layer or the third core layer.

2. In Paragraph 1, The first core layer comprises a resin and fibers disposed within the resin, and A circuit board in which the fibers of the first core layer are quartz fibers.

3. In Paragraph 2, The second core layer and the third core layer each comprise a resin and a prepreg (PPG) containing glass fibers disposed within the resin, forming a circuit board.

4. In Paragraph 1, The material of the insulating layer constituting the first build-up layer and the second build-up layer is different from the material of the core layer, and is a circuit board.

5. In Paragraph 4, A circuit board in which the insulating layer constituting the first build-up layer and the second build-up layer is ABF (Ajinomoto Build-up Film).

6. In Paragraph 1, The above second core layer and the above third core layer each include a second layer, A circuit board in which the vertical thickness of the first core layer is greater than the vertical thickness of the second layer.

7. In Paragraph 1, A circuit board in which the vertical thickness of the first core layer is thinner than the vertical thickness of the second core layer or the third core layer.

8. In Paragraph 3, The above core layer includes a via hole penetrating from one surface to the other surface, and The above quartz fiber and the above glass fiber each have a region separated from the via hole formation region of the circuit board.

9. In Paragraph 2, The above quartz fibers are arranged to form multiple layers in a vertical direction within the resin constituting the first core layer.

10. Core layer; A first build-up layer disposed on one side of the core layer and comprising at least one insulating layer; A second build-up layer disposed on the other side of the core layer and comprising at least one insulating layer; and A semiconductor chip disposed on the surface of the first build-up layer or the second build-up layer, and The core layer comprises a first core layer, a second core layer disposed on one side of the first core layer, and a third core layer disposed on the other side of the first core layer. A semiconductor package in which the material of the fiber constituting the first core layer is different from the material of the fiber constituting the second core layer or the third core layer.

Images