Power semiconductor device

Abstract

Provided in the present invention is a power semiconductor device, for example, comprising: a substrate; an epitaxial layer, which is disposed on the substrate and is provided with a trench, the trench being recessed from the top surface of the epitaxial layer; a control electrode, which is disposed inside the trench; a first-conductivity-type doped region, which is disposed inside the epitaxial layer, wherein the trench is located between first-conductivity-type doped regions, and part of the first-conductivity-type doped region is located directly below the control electrode; a second-conductivity-type doped region, which is disposed inside the epitaxial layer, wherein the area the second-conductivity-type doped region occupies between the first-conductivity-type doped region and the trench is a stepped area, the stepped area extending from the top surface of the epitaxial layer toward the bottom surface, and part of the stepped area being located directly below the control electrode; an electrode layer, which is disposed on the side of the epitaxial layer away from the substrate and forms ohmic contact with each of the first-conductivity-type doped region and the second-conductivity-type doped region; and an insulating dielectric, which fills the trench and insulates the control electrode from the first-conductivity-type doped region, the second-conductivity-type doped region, the epitaxial layer and the electrode layer.

Description

Power semiconductor device TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of electronic devices, and in particular, to a power semiconductor device. BACKGROUND

[0002] Power semiconductor devices, such as silicon carbide (SiC) MOSFETs, have a wide application prospect in high-power and high-current application fields due to their excellent switching characteristics and material characteristics. In recent years, the performance of planar SiC MOSFETs has been greatly optimized, and various manufacturers are optimizing the specific on-resistance by optimizing process platforms (such as gate oxide layer processes, ohmic contact processes, etc.) and structural designs (such as cell size designs, ion implantation designs, etc.).

[0003] The cell size of a planar SiC MOSFET is mainly limited by three sizes, namely: the size of the ohmic contact, the size of the polysilicon gate electrode, and the lateral spacing between the gate electrode and the source metal; if the lateral spacing between the gate electrode and the source metal is reduced, the risk of device gate-source short circuit will increase, and thus the lateral spacing between the gate electrode and the source metal cannot be too small, which is one of the important reasons for limiting the further reduction of the cell size of the planar SiC MOSFET. In order to overcome the technical defect that the cell size of the planar SiC MOSFET is difficult to reduce, the related technology has proposed a buried gate SiC MOSFET, which can further reduce the lateral spacing between the gate electrode and the source metal, thereby effectively reducing the cell size of the device by 20%-30%, greatly reducing the specific on-resistance of the device. However, with the reduction of the specific on-resistance, the short-circuit withstand capability of the device also decreases. Furthermore, with the reduction of the cell size, the Miller capacitance (Crss) per unit area increases to a certain extent, resulting in a certain increase in the switching loss of the device when working. TECHNICAL SOLUTION

[0004] To overcome one or more technical problems existing in the prior art, embodiments of the present application provide a power semiconductor device to improve the short-circuit withstand capability of the device and / or reduce the switching loss of the device.

[0005] Specifically, the power semiconductor device provided by the embodiment of the present application comprises: a substrate, an epitaxial layer, a control electrode, a first-conductivity-type doped region, a second-conductivity-type doped region, an electrode layer, and an insulating medium; the epitaxial layer is arranged on the substrate, the epitaxial layer is provided with a groove, and the groove is recessed from a top surface of the epitaxial layer away from the substrate; the control electrode is arranged in the groove; the first-conductivity-type doped region is arranged in the epitaxial layer, the groove is located between the first-conductivity-type doped regions, and a part of the first-conductivity-type doped region is located directly below the control electrode; the second-conductivity-type doped region is arranged in the epitaxial layer and occupies a stepped region between the first-conductivity-type doped region and the groove, the stepped region extends from the top surface of the epitaxial layer towards a bottom surface of the epitaxial layer facing the substrate, and a part of the stepped region is located directly below the control electrode; the electrode layer is arranged on a side of the epitaxial layer away from the substrate and forms an ohmic contact with the first-conductivity-type doped region and the second-conductivity-type doped region respectively; and the insulating medium fills the groove and insulates the control electrode from the first-conductivity-type doped region, the second-conductivity-type doped region, the epitaxial layer, and the electrode layer respectively.

[0006] In another aspect, the power semiconductor device provided by the embodiment of the present application comprises: a substrate, an epitaxial layer, a control electrode, a first-conductivity-type doped region, a second-conductivity-type doped region, an electrode layer, and an insulating medium; the epitaxial layer is arranged on the substrate, the epitaxial layer is provided with a groove, and the groove is recessed from a top surface of the epitaxial layer away from the substrate; the control electrode is arranged in the groove and comprises a first electrode part and a second electrode part spaced apart from each other; the first-conductivity-type doped region is arranged in the epitaxial layer, and the groove is located between the first-conductivity-type doped regions; the second-conductivity-type doped region is arranged in the epitaxial layer and located on an inner side of the first-conductivity-type doped region facing the groove; wherein, along a direction towards the groove, a difference between a junction depth of the first-conductivity-type doped region and a junction depth of the second-conductivity-type doped region forms a channel, the channel is located directly below the first electrode part and the second electrode part respectively, and a spacing region between the first electrode part and the second electrode part exposes a part of the epitaxial layer located between the channels; the electrode layer is arranged on a side of the epitaxial layer away from the substrate and forms an ohmic contact with the first-conductivity-type doped region and the second-conductivity-type doped region respectively; and the insulating medium fills the groove and insulates each of the first electrode part and the second electrode part from the first-conductivity-type doped region, the second-conductivity-type doped region, the epitaxial layer, and the electrode layer respectively.

[0007] In yet another aspect, an embodiment of the present application provides a power semiconductor device, for example, including: a substrate, an epitaxial layer, a control electrode, a first conductivity type doped region, a second conductivity type doped region, an electrode layer, and an insulating medium; the epitaxial layer is disposed on the substrate, the epitaxial layer is provided with a trench, and the trench is recessed from a top surface of the epitaxial layer facing away from the substrate; the control electrode is disposed in the trench; the first conductivity type doped region is disposed in the epitaxial layer, and the trench is located between the first conductivity type doped regions; the second conductivity type doped region is disposed in the epitaxial layer and located on an inner side of the first conductivity type doped region facing the trench; wherein, along the direction towards the trench, the difference between the junction depths of the first conductivity type doped region and the second conductivity type doped region forms a channel, the channel is located directly below the control electrode, respectively, the second conductivity type doped region has a first stepped surface facing away from the trench and a second stepped surface opposite to the first stepped surface, the distance between the first stepped surface and the second stepped surface is 50 nanometers to 600 nanometers; the electrode layer is disposed on the side of the epitaxial layer facing away from the substrate and forms an ohmic contact with the first conductivity type doped region and the second conductivity type doped region, respectively; the insulating medium fills the trench and insulates the control electrode from the first conductivity type doped region, the second conductivity type doped region, the epitaxial layer, and the electrode layer, respectively. Advantages

[0008] The above-mentioned embodiments of the present application can have the following beneficial effects: by designing the second-conductivity-type doped region between the first-conductivity-type doped region and the trench as a stepped shape, the second-conductivity-type doped region is a long and narrow strip-shaped region, which is equivalent to a low bulk resistance in series between the electrode layer (for example, the source electrode) and the channel boundary, and the bulk resistance has a positive temperature coefficient; in the normal working temperature range, the bulk resistance is small, and has little effect on the normal working of the device; but in the short-circuit endurance test working condition, the temperature of the device is much higher than the normal working temperature, and the resistance of the bulk resistance sharply increases; and accompanied by the large current in the short-circuit endurance test working condition (for example, more than 10 times the normal working current), the voltage drop on the bulk resistance sharply increases, which presents a voltage division phenomenon on the gate voltage, so that the actual gate voltage applied to the surface of the channel decreases, the concentration of the inversion layer carriers on the surface of the channel decreases, the resistance of the device increases, the peak current in the short-circuit endurance test working condition decreases, and thus the short-circuit endurance of the device is improved. On the other hand, the control electrode (for example, the gate electrode) is arranged to include a first electrode part and a second electrode part spaced apart from each other, that is, a split electrode is formed, which can reduce the overlapping area of the control electrode and the epitaxial layer, thereby reducing the Miller capacitance per unit area, and further significantly reducing the switching loss of the device, while increasing the ratio of the input capacitance to the Miller capacitance (Ciss / Crss) per unit area, which can better suppress the false opening of the device due to crosstalk in the high di / dt working condition, and thus improve the reliability of the device in the high di / dt working condition. BRIEF DESCRIPTION OF DRAWINGS

[0009] The specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0010] FIG. 1 is a schematic diagram of a cross-sectional structure of a power semiconductor device according to an embodiment of the present application.

[0011] FIG. 2 is a schematic diagram of voltage division of a gate voltage of the power semiconductor device shown in FIG. 1 in a short-circuit endurance test working condition.

[0012] FIGS. 3 to 11 are schematic diagrams of process structures of a manufacturing method of the power semiconductor device shown in FIG. 1.

[0013] FIG. 12 is a schematic diagram of a cross-sectional structure of another power semiconductor device according to an embodiment of the present application.

[0014]

MAIN REFERENCE NUMERALS EXPLANATION

[0015] 10 - power semiconductor device; 11 - substrate; 12 - epitaxial layer; 121 - trench; 12T - top surface of the epitaxial layer; 12B - bottom surface of the epitaxial layer; 12C - channel; 13 - control electrode; 130 - polysilicon layer; 131 - first electrode part; 133 - second electrode part; 14 - first conductivity type doped region; 141 - first ion implanted region; 142 - second ion implanted region; 143 - third ion implanted region; 15 - second conductivity type doped region; 151 - first lateral part; 152 - intermediate part; 153 - second lateral part; 153S - side surface of the second lateral part; 154S - first step-like surface; 155S - second step-like surface; 16 - electrode layer; 161 - contact metal layer; 163 - front side metal layer; 17 - insulating medium; 171 - thermal oxide layer; 1710 - thermal oxide material layer; 173 - interlayer dielectric layer; 18 - back side metal layer; R - direction; dl - distance; BS - boundary surface. Embodiments of the present application

[0016] In order to make the above objectives, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0017] In order to make the above objectives, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0018] It should be noted that the terms "first", "second" and the like in the description and in the claims of the present application and the above drawings are intended to distinguish similar objects and not to describe a particular order or sequence. It will be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the present application described herein can be carried out in other sequences than the one described or illustrated herein. Moreover, the terms "comprise", "have" and any variations thereof are intended to cover a non-exclusive inclusion, for example, a process, method, article, or apparatus that comprises a list of steps or units not necessarily limited to those specifically listed, but can include additional steps or units not expressly listed or inherent to such process, method, article, or apparatus.

[0019] It should also be noted that the division of the embodiments in the present application is only for the convenience of description, and should not constitute a special limitation. The features in various embodiments can be combined with each other and mutually referenced without contradiction.

[0020] Referring to FIG. 1, a power semiconductor device 10 according to an embodiment of the present application includes, for example, a substrate 11, an epitaxial layer 12, a control electrode 13, first-conductivity-type doped regions 14, second-conductivity-type doped regions 15, an electrode layer 16, and an insulating medium 17.

[0021] Specifically, the epitaxial layer 12 is disposed on the substrate 11, the epitaxial layer 12 is provided with a trench 121, and the trench 121 is recessed from a top surface 12T of the epitaxial layer 12 facing away from the substrate 11. The control electrode 13 is disposed in the trench 121, for example, as a gate electrode. The first-conductivity-type doped regions 14 are disposed in the epitaxial layer 12, the trench 121 is located between the first-conductivity-type doped regions 14 (or the first-conductivity-type doped regions 14 are located on opposite sides of the trench 121), and a portion of the first-conductivity-type doped regions 14 is located directly below the control electrode 13. The second-conductivity-type doped regions 15 are disposed in the epitaxial layer 12, on an inner side of the first-conductivity-type doped regions 14 facing the trench 121, and the second-conductivity-type doped regions 15 occupy a stepped region between the first-conductivity-type doped regions 14 and the trench 121, the stepped region extends from the top surface 12T of the epitaxial layer 12 toward a bottom surface 12B of the epitaxial layer 12 facing the substrate 11, and a portion of the stepped region is located directly below the control electrode 13. The electrode layer 16 is disposed on a side of the epitaxial layer 12 facing away from the substrate 11 and forms an ohmic contact with the first-conductivity-type doped regions 14 and the second-conductivity-type doped regions 15, respectively, for example, as a source electrode. The insulating medium 17 fills the trench 121 and insulates the control electrode 13 from the first-conductivity-type doped regions 14, the second-conductivity-type doped regions 15, the epitaxial layer 12, and the electrode layer 16, respectively. In addition, it can be seen from FIG. 1 that, along a direction R toward the trench 121, a difference between the junction depths of the first-conductivity-type doped regions 14 and the second-conductivity-type doped regions 15 forms a channel 12C, and the channel 12C is located directly below the control electrode 13.

[0022] The second conductive type doped region 15 between the first conductive type doped region 14 and the trench 121 is designed as a stepped shape, for example, two-step as shown in FIG. 1, so that the second conductive type doped region 15 is a long and narrow strip-shaped region, which is equivalent to a low bulk resistance Rs in series between the electrode layer 16 and the channel 12C boundary, as shown in FIG. 2, and the bulk resistance Rs has a positive temperature coefficient; when the device is in the normal working temperature range, the bulk resistance Rs is small, and the normal working of the device is less affected; but in the short circuit resistance test working condition, the temperature of the device is far beyond the normal working temperature, and the resistance of the bulk resistance Rs increases sharply; and accompanied by the large current condition (for example, more than 10 times the normal working current) in the short circuit resistance test working condition, the voltage drop on the bulk resistance Rs increases sharply, which presents a voltage division phenomenon on the gate voltage, that is, VGS represents the gate-source voltage, VGS0 represents the gate voltage applied to the channel surface, and I represents the current, so that the actual gate voltage applied to the channel surface decreases, which reduces the concentration of the inversion layer carriers on the channel surface, increases the resistance of the device, and reduces the peak current in the short circuit resistance test working condition, thereby improving the short circuit resistance of the device. It should be noted that G in FIG. 2 represents the control electrode 13 (for example, the gate electrode), D represents the drain electrode, S1 represents the electrode layer 16 (for example, the source electrode), and S0 represents the channel surface position.

[0023] In some embodiments, as shown in FIG. 1, the stepped region includes a first lateral part 151, an intermediate part 152, and a second lateral part 153 in sequence in the direction R towards the trench 121; the intermediate part 152 extends from the top surface 12T of the epitaxial layer 12 towards the bottom surface 12B of the epitaxial layer 12, which is, for example, a long and narrow straight strip, but the embodiments of the present application are not limited thereto, as long as the stepped region contains at least two steps; the first lateral part 151 and the second lateral part 153 are respectively connected to opposite ends of the intermediate part 152 and located on opposite sides of the intermediate part 152, the surface of the first lateral part 151 away from the substrate 11 is part of the top surface 12T of the epitaxial layer 12, and the second lateral part 153 is located directly below the trench 121, and the side surface 153S of the second lateral part 153 away from the first lateral part 151 is the channel boundary; the second conductive type doped region 15 is equivalent to a bulk resistance with a positive temperature coefficient in series between the electrode layer 16 and the channel boundary, for example, the bulk resistance Rs shown in FIG. 2.

[0024] In some embodiments, as shown in FIG. 1, the stepped region comprises a first stepped surface 154S facing away from the trench 121 and a second stepped surface 155S opposite to the first stepped surface 154S, where the first stepped surface 154S comprises, for example, two stepped surfaces and a vertical surface connecting between the two stepped surfaces, and the second stepped surface 155S also comprises, for example, two stepped surfaces and a vertical surface connecting between the two stepped surfaces, so that the second-conductivity-type doped region 15 is substantially Z-shaped; a side surface 153S of the second lateral portion 153 is connected between the first stepped surface 154S and the second stepped surface 155S, and a distance d1 between the first stepped surface 154S and the second stepped surface 155S is, for example, 50 nanometers (nm) to 600 nm.

[0025] In some embodiments, as shown in FIG. 1, in a direction R toward the trench 121, the first-conductivity-type doped region 14 comprises, in sequence, a first ion implantation region 141, a second ion implantation region 142 and a third ion implantation region 143, a doping concentration of the second ion implantation region 142 is less than a doping concentration of the first ion implantation region 141 and greater than a doping concentration of the third ion implantation region 143, and a boundary surface BS between the second ion implantation region 142 and the third ion implantation region 143 is located directly below the trench 121. In addition, it can also be known from FIG. 1 that the second ion implantation region 142 is connected between the first ion implantation region 141 and the third ion implantation region 143, the second ion implantation region 142 is substantially L-shaped, and the third ion implantation region 143 is substantially L-shaped.

[0026] In some embodiments, as shown in FIG. 1, the insulating medium 17 comprises a thermal oxide layer 171 and an interlayer dielectric layer 173, the thermal oxide layer 171 is located in the trench 121 and insulates the control electrode 13 from the first-conductivity-type doped region 14, the second-conductivity-type doped region 15 and the epitaxial layer 12, respectively, the interlayer dielectric layer 173 fills in the trench 121 and is covered by the electrode layer 16, and the interlayer dielectric layer 173 insulates the control electrode 13 from the electrode layer 16.

[0027] In some embodiments, as shown in FIG. 1, a top surface 173T of the interlayer dielectric layer 173 facing away from the substrate 11 is flush with a plane where a mouth of the trench 121 is located; or in other embodiments, the top surface 173T of the interlayer dielectric layer 173 is lower than the plane where the mouth of the trench 121 is located, so that the electrode layer 16 is correspondingly partially inserted into the trench 121.

[0028] In some embodiments, as shown in FIG. 1, the control electrode 13 includes a first electrode portion 131 and a second electrode portion 133 spaced apart by an interlayer dielectric layer 173, i.e., the control electrode 13 is a split electrode; a thermal oxide layer 171 covers two opposite sides (or outer sides) of the first electrode portion 131 and the second electrode portion 133 and a bottom surface of each of the first electrode portion 131 and the second electrode portion 133 facing the substrate 11, so as to insulate each of the first electrode portion 131 and the second electrode portion 133 from the first conductive type doped region 14, the second conductive type doped region 15 and the epitaxial layer 12, respectively; the interlayer dielectric layer 173 covers two opposite sides (or inner sides) of the first electrode portion 131 and the second electrode portion 133 and a top surface of each of the first electrode portion 131 and the second electrode portion 133 facing away from the substrate 11, so as to space apart the first electrode portion 131 and the second electrode portion 133 and insulate the first electrode portion 131 and the second electrode portion 133 from the electrode layer 16, respectively. In addition, it can be seen from FIG. 1 that the spacing region between the first electrode portion 131 and the second electrode portion 133 exposes a partial region of the epitaxial layer 12 between the channels 12C, and the first electrode portion 131 and the second electrode portion 133 completely cover the respective corresponding channels 12C, so as to ensure good control ability of the channels 12C. The present embodiment sets the control electrode 13 to include the first electrode portion 131 and the second electrode portion 133 spaced apart from each other, i.e., forms a split electrode, which can reduce the overlapping area of the control electrode 13 and the epitaxial layer 12 (the overlapping area is positively correlated with the Miller capacitance), thereby reducing the Miller capacitance (Crss) per unit area, and further significantly reducing the switching loss of the device, while increasing the ratio of the input capacitance to the Miller capacitance (Ciss / Crss) per unit area, which can better inhibit the device from being mistakenly turned on due to crosstalk under high di / dt working conditions, and thus improve the reliability of the device under high di / dt working conditions.

[0029] In some embodiments, as shown in FIG. 1, the electrode layer 16 includes a contact metal layer 161 and a front metal layer 163, the contact metal layer 161 is located on a side of the epitaxial layer 12 facing away from the substrate 11 and forms ohmic contacts with the first conductive type doped region 14 and the second conductive type doped region 15, specifically, forms ohmic contacts with the first ion implantation region 141 of the first conductive type doped region 14 and the first lateral portion 151 and the intermediate portion 152 of the second conductive type doped region 15, respectively; the front metal layer 163 is located on a side of the contact metal layer 161 facing away from the epitaxial layer 12 and covers the trench 121 and the insulating dielectric 17. Further, a back metal layer 18, such as a drain electrode, is provided on a side of the substrate 11 facing away from the epitaxial layer 12.

[0030] In order to make the power semiconductor device 10 provided by the embodiments of the present application more clearly understood, a manufacturing method of the power semiconductor device 10 shown in FIG. 1 will be described below in combination with FIGS. 3 to 11, and the manufacturing method can specifically include the following steps by taking the first conductive type as P type and the second conductive type as N type as an illustrative example.

[0031] Referring to FIG. 3, an epitaxial layer 12 is formed on the substrate 11, for example, an N-type SiC epitaxial layer is grown on an N+ type SiC substrate, and the growth can be a vapor phase epitaxy process; then, P-type ion implantation regions P1 are locally implanted on a side of the epitaxial layer 12 away from the substrate 11, and a trench 121 is formed in the epitaxial layer 12 by etching, where the trench 121 is located between the ion implantation regions P1.

[0032] Referring to FIG. 4, an implantation mask M1 is formed in the trench 121, and P-type ion implantation regions PB are formed by ion implantation, where the ion implantation regions PB are located on an inner side of the ion implantation regions P1 facing the trench 121, and a doping concentration of the ion implantation regions PB is less than a doping concentration of the ion implantation regions P1.

[0033] Referring to FIG. 5, a mask M2 is formed by a photolithography + self-alignment process, and ion implantation is performed to form a long and narrow strip-shaped N+ type ion implantation region as the second conductive type region 15, and a channel 12C and a third ion implantation region 143 of the first conductive type region 14 are simultaneously formed; the second conductive type region 15 includes a first lateral part 151, an intermediate part 15 and a second lateral part 153 in sequence in a direction R toward the trench 121, and the intermediate part 15 can be formed by ion implantation with an angle; as shown in FIG. 5, a difference between a junction depth of the second conductive type region 15 and a junction depth of the third ion implantation region 143 forms the channel 12C in the direction R toward the trench 121. Then, the mask M2 is removed.

[0034] Referring to FIG. 6, P+ type ion implantation is locally performed on a side of the epitaxial layer 12 away from the substrate 11 to convert the ion implantation regions P1 (for example, including three-level steps) in FIG. 5 into a first ion implantation region 141 and a second ion implantation region 142 of the first conductive type region 14, where a doping concentration of the first ion implantation region 141 is greater than a doping concentration of the second ion implantation region 142.

[0035] Referring to FIG. 7, a thermal oxidation material layer 1710 is formed on a top surface 12T of the epitaxial layer 12 away from the substrate 11 and on a bottom surface and a sidewall of the trench 121 by thermal oxidation, and a doped polysilicon layer 130 is formed on a surface of the thermal oxidation material layer 1710 away from the substrate 11.

[0036] Referring to Fig. 8, the thermal oxidation material layer 1710 and the doped polysilicon layer 130 are etched by self-alignment to form the thermal oxidation layer 171 and the control electrode 13, which here includes the first electrode part 131 and the second electrode part 133 spaced apart from each other, i.e. split electrodes; the thermal oxidation layer 171 covers the opposite two side surfaces (or inner side surfaces) of the first electrode part 131 and the second electrode part 133 and the bottom surface of each of the first electrode part 131 and the second electrode part 133 facing the substrate 11.

[0037] Referring to Fig. 9, the interlayer dielectric layer 173 is formed by deposition and etching process, and the top surface 173T of the interlayer dielectric layer 173 here is not higher than the top surface 12T of the epitaxial layer 12 facing away from the substrate 11; in addition, the interlayer dielectric layer 173 covers the opposite two side surfaces (or inner side surfaces) of the first electrode part 131 and the second electrode part 133 and the top surface of each of the first electrode part 131 and the second electrode part 133 facing away from the substrate 11. In addition, it is worth mentioning that the interlayer dielectric layer 173 here together with the thermal oxidation layer 171 constitutes a specific embodiment of the insulating medium 17.

[0038] Referring to Fig. 10, after depositing an ohmic contact material layer (e.g. Ti / Cu layer) on the top surface 12T of the epitaxial layer 12, annealing and patterning are performed to obtain the contact metal layer 161; the contact metal layer 161 here forms a good ohmic contact with the first ion implantation region 141 of the first conductive type region 14 and the first lateral part 151 and the intermediate part 152 of the second conductive type region 15, respectively.

[0039] Referring to Fig. 11, a thickened metal material layer is deposited on the side of the contact metal layer 161 facing away from the epitaxial layer 12 and the top surface 173T of the interlayer dielectric layer 173, and etched and patterned to form the front metal layer 163; it is worth mentioning that the front metal layer 163 here together with the contact metal layer 161 constitutes a specific embodiment of the electrode layer 16.

[0040] Finally, the back surface of the substrate 11 facing away from the epitaxial layer 12 is thinned to form the back metal layer 18, as shown in Fig. 1, and thus the power semiconductor device 10 shown in Fig. 1 can be manufactured.

[0041] In addition, it is worth mentioning that, without considering the switching loss of the device, the control electrode 13 can also not be provided as a split electrode, as shown in FIG. 12; correspondingly, the thermal oxide layer 171 covers the two side surfaces and the bottom surface facing the substrate 11 of the control electrode 13, so as to insulate the control electrode 13 from the first conductive type doped region 14, the second conductive type doped region 15 and the epitaxial layer 12 respectively; the interlayer dielectric layer 173 covers the top surface of the control electrode 13 away from the substrate 11, so as to insulate the control electrode 13 from the electrode layer 16; in addition, the control electrode 13 completely covers the channel 12C, so as to ensure good control ability of the channel 12C.

[0042] The above description is only the preferred embodiment of the present application, and does not limit the present application in any form. Although the present application has been disclosed as above with the preferred embodiment, it is not intended to limit the present application. Any person skilled in the art can make some changes or modifications to the above disclosed technical content without departing from the technical solution of the present application, and any simple modification, equivalent change and modification of the above embodiment according to the technical essence of the present application still belong to the scope of the technical solution of the present application.

Claims

1. A power semiconductor device, characterized by, Comprising: a substrate; an epitaxial layer disposed on the substrate, the epitaxial layer being provided with a trench, and the trench being recessed inwardly from a top surface of the epitaxial layer facing away from the substrate; a control electrode disposed in the trench; a first-conductivity-type doped region disposed in the epitaxial layer, the trench being located between the first-conductivity-type doped regions, and a portion of the first-conductivity-type doped region being located directly below the control electrode; a second-conductivity-type doped region disposed in the epitaxial layer and occupying a stepped region between the first-conductivity-type doped regions and the trench, the stepped region extending from the top surface of the epitaxial layer toward a bottom surface of the epitaxial layer facing the substrate, and a portion of the stepped region being located directly below the control electrode; an electrode layer disposed on a side of the epitaxial layer facing away from the substrate and forming an ohmic contact with the first-conductivity-type doped regions and the second-conductivity-type doped regions, respectively; and an insulating medium filling the trench and insulating the control electrode from the first-conductivity-type doped regions, the second-conductivity-type doped regions, the epitaxial layer, and the electrode layer, respectively. In a direction toward the trench, the stepped region comprises, in sequence, a first lateral portion, an intermediate portion, and a second lateral portion; the intermediate portion extends from the top surface of the epitaxial layer toward the bottom surface of the epitaxial layer, the first lateral portion and the second lateral portion are respectively connected to opposite ends of the intermediate portion and located on opposite sides of the intermediate portion, a surface of the first lateral portion facing away from the substrate is a portion of the top surface of the epitaxial layer, the second lateral portion is located directly below the trench, a side surface of the second lateral portion facing away from the first lateral portion is a channel boundary, and the second-conductivity-type doped region is equivalent to a positive temperature coefficient body resistor connected in series between the electrode layer and the channel boundary.

2. The power semiconductor device according to claim 1, characterized in that The stepped region comprises a first stepped surface facing away from the trench and a second stepped surface opposite to the first stepped surface, the side surface of the second lateral portion is connected between the first stepped surface and the second stepped surface, and a distance between the first stepped surface and the second stepped surface is 50 nanometers to 600 nanometers.

3. The power semiconductor device according to claim 2, characterized in that In a direction toward the trench, the first-conductivity-type doped region comprises, in sequence, a first ion implantation region, a second ion implantation region, and a third ion implantation region, a doping concentration of the second ion implantation region is less than a doping concentration of the first ion implantation region and greater than a doping concentration of the third ion implantation region, and a boundary between the second ion implantation region and the third ion implantation region is located directly below the trench.

4. The power semiconductor device according to claim 1, characterized in that The insulating medium comprises a thermal oxidation layer and an interlayer dielectric layer, the thermal oxidation layer is located in the trench and insulates the control electrode from the first-conductivity-type doped regions, the second-conductivity-type doped regions, and the epitaxial layer, respectively, the interlayer dielectric layer fills the trench and is covered by the electrode layer, and the interlayer dielectric layer insulates the control electrode from the electrode layer.

5. The power semiconductor device according to claim 1, characterized in that ​ 6. The power semiconductor device according to claim 5, characterized in that A top surface of the interlayer dielectric layer facing away from the substrate is lower than or flush with a plane where a mouth of the trench is located.

7. The power semiconductor device according to claim 5, characterized in that, The control electrode includes a first electrode portion and a second electrode portion spaced apart by the interlayer dielectric layer, the thermal oxide layer covers two opposite sides of the first electrode portion and the second electrode portion and a bottom surface of each of the first electrode portion and the second electrode portion facing the substrate, and the interlayer dielectric layer covers two opposite sides of the first electrode portion and the second electrode portion and a top surface of each of the first electrode portion and the second electrode portion facing away from the substrate.

8. The power semiconductor device according to claim 1, characterized in that The electrode layer includes a contact metal layer and a front metal layer, the contact metal layer is located on a side of the epitaxial layer facing away from the substrate and forms an ohmic contact with the first conductive type doped region and the second conductive type doped region respectively, and the front metal layer is located on a side of the contact metal layer facing away from the epitaxial layer and covers the trench and the insulating medium; and a back metal layer is arranged on a side of the substrate facing away from the epitaxial layer.

9. A power semiconductor device, characterized by Comprise: a substrate; an epitaxial layer arranged on the substrate, the epitaxial layer being provided with a trench, and the trench being recessed from a top surface of the epitaxial layer facing away from the substrate; a control electrode arranged in the trench and comprising a first electrode portion and a second electrode portion spaced apart from each other; a first conductive type doped region arranged in the epitaxial layer, the trench being located between the first conductive type doped regions; a second conductive type doped region arranged in the epitaxial layer and located on an inner side of the first conductive type doped region facing the trench, wherein, in a direction towards the trench, a difference between junction depths of the first conductive type doped region and the second conductive type doped region forms a channel, the channel being located directly below the first electrode portion and the second electrode portion respectively, and a spacing region between the first electrode portion and the second electrode portion exposes a part of the epitaxial layer located between the channels; an electrode layer arranged on a side of the epitaxial layer facing away from the substrate and forming an ohmic contact with the first conductive type doped region and the second conductive type doped region respectively; and an insulating medium filling the trench and insulating each of the first electrode portion and the second electrode portion from the first conductive type doped region, the second conductive type doped region, the epitaxial layer and the electrode layer respectively.

10. The power semiconductor device according to claim 9, characterized in that, The insulating medium includes a thermal oxide layer and an interlayer dielectric layer, the thermal oxide layer is located in the trench and insulates each of the first electrode portion and the second electrode portion from the first conductive type doped region, the second conductive type doped region and the epitaxial layer respectively, the interlayer dielectric layer fills the trench and is covered by the electrode layer, the first electrode portion and the second electrode portion are spaced apart by the interlayer dielectric layer, and the interlayer dielectric layer insulates the first electrode portion and the second electrode portion from the electrode layer respectively.

11. The power semiconductor device according to claim 10, characterized in that A top surface of the interlayer dielectric layer facing away from the substrate is lower than or flush with a plane where a mouth of the trench is located.

12. The power semiconductor device according to claim 10, characterized in that, The thermal oxide layer covers two opposite sides of the first electrode part and the second electrode part and the bottom surfaces of the first electrode part and the second electrode part respectively facing the substrate, and the interlayer dielectric layer covers two opposite sides of the first electrode part and the second electrode part and the top surfaces of the first electrode part and the second electrode part respectively facing away from the substrate.

13. The power semiconductor device of claim 9, wherein, The electrode layer includes a contact metal layer and a front metal layer, the contact metal layer is located on a side of the epitaxial layer facing away from the substrate and forms an ohmic contact with the first conductive type doped region and the second conductive type doped region respectively, and the front metal layer is located on a side of the contact metal layer facing away from the epitaxial layer and covers the trench and the insulating medium; and a back metal layer is arranged on a side of the substrate facing away from the epitaxial layer.

14. The power semiconductor device of claim 9, wherein, In a direction towards the trench, the first conductive type doped region includes a first ion implantation region, a second ion implantation region and a third ion implantation region in sequence, the doping concentration of the second ion implantation region is less than the doping concentration of the first ion implantation region and greater than the doping concentration of the third ion implantation region, and a boundary surface between the second ion implantation region and the third ion implantation region is located directly below the trench.

15. A power semiconductor device, characterized by Comprise: a substrate; an epitaxial layer arranged on the substrate, the epitaxial layer being provided with a trench, and the trench being recessed from a top surface of the epitaxial layer facing away from the substrate; a control electrode arranged in the trench; a first conductive type doped region arranged in the epitaxial layer, the trench being located between the first conductive type doped regions; a second conductive type doped region arranged in the epitaxial layer and located on an inner side of the first conductive type doped region facing the trench, wherein, in a direction towards the trench, a difference between the junction depths of the first conductive type doped region and the second conductive type doped region forms a channel, the channel being located directly below the control electrode respectively, the second conductive type doped region having a first stepped surface facing away from the trench and a second stepped surface opposite to the first stepped surface, a distance between the first stepped surface and the second stepped surface being 50 nanometers to 600 nanometers; an electrode layer arranged on a side of the epitaxial layer facing away from the substrate and forming an ohmic contact with the first conductive type doped region and the second conductive type doped region respectively; and an insulating medium filling the trench and insulating the control electrode from the first conductive type doped region, the second conductive type doped region, the epitaxial layer and the electrode layer respectively.

16. The power semiconductor device according to claim 15, characterized in that, The second conductive type doped region is a stepped region, the stepped region includes a first lateral part, a middle part and a second lateral part in sequence along a direction toward the trench, the middle part extends from the top surface of the epitaxial layer toward the bottom surface of the epitaxial layer, the first lateral part and the second lateral part are respectively connected to opposite ends of the middle part and are located on opposite sides of the middle part, a surface of the first lateral part away from the substrate is a part of the top surface of the epitaxial layer, the second lateral part is located directly below the trench, a side surface of the second lateral part away from the first lateral part is a boundary of the channel, and the second conductive type doped region is equivalent to a positive temperature coefficient bulk resistor connected in series between the electrode layer and the boundary of the channel.

17. The power semiconductor device of claim 15, wherein, Along a direction toward the trench, the first conductive type doped region includes a first ion implantation region, a second ion implantation region and a third ion implantation region in sequence, a doping concentration of the second ion implantation region is less than a doping concentration of the first ion implantation region and greater than a doping concentration of the third ion implantation region, and a boundary between the second ion implantation region and the third ion implantation region is located directly below the trench.

18. The power semiconductor device of claim 15, wherein, The control electrode includes a first electrode part and a second electrode part spaced from each other, and a spacing region between the first electrode part and the second electrode part exposes a part of the epitaxial layer between the channels.

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