Driving circuit, light-emitting assembly, display substrate and display apparatus

Abstract

A driving circuit (10), a light-emitting assembly (40), a display substrate (100) and a display apparatus (1000). The driving circuit (10) is used for connecting to a plurality of light-emitting devices (20), and comprises a plurality of pixel circuits (1) and a demultiplexing circuit (2), wherein each pixel circuit (1) is directly connected to a first power signal terminal (VDD), a second power signal terminal (VSS), a first control node (G), a data signal terminal (D) and a first node (N1); the first node (N1) is coupled to the light-emitting devices (20); the demultiplexing circuit (2) is connected to the first power signal terminal (VDD), the second power signal terminal (VSS), the data signal terminal (D), the first control nodes (G) and input signal terminals (S); and the demultiplexing circuit (2) is configured to transmit, in response to input signals transmitted by the input signal terminals (S), a first control signal to each of the first control nodes (G) connected to the plurality of pixel circuits (1), so as to write a data signal received at the data signal terminal (D) into different pixel circuits (1) in a time-division manner.

Description

Driving circuit, light emitting assembly, display substrate and display device thereof

[0001] This application claims priority to International Patent Application No. PCT / CN2024 / 122913, filed on September 30, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure relates to the technical field of display, and in particular, to a driving circuit, a light emitting assembly, a display substrate and a display device thereof. BACKGROUND

[0003] With the development of light emitting diode technology, display devices using light emitting diodes (LEDs) of sub-millimeter (Mini) level or even micrometer (Micro) level have been widely applied. At present, there are mainly two driving modes for Micro / Mini LED display devices: passive matrix (PM) driving and active matrix (AM) driving. Among them, AM driving is widely applied in various display devices due to its advantages of simple wiring, good brightness uniformity, low picture flicker and high light emitting efficiency.

[0004] SUMMARY

[0005] In one aspect, a driving circuit is provided. The driving circuit is configured to connect a plurality of light emitting devices. The driving circuit includes a plurality of pixel circuits and a plurality of distribution circuits. The pixel circuit is directly connected to a first power signal terminal, a second power signal terminal, a first control node, a data signal terminal and a first node. The first node is coupled to the light emitting device. The plurality of distribution circuits is connected to the first power signal terminal, the second power signal terminal, the data signal terminal, the first control node and an input signal terminal. The plurality of distribution circuits is configured to transmit a first control signal to the first control node of the plurality of pixel circuits in response to an input signal transmitted by the input signal terminal, so as to write a data signal received at the data signal terminal into different pixel circuits in time.

[0006] In some embodiments, the plurality of distribution circuits includes a plurality of first inverting sub-circuits, a plurality of control wires and a plurality of first NAND gate sub-circuits.

[0007] The plurality of first inverting sub-circuits respectively includes an input terminal, an output terminal, a first signal terminal and a second signal terminal. The input terminal of the first inverting sub-circuit is connected to the input signal terminal. One of the first signal terminal and the second signal terminal is connected to the first power signal terminal, and the other is connected to the second power signal terminal.

[0008] The plurality of control lines are divided into a plurality of control line groups, each of which includes two control lines. In the same control line group, one of the two control lines is connected to the input signal terminal, and the other is connected to the output terminal of the first inverting sub-circuit connected to the input signal terminal.

[0009] The plurality of first NAND sub-circuits each include an input terminal, an output terminal, a third signal terminal, and a fourth signal terminal. The input terminal of the first NAND sub-circuit is connected to the control line, and in the same first NAND sub-circuit, the control lines connected to different input terminals belong to different control line groups. In any two different first NAND sub-circuits, at least one input terminal connected to the control line is different. The output terminal of the first NAND sub-circuit is connected to the first control node. One of the third signal terminal and the fourth signal terminal is connected to the first power signal terminal, and the other is connected to the second power signal terminal.

[0010] In some embodiments, the pixel circuit is also connected to a third control node, and the third control nodes connected to a plurality of pixel circuits are also directly connected to the output terminal of the same first NAND sub-circuit, and / or the first control nodes connected to a plurality of pixel circuits are directly connected to the output terminal of one first NAND sub-circuit.

[0011] In some embodiments, the pixel circuit is also connected to a third control node, and the multiplexing circuit includes three first inverting sub-circuits, six control lines, and four first NAND sub-circuits.

[0012] The six control lines include a first control line, a second control line, a third control line, a fourth control line, a fifth control line, and a sixth control line in turn adjacent to each other. The first control line and the second control line form a control line group, the third control line and the fourth control line form a control line group, and the fifth control line and the sixth control line form a control line group. The two control lines of one control line group are connected to the same input signal terminal.

[0013] The input terminals of the three first inverting sub-circuits are respectively connected to one input signal terminal, and the first control line, the third control line, and the fifth control line are respectively connected to the output terminals of the three first inverting sub-circuits. The second control line, the fourth control line, and the sixth control line are respectively connected to one input signal terminal.

[0014] Each of the first NAND sub-circuits includes three input terminals. Among the four first NAND sub-circuits, the three input terminals of one of the first NAND sub-circuits are connected to the second control wire, the third control wire and the fifth control wire respectively, and the output terminal is connected to the third control node to which all the pixel circuits are connected. The output terminals of the remaining three first NAND sub-circuits are connected to the first control nodes of one of the pixel circuits respectively. Among the remaining three first NAND sub-circuits, the three input terminals of one of the first NAND sub-circuits are connected to the second control wire, the third control wire and the sixth control wire respectively. The three input terminals of one of the first NAND sub-circuits are connected to the second control wire, the fourth control wire and the fifth control wire respectively. The three input terminals of one of the first NAND sub-circuits are connected to the second control wire, the fourth control wire and the sixth control wire respectively.

[0015] In some embodiments, the pixel circuit includes a current generation sub-circuit and a pulse width modulation sub-circuit. The current generation sub-circuit is directly connected to the first power signal terminal, the first control node, the second control node, the data signal terminal, the third control node, the first node and the second node. The current generation sub-circuit is configured to generate a drive current signal.

[0016] In some embodiments, the pixel circuit further includes a pulse width modulation sub-circuit, which is directly connected to the third control node, the first pulse signal terminal, the fourth control node and the second node. The pulse width modulation sub-circuit is configured to control the drive current signal to be transmitted or not transmitted to the light emitting device.

[0017] In some embodiments, the multiplexing circuit further includes a plurality of second NAND sub-circuits, a plurality of second inverting sub-circuits and a plurality of first transfer gates.

[0018] The plurality of second NAND sub-circuits each includes an input terminal, an output terminal, the third signal terminal and the fourth signal terminal. The input terminal of the second NAND sub-circuit is connected to the control wire, and in the same second NAND sub-circuit, the control wires connected to different input terminals belong to different control wire groups. In any two different NAND sub-circuits, the control wires connected to at least one input terminal are different.

[0019] The second inverting sub-circuits each include an input terminal, an output terminal, the first signal terminal and the second signal terminal. The input terminal of the second inverting sub-circuit is connected to the output terminal of the second NAND gate sub-circuit. The first transfer gates each include an input terminal, an output terminal, a first control signal terminal and a second control signal terminal. The input terminal of the first transfer gate is connected to the data signal terminal, and the output terminal of the first transfer gate is connected to the fourth control node. The first control signal terminal of the first transfer gate is connected to the output terminal of the second NAND gate sub-circuit, and the second control signal terminal of the first transfer gate is connected to the output terminal of the second inverting sub-circuit.

[0020] In some embodiments, the second control nodes of the pixel circuits are connected to the output terminal of the same second inverting sub-circuit.

[0021] In some embodiments, the multiplexing circuit includes three second inverting sub-circuits, six control lines, three second NAND gate sub-circuits and three first transfer gates.

[0022] The six control lines include a first control line, a second control line, a third control line, a fourth control line, a fifth control line and a sixth control line in sequence. The first control line and the second control line form a control line group, the third control line and the fourth control line form a control line group, and the fifth control line and the sixth control line form a control line group. Two control lines in a control line group are connected to the same input signal terminal.

[0023] The input terminals of the three second inverting sub-circuits are connected to the output terminals of the second NAND gate sub-circuits, respectively. The input terminals of the three first transfer gates are connected to the same data signal terminal, and the output terminals of the three first transfer gates are connected to the fourth control nodes of the pixel circuits, respectively. The first control signal terminals of the three first transfer gates are connected to the output terminals of the second NAND gate sub-circuits, respectively, and the second control signal terminals of the three first transfer gates are connected to the output terminals of the second inverting sub-circuits, respectively. In addition, the output terminal of the second inverting sub-circuit is connected to the second control nodes of the pixel circuits.

[0024] Each of the second NAND sub-circuits includes three input terminals. Among the three second NAND sub-circuits, three input terminals of one of the second NAND sub-circuits are connected to the first control wire, the third control wire and the sixth control wire respectively. Three input terminals of one of the second NAND sub-circuits are connected to the first control wire, the fourth control wire and the fifth control wire respectively. Three input terminals of one of the second NAND sub-circuits are connected to the first control wire, the fourth control wire and the sixth control wire respectively.

[0025] In some embodiments, the multiplexing circuit includes four first NAND sub-circuits. Among the four first NAND sub-circuits, three input terminals of one of the first NAND sub-circuits are connected to the second control wire, the third control wire and the fifth control wire respectively, and the output terminal is connected to a third control node to which all the pixel circuits are connected. The output terminals of the remaining three first NAND sub-circuits are connected to first control nodes of one of the pixel circuits respectively. Among the remaining three first NAND sub-circuits, three input terminals of one of the first NAND sub-circuits are connected to the second control wire, the third control wire and the sixth control wire respectively. Three input terminals of one of the first NAND sub-circuits are connected to the second control wire, the fourth control wire and the fifth control wire respectively. Three input terminals of one of the first NAND sub-circuits are connected to the second control wire, the fourth control wire and the sixth control wire respectively.

[0026] Among the first NAND sub-circuit connected to the second control wire, the third control wire and the sixth control wire, and the second NAND sub-circuit connected to the first control wire, the third control wire and the sixth control wire, are connected to the same pixel circuit.

[0027] Among the first NAND sub-circuit connected to the second control wire, the fourth control wire and the fifth control wire, and the second NAND sub-circuit connected to the first control wire, the fourth control wire and the fifth control wire, are connected to the same pixel circuit.

[0028] Among the first NAND sub-circuit connected to the second control wire, the fourth control wire and the sixth control wire, and the second NAND sub-circuit connected to the first control wire, the fourth control wire and the sixth control wire, are connected to the same pixel circuit.

[0029] In some embodiments, the pulse width modulation sub-circuit includes a third inverting sub-circuit, a fourth inverting sub-circuit, a second transfer gate and a third transfer gate.

[0030] The third inverting sub-circuit includes an input terminal, an output terminal, the first signal terminal and the second signal terminal. The input terminal of the third inverting sub-circuit is connected with the third node, and the output terminal of the third inverting sub-circuit is connected with the fourth node. The third node is coupled to the fourth control node.

[0031] The fourth inverting sub-circuit includes an input terminal, an output terminal, the first signal terminal and the second signal terminal. The input terminal of the fourth inverting sub-circuit is connected with the fourth node, and the output terminal of the fourth inverting sub-circuit is connected with the third node. The second transfer gate includes an input terminal, an output terminal, a first control signal terminal and a second control signal terminal.

[0032] The input terminal of the second transfer gate is connected with the first pulse signal terminal, and the output terminal of the second transfer gate is connected with the second node. The first control signal terminal of the second transfer gate is connected with the fourth node N4, and the second control signal terminal of the second transfer gate is connected with the third node. The third transfer gate includes an input terminal, an output terminal, a first control signal terminal and a second control signal terminal. The input terminal of the third transfer gate is connected with the third control node, the first control signal terminal of the third transfer gate is connected with the third node, and the second control signal terminal of the third transfer gate is connected with the fourth node.

[0033] In another aspect, a light emitting assembly is provided. The light emitting assembly includes a substrate, a driving circuit layer, a plurality of light emitting devices and a plurality of conductive parts.

[0034] The driving circuit layer is disposed on one side of the substrate, and the driving circuit layer includes the driving circuit as described in any of the above embodiments. The plurality of light emitting devices is disposed on the driving circuit layer and away from the one side of the substrate. The plurality of pixel circuits of the driving circuit are respectively connected with the light emitting devices and configured to provide a driving current signal to the connected light emitting devices. The plurality of conductive parts is located in the substrate or on the one side of the substrate away from the driving circuit layer. The substrate is provided with a first via hole exposing at least part of the conductive parts.

[0035] The plurality of conductive parts includes a first conductive part, a plurality of second conductive parts, a third conductive part and a fourth conductive part. The first conductive part is configured to transmit a data signal, the plurality of second conductive parts are respectively configured to transmit different input signals, the third conductive part is configured to transmit a first power signal, and the fourth conductive part is configured to transmit a second power signal.

[0036] In some embodiments, a data signal terminal is connected to the first conductive part. One input signal terminal is connected to one second conductive part, and the number of the second conductive parts is less than or equal to the number of the pixel circuits. The first power signal terminal is connected to the third conductive part. The second power signal terminal is connected to the fourth conductive part.

[0037] In some embodiments, the driving circuit includes three pixel circuits, and the light emitting component includes at least six conductive parts, which include one first conductive part, three second conductive parts, one third conductive part, and one fourth conductive part.

[0038] In some embodiments, the plurality of conductive parts are arranged in multiple rows and multiple columns along a first direction and a second direction, at least one row includes at least two conductive parts arranged along the first direction, and at least one column includes at least two conductive parts arranged along the second direction. The first direction and the second direction intersect. The multiplexing circuit includes a first NAND sub-circuit and a second NAND sub-circuit, the first NAND sub-circuit and the second NAND sub-circuit are arranged along the first direction, and at least part of the first NAND sub-circuit and the second NAND sub-circuit are located between two adjacent conductive parts.

[0039] In some embodiments, the plurality of conductive parts include a first target conductive part and a second target conductive part, in the first direction, the first target conductive part and the second target conductive part are adjacent, and the distance between the first target conductive part and the second target conductive part is greater than or equal to the distance between any two adjacent conductive parts. In the orthogonal projection onto the substrate, at least part of the whole of the first NAND sub-circuit and the second NAND sub-circuit is located between the first target conductive part and the second target conductive part.

[0040] In some embodiments, the light emitting component includes seven conductive parts arranged in three rows and three columns. The first row and the third row each include two conductive parts, and the second row includes three conductive parts. The first column and the third column each include three conductive parts, and the second column includes one conductive part. The two conductive parts in the third row are the first target conductive part and the second target conductive part, respectively. Among them, the first target conductive part and the second target conductive part are both the second conductive part. Or,

[0041] The light-emitting component includes 8 conductive parts, and the 8 conductive parts are arranged in 3 rows and 3 columns. The first row and the second row each include 3 conductive parts, and the third row includes 2 conductive parts. The first column and the third column each include 3 conductive parts, and the second column includes 2 conductive parts. The two conductive parts in the third row are the first target conductive part and the second target conductive part respectively. The first target conductive part and the second target conductive part are both the second conductive part. Alternatively,

[0042] The light-emitting component includes 6 conductive parts, and the 6 conductive parts are arranged in 3 rows and 2 columns. The first row, the second row, and the third row each include 2 conductive parts. The first column and the second column each include 3 conductive parts. The two conductive parts in the third row are the first target conductive part and the second target conductive part respectively, and the first target conductive part and the second target conductive part are both the second conductive part. Alternatively,

[0043] The light-emitting component includes 5 conductive parts, and the 5 conductive parts are arranged in 2 rows and 3 columns. The first row includes 3 conductive parts, and the second row includes 2 conductive parts. The first column and the third column each include 2 conductive parts. The second column includes one conductive part. The two conductive parts in the second row are the first target conductive part and the second target conductive part respectively, and the first target conductive part and the second target conductive part are both the second conductive part.

[0044] In some embodiments, the multiplexing circuit further includes a first inverting sub-circuit, and in the orthogonal projection of the substrate, at least one first inverting sub-circuit is arranged between the boundary of the plurality of NAND gate sub-circuits and the substrate along the first direction.

[0045] In some embodiments, at least one first inverting sub-circuit is located between a target conductive part and another conductive part adjacent to the target conductive part in the second direction.

[0046] In some embodiments, the multiplexing circuit includes three first inverting sub-circuits, and the light-emitting component includes three second conductive parts. One first inverting sub-circuit is located between the first target conductive part and a third target conductive part adjacent to the first target conductive part in the second direction. One first inverting sub-circuit is located between the second target conductive part and a fourth target conductive part adjacent to the second target conductive part in the second direction. The remaining one first inverting sub-circuit is located between the plurality of NAND gate sub-circuits and the second target conductive part. The fourth target conductive part is the second conductive part.

[0047] In some embodiments, the light emitting component includes 7 conductive parts, and the 7 conductive parts are arranged in 3 rows and 3 columns. The first and third rows each include 2 conductive parts, and the second row includes 3 conductive parts. The first and third columns each include 3 conductive parts, and the second column includes 1 conductive part. Among them, the 2 conductive parts in the third row and the conductive part in the third column of the second row are the second conductive parts.

[0048] In some embodiments, the demultiplexing circuit includes a second inverting sub-circuit. In the orthogonal projection onto the substrate, at least one second inverting sub-circuit is arranged along the first direction with the second NAND gate sub-circuit, and / or, along the second direction, at least one second inverting sub-circuit is located on the side of the second NAND gate sub-circuit away from the first boundary of the substrate, and the first boundary is the boundary of the substrate extending along the first direction and adjacent to the second NAND gate sub-circuit.

[0049] In some embodiments, the demultiplexing circuit further includes a second inverting sub-circuit and a first transfer gate, and the substrate has a first middle line extending along the second direction. In the orthogonal projection onto the substrate, along the first direction, a plurality of second NAND gate sub-circuits are located on the first side of the first middle line, and / or, in the orthogonal projection onto the substrate, the second inverting sub-circuit is located on the first side of the first middle line, and / or, in the orthogonal projection onto the substrate, the first transfer gate is located on the first side of the first middle line.

[0050] In some embodiments, the light emitting component includes 7 conductive parts, and the 7 conductive parts are arranged in 3 rows and 3 columns. The first and third rows each include 2 conductive parts, and the second row includes 3 conductive parts. The first and third columns each include 3 conductive parts, and the second column includes 1 conductive part. In the orthogonal projection onto the substrate, the second inverting sub-circuit is located on the side of the conductive part in the second column close to the conductive part in the first column, and / or, the first transfer gate is located on the side of the conductive part in the second column close to the conductive part in the first column.

[0051] In some embodiments, the pixel circuit includes a pulse width modulation sub-circuit, and the pulse width modulation sub-circuit is arranged on the first side of the first middle line.

[0052] In some embodiments, the pixel circuit includes a pulse width modulation sub-circuit. Along the second direction, the second NAND gate sub-circuit, at least one second inverting sub-circuit, the first transfer gate and the pulse width modulation sub-circuit are arranged in sequence.

[0053] In some embodiments, the light emitting component includes 7 conductive parts, and the 7 conductive parts are arranged in 3 rows and 3 columns. The first and third rows each include 2 conductive parts, and the second row includes 3 conductive parts. The first and third columns each include 3 conductive parts, and the second column includes 1 conductive part.

[0054] In the orthogonal projection onto the substrate, the straight line on which the boundary of the conductive part of the second row is located is a first boundary line. Along the second direction, the second NAND sub-circuit, the second inverting sub-circuit, and the first transfer gate are arranged on a first side of the first boundary line, and the pulse width modulation sub-circuit is arranged on a second side of the first boundary line. The first side and the second side of the first boundary line are opposite sides of the first boundary line.

[0055] In some embodiments, the pulse width modulation sub-circuit includes a third inverting sub-circuit, a fourth inverting sub-circuit, a second transfer gate, and a third transfer gate. The second transfer gate and the third transfer gate are arranged along the first direction. Along the second direction, the third inverting sub-circuit and the fourth inverting sub-circuit are located between the second transfer gate and the first transfer gate, and between the third transfer gate and the first transfer gate.

[0056] In some embodiments, the light emitting component includes 7 conductive parts, and the 7 conductive parts are arranged in 3 rows and 3 columns. The first and third rows each include 2 conductive parts, and the second row includes 3 conductive parts. The first and third columns each include 3 conductive parts, and the second column includes 1 conductive part. Among them, the 7 conductive parts include a fifth conductive part, and the fifth conductive part is configured to transmit a pulse signal. Any one of the 2 conductive parts in the first row is the fifth conductive part, and / or the conductive part in the first column of the second row is the third conductive part or the fourth conductive part.

[0057] In some embodiments, along the first direction, at least one first NAND sub-circuit is located on the second side of the first middle line. The first side and the second side of the first middle line are opposite sides of the first middle line.

[0058] In some embodiments, the light emitting component includes 4 first NAND sub-circuits and 3 second NAND sub-circuits, and 3 second NAND sub-circuits and 1 first NAND sub-circuit are located on the first side of the first middle line, and the remaining 3 first NAND sub-circuits are located on the second side of the first middle line.

[0059] In some embodiments, the pixel circuit comprises a current generation sub-circuit. In a projection onto the substrate, the current generation sub-circuit is disposed on a second side of the first median line, and / or the current generation sub-circuit is located on a side of the first NAND gate sub-circuit away from a first boundary of the substrate, the first boundary being a boundary of the substrate extending along the first direction and adjacent to the first NAND gate sub-circuit.

[0060] In some embodiments, the light emitting component comprises 7 conductive parts, and the 7 conductive parts are arranged in 3 rows and 3 columns. The first row and the third row each comprise 2 conductive parts, and the second row comprises 3 conductive parts. The first column and the third column each comprise 3 conductive parts, and the second column comprises 1 conductive part. In a projection onto the substrate, the current generation sub-circuit is located on a side of the conductive part in the second column close to the conductive part in the third column.

[0061] In some embodiments, the substrate has a second median line extending along the first direction, and along the second direction, a plurality of NAND gate sub-circuits are located on a first side of the second median line.

[0062] The current generation sub-circuit comprises a driving transistor, a first transistor and a second transistor. The first electrode of the driving transistor is connected with a fifth node, the second electrode is connected with a sixth node, and the control electrode is connected with a seventh node. The fifth node is coupled to the first power signal terminal, and the sixth node is coupled to the light emitting device. The first electrode of the first transistor is connected with the data signal terminal, the second electrode is connected with the fifth node, and the control electrode is connected with the first control node. The first electrode of the second transistor is connected with the sixth node, the second electrode is connected with the seventh node, and the control electrode is connected with the first control node. Wherein, along the second direction, the first transistor and / or the second transistor are located on the first side of the second median line.

[0063] In some embodiments, the light emitting component comprises 7 conductive parts, and the 7 conductive parts are arranged in 3 rows and 3 columns. Wherein, the first row and the third row each comprise 2 conductive parts, and the second row comprises 3 conductive parts. The first column and the third column each comprise 3 conductive parts, and the second column comprises 1 conductive part.

[0064] In a projection onto the substrate, the NAND gate sub-circuit is located between the 2 conductive parts in the third row, and the first transistor and the second transistor are located between the conductive parts in the second row and the conductive parts in the third row.

[0065] In some embodiments, the light emitting component includes 7 conductive parts arranged in 3 rows and 3 columns. The first and third rows each include 2 conductive parts, and the second row includes 3 conductive parts. The first and third columns each include 3 conductive parts, and the second column includes 1 conductive part. The conductive part in the second row and the second column is the first conductive part.

[0066] In some embodiments, the light emitting component includes a first power supply trace connected to the third conductive part. The first power supply trace encloses at least one enclosed area.

[0067] In some embodiments, the substrate has a second center line extending along the first direction, and the first power supply trace includes a first main trace segment, a second main trace segment, a first connection segment, and a second connection segment. The first main trace segment is connected to the multiplexing circuit. The first main trace segment is located on a first side of the second center line. The second main trace segment is connected to the pixel circuit. The second main trace segment is located on a second side of the second center line. The first connection segment connects the first main trace segment and the second main trace segment. The first connection segment is located between the second and third columns of conductive parts and on a side of the pixel circuit and the transistors included in the multiplexing circuit closer to the third column of conductive parts. The second connection segment connects the first main trace segment and the second main trace segment. The second connection segment is located on a side of the first column of conductive parts away from the second column of conductive parts.

[0068] In some embodiments, the light emitting component includes a second power supply trace connected to the fourth conductive part. The second power supply trace encloses at least one enclosed area.

[0069] In some embodiments, the substrate has a second center line extending along the first direction, and the second power supply trace includes a third main trace segment, a fourth main trace segment, a third connection segment, and a fourth connection segment. The third main trace segment is connected to the multiplexing circuit. The third main trace segment is located on a first side of the second center line. The fourth main trace segment is connected to the pixel circuit of the multiplexing circuit. The fourth main trace segment is located on a second side of the second center line. The third connection segment connects the third main trace segment and the fourth main trace segment. The third connection segment is located between the first and second columns of conductive parts and on a side of the pixel circuit and the transistors included in the multiplexing circuit closer to the second column of conductive parts. The fourth connection segment connects the third main trace segment and the fourth main trace segment. The fourth connection segment is located between the first and second columns of conductive parts and on a side of the pixel circuit and the transistors included in the multiplexing circuit closer to the first column of conductive parts.

[0070] In some embodiments, the light emitting component includes a first circuit trace and a second circuit trace. The first circuit trace includes a first sub-section and a second sub-section. In a projection onto the substrate, the first sub-section overlaps the first via, and the second sub-section is staggered from the first via. In a projection onto the substrate, the second circuit trace is staggered from the first via.

[0071] In some embodiments, a width of the first sub-section is greater than a width of the second circuit trace, and / or, in a projection onto the substrate, a distance between the first sub-section and an adjacent circuit trace is greater than a distance between the second circuit trace and an adjacent circuit trace.

[0072] In some embodiments, a difference between the width of the first sub-section and the width of the second circuit trace is 0.5 μm to 1 μm, and / or, in a projection onto the substrate, a difference between the distance between the first sub-section and an adjacent circuit trace and the distance between the second circuit trace and an adjacent circuit trace is 2 μm to 5 μm.

[0073] In some embodiments, the light emitting device includes a first electrode and a second electrode. The driving circuit layer is provided with a first conductive pad on a side close to the light emitting device, and the first electrode and the second electrode are connected to the first conductive pad. The substrate has a first via that exposes at least part of the conductive portion, and the conductive portion is connected to the driving circuit through the first via and the driving circuit. A projection of the first electrode and / or the second electrode onto the substrate does not overlap a projection of the first via onto the substrate.

[0074] In some embodiments, one of the conductive portions and one of the first vias correspond, and in a projection onto the substrate, the first electrode and / or the second electrode is located between two adjacent rows of the first vias. And / or, the first electrode and / or the second electrode is located between two adjacent columns of the first vias.

[0075] In some embodiments, the conductive portion includes a first conductive part located in the substrate, and a second conductive part located on a side of the substrate away from the light emitting device, and the first conductive part is connected to the second conductive part.

[0076] In some embodiments, the light emitting device further includes a first semiconductor layer, a light emitting functional layer, and a second semiconductor layer arranged in a stack. The first semiconductor layers of the plurality of light emitting devices are in an integrated structure, and the light emitting functional layers and the second semiconductor layers of the plurality of light emitting devices are arranged in a spaced manner.

[0077] In some embodiments, the substrate has a first via hole exposing at least part of the conductive portion, and the conductive portion is connected with the driving circuit through the first via hole. The light emitting component further comprises an adapter block comprising a main body portion and an adapter portion connected with each other, the main body portion covers the first via hole and is connected with the conductive portion. The adapter portion is arranged at one side of the main body portion and is connected with the driving circuit in the driving circuit layer.

[0078] In some embodiments, the driving circuit comprises a P-type transistor and an N-type transistor. The light emitting component further comprises a third semiconductor layer and a fourth semiconductor layer, one of the third semiconductor layer and the fourth semiconductor layer comprises an active portion of the P-type transistor, and the other one comprises an active portion of the N-type transistor. The third semiconductor layer and the fourth semiconductor layer are different layers.

[0079] In another aspect, a display substrate is provided. The display substrate comprises a driving backplane and a plurality of light emitting components arranged in an array, the driving backplane comprises a second conductive pad, and the conductive portions of the plurality of light emitting components are further connected with the second conductive pad.

[0080] In yet another aspect, a display device is provided. The display device comprises the display substrate as described in the above embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0081] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings needed to be used in some embodiments of the present disclosure. Obviously, the drawings described in the following description are only the drawings of some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings described in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual time sequence, etc. of the products involved in the embodiments of the present disclosure.

[0082] FIG. 1 is a structural diagram of a display device according to some embodiments;

[0083] FIG. 2 is a structural diagram of another display device according to some embodiments;

[0084] FIG. 3 is a sectional view along the section line A-A in FIG. 1;

[0085] FIG. 4 is another sectional view along the section line A-A in FIG. 1;

[0086] FIG. 5 is a circuit diagram of a driving circuit according to some embodiments;

[0087] FIG. 6 is a circuit diagram of a pixel circuit according to some embodiments;

[0088] FIG. 7 is a circuit diagram of an inverter sub-circuit, according to some embodiments;

[0089] FIG. 8 is a circuit diagram of a pass gate, according to some embodiments;

[0090] FIG. 9 is a timing diagram of the pixel circuit shown in FIG. 6;

[0091] FIG. 10 is a circuit diagram of a demultiplexing circuit, according to some embodiments;

[0092] FIG. 11 is a circuit diagram of a NAND gate sub-circuit, according to some embodiments;

[0093] FIG. 12 is a timing diagram of the demultiplexing circuit shown in FIG. 10;

[0094] FIG. 13 is a structure diagram of a display substrate, according to some embodiments;

[0095] FIG. 14 is a cross-sectional view along section line B-B in FIG. 13;

[0096] FIG. 15 is another cross-sectional view along section line B-B in FIG. 13;

[0097] FIG. 16A is a structure diagram of an arrangement of conductive portions, according to some embodiments;

[0098] FIG. 16B is a structure diagram of another arrangement of conductive portions, according to some embodiments;

[0099] FIG. 16C is a structure diagram of yet another arrangement of conductive portions, according to some embodiments;

[0100] FIG. 16D is a structure diagram of still another arrangement of conductive portions, according to some embodiments;

[0101] FIG. 17 is a structure diagram of a layout of a driving circuit of a light emitting component, according to some embodiments;

[0102] FIG. 18 is a structure diagram of another arrangement of conductive portions of a light emitting component, according to some embodiments;

[0103] FIG. 19 is a structure diagram of still another arrangement of conductive portions of a light emitting component, according to some embodiments;

[0104] FIG. 20 is a structure diagram of a first power supply trace of a light emitting component, according to some embodiments;

[0105] FIG. 21 is a structure diagram of a first power supply trace of another light emitting component, according to some embodiments;

[0106] FIG. 22 is a structure diagram of a second power supply trace of a light emitting component, according to some embodiments;

[0107] FIG. 23 is a structure diagram of a second power supply routing of another light emitting assembly according to some embodiments;

[0108] FIG. 24 is a structure diagram of a first conductive layer according to some embodiments;

[0109] FIG. 25 is a structure diagram of a first conductive layer and a second conductive layer stack according to some embodiments;

[0110] FIG. 26 is a structure diagram of a second source-drain conductive layer according to some embodiments;

[0111] FIG. 27 is a partial enlarged view of a layout of a driving circuit of a light emitting assembly according to some embodiments. DETAILED DESCRIPTION

[0112] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings. It should be apparent that the described embodiments are only a part of the embodiments of the present disclosure, and not all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0113] Unless otherwise required by context, the term “comprise” and other forms thereof such as “comprises” and “comprising,” are used throughout the specification and claims in an open-ended, inclusive sense, that is, as “including, but not limited to.” In the description of the specification, the terms “one embodiment,” “some embodiments,” “exemplary embodiments,” “example,” “specific example” or “some examples” are used to indicate that the particular feature, structure, material, or characteristic being described is included in at least one embodiment or example of the disclosure. The illustrative appearance of these terms in various places in the specification are not necessarily intended to be referred to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics can be included in any one or more embodiments or examples in any suitable manner.

[0114] Hereinafter, the terms “first” and “second” are used only for the purpose of description, and should not be understood to indicate or imply relative importance or to implicitly indicate the number of the indicated technical features. Thus, the features defined with “first” and “second” can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, the meaning of “a plurality of” is two or more, unless otherwise specified.

[0115] In describing some embodiments, "coupled" and "connected," along with their derivatives, can be used. It should be understood that these terms are not intended as synonyms for each other. Rather, "connected" can be used to indicate that two or more elements are in direct physical or electrical contact with each other. "Coupled" can be used to indicate that two or more elements are in either physical or electrical contact with each other, even at a distance. As will be apparent, "a" or "an" can be used herein to refer to one or more than one (i.e., to "one or more") of the referenced material or object. The disclosure presented herein is not intended to be limited to the particular embodiments described.

[0116] "at least one of A, B, and C" has the same meaning as "at least one of A, B, or C" and includes the following combinations: only A, only B, only C, A and B, A and C, B and C, and A and B and C.

[0117] "A and / or B" includes the following combinations: A alone, B alone, and A and B together.

[0118] As used herein, "about," "approximately," or "around" includes the recited value and the average value within an acceptable range of deviation from the recited value, as determined by one of ordinary skill in the art considering the measurement in question and the error in measuring the particular quantity (i.e., the limitations of the measurement system).

[0119] As used herein, "parallel," "perpendicular," and "equal" include the recited condition and conditions that are approximately the recited condition, the approximation being within an acceptable range of deviation, as determined by one of ordinary skill in the art considering the measurement in question and the error in measuring the particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallel and near parallel, where near parallel can be within an acceptable deviation of, for example, 5°; "perpendicular" includes absolute perpendicular and near perpendicular, where near perpendicular can also be within an acceptable deviation of, for example, 5°. "Equal" includes absolute equality and near equality, where near equality can be within an acceptable deviation of, for example, less than or equal to 5% of either of the two quantities being compared.

[0120] It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate or intervening layers can also be present.

[0121] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are schematic illustrations of idealized embodiments. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will, typically, have jagged edges. Thus, the regions illustrated in the figures are schematic and not drawn to scale. The same can be said of the regions of the devices illustrated in the figures.

[0122] In the circuit provided by the embodiments of the present disclosure, the transistor used can be a thin film transistor (TFT), a metal oxide semiconductor (MOS), or other switching devices with the same characteristics. In the embodiments of the present disclosure, the thin film transistor is taken as an example for illustration.

[0123] In the circuit provided by the embodiments of the present disclosure, the control electrode of each transistor is the gate of the transistor, the first electrode is one of the source and the drain of the thin film transistor, and the second electrode is the other of the source and the drain of the thin film transistor. Since the source and the drain of the thin film transistor can be symmetrical in structure, the source and the drain of the thin film transistor can be indistinguishable in structure, that is, the first electrode and the second electrode of the thin film transistor in the embodiments of the present disclosure can be indistinguishable in structure. Exemplarily, in the case where the transistor is a P-type transistor, the first electrode of the transistor is the source, and the second electrode is the drain; and exemplarily, in the case where the transistor is an N-type transistor, the first electrode of the transistor is the drain, and the second electrode is the source.

[0124] In the embodiments of the present disclosure, the capacitor can be a capacitor device made separately through a process, for example, a capacitor device realized by making a special capacitor electrode, and each capacitor electrode of the capacitor can be realized by a metal layer, a semiconductor layer (for example, doped polysilicon), or the like. The capacitor can also be a parasitic capacitor between transistors, or realized by a transistor itself and other devices and lines, or realized by using a parasitic capacitor between lines of the circuit itself.

[0125] In the embodiments of the present disclosure, the first node, the second node, the third node, the first control node, the second control node, and the like are not actual components, but are convergence points of relevant electrical connections in a circuit diagram, that is, these nodes are nodes equivalent to convergence points of relevant electrical connections in a circuit diagram.

[0126] As shown in FIG. 1, some embodiments of the present disclosure provide a display device 1000, which can be any device that displays images whether in motion (e.g., video) or stationary (e.g., a still image) and whether textual or pictorial.

[0127] For example, referring to FIG. 1, the display device 1000 can be a television, a computer, a portable display product, a wearable device, a vehicle-mounted display, a projection device, a personal digital assistant (PDA), a navigation device, a virtual reality (VR) device, an augmented reality (AR) device, a mixed reality (MR) device, an extended reality (XR) device, or any product or component having a display function.

[0128] For example, as shown in FIG. 1, the display device 1000 can be a portable display product; for example, the display device 1000 can be a mobile phone as shown in FIG. 1. For another example, referring to FIG. 2, the display device 1000 can be a VR device as shown in FIG. 2.

[0129] It should be noted that the display device 1000 can be a flat display device, a curved display device, a foldable display device, or the like, and the shape of the display surface of the display device 1000 can be any one of a circle, an ellipse, a polygon, or an irregular shape.

[0130] In some embodiments, referring to FIGS. 3 and 4, the display device 1000 includes a display substrate 100, a housing 200, and a cover plate 300.

[0131] The housing 200 can be a box-shaped structure having an opening, the display substrate 100 can be disposed in the housing 200, the cover plate 300 is disposed on the light-emitting side of the display substrate 100 and at the opening of the housing 200.

[0132] It should be noted that the display substrate 100 has opposite light-emitting and non-light-emitting sides, the light-emitting side refers to the side of the display substrate 100 that can emit light (the upper side of the display substrate 100 in FIGS. 3 and 4), and the non-light-emitting side refers to the other side opposite to the light-emitting side (the lower side of the display substrate 100 in FIGS. 3 and 4).

[0133] Exemplarily, referring to FIG. 3, the display substrate 100 can directly emit light of multiple colors, so as to realize full-color display. Alternatively, referring to FIG. 4, the display device 1000 further includes an optical film 400, which is arranged between the display substrate 100 and the cover plate 300. For example, the optical film 400 can include multiple film layers. At this time, the display substrate 100 can also emit monochromatic light (for example, white light or blue light), and then the light is filtered or color-converted by the optical film 400, so as to realize full-color display. For example, the display substrate 100 emits blue light, and the optical film 400 maintains the blue light unchanged in some areas and converts the blue light into red light and green light in other areas. For example, the display substrate 100 emits white light, and the optical film 400 filters the white light into blue light in some areas, filters the white light into red light in some areas, and filters the white light into green light in some areas.

[0134] In some embodiments, referring to FIGS. 3 and 4, the display device 1000 can further include a circuit board 500, which is arranged in the housing 200 and located on the non-light-emitting side of the display substrate 100.

[0135] In some embodiments, referring to FIGS. 3 and 5, the display substrate 100 includes a driving circuit 10 and a light-emitting device 20. The driving circuit 10 is connected with a first electrode of the light-emitting device 20, so as to provide a driving current signal to the connected light-emitting device 20 and drive the light-emitting device 20 to emit light. The first electrode of the light-emitting device 20 can be an anode, and the second electrode can be a cathode. The second electrode can be connected to a second power signal end VSS to transmit a second power signal.

[0136] The light-emitting device 20 can include one or more of a Micro Light Emitting Diode (Micro LED) and / or a Mini Light Emitting Diode (Mini LED).

[0137] It should be noted that the size (for example, length) of the Micro LED is less than 50 microns, for example, 10 microns to 50 microns. The size (for example, length) of the Mini LED is 50 microns to 150 microns, for example, 80 microns to 120 microns.

[0138] In the related art, one driving circuit is connected with one light-emitting device, that is, one driving circuit drives one light-emitting device to emit light alone, and each driving circuit needs to provide a display signal (for example, a data signal and a light-emitting control signal) respectively. The circuit of the display substrate is complex, which is not conducive to the design of high resolution of the display device.

[0139] Based on this, referring to Figure 5, the driving circuit 10 provided in some embodiments of this disclosure is connected to the data signal terminal D, the first power signal terminal VDD, the second power signal terminal VSS, and the input signal terminal S.

[0140] Referring to Figures 5 and 6, the driving circuit 10 includes multiple pixel circuits 1 and a multiplexing circuit 2. The pixel circuits 1 are each connected to a light-emitting device 20 and configured to provide driving current signals to the connected light-emitting devices 20. The multiplexing circuit 2 is connected to the multiple pixel circuits 1 to time-division multiplexing the data signal transmitted from the data signal terminal D to different pixel circuits 1. For example, the driving circuit 10 includes three pixel circuits 1 and a multiplexing circuit 2. The three pixel circuits 1 are each connected to a light-emitting device 20, and the multiplexing circuit 2 is connected to the three pixel circuits 1 to time-division multiplexing the data signal transmitted from the data signal terminal D to the three pixel circuits 1. In this case, the driving circuit 10 can drive multiple pixel circuits 1 to generate driving currents while receiving a smaller amount of signal.

[0141] The following illustrative description of an embodiment of this disclosure uses a driving circuit 10 comprising three pixel circuits 1 as an example. However, the implementation of this disclosure is not limited to this, and it is also possible to include two, four, or more pixel circuits 1, as long as the same technical concept is applied.

[0142] In some embodiments, as shown in FIG6, the pixel circuit 1 is directly connected to the first power supply signal terminal VDD, the second power supply signal terminal VSS, the first control node G, the data signal terminal D, and the first node N1.

[0143] The first node N1 is coupled to the light-emitting device 20, such as the first node N1 being coupled to the first electrode of the light-emitting device 20, and the second electrode of the light-emitting device 20 being coupled to the second power signal terminal VSS.

[0144] The aforementioned first power signal terminal VDD is configured to transmit a first power signal, and the second power signal terminal VSS is configured to transmit a second power signal. Both the first and second power signals are constant voltage signals. For example, the first power signal is a high-voltage DC signal, and the second power signal is a low-voltage DC signal. The data signal terminal D is configured to transmit a data signal; the specific timing details are described below, and will not be repeated here.

[0145] It is understood that the structure of the pixel circuit 1 described above includes various types, and can be selected and configured according to actual needs. This disclosure uses the pixel circuit 1 shown in FIG6 as an example to illustrate the embodiments of this disclosure, and details can be found below. However, the implementation of this disclosure is not limited to this, and any other pixel circuit 1 structure can be considered, as long as the same technical concept is applied.

[0146] Exemplarily, referring to FIG. 6, the pixel circuit 1 can include a current generation sub-circuit 11 and a pulse width modulation (PWM) sub-circuit 12. The current generation sub-circuit 11 is configured to generate a driving current signal; and the PWM sub-circuit 12 is configured to control a light emitting time of the light emitting device 20.

[0147] In some examples, referring to FIG. 6, the current generation sub-circuit 11 is directly connected with the first power signal terminal VDD, the second power signal terminal VSS, the first control node G, the second control node R, the data signal terminal D, the third control node EM, the first node N1 and the second node N2.

[0148] For example, referring to FIG. 6, the current generation sub-circuit 11 includes a driving transistor T0, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5 and a sixth transistor T6.

[0149] As shown in FIG. 6, the first electrode of the driving transistor T0 is connected with the fifth node N5, the second electrode is connected with the sixth node N6, and the control electrode is connected with the seventh node N7. The fifth node N5 is coupled to the first power signal terminal VDD, and the sixth node N6 is coupled to the light emitting device 20.

[0150] As shown in FIG. 6, the first electrode of the first transistor T1 is connected with the data signal terminal D, the second electrode is connected with the fifth node N5, and the control electrode is connected with the first control node G.

[0151] As shown in FIG. 6, the first electrode of the second transistor T2 is connected with the sixth node N6, the second electrode is connected with the seventh node N7, and the control electrode is connected with the first control node G.

[0152] As shown in FIG. 6, the first electrode of the third transistor T3 is connected with the first power signal terminal VDD, the second electrode is connected with the fifth node N5, and the control electrode is connected with the third control node EM.

[0153] As shown in FIG. 6, the first electrode of the fourth transistor T4 is connected with the sixth node N6, the second electrode is connected with the first node N1, and the control electrode is connected with the second node N2.

[0154] As shown in FIG. 6, the first electrode of the fifth transistor T5 is connected with the second power signal terminal VSS, the second electrode is connected with the seventh node N7, and the control electrode is connected with the second control node R.

[0155] As shown in FIG. 6, the first electrode of the sixth transistor T6 is connected with the second power signal terminal VSS, the second electrode is connected with the first node N1, and the control electrode is connected with the second control node R. At this time, the fifth transistor T5 and the sixth transistor T6 can reset the seventh node N7 and the first node N1 respectively by using the second power signal transmitted by the second power signal terminal VSS, so that the types of the input display signals required by the current generation sub-circuit 11 can be reduced, thereby reducing the number of different display signals required by the driving circuit 10, simplifying the circuit of the display substrate 100, and reducing the manufacturing cost.

[0156] In addition, referring to FIG. 6, the current generation sub-circuit 11 can further include a capacitor Cst, the first plate of the capacitor Cst is connected with the first power signal terminal VDD, and the second plate is connected with the seventh node N7.

[0157] In the current generation sub-circuit 11 provided by the embodiment of the present disclosure, each transistor can be a P-type transistor or an N-type transistor, which can be set according to the actual situation. For example, referring to the drawings, the driving transistor T0, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 can be P-type transistors, and the fifth transistor T5 and the sixth transistor T6 can be N-type transistors.

[0158] For example, the active layer of the P-type transistor can be low-temperature polysilicon, and the active layer of the fifth transistor T5 and the sixth transistor T6 can be oxide semiconductor. In this way, the advantages of high mobility and fast charging of the low-temperature polysilicon transistor can be combined with the advantage of low leakage current of the oxide transistor, so that the power consumption can be reduced and the display quality can be improved.

[0159] The embodiment of the present disclosure will be described illustratively below by taking the driving transistor T0, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4 as P-type transistors, and the fifth transistor T5 and the sixth transistor T6 as N-type transistors. However, the embodiments of the present disclosure are not limited thereto.

[0160] It should be understood that the width-length ratios of the transistors with the same function can be different in the pixel circuit 1 connected with the light emitting device 20 with different light emitting colors, and the capacitances of the capacitors Cst with the same function can be different.

[0161] Exemplarily, the driving circuit 10 is connected with 3 light emitting devices 20, which include a first light emitting device emitting blue light, a second light emitting device emitting green light, and a third light emitting device emitting red light. The first light emitting device is directly connected with the first current generating sub-circuit 111 (see FIG. 17), the second light emitting device is directly connected with the second current generating sub-circuit 112 (see FIG. 17), and the third light emitting device is directly connected with the third current generating sub-circuit 113 (see FIG. 17).

[0162] The width-length ratio of the channel of the driving transistor T0 of the second current generating sub-circuit 112 is greater than the width-length ratio of the channel of the driving transistor T0 of the third current generating sub-circuit 113. And the width-length ratio of the channel of the driving transistor T0 of the third current generating sub-circuit 113 is greater than the width-length ratio of the channel of the driving transistor T0 of the first current generating sub-circuit 111.

[0163] The width-length ratio of the channel of the third transistor T3 of the second current generating sub-circuit 112 is greater than the width-length ratio of the channel of the third transistor T3 of the third current generating sub-circuit 113. And the width-length ratio of the channel of the third transistor T3 of the third current generating sub-circuit 113 is greater than the width-length ratio of the channel of the third transistor T3 of the first current generating sub-circuit 111.

[0164] The width-length ratio of the channel of the fourth transistor T4 of the second current generating sub-circuit 112 is greater than the width-length ratio of the channel of the fourth transistor T4 of the third current generating sub-circuit 113. And the width-length ratio of the channel of the fourth transistor T4 of the third current generating sub-circuit 113 is greater than the width-length ratio of the channel of the fourth transistor T4 of the first current generating sub-circuit 111.

[0165] The capacitance of the capacitor Cst of the second current generating sub-circuit 112 is greater than the capacitance of the capacitor Cst of the third current generating sub-circuit 113. And the capacitance of the capacitor Cst of the third current generating sub-circuit 113 is greater than the capacitance of the capacitor Cst of the first current generating sub-circuit 111.

[0166] In addition, the first current generating sub-circuit 111 (see FIG. 17) is directly connected with the first pulse width sub-circuit 121 (see FIG. 17). The second current generating sub-circuit 112 (see FIG. 17) is directly connected with the second pulse width sub-circuit 122 (see FIG. 17). The third current generating sub-circuit 113 (see FIG. 17) is directly connected with the third pulse width sub-circuit 123 (see FIG. 17).

[0167] In some examples, referring to FIG. 6, the pulse width modulation sub-circuit 12 is directly connected with the third control node EM, the pulse signal end HF, the fourth control node DT, and the second node N2.

[0168] The pulse signal end HF is configured to transmit a pulse signal. The frequency of the pulse signal can be 3000Hz-60000Hz. For example, the frequency of the pulse signal can be any one of 3000Hz, 5000Hz, 8000Hz, 10000Hz, 15000Hz, 20000Hz, 25000Hz, 30000Hz, 35000Hz, 40000Hz, 45000Hz, 50000Hz, 55000Hz and 60000Hz.

[0169] For example, referring to FIG. 6, the pulse width modulation sub-circuit 12 includes a third inverting sub-circuit I3, a fourth inverting sub-circuit I4, a second transfer gate C2 and a third transfer gate C3.

[0170] Herein, in combination with FIG. 7, the first inverting sub-circuit I1 (see below), the second inverting sub-circuit I2 (see below), the third inverting sub-circuit I3 and the fourth inverting sub-circuit I4 all belong to the inverting sub-circuit I. The inverting sub-circuit I includes an input end INI, an output end OTI, a first signal end V1 and a second signal end V2. One of the first signal end V1 and the second signal end V2 is connected with the first power signal end VDD, and the other is connected with the second power signal end VSS. For example, the first signal end V1 is connected with the first power signal end VDD, and the second signal end V2 is connected with the second power signal end VSS.

[0171] The inverting sub-circuit I is configured to output a low-level signal at the output end OTI of the inverting sub-circuit I when a high-level signal is input at the input end INI of the inverting sub-circuit I, and output a high-level signal at the output end OTI of the inverting sub-circuit I when a low-level signal is input at the input end INI of the inverting sub-circuit I.

[0172] For example, as shown in FIG. 7, the inverting sub-circuit I includes a seventh transistor T7 and an eighth transistor T8. One of the seventh transistor T7 and the eighth transistor T8 is a P-type transistor, and the other is an N-type transistor. For example, the seventh transistor T7 is a P-type transistor, and the eighth transistor T8 is an N-type transistor.

[0173] On this basis, as shown in FIG. 7, the first signal end V1 is connected with the first power signal end VDD, and the second signal end V2 is connected with the second power signal end VSS. The first electrode of the seventh transistor T7 is connected with the first signal end V1, the second electrode is connected with the output end OTI of the inverting sub-circuit I, and the control electrode is connected with the input end INI of the inverting sub-circuit I. The first electrode of the eighth transistor T8 is connected with the second signal end V2, the second electrode is connected with the output end OTI of the inverting sub-circuit I, and the control electrode is connected with the input end INI of the inverting sub-circuit I.

[0174] The first inverting sub-circuit I1 (see below), the second inverting sub-circuit I2 (see below), the third inverting sub-circuit I3, and the fourth inverting sub-circuit I4 are all illustratively described below with the inverting sub-circuit I including the seventh transistor T7 and the eighth transistor T8 as an example. However, the embodiments of the present disclosure are not limited thereto, and any other structure of the inverting sub-circuit I can also be considered as long as the same technical idea is applied.

[0175] Herein, in combination with FIG. 8, the first transfer gate C1, the second transfer gate C2, and the third transfer gate C3 all belong to the transfer gate C. The transfer gate C includes an input end INC, an output end OTC, a first control signal end K1, and a second control signal end K2. The signals transmitted by the first control signal end K1 and the second control signal end K2 are opposite in level.

[0176] For example, as shown in FIG. 8, the transfer gate C includes the ninth transistor T9 and the tenth transistor T10, one of which is a P-type transistor and the other of which is an N-type transistor. For example, the ninth transistor T9 is a P-type transistor, and the tenth transistor T10 is an N-type transistor.

[0177] On this basis, as shown in FIG. 8, the first electrode of the ninth transistor T9 is connected with the input end INC of the first transfer gate C1, the second electrode is connected with the output end OTC of the first transfer gate C1, and the control electrode is connected with the first control signal end K1. The first electrode of the tenth transistor T10 is connected with the input end INC of the first transfer gate C1, the second electrode is connected with the output end OTC of the first transfer gate C1, and the control electrode is connected with the second control signal end K2.

[0178] The first transfer gate C1, the second transfer gate C2, and the third transfer gate C3 are all illustratively described below with the transfer gate C including the ninth transistor T9 and the tenth transistor T10 as an example. However, the embodiments of the present disclosure are not limited thereto, and any other structure of the transfer gate C can also be considered as long as the same technical idea is applied.

[0179] As shown in FIGS. 6 and 7, the input end INI of the third inverting sub-circuit I3 is connected with the third node N3, and the output end OTI of the third inverting sub-circuit I3 is connected with the fourth node N4. The third node N3 is coupled to the fourth control node DT.

[0180] As shown in FIGS. 6 and 7, the input end INI of the fourth inverting sub-circuit I4 is connected with the fourth node N4, and the output end OTI of the fourth inverting sub-circuit is connected with the third node N3.

[0181] As shown in FIG. 6 and FIG. 8, the input end INC of the second transfer gate C2 is connected with the pulse signal end HF, and the output end OTC of the second transfer gate C2 is connected with the second node N2. The first control signal end K1 of the second transfer gate C2 is connected with the fourth node N4, and the second control signal end K2 of the second transfer gate T is connected with the third node.

[0182] As shown in FIG. 6 and FIG. 8, the input end INC of the third transfer gate C3 is connected with the third control node EM, the first control signal end K1 of the third transfer gate C3 is connected with the third node, and the second control signal end K2 of the third transfer gate C3 is connected with the fourth node N4.

[0183] At this time, the pulse width modulation sub-circuit 12 transmits the third control signal received at the third control node EM or the pulse signal received at the pulse signal end HF to the second node N2 in response to the control signal received at the fourth control node DT, so as to control the light emitting time of the light emitting device 20. The specific timing can be referred to below.

[0184] FIG. 9 is a timing diagram of the pixel circuit shown in FIG. 6. The working process of the pixel circuit 1 shown in FIG. 6 will be exemplarily described below in combination with the timing diagram shown in FIG. 9. As shown in FIG. 9, the pixel circuit 1 includes a reset stage P1, a data writing stage P2 and a light emitting stage P3 which are sequentially performed.

[0185] In the reset stage P1, the first control signal received at the first control node G is a high level signal, the reset signal received at the second control node R is a high level signal, the third control signal received at the third control node EM is a high level signal, and the fourth control signal received at the fourth control node DT is a high level signal.

[0186] That is, the fifth transistor T5, the sixth transistor T6 and the third transfer gate C3 (the transistor included in the third transfer gate C3) are turned on, and other transistors are all turned off. The second power supply signal received at the second power supply signal end VSS is transmitted to the first node N1 and the seventh node N7, so as to reset the first node N1 and the seventh node N7.

[0187] In the data writing stage P2, the first control signal received at the first control node G is a low level signal, the reset signal received at the second control node R is a low level signal, the third control signal received at the third control node EM is a high level signal, and the fourth control signal received at the fourth control node DT is a high level signal.

[0188] That is, the driving transistor T0, the first transistor T1, the second transistor T2, and the third pass transistor C3 (the transistor included in the third pass transistor C3) are turned on, and other transistors are turned off. The data signal received at the data signal terminal D is written to the seventh node N7 after being compensated by the threshold voltage of the second transistor T2, so as to form a corresponding driving current signal in the light emitting stage P3.

[0189] In the light emitting stage P3, the first control signal received at the first control node G is a high-level signal, the reset signal received at the second control node R is a low-level signal, the third control signal received at the third control node EM is a low-level signal, and the fourth control signal received at the fourth control node DT is a high-level signal.

[0190] That is, the driving transistor T0, the third transistor T3, the third pass transistor C3 (the transistor included in the third pass transistor C3), and the fourth transistor T4 are turned on, and other transistors are turned off. At this time, the driving transistor T0 generates a driving current signal under the action of the fifth node N5 and the seventh node N7. And the driving current signal can be transmitted to the light emitting device 20 to drive the light emitting device 20 to emit light.

[0191] In some embodiments, as shown in FIG. 5 and FIG. 10, the demultiplexing circuit 2 is connected with the first power signal terminal VDD, the second power signal terminal VSS, the data signal terminal D, the first control node G, and the input signal terminal S. It should be noted that the first power signal terminal VDD and the second power signal terminal VSS are not shown in FIG. 10.

[0192] The demultiplexing circuit 2 is configured to transmit the first control signal to the first control node G connected with the plurality of pixel circuits 1 respectively in response to the input signal transmitted by the input signal terminal S, so as to write the data signal received at the data signal terminal D to different pixel circuits 1 in time division. At this time, the demultiplexing circuit 2 can directly transmit the first control signal to the first control node G, control the corresponding transistors (for example, the first transistor T1 and the second transistor T2) in different pixel circuits 1 to be turned on in time division, so as to write the data signal received at the data signal terminal D to the seventh node N7 of different pixel circuits 1 in time division. In this way, the pixel circuit 1 can be directly connected with the data signal terminal D, and there is no need to design a gating circuit between the pixel circuit 1 and the data signal terminal D, so the structure is simple.

[0193] In addition, the multiplexing circuit 2 can also be connected with the second control node R, the third control node EM and the fourth control node DT. The multiplexing circuit 2 can be configured to transmit a third control signal and a fourth control signal to the third control node EM and the fourth control node DT connected with the plurality of pixel circuits 1 respectively in response to the input signal transmitted by the input signal terminal S, so as to control the light emitting time of the light emitting device 20. In addition, the multiplexing circuit 2 can be configured to transmit a reset signal to the second control node R connected with the plurality of pixel circuits 1 in response to the input signal transmitted by the input signal terminal S, so as to reset the first node N1 and the seventh node N7. Of course, the second control node R, the third control node EM and the fourth control node DT can also not be directly connected with the multiplexing circuit 2, that is, the multiplexing circuit 2 does not need to transmit the reset signal, the third control signal and the fourth control signal to the pixel circuit 1. At this time, the second control node R, the third control node EM and the fourth control node DT can be directly connected with the conductive part 43 to receive the reset signal, the third control signal and the fourth control signal provided by an external circuit (such as a source driving circuit or a gate driving circuit).

[0194] At this time, the driving circuit 10 does not need to introduce a signal (reset signal) for controlling the reset of the first node N1 and the seventh node N7, and a control signal (third control signal) for controlling the light emitting of the light emitting device 20. The reset and light emitting control of the plurality of pixel circuits 1 can be realized only by the input signal transmitted by the input signal terminal S, which is beneficial to reduce the number of signals needed to be introduced by the driving circuit 10. Details can be referred to below.

[0195] It can be understood that the structure of the multiplexing circuit 2 described above is not unique and can be selected and arranged according to actual needs. The embodiment of the present disclosure is schematically described by taking the multiplexing circuit 2 shown in FIG. 10 as an example, and details can be referred to below. However, the embodiments of the present disclosure are not limited thereto.

[0196] Exemplarily, referring to FIG. 10, the multiplexing circuit 2 includes a plurality of first inverting sub-circuits I1, a plurality of control wires 21 and a plurality of first NAND sub-circuits AN1.

[0197] Herein, the first NAND sub-circuit AN1 and the second NAND sub-circuit AN2 (see below) both belong to the NAND sub-circuit AN in combination with FIG. 11. The NAND sub-circuit AN includes an input terminal INA, an output terminal OTA, a third signal terminal V3 and a fourth signal terminal V4. One of the third signal terminal V3 and the fourth signal terminal V4 is connected with the first power signal terminal VDD, and the other is connected with the second power signal terminal VSS. For example, the third signal terminal V3 is connected with the first power signal terminal VDD, and the fourth signal terminal V4 is connected with the second power signal terminal VSS.

[0198] The above NAND sub-circuit AN is configured to output a high level signal at the output terminal OTA of the NAND sub-circuit AN when a low level signal is input at at least one input terminal INA of the NAND sub-circuit AN, and output a low level signal at the output terminal OTA of the NAND sub-circuit AN when high level signals are input at all input terminals INA of the NAND sub-circuit AN.

[0199] For example, as shown in FIG. 11, the NAND sub-circuit AN includes three input terminals INA. At this time, the NAND sub-circuit AN includes an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15 and a sixteenth transistor T16.

[0200] Among the eleventh transistor T11 and the twelfth transistor T12, one is a P-type transistor and the other is an N-type transistor. Among the thirteenth transistor T13 and the fourteenth transistor T14, one is a P-type transistor and the other is an N-type transistor. Among the fifteenth transistor T15 and the sixteenth transistor T16, one is a P-type transistor and the other is an N-type transistor.

[0201] For example, the eleventh transistor T11, the thirteenth transistor T13 and the fifteenth transistor T15 are P-type transistors, and the twelfth transistor T12, the fourteenth transistor T14 and the sixteenth transistor T16 are N-type transistors.

[0202] On this basis, as shown in the figure, the third signal terminal V3 is connected with the first power signal terminal VDD, and the fourth signal terminal V4 is connected with the second power signal terminal VSS. The control electrodes of the eleventh transistor T11, the thirteenth transistor T13 and the fifteenth transistor T15 are respectively connected with the output terminal OTA of the NAND sub-circuit AN, the first electrodes are all connected with the third signal terminal V3, and the second electrodes are all connected with the output terminal OTA of the NAND sub-circuit AN. The control electrodes of the twelfth transistor T12, the fourteenth transistor T14 and the sixteenth transistor T16 are respectively connected with the output terminal OTA of the NAND sub-circuit AN, the first electrode of the twelfth transistor T12 is connected with the fourth signal terminal V4, the second electrode of the twelfth transistor T12 is connected with the first electrode of the fourteenth transistor T14, the second electrode of the fourteenth transistor T14 is connected with the first electrode of the sixteenth transistor T16, and the second electrode of the sixteenth transistor T16 is connected with the output terminal OTA of the NAND sub-circuit AN.

[0203] At this time, the output terminal OTA of the NAND sub-circuit AN outputs a low level signal when a high level signal is input at at least one input terminal INA of the NAND sub-circuit AN, and outputs a high level signal when low level signals are input at all input terminals INA of the NAND sub-circuit AN.

[0204] The first NAND sub-circuit AN1 and the second NAND sub-circuit AN2 are both NAND sub-circuits AN including an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15 and a sixteenth transistor T16, and in the case that a low-level signal is input to at least one input terminal INA of the NAND sub-circuit AN, a high-level signal is output from an output terminal OTA of the NAND sub-circuit AN; in the case that high-level signals are input to all input terminals INA of the NAND sub-circuit AN, a low-level signal is output from the output terminal OTA of the NAND sub-circuit AN. However, the embodiments of the present disclosure are not limited thereto, and any other structure of the NAND sub-circuit AN can also be considered as long as the same technical idea is applied.

[0205] Referring to FIGS. 10 and 11, the input terminal INI of the first inverting sub-circuit I1 is connected with the input signal terminal S. The output terminal OTI of the first inverting sub-circuit I1 is connected with a control wire 21.

[0206] Referring to FIGS. 10 and 11, the plurality of control wires 21 are divided into a plurality of control wire groups 210, each of which includes two control wires 21. In the same control wire group 210, one of the two control wires 21 is connected with the input signal terminal S, and the other is connected with the output terminal OTI of the first inverting sub-circuit I1 connected with the input signal terminal S.

[0207] Referring to FIGS. 10 and 11, the input terminal INA of the first NAND sub-circuit AN1 is connected with the control wire 21, and in the same first NAND sub-circuit AN1, the control wires 21 connected with different input terminals INA belong to different control wire groups 210. In any two different first NAND sub-circuits AN1, the control wires 21 connected with at least one input terminal INA are different. The output terminal OTA of the first NAND sub-circuit AN1 is connected with the first control node G or the third control node EM.

[0208] At this time, the first control nodes G connected with the plurality of pixel circuits 1 can be directly connected with the output terminals OTA of one first NAND sub-circuit AN1 respectively. The multiplexing circuit 2 can output first control signals to the output terminals OTA of the plurality of first NAND sub-circuits AN1 respectively in response to the clock signal received at the input signal terminal S, to control the pixel circuit 1 to write the data signal. In addition, the multiplexing circuit 2 can also output third control signals to the output terminals OTA of at least one first NAND sub-circuit AN1 in response to the clock signal received at the input signal terminal S, to provide the third control signals to the pixel circuit 1, and the specific timing can be referred to below, which will not be described here in detail.

[0209] On this basis, the third control nodes EM of the plurality of pixel circuits 1 are respectively connected with the output terminal OTA of the same first NAND sub-circuit AN1. In this way, the third control nodes EM of the pixel circuits 1 are directly connected with the output terminal OTA of the first NAND sub-circuit AN1, and no other circuit design is needed between the pixel circuits 1 and the output terminal OTA of the first NAND sub-circuit AN1, and the structure is simple.

[0210] For example, as shown in FIGS. 10 and 11, the demultiplexing circuit 2 is connected with three signal input terminals S, and the demultiplexing circuit 2 includes three first inverting sub-circuits I1, six control lines 21, and four first NAND sub-circuits AN1, and each first NAND sub-circuit AN1 includes three input terminals INA.

[0211] Among them, the three input signal terminals S connected with the demultiplexing circuit 2 are S0, S1 and S2 respectively, the first control nodes G connected with the three pixel circuits 1 are G1, G2 and G3 respectively, the three first inverting sub-circuits I1 are I10, I11 and I12 respectively, and the four first NAND sub-circuits AN1 are AN10, AN11, AN12 and AN13 respectively.

[0212] The pixel circuits 1 connected with the first control nodes G1, G2 and G3 are respectively connected with the first light emitting device, the second light emitting device and the third light emitting device mentioned above, which are exemplarily described below, but the embodiments of the present disclosure are not limited thereto. That is, the first control nodes G1, G2 and G3 are directly connected with the first current generating sub-circuit 111, the second current generating sub-circuit 112 and the third current generating sub-circuit 113 respectively.

[0213] As shown in FIGS. 10 and 11, the six control lines 21 include the first control line 211, the second control line 212, the third control line 213, the fourth control line 214, the fifth control line 215 and the sixth control line 216 in turn, the first control line 211 and the second control line 212 are a control line group 210, the third control line 213 and the fourth control line 214 are a control line group 210, and the fifth control line 215 and the sixth control line 216 are a control line group 210. Two control lines 21 of a control line group 210 are connected to the same input signal terminal S.

[0214] As shown in FIGS. 10 and 11, the input terminals INI of the three first inverting sub-circuits I1 are respectively connected with an input signal terminal S, and the first control line 211, the third control line 213 and the fifth control line 215 are respectively connected with the output terminals OTI of the three first inverting sub-circuits I1. The second control line 212, the fourth control line 214 and the sixth control line 216 are respectively connected with an input signal terminal S.

[0215] For example, the input terminals INI of the first inverting sub-circuits I10, I11 and I12 are connected to the input signal terminals S0, S1 and S2 respectively. The first control line 211, the third control line 213 and the fifth control line 215 are connected to the output terminals OTI of the first inverting sub-circuits I12, I11 and I10 respectively. The second control line 212, the fourth control line 214 and the sixth control line 216 are connected to the input signal terminals S2, S1 and S0 respectively.

[0216] As shown in FIG. 10 and FIG. 11, in the four first NAND sub-circuits AN1, the three input terminals INA of one first NAND sub-circuit AN1 are connected to the second control line 212, the third control line 213 and the fifth control line 215 respectively, and the output terminal OTA is connected to the third control node EM connected to all the pixel circuits 1. The output terminals OTA of the remaining three first NAND sub-circuits AN1 are connected to the first control nodes G connected to one pixel circuit 1 respectively. In the remaining three first NAND sub-circuits AN1, the three input terminals INA of one first NAND sub-circuit AN1 are connected to the second control line 212, the third control line 213 and the sixth control line 216 respectively. The three input terminals INA of one first NAND sub-circuit AN1 are connected to the second control line 212, the fourth control line 214 and the fifth control line 215 respectively. The three input terminals INA of one first NAND sub-circuit AN1 are connected to the second control line 212, the fourth control line 214 and the sixth control line 216 respectively.

[0217] For example, the three input terminals INA of the first NAND sub-circuit AN10 are connected to the second control line 212, the third control line 213 and the fifth control line 215 respectively, and the output terminal OTA is connected to the third control node EM connected to all the pixel circuits 1. The output terminals OTA of the first NAND sub-circuits AN11, AN12 and AN13 are connected to the first control nodes G1, G2 and G3 respectively. The three input terminals INA of the first NAND sub-circuit AN11 are connected to the second control line 212, the third control line 213 and the sixth control line 216 respectively. The three input terminals INA of the first NAND sub-circuit AN12 are connected to the second control line 212, the fourth control line 214 and the fifth control line 215 respectively. The three input terminals INA of the first NAND sub-circuit AN13 are connected to the second control line 212, the fourth control line 214 and the sixth control line 216 respectively.

[0218] In addition, as shown in FIG. 10 and FIG. 11, the multiplexing circuit 2 can further include a plurality of second NAND sub-circuits AN2, a plurality of second inverting sub-circuits I2 and a plurality of first transfer gates C1.

[0219] Referring to FIGS. 10 and 11, the input terminal INA of the second NAND sub-circuit AN2 is connected with the control wire 21, and the control wires 21 connected with different input terminals INA of the same second NAND sub-circuit AN2 belong to different control wire groups 210. At least one input terminal INA of any two different NAND sub-circuits AN (including the first NAND sub-circuit AN1 and the second NAND sub-circuit AN2) is connected with different control wires 21.

[0220] Referring to FIGS. 10 and 11, the input terminal INI of the second inversion sub-circuit I2 is connected with the output terminal OTA of the second NAND sub-circuit AN2, and the output terminal OTI of the second inversion sub-circuit I2 is connected with the second control signal terminal K2 of the first transfer gate C1.

[0221] Referring to FIGS. 10 and 11, the input terminal INC of the first transfer gate C1 is connected with the data signal terminal D, and the output terminal OTC of the first transfer gate C1 is connected with the fourth control node DT. The first control signal terminal K1 of the first transfer gate C1 is connected with the output terminal OTA of the second NAND sub-circuit AN2, and the second control signal terminal K2 of the first transfer gate C1 is connected with the output terminal OTI of the second inversion sub-circuit I2.

[0222] On this basis, as shown in FIGS. 10 and 11, the second control nodes R connected with the plurality of pixel circuits 1 can be connected with the output terminal OTI of the same second inversion sub-circuit I2, so as to transmit a signal (reset signal) for controlling the first node N1 and the seventh node N7 to reset to the plurality of pixel circuits 1, thereby reducing the number of signals required to be led out by the driving circuit 10.

[0223] At this time, the multiplexing circuit 2 can output reset signals to the output terminals OTI of the plurality of second inversion sub-circuits I2 respectively in response to the clock signal received at the input signal terminal S, so as to control the pixel circuit 1 to reset the first node N1 and the seventh node N7. In addition, the multiplexing circuit 2 can also output a fourth control signal to the output terminal OTC of the first transfer gate C1 in response to the clock signal received at the input signal terminal S, and the pixel circuit 1 controls the light emitting time of the light emitting device 20 by combining the fourth control signal with the third control signal output by the output terminal OTA of the first NAND sub-circuit AN1, and the specific timing can be referred to below, which will not be described herein again.

[0224] For example, as shown in FIGS. 10 and 11, the multiplexing circuit 2 includes three second inversion sub-circuits I2, six control wires 21, three second NAND sub-circuits AN2 and three first transfer gates C1.

[0225] The three input signal terminals S connected by the multiplexing circuit 2 are S0, S1 and S2, respectively, and the fourth control nodes DT connected by the three pixel circuits 1 are DT1, DT2 and DT3, respectively. The three second inverting sub-circuits I2 are I20, I21 and I22, respectively, the three second NAND sub-circuits AN2 are AN20, AN21 and AN22, respectively, and the three first transfer gates C1 are C10, C11 and C12, respectively.

[0226] The pixel circuit 1 connected with the fourth control nodes DT1, DT2 and DT3, respectively, is connected with the first light emitting device, the second light emitting device and the third light emitting device mentioned above, respectively, as an example, but the embodiment of the present disclosure is not limited thereto. That is, the fourth control nodes DT1, DT2 and DT3 are directly connected with the first pulse width sub-circuit 121, the second pulse width sub-circuit 122 and the third pulse width sub-circuit 123, respectively.

[0227] As shown in FIGS. 10 and 11, the six control wires 21 include the first control wire 211, the second control wire 212, the third control wire 213, the fourth control wire 214, the fifth control wire 215 and the sixth control wire 216 in turn adjacent to each other, the first control wire 211 and the second control wire 212 are a control wire group 210, the third control wire 213 and the fourth control wire 214 are a control wire group 210, and the fifth control wire 215 and the sixth control wire 216 are a control wire group 210. Two control wires 21 of one control wire group 210 are connected to the same input signal terminal S.

[0228] As shown in FIGS. 10 and 11, the input terminals INI of the three second inverting sub-circuits I2 are connected with the output terminals OTA of one second NAND sub-circuit AN2, respectively. The input terminals INC of the three first transfer gates C1 are connected with the same data signal terminal D, the output terminals OTC of the three first transfer gates C1 are connected with the fourth control nodes DT of one pixel circuit 1, respectively, the first control signal terminals K1 of the three first transfer gates C1 are connected with the output terminals OTA of one second NAND sub-circuit AN2, respectively, and the second control signal terminals K2 of the three first transfer gates C1 are connected with the output terminals OTI of one second inverting sub-circuit I2, respectively. In addition, the output terminal of one second inverting sub-circuit I2 is also connected with the second control nodes R of all the pixel circuits 1.

[0229] For example, the input ends INI of the three second inverting sub-circuits I20, I11 and I12 are connected with the output ends OTA of the second NAND sub-circuits AN20, A21 and A22 respectively. The input ends INC of the three first transfer gates C10, C11 and C12 are connected with the same data signal end D, and the output ends OTC of the three first transfer gates C10, C11 and C12 are connected with the fourth control nodes DT1, DT2 and DT3 respectively. The first control signal ends K1 of the three first transfer gates C10, C11 and C12 are connected with the output ends OTA of the second NAND sub-circuits AN20, A21 and A22 respectively, and the second control signal ends K2 of the three first transfer gates C10, C11 and C12 are connected with the output ends OTI of the second inverting sub-circuits I20, I11 and I12 respectively. In addition, the output end of the second inverting sub-circuit I20 is also connected with the second control node R connected with all the pixel circuits 1.

[0230] It should be noted that the first control node G1 and the fourth control node DT1 are directly connected with the same pixel circuit 1, the first control node G2 and the fourth control node DT2 are directly connected with the same pixel circuit 1, and the first control node G3 and the fourth control node DT3 are directly connected with the same pixel circuit 1.

[0231] As shown in FIGS. 10 and 11, each second NAND sub-circuit AN2 includes three input ends INA. Among the three second NAND sub-circuits AN2, the three input ends INA of one second NAND sub-circuit AN2 are connected with the first control wire 211, the third control wire 213 and the sixth control wire 216 respectively. The three input ends INA of one second NAND sub-circuit AN2 are connected with the first control wire 211, the fourth control wire 214 and the fifth control wire 215 respectively. The three input ends INA of one second NAND sub-circuit AN2 are connected with the first control wire 211, the fourth control wire 214 and the sixth control wire 216 respectively.

[0232] For example, the three input ends INA of the second NAND sub-circuit AN20 are connected with the first control wire 211, the third control wire 213 and the sixth control wire 216 respectively. The three input ends INA of the second NAND sub-circuit AN21 are connected with the first control wire 211, the fourth control wire 214 and the fifth control wire 215 respectively. The three input ends INA of the second NAND sub-circuit AN22 are connected with the first control wire 211, the fourth control wire 214 and the sixth control wire 216 respectively.

[0233] That is, the first NAND sub-circuit AN11 connected to the second control line 212, the third control line 213 and the sixth control line 216, and the second NAND sub-circuit AN20 connected to the first control line 211, the third control line 213 and the sixth control line 216 are connected to the same pixel circuit 1.

[0234] The first NAND sub-circuit AN12 connected to the second control line 212, the fourth control line 214 and the fifth control line 215, and the second NAND sub-circuit AN21 connected to the first control line 211, the fourth control line 214 and the fifth control line 215 are connected to the same pixel circuit 1.

[0235] The first NAND sub-circuit AN13 connected to the second control line 212, the fourth control line 214 and the sixth control line 216, and the second NAND sub-circuit AN22 connected to the first control line 211, the fourth control line 214 and the sixth control line 216 are connected to the same pixel circuit 1.

[0236] The input end INI of the second inverting sub-circuit I20 connected to the second control node R and connected to all the pixel circuits 1, and the output end OTA of the second NAND sub-circuit AN20 connected to the first control line 211, the third control line 213 and the sixth control line 216 are connected. At this time, the timing of the multiplexing circuit 2 is shown in the timing chart of Fig. 12.

[0237] Fig. 12 is a timing chart of the multiplexing circuit shown in Fig. 10. The working process of the multiplexing circuit 2 shown in Fig. 10 will be described exemplarily below in conjunction with the timing chart shown in Fig. 12.

[0238] As shown in Fig. 10 and Fig. 12, the multiplexing circuit 2 comprises a first stage P10, a second stage P20, a third stage P30, a fourth stage P40, a fifth stage P50, a sixth stage P60 and a seventh stage P70 in sequence.

[0239] In the first stage P10, the input signal end S0 inputs a high level signal, and the input signal ends S1 and S2 both input low level signals. At this time, the first inverting sub-circuits I10, I11 and I12 output low level signals, high level signals and high level signals respectively. The first control line 211, the second control line 212, the third control line 213, the fourth control line 214, the fifth control line 215 and the sixth control line 216 transmit high level signals, low level signals, high level signals, low level signals, low level signals and high level signals respectively.

[0240] On this basis, the first NAND sub-circuit AN10, AN11, AN12 and AN13 all output high level signals. That is, the third control node EM, the first control node G1, G2 and G3 are all high level signals. All the first transistors T1 are cut off, and the data signal cannot be transmitted to the data signal end D. The second NAND sub-circuit AN20, AN21 and AN22 respectively output high level signals, low level signals and high level signals.

[0241] At this time, the second inverting sub-circuit I20, I11 and I12 respectively output high level signals, low level signals and low level signals. The second control node R is connected with the output end OTI of the second inverting sub-circuit I20, that is, the second control node R of all the pixel circuits 1 outputs high level signals to reset the first node 1 and the seventh node N7.

[0242] And the first control signal end K1 of the first transfer gate C10, C11 and C12 respectively receives low level signals, high level signals and high level signals, the second control signal end K2 of the first transfer gate C10, C11 and C12 respectively receives high level signals, low level signals and low level signals, the first transfer gate C10 is turned on, and the first transfer gates C11 and C12 are cut off. The data signal at the data signal end can be transmitted to the fourth control node DT1 to write the pulse signal or the third control signal to control the light-emitting time length of the corresponding light-emitting device 20 of the pixel circuit 1 connected with the first transfer gate C10.

[0243] In the second stage P20, the input signal end S1 inputs high level signals, and the input signal ends S0 and S2 input low level signals. At this time, the first inverting sub-circuit I10, I11 and I12 respectively output high level signals, low level signals and high level signals. The first control wire 211, the second control wire 212, the third control wire 213, the fourth control wire 214, the fifth control wire 215 and the sixth control wire 216 respectively transmit high level signals, low level signals, low level signals, high level signals, high level signals and low level signals.

[0244] On this basis, the first NAND sub-circuit AN10, AN11, AN12 and AN13 all output high level signals. That is, the third control node EM, the first control node G1, G2 and G3 are all high level signals. All the first transistors T1 are cut off, and the data signal cannot be transmitted to the data signal end D. The second NAND sub-circuit AN20, AN21 and AN22 respectively output high level signals, low level signals and high level signals.

[0245] At this time, the second inverting sub-circuit I20, I11 and I12 output low level signal, high level signal and low level signal respectively. The second control node R is connected with the output terminal OTI of the second inverting sub-circuit I20, and the fifth transistor T5 and the sixth transistor T6 are cut off.

[0246] The first control signal end K1 of the first transfer gate C10, C11 and C12 receives high level signal, low level signal and high level signal respectively, the second control signal end K2 of the first transfer gate C10, C11 and C12 receives low level signal, high level signal and low level signal respectively, and the first transfer gate C11 is turned on, and the first transfer gate C10 and C12 are cut off. The data signal at the data signal end can be transmitted to the fourth control node DT1 to write pulse signal or third control signal to the second node N2, so as to control the light emitting time length of the light emitting device 20 corresponding to the pixel circuit 1 connected with the first transfer gate C11.

[0247] In the third phase P30, the input signal end S0 and S1 input high level signal, and the input signal end S2 input low level signal. At this time, the first inverting sub-circuit I10, I11 and I12 output low level signal, low level signal and high level signal respectively. The first control wire 211, the second control wire 212, the third control wire 213, the fourth control wire 214, the fifth control wire 215 and the sixth control wire 216 transmit high level signal, low level signal, low level signal, high level signal, low level signal and high level signal respectively.

[0248] On this basis, the first NAND sub-circuit AN10, AN11, AN12 and AN13 all output high level signal. That is, the third control node EM, the first control node G1, G2 and G3 are all high level signal. All the first transistor T1 is cut off, and the data signal cannot be transmitted to the data signal end D. The second NAND sub-circuit AN20, AN21 and AN22 output high level signal, high level signal and low level signal respectively.

[0249] At this time, the second inverting sub-circuit I20, I11 and I12 output low level signal, low level signal and high level signal respectively. The second control node R is connected with the output terminal OTI of the second inverting sub-circuit I20, and the fifth transistor T5 and the sixth transistor T6 are cut off.

[0250] And, the first control signal end K1 of the first transfer gate C10, C11 and C12 receives high level signal, high level signal and low level signal respectively, the second control signal end K2 of the first transfer gate C10, C11 and C12 receives low level signal, low level signal and high level signal respectively, the first transfer gate C12 is turned on, and the first transfer gate C10 and C11 are turned off. The data signal at the data signal end can be transmitted to the fourth control node DT1 to write pulse signal or third control signal to the second node N2, thereby controlling the light emitting time length of the light emitting device 20 connected with the pixel circuit 1 corresponding to the first transfer gate C12.

[0251] In the fourth stage P40, the input signal end S0 and S2 input high level signal, and the input signal end S1 input low level signal. At this time, the first inverting sub-circuit I10, I11 and I12 outputs low level signal, high level signal and low level signal respectively. The first control wire 211, the second control wire 212, the third control wire 213, the fourth control wire 214, the fifth control wire 215 and the sixth control wire 216 transmit low level signal, high level signal, high level signal, low level signal, low level signal and high level signal respectively.

[0252] On this basis, the second NAND gate sub-circuit AN20, AN21 and AN22 all output high level signal. The second inverting sub-circuit I20, I11 and I12 all output low level signal. At this time, the first control signal end K1 of the first transfer gate C10, C11 and C12 all receives high level signal, the second control signal end K2 of the first transfer gate C10, C11 and C12 all receives low level signal, and the first transfer gate C10, C11, C12 is turned off, and the data signal cannot be transmitted to the fourth control node DT1.

[0253] And, the second inverting sub-circuit I20, I11 and I12 all output low level signal. The second control node R is connected with the output end OTI of the second inverting sub-circuit I20, and the fifth transistor T5 and the sixth transistor T6 are turned off.

[0254] In addition, the first NAND gate sub-circuit AN10, AN11, AN12 and AN13 outputs high level signal, low level signal, high level signal and high level signal respectively. That is, the third control node EM, the first control node G2 and G3 are all high level signal, and the first control node G1 is low level signal. The first transistor T1 of the pixel circuit 1 connected with the first control node G1 is turned on, and the data signal at the data signal end can be transmitted to the seventh node N7 to write into the pixel circuit 1.

[0255] In the fifth stage P50, the input signal terminals S1 and S2 input high level signals, and the input signal terminal S0 inputs a low level signal. At this time, the first inverting sub-circuits I10, I11 and I12 output high level signals, low level signals and low level signals respectively. The first control line 211, the second control line 212, the third control line 213, the fourth control line 214, the fifth control line 215 and the sixth control line 216 transmit low level signals, high level signals, low level signals, high level signals, high level signals and low level signals respectively.

[0256] On this basis, the second NAND sub-circuits AN20, AN21 and AN22 all output high level signals. The second inverting sub-circuits I20, I11 and I12 all output low level signals. At this time, the first control signal terminals K1 of the first transfer gates C10, C11 and C12 all receive high level signals, the second control signal terminals K2 of the first transfer gates C10, C11 and C12 all receive low level signals, the first transfer gates C10, C11 and C12 are cut off, and the data signals cannot be transmitted to the fourth control node DT1.

[0257] In addition, the second inverting sub-circuits I20, I11 and I12 all output low level signals. The second control node R is connected with the output terminal OTI of the second inverting sub-circuit I20, and the fifth transistor T5 and the sixth transistor T6 are cut off.

[0258] In addition, the first NAND sub-circuits AN10, AN11, AN12 and AN13 output high level signals, high level signals, low level signals and high level signals respectively. That is, the third control node EM, the first control nodes G1 and G3 are all high level signals, and the first control node G2 is a low level signal. The first transistor T1 of the pixel circuit 1 connected with the first control node G2 is turned on, and the data signal at the data signal terminal can be transmitted to the seventh node N7 and written into the pixel circuit 1.

[0259] In the sixth stage P60, the input signal terminals S1, S2 and S3 all input high level signals. At this time, the first inverting sub-circuits I10, I11 and I12 all output low level signals. The first control line 211, the second control line 212, the third control line 213, the fourth control line 214, the fifth control line 215 and the sixth control line 216 transmit low level signals, high level signals, low level signals, high level signals, low level signals and high level signals respectively.

[0260] On this basis, the second NAND sub-circuit AN20, AN21 and AN22 all output high level signals. The second inverting sub-circuit I20, I11 and I12 all output low level signals. At this time, the first control signal end K1 of the first transfer gate C10, C11 and C12 all receives high level signals, the second control signal end K2 of the first transfer gate C10, C11 and C12 all receives low level signals, the first transfer gate C10, C11 and C12 are cut off, and the data signal cannot be transmitted to the fourth control node DT1.

[0261] And, the second inverting sub-circuit I20, I11 and I12 all output low level signals. The second control node R is connected with the output end OTI of the second inverting sub-circuit I20, and the fifth transistor T5 and the sixth transistor T6 are cut off.

[0262] In addition, the first NAND sub-circuit AN10, AN11, AN12 and AN13 respectively output high level signals, high level signals, high level signals and low level signals. That is, the third control node EM, the first control node G1 and G2 are all high level signals, and the first control node G3 is low level signal. The first transistor T1 of the pixel circuit 1 connected with the first control node G3 is turned on, and the data signal at the data signal end can be transmitted to the seventh node N7 and written into the pixel circuit 1.

[0263] In the seventh stage P70, the input signal end S0 and S1 all input low level signals, and the input signal end S2 inputs high level signal. At this time, the first inverting sub-circuit I10, I11 and I12 respectively output high level signals, high level signals and low level signals. The first control wire 211, the second control wire 212, the third control wire 213, the fourth control wire 214, the fifth control wire 215 and the sixth control wire 216 respectively transmit low level signals, high level signals, high level signals, low level signals, high level signals and low level signals.

[0264] On this basis, the second NAND sub-circuit AN20, AN21 and AN22 all output high level signals. The second inverting sub-circuit I20, I11 and I12 all output low level signals. At this time, the first control signal end K1 of the first transfer gate C10, C11 and C12 all receives high level signals, the second control signal end K2 of the first transfer gate C10, C11 and C12 all receives low level signals, the first transfer gate C10, C11 and C12 are cut off, and the data signal cannot be transmitted to the fourth control node DT1.

[0265] And, the second inverting sub-circuit I20, I11 and I12 all output low level signals. The second control node R is connected with the output end OTI of the second inverting sub-circuit I20, and the fifth transistor T5 and the sixth transistor T6 are cut off.

[0266] In addition, the first NAND sub-circuits AN10, AN11, AN12 and AN13 output low-level signals, high-level signals, high-level signals and high-level signals, respectively. That is, the first control nodes G1, G2 and G3 are all high-level signals. All the first transistors T1 are turned off, and the data signal cannot be transmitted to the data signal terminal D. The third control node EM is a low-level signal, and the third transistor T3 is turned on to drive the light emitting device 20 to emit light.

[0267] It should be noted that the intervals between the first stage P10, the second stage P20, the third stage P30, the fourth stage P40, the fifth stage P50, the sixth stage P60 and the seventh stage P70 in FIG. 12 can be understood as the delay time of the rising and falling edges of the signals.

[0268] Referring to FIG. 13, the display substrate 100 provided by some embodiments of the present disclosure includes a driving backplane 30 and a light emitting assembly 40 fixed on the driving backplane 30.

[0269] Referring to FIGS. 14 and 15, the light emitting assembly 40 includes a substrate 41, a light emitting device 20, a driving circuit layer 42 and a plurality of conductive parts 43. The driving circuit layer 42 is disposed on one side of the substrate 41, and the light emitting device 20 is disposed on the side of the driving circuit layer 42 away from the substrate 41. The driving circuit layer 42 includes the driving circuit 10 of any of the above embodiments, and the plurality of pixel circuits 1 of the driving circuit 10 are respectively connected with the light emitting device 20 and configured to provide a driving current signal to the connected light emitting device 20. The plurality of conductive parts 43 are located in the substrate 41, or on the side of the substrate 41 away from the driving circuit layer 42.

[0270] The plurality of conductive parts 43 can include a first conductive part 431, a plurality of second conductive parts 432, a third conductive part 433 and a fourth conductive part 434. The first conductive part 431 is configured to transmit a data signal. The plurality of second conductive parts 432 are configured to respectively transmit different input signals. The third conductive part 433 is configured to transmit a first power signal. The fourth conductive part 434 is configured to transmit a second power signal.

[0271] As shown in FIG. 13, the plurality of light emitting assemblies 40 are arranged in multiple rows and multiple columns, i.e., in an array. Each row includes at least two light emitting assemblies 40 arranged along a first direction X, and each column includes at least two light emitting assemblies 40 arranged along a second direction Y. The first direction X intersects the second direction Y. For example, the first direction X and the second direction Y are perpendicular.

[0272] Referring to FIG. 13, the light emitting assembly 40 provided by some embodiments of the present disclosure can include the driving circuit 10 of any of the above embodiments and a plurality of light emitting devices 20. The driving backboard 30 includes a plurality of signal lines. The driving circuit 10 of the light emitting assembly 40 is connected to the signal lines of the driving backboard 30 to receive display signals and drive the light emitting devices 20 of the light emitting assembly 40 to emit light.

[0273] For example, referring to FIGS. 14 and 15, the driving backboard 30 can include a plurality of first conductive pads 310 exposed to one side of the driving backboard 30.

[0274] In addition, the light emitting assembly 40 includes a plurality of light emitting devices 20 having the same light emitting color. Alternatively, the light emitting assembly 40 can include first, second, and third light emitting devices having different light emitting colors. For example, the first light emitting device emits light of a first color, the second light emitting device emits light of a second color, and the third light emitting device emits light of a third color. The first, second, and third colors constitute three primary colors, for example, the first color is blue, the second color is green, and the third color is red.

[0275] The following exemplary description of some embodiments of the present disclosure is based on the light emitting assembly 40 including one first light emitting device, one second light emitting device, and one third light emitting device. However, the embodiments of the present disclosure are not limited thereto, and any other number and light emitting color of light emitting devices can also be considered as long as the same technical idea is applied.

[0276] In some embodiments, referring to FIG. 14, the light emitting assembly 40 includes a plurality of independently encapsulated light emitting devices 20. Each light emitting device 20 includes a first semiconductor layer 201, a light emitting functional layer 202, a second semiconductor layer 203, an encapsulation layer 204, a first electrode 205, and a second electrode 206. The first semiconductor layer 201, the light emitting functional layer 202, the second semiconductor layer 203, and the encapsulation layer 204 are sequentially stacked, and the encapsulation layer 204 covers the first semiconductor layer 201, the light emitting functional layer 202, and the second semiconductor layer 203. The first electrode 205 and the second electrode 206 penetrate the encapsulation layer 204 and are connected to the first semiconductor layer 201 and the second semiconductor layer 203, respectively.

[0277] In addition, the first semiconductor layer 201, the light emitting functional layer 202, the second semiconductor layer 203, and the encapsulation layer 204 of the plurality of light emitting devices 20 are spaced apart; that is, the first semiconductor layer 201, the light emitting functional layer 202, the second semiconductor layer 203, and the encapsulation layer 204 of the plurality of light emitting devices 20 are separated from each other. In this way, the second electrodes 206 of the respective light emitting devices 20 are independent of each other, and the signals received by the second electrodes 206 of the plurality of light emitting devices 20 do not affect each other.

[0278] It should be noted that the projection of the second semiconductor layer 203 of the plurality of light emitting devices 20 on the substrate 41 covers the orthographic projection of the plurality of conductive portions 43 on the substrate 41.

[0279] In some other embodiments, referring to FIG. 15, the light emitting assembly 40 includes a plurality of light emitting devices 20 integrated in a package. The light emitting device 20 includes a first semiconductor layer 201, a light emitting functional layer 202, a second semiconductor layer 203, a packaging layer 204, a first electrode 205 and a second electrode 206. The first semiconductor layer 201, the light emitting functional layer 202, the second semiconductor layer 203 and the packaging layer 204 are sequentially stacked, and the packaging layer 204 covers the first semiconductor layer 201, the light emitting functional layer 202 and the second semiconductor layer 203. The first electrode 205 and the second electrode 206 penetrate the packaging layer 204 and are respectively connected to the first semiconductor layer 201 and the second semiconductor layer 203.

[0280] In addition, the first semiconductor layer 201 and the packaging layer 204 of the plurality of light emitting devices 20 are in an integrated structure, and the light emitting functional layer 202, the second semiconductor layer 203 and the packaging layer 204 are spaced apart; that is, the light emitting functional layer 202, the second semiconductor layer 203 and the packaging layer 204 of the plurality of light emitting devices 20 are separated from each other. In this way, the plurality of light emitting devices 20 can share one second electrode 206 connected to the second power signal terminal VSS, and the plurality of light emitting devices 20 in the light emitting assembly 40 have fewer bonding times with the first conductive pads P mentioned below, which is beneficial to improve the production yield.

[0281] It should be noted that the projection of the second semiconductor layer 203 of the plurality of light emitting devices 20 on the substrate 41 covers the orthographic projection of the plurality of conductive portions 43 on the substrate 41.

[0282] In addition, referring to FIG. 14 and FIG. 15, the light emitting assembly 40 can further include a light filtering layer 440 and / or a color conversion layer 450, which are arranged on the side of the light emitting device 20 away from the driving backboard 30. FIG. 14 illustrates an example in which the light emitting assembly 40 includes the light filtering layer 440, and FIG. 15 illustrates an example in which the light emitting assembly 40 includes the color conversion layer 450.

[0283] As shown in FIG. 14, the light filtering layer 440 includes a plurality of light filtering portions 4410 and a light shielding portion 4420. The plurality of light filtering portions 4410 includes a first light filtering portion, a second light filtering portion and a third light filtering portion. For example, the first light filtering portion is a blue light filtering portion, the second light filtering portion is a green light filtering portion, and the third light filtering portion is a red light filtering portion (for example, the first light filtering portion can only transmit blue light, the second light filtering portion can only transmit green light, and the third light filtering portion can only transmit red light). The light shielding portion 4420 is arranged between different light filtering portions 4410 to separate the light filtering portions 4410 and prevent color mixing between different light filtering portions 4410, which affects the display effect.

[0284] As shown in FIG. 15, the color conversion layer 450 includes a defined portion 4510 and an optical functional portion 4520. The defined portion 4510 has a plurality of openings defined thereon, and one optical functional portion 4520 is located in one opening. The material of the optical functional portion 4520 includes quantum dots. The quantum dots can emit light of a predetermined color under an additional electric field or light pressure. For example, the quantum dots can absorb short-wave blue light and emit long-wave red light and green light. This characteristic enables the quantum dots to change the color of light emitted by a light source.

[0285] In some embodiments, referring to FIGS. 14 and 15, the light emitting assembly 40 includes a substrate 41, a driving circuit layer 42, and a plurality of conductive portions 43.

[0286] As shown in FIGS. 14 and 15, the material of the substrate 41 can include a flexible material or a rigid material. The flexible material includes at least one of epoxy, triazine, polyethylene naphthalate, polyethylene terephthalate, silicone, polyether sulfone, polyarylate, polyetherimide, polyethylene naphthalate, polyphenylene sulfide, polycarbonate, cellulose acetate propionate, and polyimide. The rigid material includes a glass material including silicon dioxide as a main component. For example, the material of the substrate 41 can include a flexible material. For example, the material of the substrate 41 can be polyethylene terephthalate. In this case, the driving circuit layer 42 can be directly formed on the substrate 41 by a thin film growth technique. The substrate 41 can serve as a buffer protection to improve production yield.

[0287] It should be noted that the thickness of the substrate 41 can be, for example, 2 μm to 5 μm. The substrate 41 can have a single-layer structure or a multi-layer structure. For example, in the case of the multi-layer structure, the substrate 41 can include a base 411 and a passivation layer 412 disposed on the base 411. The passivation layer 412 is disposed on the base 411. The material of the passivation layer 412 can include an inorganic insulating material such as silicon nitride, silicon oxynitride, and silicon oxide.

[0288] As shown in FIGS. 14 and 15, the driving circuit layer 42 is disposed on one side of the substrate 41, and the light emitting device 20 is disposed on the side of the driving circuit layer 42 away from the substrate 41. The driving circuit layer 42 includes the driving circuit 10 of any one of the above-described embodiments. For example, the driving circuit layer 42 has a first conductive pad P on the side close to the light emitting device 20. The first electrode 205 and the second electrode 206 can be connected to the first conductive pad P to connect the light emitting device 20 to the driving circuit 10 in the driving circuit layer 42. The first conductive pad P can be a solder pad.

[0289] As shown in FIG. 14 and FIG. 15, the plurality of conductive portions 43 are located in the substrate 41, or are located on a side of the substrate 41 away from the driving circuit layer 42. The substrate 41 is provided with a first via hole H1, and the first via hole H1 exposes at least part of the conductive portions 43. The shape of the orthogonal projection of the conductive portions 43 on the substrate 41 can be a circle, an ellipse, or any other polygonal shape, and the present disclosure does not make a specific limitation thereon.

[0290] For example, the conductive portions 43 are located in the substrate 41, and the conductive portions 43 are continuously distributed on a surface of the substrate 41 away from the driving circuit layer 42. That is, the conductive portions 43 are coplanar with the surface of the substrate 41 away from the driving circuit layer 42.

[0291] For another example, the conductive portions 43 include a first conductive portion 403 located in the substrate 41, and a second conductive portion 410 located on a side of the substrate 41 away from the light emitting device 20, and the first conductive portion 403 is connected to the second conductive portion 420. For example, the first conductive portion 403 is in contact with the second conductive portion 420.

[0292] In this case, during the display of a frame of image, the pixel circuit 1 of the driving circuit 10 can continuously provide a driving current for the light emitting device 20, so that the light emitting device 20 continuously emits light, and thus the flicker of the display device 1000 is low, and the display effect can be improved. Moreover, each light emitting device 20 can be controlled by an independent pixel circuit 1, and the light emitting device 20 has high independent controllability, which is beneficial to improve the brightness uniformity and contrast, and improve the display effect.

[0293] Based on the above driving circuit 10, referring to FIG. 16A, the plurality of conductive portions 43 can include a first conductive portion 431, a plurality of second conductive portions 432, a third conductive portion 433, and a fourth conductive portion 434. The first conductive portion 431 is configured to transmit a data signal. The plurality of second conductive portions 432 are configured to respectively transmit different input signals. The third conductive portion 433 is configured to transmit a first power signal. The fourth conductive portion 434 is configured to transmit a second power signal.

[0294] In this case, the number of the conductive portions 43 of the light emitting assembly 40 is small, and the structure of the light emitting assembly 40 can be simplified. Moreover, the bonding points of the light emitting assembly 40 and the driving backboard 30 can be reduced, and the bonding yield of the light emitting assembly 40 and the driving backboard 30 can be improved, and the production yield can be improved.

[0295] For example, the first conductive portion 431 can be connected to a data signal end D. One second conductive portion 432 can be connected to one input signal end S. The third conductive portion 433 can be connected to a first power signal end VDD. The fourth conductive portion 434 can be connected to a second power signal end VSS.

[0296] In addition, the number of the second conductive parts 432 is less than or equal to the number of the pixel circuits 1. At this time, the plurality of pixel circuits 1 in one light emitting component 40 can be provided with only one first conductive part 431, and the data signal is written to the plurality of pixel circuits 1 in time division, so as to reduce the number of the conductive parts 43 of the light emitting component 40, thereby simplifying the structure of the light emitting component 40, improving the bonding yield of the light emitting component 40 and the driving backboard 30, and improving the production yield.

[0297] At this time, in the case that the driving circuit 10 includes 3 pixel circuits 1, the light emitting component 40 can include at least 6 conductive parts 43, and the 6 conductive parts 43 include one first conductive part 431, three second conductive parts 432, one third conductive part 433 and one fourth conductive part 434. That is, in the case that the light emitting component 40 includes 3 pixel circuits 1, only 6 conductive parts 43 need to be provided.

[0298] In addition, as shown in FIG. 16A, the plurality of conductive parts 43 can further include one fifth conductive part 435, and the fifth conductive part 435 can be connected with the pulse signal end HF, for example.

[0299] Exemplarily, as shown in FIG. 6, FIG. 10 and FIG. 16A, the driving circuit 10 includes 3 pixel circuits 1, and the light emitting component 40 includes 7 conductive parts 43, and the 7 conductive parts 43 include one first conductive part 431, three second conductive parts 432, one third conductive part 433, one fourth conductive part 434 and one fifth conductive part 435. That is, in the case that the light emitting component 40 includes 3 pixel circuits 1, only 7 conductive parts 43 need to be provided.

[0300] In some embodiments, referring to FIG. 16A, the plurality of conductive parts 43 are arranged into multiple rows and multiple columns along the first direction X and the second direction Y, at least one row includes at least two conductive parts 43 arranged along the first direction X, and at least one column includes at least two conductive parts 43 arranged along the second direction Y. The first direction X and the second direction Y intersect, for example, the first direction X is perpendicular to the second direction Y.

[0301] In the case that the plurality of conductive parts 43 are uniformly distributed along the first direction X and the second direction Y, that is, in the first direction X, the distance between the adjacent two conductive parts 43 is equal; in the second direction Y, the distance between the adjacent two conductive parts is equal. Herein, in the first direction X and / or the second direction Y, the size of the conductive part 43 is equal to or greater than 10 μm, and the distance between the adjacent two conductive parts 43 is greater than or equal to 20 μm. For example, the shape of the orthographic projection of the conductive part 43 on the substrate 41 is a square, the side length of the square is 30 μm, and the pitch of the conductive part 43 in the first direction X and the second direction Y is 75 μm.

[0302] Exemplarily, as shown in FIG. 16A, the light-emitting assembly 40 includes 7 conductive parts 43 arranged in 3 rows and 3 columns. The first and third rows each include 2 conductive parts 43, and the second row includes 3 conductive parts 43. The first and third columns each include 3 conductive parts 43, and the second column includes 1 conductive part 43.

[0303] It should be noted that the 7 conductive parts 43 can also be arranged in 2 rows and 4 columns, in which any column includes only 1 conductive part 43, and the other columns each include 2 conductive parts 43.

[0304] In this article, the "first row", "second row", and "third row" are the order from top to bottom based on the drawing, which is exemplarily described with reference to the drawing. The "first column", "second column", and "third column" are the order from left to right based on the drawing, which is exemplarily described with reference to the drawing.

[0305] Exemplarily, as shown in FIG. 16B, the light-emitting assembly 40 includes 8 conductive parts 43 arranged in 3 rows and 3 columns; the first and second rows each include 3 conductive parts 43, and the third row includes 2 conductive parts 43. The first and third columns each include 3 conductive parts 43, and the second column includes 2 conductive parts 43.

[0306] Exemplarily, as shown in FIG. 16C, the light-emitting assembly 40 includes 6 conductive parts 43 arranged in 3 rows and 2 columns. The first, second, and third rows each include 2 conductive parts 43. The first and second columns each include 3 conductive parts 43.

[0307] Exemplarily, as shown in FIG. 16D, the light-emitting assembly includes 5 conductive parts 43 arranged in 2 rows and 3 columns. The first row includes 3 conductive parts 43, and the second row includes 2 conductive parts 43. The first and third columns each include 2 conductive parts 43. The second column includes 1 conductive part 43.

[0308] Hereinafter, the 7 conductive parts 43 are arranged in 3 rows and 3 columns; the first and third rows each include 2 conductive parts 43, and the second row includes 3 conductive parts 43. The first and third columns each include 3 conductive parts 43, and the second column includes 1 conductive part 43 are taken as examples to schematically describe the embodiments of the present disclosure. However, the embodiments of the present disclosure are not limited thereto, and any other arrangement can also be considered as long as the same technical idea is applied.

[0309] In some embodiments, referring to FIG. 10, FIG. 16A and FIG. 17, the first NAND sub-circuits AN1 and the second NAND sub-circuits AN2 are arranged along the first direction X and at least partially located between two adjacent conductive parts 43. For example, all the first NAND sub-circuits AN1 and the second NAND sub-circuits AN2 are located between two adjacent conductive parts 43. In this way, the NAND sub-circuits AN can be distributed in a concentrated manner, the internal connection wires of the NAND sub-circuits AN are more compact, and the layout space of the driving circuit 10 can be reduced.

[0310] For example, referring to FIG. 16A, the plurality of conductive parts 43 includes a first target conductive part M1 and a second target conductive part M2. In the first direction X, the first target conductive part M1 and the second target conductive part M2 are adjacent, and the distance between the first target conductive part M1 and the second target conductive part M2 is greater than or equal to the distance between any two adjacent conductive parts 43. That is, the first target conductive part M1 and the second target conductive part M2 are the two conductive parts 43 that are farthest apart and adjacent in the plurality of conductive parts 43.

[0311] On this basis, referring to FIG. 9, FIG. 16A and FIG. 17, in the orthographic projection onto the substrate 41, at least part of the whole of the first NAND sub-circuits AN1 and the second NAND sub-circuits AN2 is located between the first target conductive part M1 and the second target conductive part M2. In this case, considering that the first NAND sub-circuits AN1 and the second NAND sub-circuits AN2 occupy a large area, placing them between the first target conductive part M1 and the second target conductive part M2 that are far apart has a high space utilization rate, the circuit structure is more compact, and the layout space of the driving circuit 10 can be reduced.

[0312] For example, as shown in FIG. 16A and FIG. 17, the light emitting assembly 40 includes 7 conductive parts 43 arranged in 3 rows and 3 columns. The first row and the third row each include 2 conductive parts 43, and the second row includes 3 conductive parts 43. The first column and the third column each include 3 conductive parts 43, and the second column includes 1 conductive part 43. The two conductive parts 43 in the third row are the first target conductive part M1 and the second target conductive part M2, respectively.

[0313] For example, as shown in FIG. 16B, the light emitting component 40 includes 8 conductive parts 43 arranged in 3 rows and 3 columns. The first and second rows each include 3 conductive parts 43, and the third row includes 2 conductive parts 43. The first and third columns each include 3 conductive parts 43, and the second column includes 2 conductive parts 43. The two conductive parts 43 in the third row are a first target conductive part M1 and a second target conductive part M2, both of which are second conductive parts 432. At this time, the second control node R or the third control node EM of the pixel circuit 1 can be connected to an external circuit through the conductive parts 43 to receive a reset signal or a third control signal.

[0314] For example, as shown in FIG. 16C, the light emitting component includes 6 conductive parts 43 arranged in 3 rows and 2 columns. The first, second, and third rows each include 2 conductive parts 43. The first and second columns each include 3 conductive parts 43. The two conductive parts 43 in the third row are a first target conductive part M1 and a second target conductive part M2. Both of the first and second target conductive parts M1 and M2 are second conductive parts 432. At this time, the pixel circuit 1 may, for example, be a pixel circuit 1 that is not connected to the pulse signal end HF, for example, a pixel circuit 1 that only includes the current generation sub-circuit 11, or a pulse width modulation sub-circuit 12 that does not need to access a pulse signal.

[0315] For example, as shown in FIG. 16D, the light emitting component includes 5 conductive parts 43 arranged in 2 rows and 3 columns. The first row includes 3 conductive parts 43, and the second row includes 2 conductive parts 43. The first and third columns each include 2 conductive parts 43. The second column includes one conductive part 43. The two conductive parts 43 in the second row are a first target conductive part M1 and a second target conductive part M2. Both of the first and second target conductive parts M1 and M2 are second conductive parts 432. At this time, the pixel circuit 1 may, for example, be a pixel circuit 1 that is not connected to the pulse signal end HF, and the multiplexing circuit 2 only accesses two input signal ends S. For example, the pixel circuit 1 only includes the current generation sub-circuit 11, or the pulse width modulation sub-circuit 12 does not need to access a pulse signal, and the multiplexing circuit 2 is only connected to two pixel circuits 1.

[0316] At this time, the first target conductive part M1 and the second target conductive part M2 are both second conductive parts 432. In this way, the distance between the second conductive part 432 and the NAND sub-circuit AN is closer, which is beneficial to reducing the length of the connection wire between the second conductive part 432 and the NAND sub-circuit AN, reducing the resistance, reducing the power consumption, and reducing the signal delay.

[0317] In some embodiments, referring to FIG. 9 and FIG. 17, there are at least two NAND sub-circuits AN (including a first NAND sub-circuit AN1 and a second NAND sub-circuit AN2) symmetrically arranged in the first direction X. As such, any two NAND sub-circuits AN are symmetrically arranged in the first direction X. In this way, the circuit layout is regular, facilitating maintenance, and the structure is more compact.

[0318] In addition, the third signal terminal V3 of the NAND sub-circuit AN can be connected to the third conductive part 433 through the first power supply line 510, and the input terminal INA of the NAND sub-circuit AN can be connected to the second conductive part 432 through the input line 520. At this time, in view of the symmetric arrangement of the two adjacent NAND sub-circuits AN, there are at least two NAND sub-circuits AN symmetrically arranged in the first direction X, so that a first power supply line 510 and an input line 520 can be shared, saving circuit layout space, making the structure more compact, and facilitating the improvement of pixel density.

[0319] In some embodiments, referring to FIG. 9 and FIG. 17, in the orthogonal projection onto the substrate 41, the first inverting sub-circuit I1 is arranged between the plurality of NAND sub-circuits AN and the edge of the substrate 41 along the first direction X.

[0320] For example, referring to FIG. 9, FIG. 16A and FIG. 17, the at least one first inverting sub-circuit I1 is located between the target conductive part M (including the first target conductive part M1 and the second target conductive part M2) and another conductive part 43 adjacent to it in the second direction Y.

[0321] For example, as shown in FIG. 9, FIG. 16A and FIG. 17, the light emitting component 40 includes three second conductive parts 432, and the multiplexing circuit 2 includes three first inverting sub-circuits I1. One first inverting sub-circuit I1 is located between the first target conductive part M1 and the third target conductive part M3, which is a conductive part 43 adjacent to the first target conductive part M1 in the second direction Y. One first inverting sub-circuit I1 is located between the second target conductive part M2 and the fourth target conductive part M4, which is a conductive part 43 adjacent to the second target conductive part M2 in the second direction Y. The remaining one first inverting sub-circuit I1 is located between the plurality of NAND sub-circuits AN and the second target conductive part M2.

[0322] At this time, the fourth target conductive part M4 is the second conductive part 432. In this way, the second conductive part 432 and the first inverting sub-circuit I1 located between the plurality of NAND sub-circuits AN and the second target conductive part M2 are closer, facilitating the reduction of the length of the connection line between them, the reduction of resistance, the reduction of power consumption, and the reduction of signal delay.

[0323] For example, the light emitting component 40 includes 7 conductive parts 43 arranged in 3 rows and 3 columns. The first and third rows each include 2 conductive parts 43, and the second row includes 3 conductive parts 43. The first and third columns each include 3 conductive parts 43, and the second column includes 1 conductive part 43. Among them, the 2 conductive parts 43 of the third row and the conductive part 43 of the second row and the third column are the second conductive parts 432.

[0324] In some embodiments, referring to FIG. 9, FIG. 16A and FIG. 17, the demultiplexing circuit 2 includes a second inverting sub-circuit I2. In the orthographic projection onto the substrate 41, at least one second inverting sub-circuit I2 is arranged along the first direction X with a second NAND gate sub-circuit AN2, and / or, along the second direction Y, at least one second inverting sub-circuit I2 is located on the side of the second NAND gate sub-circuit AN2 away from the first boundary L1 of the substrate 41, the first boundary L1 being the boundary of the substrate 41 extending along the first direction X and adjacent to the second NAND gate sub-circuit AN2. In this way, the distance between the second inverting sub-circuit I2 and the second NAND gate sub-circuit AN2 is closer, which helps to reduce the length of the connection wire between the second inverting sub-circuit I2 and the second NAND gate sub-circuit AN2, has small resistance, low power consumption, and can reduce signal delay.

[0325] For example, as shown in FIG. 9, FIG. 16A and FIG. 17, along the second direction Y, all the second inverting sub-circuits I2 are located on the side of the second NAND gate sub-circuits AN2 away from the first boundary L1 of the substrate 41.

[0326] In some embodiments, referring to FIG. 9, FIG. 16A and FIG. 17, the substrate 41 has a first median line Z1 extending along the second direction Y, and in the orthographic projection onto the substrate 41, along the first direction X, a plurality of second NAND gate sub-circuits AN2 are located on the first side of the first median line Z1. In this case, the second NAND gate sub-circuits AN2 are arranged on the first side of the first median line Z1, and the circuits connected to the second NAND gate sub-circuits AN2 can be arranged on the first side of the first median line Z1, so that the distance between the second NAND gate sub-circuits AN2 is closer, which helps to shorten the connection wire with the second NAND gate sub-circuits AN2.

[0327] On this basis, in the orthographic projection onto the substrate 41, the second inverting sub-circuit I2 is located on the first side of the first median line Z1, and the first transfer gate C1 is located on the first side of the first median line Z1. At this time, the length of the connection wire between the second NAND gate sub-circuit AN2 and the second inverting sub-circuit I2 and the first transfer gate C1 can be reduced, and the length of the connection wire between the second inverting sub-circuit I2 and the first transfer gate C1 can also be reduced.

[0328] For example, as shown in FIG. 9, FIG. 16A and FIG. 17, the light emitting component 40 includes 7 conductive parts 43 arranged in 3 rows and 3 columns. The first and third rows each include 2 conductive parts 43, and the second row includes 3 conductive parts 43. The first and third columns each include 3 conductive parts 43, and the second column includes 1 conductive part 43. At this time, in the orthographic projection onto the substrate 41, the second inverting sub-circuit I2 is located on the side of the conductive part 43 of the second column close to the conductive part 43 of the first column, and / or the first transfer gate C1 is located on the side of the conductive part 43 of the second column close to the conductive part 43 of the first column.

[0329] On this basis, referring to FIG. 9, FIG. 16A and FIG. 17, the pulse width modulation sub-circuit 12 is arranged on the first side of the first middle line Z1. In this way, the length of the connection wire between the pulse width modulation sub-circuit 12 and the first transfer gate C1 can be reduced.

[0330] In addition, referring to FIG. 9, FIG. 16A and FIG. 17, along the second direction Y, the second NAND gate sub-circuit AN2, the at least one second inverting sub-circuit I2, the first transfer gate C1 and the pulse width modulation sub-circuit 12 are arranged in sequence. And, along the second direction Y, the third inverting sub-circuit I3 and the fourth inverting sub-circuit I4, for example, can be located between the second transfer gate C2 and the first transfer gate C1, and between the third transfer gate C3 and the first transfer gate C1, which facilitates reducing the length of the connection wire between the third inverting sub-circuit I3, the fourth inverting sub-circuit I4 and the first transfer gate C1.

[0331] For example, as shown in FIG. 16A, the light emitting component includes 7 conductive parts 43 arranged in 3 rows and 3 columns. The first and third rows each include 2 conductive parts 43, and the second row includes 3 conductive parts 43. The first and third columns each include 3 conductive parts 43, and the second column includes 1 conductive part 43.

[0332] At this time, in the orthographic projection onto the substrate 41, the straight line where the boundary of the conductive part 43 of the second row close to the conductive part 43 of the first row is located is the first boundary line L2. Along the second direction Y, the second NAND gate sub-circuit AN2, the second inverting sub-circuit I2 and the first transfer gate C1 are arranged on the first side of the first boundary line L2, and the pulse width modulation sub-circuit 12 is arranged on the second side of the first boundary line L2. It should be noted that the first side and the second side of the first boundary line L2 are opposite sides of the first boundary line L2.

[0333] On this basis, referring to FIG. 16A, any one of the 2 conductive parts 43 of the first row is the fifth conductive part 435. And / or, the conductive part 43 of the second row and the first column is the third conductive part 433 or the fourth conductive part 434.

[0334] For example, as shown in FIG. 16A, the conductive part 43 in the first row and the first column is the fourth conductive part 434, the conductive part 43 in the first row and the third column is the fifth conductive part 435, and the conductive part 43 in the second row and the first column is the third conductive part 433.

[0335] For example, as shown in FIG. 18, the conductive part 43 in the first row and the first column is the fifth conductive part 435, the conductive part 43 in the first row and the third column is the fourth conductive part 434, and the conductive part 43 in the second row and the first column is the third conductive part 433. In this way, the connection wire between the fifth conductive part 435 and the second transfer gate C2 is short, does not overlap with other connection wires, and can reduce parasitic capacitance, reduce signal delay, and improve display effect.

[0336] For example, as shown in FIG. 19, the conductive part 43 in the first row and the first column is the third conductive part 433, the conductive part 43 in the first row and the third column is the fifth conductive part 435, and the conductive part 43 in the second row and the first column is the fourth conductive part 434.

[0337] In some embodiments, referring to FIGS. 10, 16A, and 17, along the first direction X, the at least one first NAND sub-circuit AN1 is located on the second side of the first middle line Z1. The first side and the second side of the first middle line Z1 are opposite sides of the first middle line Z1.

[0338] For example, as shown in FIGS. 10, 16A, and 17, 3 second NAND sub-circuits AN2 and 1 first NAND sub-circuit AN1 are located on the first side of the first middle line Z1, and the remaining 3 first NAND sub-circuits AN1 are located on the second side of the first middle line Z1. At this time, the gap between the first NAND sub-circuit AN1 and the second target conductive part M2 is large, and a first inversion sub-circuit I1 can be arranged between the first NAND sub-circuit AN1 and the second target conductive part M2, and the circuit structure is more compact.

[0339] In some embodiments, referring to FIGS. 10, 16A, and 17, the pixel circuit 1 includes a current generation sub-circuit 11, in a normal projection to the substrate 41, the current generation sub-circuit 11 is arranged on the second side of the first middle line Z1, and / or the current generation sub-circuit 11 is located on the side of the first NAND sub-circuit AN1 away from the first boundary L1 of the substrate 41. In this case, the current generation sub-circuit 11 is close to the first NAND sub-circuit AN1, and the length of the connection wire between the current generation sub-circuit 11 and the first NAND sub-circuit AN1 can be reduced.

[0340] Exemplarily, as shown in FIG. 10, FIG. 16A and FIG. 17, the light-emitting component 40 includes 7 conductive parts 43 arranged in 3 rows and 3 columns. The first and third rows each include 2 conductive parts 43, and the second row includes 3 conductive parts 43. The first and third columns each include 3 conductive parts 43, and the second column includes 1 conductive part 43. In the orthographic projection onto the substrate 41, the current generation sub-circuit 11 is located on the side of the conductive part 43 in the second column close to the conductive part 43 in the third column.

[0341] In some embodiments, referring to FIG. 10, FIG. 16A and FIG. 17, the substrate 41 has a second center line Z2 extending along the first direction X, and the plurality of NAND sub-circuits AN are located on the first side of the second center line Z2 along the second direction Y.

[0342] On this basis, referring to FIG. 10, FIG. 16A and FIG. 20, the first transistor T1 and / or the second transistor T2 are located on the first side of the second center line Z2. In this way, the control electrodes of the first transistor T1 and the second transistor T2 are adjacent to the output terminal of the first NAND sub-circuit AN1, and the length of the connection wire can be shortened.

[0343] In this case, the first transistor T1 and the second transistor T2 can be arranged along the first direction X. At this time, the driving transistor T0, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are all located on the side of the first transistor T1 and the second transistor T2 away from the NAND sub-circuit AN.

[0344] Exemplarily, referring to FIG. 10, FIG. 16A, FIG. 17 and FIG. 20, in the orthographic projection onto the substrate 41, the NAND sub-circuit AN is located between the 2 conductive parts 43 in the third row, and the first transistor T1 and the second transistor T2 may, for example, be located between the conductive parts 43 in the second row and the conductive parts 43 in the third row.

[0345] At this time, as shown in FIG. 16A, the 7 conductive parts are arranged in 3 rows and 3 columns, the first and third rows each include 2 conductive parts 43, and the second row includes 3 conductive parts 43. The first and third columns each include 3 conductive parts 43, and the second column includes 1 conductive part 43. The conductive part 43 in the second column in the second row is the first conductive part 431, so that the first conductive part 431 is relatively close to the first transmission gate C1 and the second transistor T2, and the length of the connection wire is short.

[0346] In some embodiments, referring to FIG. 20 and FIG. 21, the driving circuit layer 42 includes a first power supply wire VDL and a second power supply wire VSL.

[0347] The first power supply line VDL is connected with the third conductive part 433. The first power supply line VDL surrounds at least one closed area N1. The second power supply line VSL is connected with the fourth conductive part 434. The second power supply line VSL surrounds at least one closed area N2. In this way, the resistance of the first power supply line VDL and the second power supply line VSL is reduced, and the voltage drop is reduced.

[0348] Exemplarily, as shown in FIG. 20, the first power supply line VDL includes a first main line segment VDL1, a second main line segment VDL2, a first connecting line segment VDL3 and a second connecting line segment VDL4.

[0349] The first main line segment VDL1 is located on the first side of the second middle line Z2. The second main line segment VDL2 is located on the second side of the second middle line Z2.

[0350] On this basis, the first connecting line segment VDL3 is connected with the first main line segment VDL1 and the second main line segment VDL2. The first connecting line segment VDL3 is located between the second column and the third column of conductive parts 43, and is located on the side of the transistor included in the pixel circuit 1 and the multiplexing circuit 2 close to the third column of conductive parts 43. The second connecting line segment VDL4 is connected with the first main line segment VDL1 and the second main line segment VDL2. The second connecting line segment VDL4 is located on the side of the first column of conductive parts 43 away from the second column of conductive parts 43.

[0351] It should be noted that, as shown in FIG. 22, the first power supply line VDL can also be open, i.e., not surrounded by any closed area, for example, not including the second connecting line segment.

[0352] Exemplarily, as shown in FIG. 20, the second power supply line VSL includes a third main line segment VSL1, a fourth main line segment VSL2, a third connecting line segment VSL3 and a fourth connecting line segment VSL4.

[0353] The third main line segment VSL1 is located on the first side of the second middle line Z2. The fourth main line segment VSL2 is located on the second side of the second middle line Z2.

[0354] On this basis, the third connecting line segment VSL3 is connected with the third main line segment VSL1 and the fourth main line segment VSL2. The third connecting line segment VSL3 is located between the first column and the second column of conductive parts 43, and is located on the side of the transistor included in the pixel circuit 1 and the multiplexing circuit 2 close to the second column of conductive parts 43. The fourth connecting line segment VSL4 is connected with the third main line segment VSL1 and the fourth main line segment VSL2. The fourth connecting line segment VSL4 is located between the first column and the second column of conductive parts 43, and is located on the side of the transistor included in the pixel circuit 1 and the multiplexing circuit 2 close to the first column of conductive parts 43.

[0355] It should be noted that, as shown in FIG. 23, the second power supply wire VSL can also be open, i.e., not surrounded by any closed region, for example, not including the third connection line segment.

[0356] The circuit structure of the driving circuit 10 will be described below in conjunction with specific film layers, but the embodiments of the present disclosure are not limited thereto.

[0357] In some embodiments, as shown in FIGS. 24 and 25, the light-emitting assembly 40 further includes a first conductive layer 421 and a second conductive layer 422 arranged in sequence, and the first conductive layer 421 and the second conductive layer 422 are located between the substrate 41 and the driving circuit layer 42.

[0358] It should be understood that between any two adjacent ones of the first conductive layer 421, the second conductive layer 422 and the driving circuit layer 42, an insulating layer is arranged. The second conductive layer 422 and the driving circuit layer 42 can be provided with multiple inorganic insulating layers to play a buffering and protective role.

[0359] As shown in FIG. 24, the first conductive layer 421 includes multiple conductive portions 43, and the arrangement and structure of the multiple conductive portions 43 can refer to the above, which will not be described herein again.

[0360] As shown in FIGS. 24 and 25, the second conductive layer 422 includes multiple adapter blocks 44. In conjunction with FIG. 14, each adapter block 44 is connected with a conductive portion 43 through a first via hole H1.

[0361] For example, referring to FIG. 25, the adapter block 44 includes a main body portion 441, which covers the first via hole H1 and is in contact with the conductive portion 43. The main body portion 441 can be consistent with the shape of the outer contour of the first via hole H1 and coincide with the first via hole H1, or the area of the main body portion 441 is greater than the area of the first via hole H1 to ensure that the main body portion 441 can completely cover the first via hole H1.

[0362] In addition, referring to FIG. 25, the adapter block 44 can further include an adapter portion 442 connected with the main body portion 441, and the adapter portion 442 is arranged on one side of the main body portion 441 and used for lapping with the driving circuit 10 in the driving circuit layer 42. The number of the adapter portion 442 can be one or more, which will not be limited herein.

[0363] In this way, the size of the main body part 441 is designed to be small according to actual conditions, and the first via hole H1 can be covered. The adapter part 442 can be set according to the specific position of the driving circuit 10. The area of the adapter part 442 can be set to be small, which is beneficial to reduce the area of the adapter block 44, thereby reducing the cost and reducing the parasitic capacitance of the light-emitting assembly 40. In addition, the driving circuit 10 in the driving circuit layer 42 can be connected with the adapter block 44 outside the first via hole H1. In this way, the depth of the adapter hole of the driving circuit layer 42 for connecting the adapter block 44 can be reduced, and the preparation difficulty of the adapter hole can be reduced.

[0364] In some embodiments, as shown in FIGS. 14, 15 and 17, the driving circuit layer 42 comprises a third conductive layer (not shown in FIGS. 14 and 15), a third semiconductor layer 424, a first gate conductive layer 425, a second gate conductive layer 426, a fourth semiconductor layer 427, a third gate conductive layer 428, a first source-drain conductive layer 429 and a second source-drain conductive layer 430 which are sequentially arranged.

[0365] It should be noted that among the third conductive layer, the third semiconductor layer 424, the first gate conductive layer 425, the second gate conductive layer 426, the fourth semiconductor layer 427, the third gate conductive layer 428 and the first source-drain conductive layer 429, an insulating layer is arranged between any two adjacent layers.

[0366] Referring to FIGS. 14, 15 and 17, the third conductive layer comprises a gate of a P-type transistor, which serves as a bottom gate of the P-type transistor and can also serve as a light shielding layer. For example, the third conductive layer 423 comprises the gate of the driving transistor T0, the third transistor T3 and the fourth transistor T4.

[0367] Referring to FIGS. 14, 15 and 17, the third semiconductor layer 424 comprises an active part of a P-type transistor. For example, the third semiconductor layer 424 comprises the active part of the driving transistor T0, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the seventh transistor T7, the ninth transistor T9, the eleventh transistor T11, the thirteenth transistor T13 and the fifteenth transistor T15.

[0368] It should be noted that the material of the third semiconductor layer 424 comprises low-temperature polysilicon and / or metal oxide. For example, the material of the third semiconductor layer 424 comprises low-temperature polysilicon, and the embodiments of the present disclosure are not limited thereto.

[0369] The active part of the third semiconductor layer 424 includes a projection on the substrate 41, which is arranged away from the projection on the substrate 41 of the first via hole H1. For example, the active part of the driving transistor T0, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the seventh transistor T7, the ninth transistor T9, the eleventh transistor T11, the thirteenth transistor T13, and the fifteenth transistor T15 includes a projection on the substrate 41, which is arranged away from the projection on the substrate 41 of the first via hole H1. In this way, the difficulty of the preparation process of the third semiconductor layer 424 can be reduced, and in particular, when the material of the third semiconductor layer 424 includes low-temperature polysilicon, the risk of poor crystallization of the low-temperature polysilicon at the first via hole H1 can be avoided.

[0370] Referring to FIGS. 14, 15, and 17, the first gate conductive layer 425 includes the gate of each P-type transistor, as a top gate of the P-type transistor, and one plate of the capacitor Cst. For example, the first gate conductive layer 425 includes the gate of the driving transistor T0, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the seventh transistor T7, the ninth transistor T9, the eleventh transistor T11, the thirteenth transistor T13, and the fifteenth transistor T15.

[0371] Referring to FIGS. 14, 15, and 17, the second gate conductive layer 426 includes the gate of each N-type transistor, as a bottom gate of the N-type transistor, and one plate of the capacitor Cst. For example, the second gate conductive layer 426 includes the gate of the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, the tenth transistor T10, the twelfth transistor T12, the fourteenth transistor T14, and the sixteenth transistor T16.

[0372] Referring to FIGS. 14, 15, and 17, the fourth semiconductor layer 427 includes the active part of the N-type transistor. For example, the fourth semiconductor layer 427 includes the active part of the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, the tenth transistor T10, the twelfth transistor T12, the fourteenth transistor T14, and the sixteenth transistor T16.

[0373] It should be noted that the material of the fourth semiconductor layer 427 includes low-temperature polysilicon and / or metal oxide. For example, the material of the fourth semiconductor layer 427 includes metal oxide, and the embodiments of the present disclosure are not limited thereto.

[0374] The active part of the fourth semiconductor layer 427 includes a projection on the substrate 41, which is arranged to be staggered with the projection on the substrate 41 of the first via hole H1. For example, the active part of the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, the tenth transistor T10, the twelfth transistor T12, the fourteenth transistor T14, and the sixteenth transistor T16 includes a projection on the substrate 41, which is arranged to be staggered with the projection on the substrate 41 of the first via hole H1. In this way, the difficulty of the preparation process of the fourth semiconductor layer 427 can be reduced.

[0375] Referring to FIGS. 14, 15, and 17, the third gate conductive layer 428 includes the gate of each N-type transistor, as the top gate of the N-type transistor, and one plate of the capacitor Cst. For example, the second gate conductive layer 426 includes the gate of the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, the tenth transistor T10, the twelfth transistor T12, the fourteenth transistor T14, and the sixteenth transistor T16.

[0376] Referring to FIGS. 14, 15, and 17, the first source-drain conductive layer 429 includes a wiring connecting between the plurality of transistors in the current generation sub-circuit 11, a wiring connecting between the plurality of transistors in the pulse width modulation sub-circuit 12, and the like, which are not illustrated herein.

[0377] Referring to FIGS. 14, 15, and 17, the second source-drain conductive layer 430 includes a plurality of first conductive pads P and the support 401. The plurality of first conductive pads P can be arranged in multiple rows and multiple columns along the first direction X and the second direction Y, and the plurality of first conductive pads P can be uniformly distributed. The plurality of first conductive pads P can include a first first conductive pad P1 and a second first conductive pad P2. The first electrode 205 of the light emitting device 20 can be connected to the first first conductive pad P1, and the second electrode 206 of the light emitting device 20 can be connected to the second first conductive pad P2.

[0378] In the case where the light emitting assembly 40 includes three light emitting devices 20 and the three light emitting devices 20 are individually packaged, the second source-drain conductive layer 430 can include six first conductive pads P. In the case where the light emitting assembly 40 includes three light emitting devices 20 and the three light emitting devices 20 are integrally packaged, the three light emitting devices 20 can share one second electrode 206 connected to one first conductive pad P transmitting the second power signal end VSS. In this case, the number of first conductive pads P is four, the number of first conductive pads P is small, the bonding frequency between the light emitting device 20 and the first conductive pad P is low, and the production yield can be improved. In FIG. 26, six first conductive pads P are taken as an example for illustration.

[0379] Furthermore, the first electrode 205 and the second electrode 206 are arranged in a position deviated from the orthographic projection of the first via hole H1 on the substrate 41. That is, the orthographic projection of the portion of the first conductive pad P connected to the first electrode 205 and the second electrode 206 on the substrate 41 is arranged in a position deviated from the orthographic projection of the first via hole H1 on the substrate 41. In other words, the portion of the first conductive pad P connected to the first electrode 205 and the second electrode 206 does not overlap with the orthographic projection of the first via hole H1 on the substrate 41.

[0380] For example, the orthographic projection of the first conductive pad P, the first electrode 205 and the second electrode 206 on the substrate 41 is arranged in a position deviated from the orthographic projection of the first via hole H1 on the substrate 41. In this way, the flatness of the film layer under the first conductive pad P is higher, which is conducive to improving the flatness of the prepared first conductive pad P, thereby reducing the difficulty of bonding the first conductive pad P and the light emitting device 20 and improving the bonding yield.

[0381] At this time, in the orthographic projection on the substrate 41, the first electrode 205 and / or the second electrode 206 is located between two adjacent rows of first via holes H1, and / or the first electrode 205 and / or the second electrode 206 is located between two adjacent columns of first via holes H1. For example, the first conductive pad P is located between two adjacent rows of first via holes H1, and / or the first conductive pad P is located between two adjacent columns of first via holes H1.

[0382] In addition, the support 401 is arranged around the plurality of first conductive pads P, and the orthographic projection of the plurality of light emitting devices 20 on the substrate 41 may, for example, be located within the range of the orthographic projection of the outer boundary of the support 401 on the substrate 41. For example, in the case where the light emitting assembly 40 includes a plurality of light emitting device 20 integrated packages, the orthographic projection of the first semiconductor layer 201 of the integrated structure of the plurality of light emitting devices 20 on the substrate 41 is located within the range of the orthographic projection of the outer boundary of the support 401 on the substrate 41.

[0383] In this way, in the process of bonding the first electrode 205 and the second electrode 206 of the light emitting device 20 with the first first conductive pad P1 and the second first conductive pad P2, the support 401 can provide support and reduce the risk of deformation of the light emitting device 20 leading to disconnection of the light emitting device 20 and the pixel circuit 1.

[0384] In some embodiments, referring to FIGS. 17 and 27, the light emitting assembly 40 includes a first circuit trace 610 and a second circuit trace 620. The first circuit trace 610 includes a first sub-section 611 and a second sub-section 612. In the orthographic projection on the substrate 41, the first sub-section 611 overlaps with the first via hole H1, and the second sub-section 612 is deviated from the first via hole H1. Furthermore, in the orthographic projection on the substrate 41, the second circuit trace 620 is deviated from the first via hole H1.

[0385] On this basis, as shown in FIG. 27, the width of the first sub-section 611 is greater than the width of the second circuit trace 620, and / or, in the orthogonal projection onto the substrate 41, the minimum distance between the first sub-section 611 and an adjacent circuit trace is greater than the minimum distance between the second circuit trace 620 and an adjacent circuit trace. In this way, the risk of the first sub-section 611 breaking can be reduced. Exemplarily, in combination with FIG. 17 and FIG. 27, the first circuit trace 610 may, for example, be a signal line connected between the fourth transistor T4 and the second pass gate C2 and the third pass gate C3, and the second circuit trace 620 may, for example, be any trace that does not overlap the first via H1, and the embodiments of the present disclosure are not limited in this regard.

[0386] The difference between the width of the first sub-section 611 and the width of the second circuit trace 620 is 0.5 μm to 1 μm. For example, the difference between the width of the first sub-section 611 and the width of the second circuit trace 620 is any one of 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm or 1 μm. And / or, in the orthogonal projection onto the substrate 41, the difference between the distance between the first sub-section 611 and an adjacent circuit trace and the distance between the second circuit trace 620 and an adjacent circuit trace is 2 μm to 5 μm. For example, the difference between the distance between the first sub-section 611 and an adjacent circuit trace and the distance between the second circuit trace 620 and an adjacent circuit trace is any one of 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm or 5 μm.

[0387] The above merely provides a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can think of changes or replacements within the technical scope disclosed by the present disclosure, which shall be encompassed within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A driving circuit for connecting a plurality of light emitting devices, the driving circuit comprising: a plurality of pixel circuits directly connected to a first power signal terminal, a second power signal terminal, a first control node, a data signal terminal and a first node; the first node being coupled to the light emitting devices; a plurality of demultiplexing circuits connected to the first power signal terminal, the second power signal terminal, the data signal terminal, the first control node and an input signal terminal; the plurality of demultiplexing circuits being configured to transmit a first control signal to the first control node of the plurality of pixel circuits respectively in response to an input signal transmitted by the input signal terminal, so as to write a data signal received at the data signal terminal to different pixel circuits in time division.

2. The drive circuit of claim 1, wherein, the plurality of demultiplexing circuits comprising: a plurality of first inverting sub-circuits respectively comprising an input terminal, an output terminal, a first signal terminal and a second signal terminal; the input terminal of the first inverting sub-circuit being connected to the input signal terminal; one of the first signal terminal and the second signal terminal being connected to the first power signal terminal, and the other being connected to the second power signal terminal; a plurality of control wires being divided into a plurality of control wire groups, each of the control wire groups comprising two control wires; in the same control wire group, one of the two control wires is connected to the input signal terminal, and the other is connected to the output terminal of the first inverting sub-circuit connected to the input signal terminal; a plurality of first NAND gate sub-circuits respectively comprising an input terminal, an output terminal, a third signal terminal and a fourth signal terminal; the input terminal of the first NAND gate sub-circuit being connected to the control wire, and in the same first NAND gate sub-circuit, the control wires connected to different input terminals belong to different control wire groups; in any two different first NAND gate sub-circuits, the control wires connected to at least one input terminal are different; the output terminal of the first NAND gate sub-circuit being connected to the first control node; one of the third signal terminal and the fourth signal terminal being connected to the first power signal terminal, and the other being connected to the second power signal terminal.

3. The drive circuit of claim 2, wherein, the pixel circuit is further connected to a third control node, and the third control nodes connected to the plurality of pixel circuits respectively are further directly connected to the output terminal of the same first NAND gate sub-circuit, and / or the first control nodes connected to the plurality of pixel circuits respectively are directly connected to the output terminal of one first NAND gate sub-circuit respectively.

4. The drive circuit according to claim 2 or 3, wherein the pixel circuit is further connected to a third control node, and the plurality of demultiplexing circuits comprise three first inverting sub-circuits, six control wires and four first NAND gate sub-circuits; The six control lines include a first control line, a second control line, a third control line, a fourth control line, a fifth control line and a sixth control line in turn and adjacently, the first control line and the second control line form a control line group, the third control line and the fourth control line form a control line group, and the fifth control line and the sixth control line form a control line group; two control lines of one control line group are connected to one input signal terminal; The input terminals of the three first inversion sub-circuits are connected to one input signal terminal respectively, and the first control line, the third control line and the fifth control line are connected to the output terminals of the three first inversion sub-circuits respectively; the second control line, the fourth control line and the sixth control line are connected to one input signal terminal respectively; Each first NAND gate sub-circuit includes three input terminals; in the four first NAND gate sub-circuits, the three input terminals of one first NAND gate sub-circuit are connected to the second control line, the third control line and the fifth control line respectively, and the output terminal is connected to the third control node connected to all pixel circuits; the output terminals of the remaining three first NAND gate sub-circuits are connected to the first control node of one pixel circuit respectively; and in the remaining three first NAND gate sub-circuits, the three input terminals of one first NAND gate sub-circuit are connected to the second control line, the third control line and the sixth control line respectively; the three input terminals of one first NAND gate sub-circuit are connected to the second control line, the fourth control line and the fifth control line respectively; and the three input terminals of one first NAND gate sub-circuit are connected to the second control line, the fourth control line and the sixth control line respectively.

5. The drive circuit according to any one of claims 2 to 4, wherein The pixel circuit includes: A current generation sub-circuit directly connected to the first power signal terminal, the first control node, the second control node, the data signal terminal, the third control node, the first node and the second node; the current generation sub-circuit is configured to generate a drive current signal.

6. The drive circuit of claim 5, wherein, The pixel circuit further includes: A pulse width modulation sub-circuit directly connected to the third control node, the first pulse signal terminal, the fourth control node and the second node; the pulse width modulation sub-circuit is configured to control the drive current signal to be transmitted or not transmitted to the light emitting device.

7. The drive circuit of claim 6, wherein, The multiplexing circuit further includes: A plurality of second NAND gate sub-circuits each including an input terminal, an output terminal, the third signal terminal and the fourth signal terminal; the input terminal of the second NAND gate sub-circuit is connected to the control line, and in the same second NAND gate sub-circuit, the control lines connected to different input terminals belong to different control line groups; in any two different NAND gate sub-circuits, the control lines connected to at least one input terminal are different; a plurality of second inverting sub-circuits, each comprising an input terminal, an output terminal, the first signal terminal and the second signal terminal; the input terminal of the second inverting sub-circuit is connected with the output terminal of the second NAND gate sub-circuit; a plurality of first transfer gates, each comprising an input terminal, an output terminal, a first control signal terminal and a second control signal terminal; the input terminal of the first transfer gate is connected with the data signal terminal, the output terminal of the first transfer gate is connected with the fourth control node; the first control signal terminal of the first transfer gate is connected with the output terminal of the second NAND gate sub-circuit, and the second control signal terminal of the first transfer gate is connected with the output terminal of the second inverting sub-circuit.

8. The drive circuit of claim 7, wherein, The second control nodes connected with the plurality of pixel circuits are connected with the output terminal of the same second inverting sub-circuit.

9. The drive circuit according to claim 7 or 8, wherein, The multiplexing circuit comprises three second inverting sub-circuits, six control lines, three second NAND gate sub-circuits and three first transfer gates; The six control lines comprise a first control line, a second control line, a third control line, a fourth control line, a fifth control line and a sixth control line in turn; the first control line and the second control line form a control line group, the third control line and the fourth control line form a control line group, and the fifth control line and the sixth control line form a control line group; two control lines of one control line group are connected with the same input signal terminal; The input terminals of the three second inverting sub-circuits are respectively connected with the output terminals of one second NAND gate sub-circuit; the input terminals of the three first transfer gates are connected with the same data signal terminal, and the output terminals of the three first transfer gates are respectively connected with the fourth control nodes of one pixel circuit; the first control signal terminals of the three first transfer gates are respectively connected with the output terminals of one second NAND gate sub-circuit, and the second control signal terminals of the three first transfer gates are respectively connected with the output terminals of one second inverting sub-circuit; and the output terminal of one second inverting sub-circuit is also connected with the second control nodes of all pixel circuits. Each second NAND gate sub-circuit comprises three input terminals; and in the three second NAND gate sub-circuits, the three input terminals of one second NAND gate sub-circuit are respectively connected with the first control line, the third control line and the sixth control line; the three input terminals of one second NAND gate sub-circuit are respectively connected with the first control line, the fourth control line and the fifth control line; and the three input terminals of one second NAND gate sub-circuit are respectively connected with the first control line, the fourth control line and the sixth control line.

10. The drive circuit of claim 9, wherein, The multiplexing circuit comprises four first NAND gate sub-circuits. Among the four first NAND sub-circuits, three inputs of one of the first NAND sub-circuits are connected with the second control wire, the third control wire and the fifth control wire respectively, and the output is connected with the third control node to which all the pixel circuits are connected; the outputs of the remaining three first NAND sub-circuits are connected with the first control node of one pixel circuit respectively; and among the remaining three first NAND sub-circuits, three inputs of one of the first NAND sub-circuits are connected with the second control wire, the third control wire and the sixth control wire respectively; three inputs of one of the first NAND sub-circuits are connected with the second control wire, the fourth control wire and the fifth control wire respectively; and three inputs of one of the first NAND sub-circuits are connected with the second control wire, the fourth control wire and the sixth control wire respectively; Among the four first NAND sub-circuits, three inputs of one of the first NAND sub-circuits are connected with the second control wire, the third control wire and the fifth control wire respectively, and the output is connected with the third control node to which all the pixel circuits are connected; the outputs of the remaining three first NAND sub-circuits are connected with the first control node of one pixel circuit respectively; and among the remaining three first NAND sub-circuits, three inputs of one of the first NAND sub-circuits are connected with the second control wire, the third control wire and the sixth control wire respectively; three inputs of one of the first NAND sub-circuits are connected with the second control wire, the fourth control wire and the fifth control wire respectively; and three inputs of one of the first NAND sub-circuits are connected with the second control wire, the fourth control wire and the sixth control wire respectively; Among the four first NAND sub-circuits, three inputs of one of the first NAND sub-circuits are connected with the second control wire, the third control wire and the fifth control wire respectively, and the output is connected with the third control node to which all the pixel circuits are connected; the outputs of the remaining three first NAND sub-circuits are connected with the first control node of one pixel circuit respectively; and among the remaining three first NAND sub-circuits, three inputs of one of the first NAND sub-circuits are connected with the second control wire, the third control wire and the sixth control wire respectively; three inputs of one of the first NAND sub-circuits are connected with the second control wire, the fourth control wire and the fifth control wire respectively; and three inputs of one of the first NAND sub-circuits are connected with the second control wire, the fourth control wire and the sixth control wire respectively; The pulse width modulation sub-circuit comprises: a third inverting sub-circuit comprising an input end, an output end, the first signal end and the second signal end; the input end of the third inverting sub-circuit is connected with a third node, and the output end of the third inverting sub-circuit is connected with a fourth node; the third node is coupled to the fourth control node; 11. The drive circuit according to any one of claims 6 to 10, wherein a fourth inverting sub-circuit comprising an input end, an output end, the first signal end and the second signal end; the input end of the fourth inverting sub-circuit is connected with the fourth node, and the output end of the fourth inverting sub-circuit is connected with the third node; a second transfer gate comprising an input end, an output end, a first control signal end and a second control signal end; the input end of the second transfer gate is connected with the first pulse signal end, and the output end of the second transfer gate is connected with the second node; the first control signal end of the second transfer gate is connected with the fourth node N4, and the second control signal end of the second transfer gate is connected with the third node; ​ ​ A third pass gate includes an input terminal, an output terminal, a first control signal terminal and a second control signal terminal; the input terminal of the third pass gate is connected with the third control node, the first control signal terminal of the third pass gate is connected with the third node, and the second control signal terminal of the third pass gate is connected with the fourth node.

12. A light emitting assembly, comprising: a substrate; a driving circuit layer disposed on one side of the substrate, and the driving circuit layer comprises the driving circuit according to any one of claims 1-11; a plurality of light emitting devices disposed on the driving circuit layer and away from the substrate, and the plurality of pixel circuits of the driving circuit are respectively connected with the light emitting devices and configured to provide a driving current signal to the connected light emitting devices; a plurality of conductive parts located in the substrate or on a side of the substrate away from the driving circuit layer; wherein the plurality of conductive parts comprises a first conductive part, a plurality of second conductive parts, a third conductive part and a fourth conductive part; the first conductive part is configured to transmit a data signal, the plurality of second conductive parts are configured to respectively transmit different input signals, the third conductive part is configured to transmit a first power signal, and the fourth conductive part is configured to transmit a second power signal.

13. The light emitting assembly of claim 12, wherein, a data signal terminal connected with the first conductive part; an input signal terminal connected with one of the second conductive parts, and the number of the second conductive parts is less than or equal to the number of the pixel circuits; a first power signal terminal connected with the third conductive part; and a second power signal terminal connected with the fourth conductive part.

14. The light emitting assembly of claim 12 or 13, wherein, The driving circuit comprises three pixel circuits, the light emitting assembly comprises at least six conductive parts, and the six conductive parts comprise the first conductive part, three second conductive parts, the third conductive part and the fourth conductive part.

15. The light emitting assembly according to any one of claims 12-14, wherein, The plurality of conductive parts are arranged in multiple rows and multiple columns along a first direction and a second direction, at least one row comprises at least two conductive parts arranged along the first direction, at least one column comprises at least two conductive parts arranged along the second direction, and the first direction and the second direction intersect. The multiplexing circuit comprises a first NAND sub-circuit and a second NAND sub-circuit, the first NAND sub-circuit and the second NAND sub-circuit are arranged along the first direction, and at least part of the first NAND sub-circuit and the second NAND sub-circuit are located between two adjacent conductive parts.

16. The light emitting assembly of claim 15, wherein, The plurality of conductive parts comprise a first target conductive part and a second target conductive part, in the first direction, the first target conductive part and the second target conductive part are adjacent, and the distance between the first target conductive part and the second target conductive part is greater than or equal to the distance between any two adjacent conductive parts. In the orthographic projection of the substrate, at least part of the whole of the first NAND sub-circuit and the second NAND sub-circuit is located between the first target conductive part and the second target conductive part.

17. The light emitting assembly of claim 16, wherein, The light-emitting component includes 7 conductive parts, which are arranged in 3 rows and 3 columns; the first and third rows each include 2 conductive parts, and the second row includes 3 conductive parts; the first and third columns each include 3 conductive parts, and the second column includes 1 conductive part; the two conductive parts in the third row are the first target conductive part and the second target conductive part, wherein the first target conductive part and the second target conductive part are both the second conductive part, or, The light-emitting component includes 8 conductive parts, which are arranged in 3 rows and 3 columns; the first and second rows each include 3 conductive parts, and the third row includes 2 conductive parts; the first and third columns each include 3 conductive parts, and the second column includes 2 conductive parts; the two conductive parts in the third row are the first target conductive part and the second target conductive part, wherein the first target conductive part and the second target conductive part are both the second conductive part, or, The light-emitting component includes 6 conductive parts, which are arranged in 3 rows and 2 columns; the first, second, and third rows each include 2 conductive parts; the first and second columns each include 3 conductive parts; the two conductive parts in the third row are the first target conductive part and the second target conductive part, wherein the first target conductive part and the second target conductive part are both the second conductive part, or, The light-emitting component includes 5 conductive parts, which are arranged in 2 rows and 3 columns; the first row includes 3 conductive parts, and the second row includes 2 conductive parts; the first and third columns each include 2 conductive parts; the second column includes one conductive part; the two conductive parts in the second row are the first target conductive part and the second target conductive part, wherein the first target conductive part and the second target conductive part are both the second conductive part. The multiplexing circuit further includes a first inverting sub-circuit; 18. The light emitting assembly according to any one of claims 15-17, wherein, In the orthographic projection of the substrate, along the first direction, at least one first inverting sub-circuit is disposed between a plurality of NAND gate sub-circuits and the boundary of the substrate. At least one first inverting sub-circuit is located between a target conductive part and another conductive part adjacent to the target conductive part in the second direction.

19. The light emitting assembly of claim 18, wherein, The multiplexing circuit includes three first inverting sub-circuits, and the light-emitting component includes three second conductive parts; 20. The light emitting assembly of claim 19, wherein, One first inverting sub-circuit is located between the first target conductive part and a third target conductive part adjacent to the first target conductive part in the second direction; One first inverting sub-circuit is located between the second target conductive part and a fourth target conductive part adjacent to the second target conductive part in the second direction; The remaining one first inverting sub-circuit is located between a plurality of NAND gate sub-circuits and the second target conductive part; wherein the fourth target conductive part is the second conductive part. ​ 21. The light emitting component of claim 20, comprising 7 of the conductive portions arranged in 3 rows and 3 columns; the first and third rows each comprising 2 of the conductive portions, and the second row comprising 3 of the conductive portions; the first and third columns each comprising 3 of the conductive portions, and the second column comprising 1 of the conductive portions; wherein the 2 of the conductive portions of the third row and the conductive portion of the second row and third column are the second conductive portions.

22. The light emitting assembly according to any one of claims 15-21, wherein, the multiplexing circuit comprises a second inverting sub-circuit; in the orthographic projection onto the substrate, the at least one second inverting sub-circuit and the second NAND gate sub-circuit are arranged along the first direction, and / or, in the orthographic projection onto the substrate, the at least one second inverting sub-circuit is located on a side of the second NAND gate sub-circuit away from a first boundary of the substrate, the first boundary being a boundary of the substrate along the first direction and adjacent to the second NAND gate sub-circuit.

23. The light emitting assembly according to any one of claims 15-22, wherein, the multiplexing circuit further comprises a second inverting sub-circuit and a first pass gate, the substrate having a first midline extending along the second direction; in the orthographic projection onto the substrate, along the first direction, a plurality of the second NAND gate sub-circuits are located on a first side of the first midline, and / or, in the orthographic projection onto the substrate, the second inverting sub-circuit is located on the first side of the first midline, and / or, in the orthographic projection onto the substrate, the first pass gate is located on the first side of the first midline.

24. The light emitting component of claim 23, comprising 7 of the conductive portions arranged in 3 rows and 3 columns; the first and third rows each comprising 2 of the conductive portions, and the second row comprising 3 of the conductive portions; the first and third columns each comprising 3 of the conductive portions, and the second column comprising 1 of the conductive portions; in the orthographic projection onto the substrate, the second inverting sub-circuit is located on a side of the conductive portion of the second column closer to the conductive portion of the first column, and / or, the first pass gate is located on the side of the conductive portion of the second column closer to the conductive portion of the first column.

25. The light emitting assembly of claim 23 or 24, wherein, the pixel circuit comprises a pulse width modulation sub-circuit, the pulse width modulation sub-circuit being located on the first side of the first midline.

26. The light emitting assembly according to any one of claims 23-25, wherein, the pixel circuit comprises a pulse width modulation sub-circuit; in the orthographic projection onto the substrate, along the second direction, the second NAND gate sub-circuit, the at least one second inverting sub-circuit, the first pass gate and the pulse width modulation sub-circuit are arranged in sequence.

27. The light emitting component of claim 26, comprising 7 of the conductive portions arranged in 3 rows and 3 columns; the first and third rows each comprising 2 of the conductive portions, and the second row comprising 3 of the conductive portions; the first and third columns each comprising 3 of the conductive portions, and the second column comprising 1 of the conductive portions; In a projection onto the substrate, a straight line where boundaries of the conductive parts of the second row are located is a first boundary line; along the second direction, the second NAND sub-circuit, the second inverting sub-circuit and the first transfer gate are disposed on a first side of the first boundary line, and the pulse width modulation sub-circuit is disposed on a second side of the first boundary line; the first side and the second side of the first boundary line are opposite sides of the first boundary line.

28. The light emitting assembly of claim 26 or 27, wherein, The pulse width modulation sub-circuit comprises a third inverting sub-circuit, a fourth inverting sub-circuit, a second transfer gate and a third transfer gate; The second transfer gate and the third transfer gate are arranged along the first direction; along the second direction, the third inverting sub-circuit and the fourth inverting sub-circuit are located between the second transfer gate and the first transfer gate, and between the third transfer gate and the first transfer gate.

29. The light emitting component of any one of claims 26-28, comprising 7 conductive parts arranged in 3 rows and 3 columns; the first row and the third row each comprising 2 conductive parts, and the second row comprising 3 conductive parts; the first column and the third column each comprising 3 conductive parts, and the second column comprising 1 conductive part; wherein The 7 conductive parts comprise a fifth conductive part configured to transmit a pulse signal; any one of the 2 conductive parts of the first row is the fifth conductive part, and / or the conductive part of the second row and the first column is the third conductive part or the fourth conductive part.

30. The light emitting assembly according to any one of claims 23-29, wherein, Along the first direction, at least one first NAND sub-circuit is located on the second side of the first middle line; the first side and the second side of the first middle line are opposite sides of the first middle line.

31. The light emitting component of claim 30, comprising 4 first NAND sub-circuits and 3 second NAND sub-circuits; 3 second NAND sub-circuits and 1 first NAND sub-circuit are located on the first side of the first middle line, and the remaining 3 first NAND sub-circuits are located on the second side of the first middle line.

32. The light emitting assembly of claim 30 or 31, wherein, The pixel circuit comprises a current generation sub-circuit; In a projection onto the substrate, the current generation sub-circuit is disposed on the second side of the first middle line, and / or, The current generation sub-circuit is located on a side of the first NAND sub-circuit away from a first boundary of the substrate, and the first boundary is a boundary of the substrate extending along the first direction and adjacent to the first NAND sub-circuit.

33. The light emitting component of claim 32, comprising 7 conductive parts arranged in 3 rows and 3 columns; the first row and the third row each comprising 2 conductive parts, and the second row comprising 3 conductive parts; the first column and the third column each comprising 3 conductive parts, and the second column comprising 1 conductive part; In a projection onto the substrate, the current generation sub-circuit is located on a side of the conductive part of the second column close to the conductive part of the third column.

34. The light emitting assembly of claim 32 or 33, wherein, The substrate has a second middle line extending along the first direction, and along the second direction, a plurality of NAND sub-circuits are located on the first side of the second middle line; The current generation sub-circuit comprises: a driving transistor, a first electrode of the driving transistor being connected with the fifth node, a second electrode of the driving transistor being connected with the sixth node, and a control electrode of the driving transistor being connected with the seventh node; the fifth node being coupled to the first power signal terminal, and the sixth node being coupled to the light emitting device; a first transistor, a first electrode of the first transistor being connected with the data signal terminal, a second electrode of the first transistor being connected with the fifth node, and a control electrode of the first transistor being connected with the first control node; a second transistor, a first electrode of the second transistor being connected with the sixth node, a second electrode of the second transistor being connected with the seventh node, and a control electrode of the second transistor being connected with the first control node; wherein, along the second direction, the first transistor and / or the second transistor is / are located on the first side of the second middle line.

35. The light emitting assembly of claim 34, comprising 7 of the conductive portions, the 7 conductive portions arranged in 3 rows of 3 columns; wherein, The first row and the third row each comprise two conductive parts, and the second row comprises three conductive parts; the first column and the third column each comprise three conductive parts, and the second column comprises one conductive part; In the orthogonal projection onto the substrate, the NAND gate sub-circuit is located between the two conductive parts in the third row, and the first transistor and the second transistor are located between the conductive parts in the second row and the conductive parts in the third row.

36. The light emitting component according to any one of claims 32-35, comprising seven conductive parts arranged in three rows and three columns; the first row and the third row each comprise two conductive parts, and the second row comprises three conductive parts; the first column and the third column each comprise three conductive parts, and the second column comprises one conductive part; wherein The conductive part in the second column of the second row is the first conductive part.

37. The light emitting component according to any one of claims 12-36, comprising: a first power supply wire connected with the third conductive part; the first power supply wire surrounds at least one enclosed area.

38. The light emitting assembly of claim 37, wherein, The substrate has a second middle line extending along the first direction, and the first power supply wire comprises: a first main wire segment located on the first side of the second middle line; a second main wire segment located on the second side of the second middle line; a first connecting wire segment connected with the first main wire segment and the second main wire segment; the first connecting wire segment is located between the conductive parts in the second column and the third column, and is located on the side of the pixel circuit and the transistors included in the multiplexing distribution circuit close to the conductive parts in the third column; a second connecting wire segment connected with the first main wire segment and the second main wire segment; the second connecting wire segment is located on the side of the conductive parts in the first column away from the conductive parts in the second column.

39. The light emitting component according to any one of claims 12-38, comprising: a second power supply wire connected with the fourth conductive part; the second power supply wire surrounds at least one enclosed area.

40. The light emitting assembly of claim 39, wherein, The substrate has a second middle line extending along the first direction, and the second power supply wire comprises: a third main wire segment located on the first side of the second middle line; a fourth main wire segment located on the second side of the second middle line; a third connecting line segment connected with the third main wire segment and the fourth main wire segment; the third connecting line segment is located between the first column and the second column of the conductive portions and is located on a side of the pixel circuit and the transistors included in the multiplexing circuit close to the second column of the conductive portions; a fourth connecting line segment connected with the third main wire segment and the fourth main wire segment; the fourth connecting line segment is located between the first column and the second column of the conductive portions and is located on a side of the pixel circuit and the transistors included in the multiplexing circuit close to the first column of the conductive portions.

41. The light emitting component according to any one of claims 12-40, comprising: a first circuit wire including a first sub-segment and a second sub-segment; in a projection onto the substrate, the first sub-segment overlaps the first via, and the second sub-segment is staggered with the first via; a second circuit wire, in a projection onto the substrate, the second circuit wire is staggered with the first via; wherein a width of the first sub-segment is greater than a width of the second circuit wire, and / or, in a projection onto the substrate, a minimum distance between the first sub-segment and an adjacent circuit wire is greater than a minimum distance between the second circuit wire and an adjacent circuit wire. a difference between the width of the first sub-segment and the width of the second circuit wire is 0.5-1 μm, and / or, in a projection onto the substrate, a difference between a distance between the first sub-segment and an adjacent circuit wire and a distance between the second circuit wire and an adjacent circuit wire is 2-5 μm.

42. The light emitting assembly of claim 41, wherein, the light emitting device includes a first electrode and a second electrode; a first conductive pad is arranged on a side of the driving circuit layer close to the light emitting device, and the first electrode and the second electrode are connected with the first conductive pad; 43. The light emitting assembly according to any of claims 12-42, wherein, the substrate has a first via, the first via exposes at least part of the conductive portion, the conductive portion is connected with the driving circuit through the first via and the driving circuit, and a projection of the first electrode and / or the second electrode on the substrate does not overlap a projection of the first via on the substrate. one of the conductive portions and one of the first vias correspond, in a projection onto the substrate, the first electrode and / or the second electrode is located between two adjacent rows of the first vias, and / or, the first electrode and / or the second electrode is located between two adjacent columns of the first vias.

44. The light emitting assembly of claim 43, wherein, the conductive portion includes a first conductive part located in the substrate and a second conductive part located on a side of the substrate away from the light emitting device, and the first conductive part is connected with the second conductive part.

45. The light emitting assembly according to any of claims 12-44, wherein, the light emitting device further includes a first semiconductor layer, a light emitting functional layer and a second semiconductor layer arranged in a stack; the first semiconductor layers of the plurality of light emitting devices are in an integrated structure, and the light emitting functional layers and the second semiconductor layers of the plurality of light emitting devices are arranged in a spaced manner.

46. The light emitting assembly according to any of claims 12-45, wherein, the substrate has a first via, the first via exposes at least part of the conductive portion, the conductive portion is connected with the driving circuit through the first via and the driving circuit; 47. The light emitting assembly according to any of claims 12-46, wherein, the light emitting component further includes: ​ The adapter block comprises a main body and an adapter, the main body covers the first via hole and is connected with the conductive part; The adapter is arranged on one side of the main body and is connected with the driving circuit in the driving circuit layer.

48. The light emitting assembly according to any of claims 12-47, wherein, The driving circuit comprises a P-type transistor and an N-type transistor. The light emitting component further comprises a third semiconductor layer and a fourth semiconductor layer, one of the third semiconductor layer and the fourth semiconductor layer comprises an active part of a P-type transistor, and the other comprises an active part of an N-type transistor; wherein the third semiconductor layer and the fourth semiconductor layer are different layers.

49. A display substrate, comprising: a driving backplane comprising a second conductive pad; a plurality of light emitting components arranged in an array according to any one of claims 12-48, the conductive parts of the plurality of light emitting components are further connected with the second conductive pad.

50. A display device comprising: The display substrate according to claim 49.

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