Hardware-in-the-loop test method and system for protection device

Abstract

A hardware-in-the-loop test method and system for a protection device. The method comprises: constructing a simulation scenario in a hardware-in-the-loop simulation test system; on the basis of the mounting position of a protection device (4) to be verified in the simulation scenario, determining the minimum sampling signals required for said protection device (4) to work normally, and establishing a current transformer model capable of restoring a transient saturation scenario; performing a power-on operation on said protection device (4), and enabling the hardware-in-the-loop simulation test system to output an electrical signal; and after a correct sampling reading is acquired on said protection device (4), simulating a fault scenario in the simulation scenario, and on the basis of a current signal having transient saturation characteristics calculated by a model and a logic determination of the protection device, determining whether an action result of the fault scenario satisfies a setting value and an action logic. The present hardware-in-the-loop test method for a protection device restores a true current in a non-ideal fault condition, thereby deeply testing the working characteristics of a relay protection device in a power station.

Description

A protection device hardware-in-the-loop test method and system

[0001] The present application claims priority to the Chinese patent application No. 202411374008.4, filed on September 29, 2024, and entitled "A protection device hardware-in-the-loop test method and system", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of computer platform load balancing, in particular to a protection device hardware-in-the-loop test method and system. BACKGROUND

[0003] In the verification test of overhauling the protection device of a power station, the through-flow and through-voltage verification method of the steady-state quantity protection device based on the effective value has been relatively mature, but when the system fails, the behavior of the protection device will still misoperate or refuse to operate due to insufficient setting value margin, insufficient device logic test, etc. The reason is that the effective value of the added amount simulation operation is not enough to reflect the real system situation, and the non-linear transient characteristics caused by the transformer core inrush problem and the transient saturation problem of the current transformer are difficult to stimulate the real fault scene in the conventional relay protection instrument added amount verification protection device action logic, thereby bringing the untrustworthy verification result. Increasing the setting threshold of the relay protection setting value can eliminate this problem to a certain extent, but excessive unbalanced quantity margin value will make the sensitivity worse, so developing a device test system using hardware-in-the-loop and considering the non-linear characteristics of transient saturation can deeply test the related work of protection device action logic and setting value verification, effectively ensuring the safety and reliability of the protection system of the power station.

[0004] Hardware-in-the-loop simulation test is a new type of test technology, which realizes the restoration of us-level or even ns-level fine system change process through the hardware architecture of CPU+FPGA. Through the peripheral interface device, the sampling part of the protection device can be connected, and the whole process of fault triggering, maintenance to fault removal can be simulated according to the set program. This architecture provides a good test platform, but the system modeling in the computer also needs to be accurate enough to reflect the characteristics of the real fault transient state that can be simulated. Among the general fault types of power stations, the motor model is accepted and absorbed by a large number of software, but elements such as transformers generally use ideal transformers, and accurate transformer transfer characteristics can benefit the real effectiveness of the test. J-A (Jiles-Atherton) theory, as a classic ferromagnetic theory, is used to describe the magnetization characteristics of ferromagnetic materials, which has very good phenomenon explanation and is easy to calculate, and can be used in the transient saturation modeling work of the current transformer. SUMMARY

[0005] In view of the above problems, the present application is proposed.

[0006] Therefore, the technical problem solved by the present application is: in order to realize the function measurement and deep checking task of the relay protection device, ensure the safe and stable operation of the power system.

[0007] The existing through-flow and through-voltage checking method of the steady-state quantity protection device based on the effective value cannot reflect the real system fault state, leading to the misoperation or refusal of the protection device, and the optimization problem of how to accurately restore the transient saturation characteristics and test the action logic of the protection device.

[0008] To solve the above technical problems, the present application provides the following technical solutions: a protection device hardware-in-the-loop test method, comprising:

[0009] Constructing a simulation scene in a hardware-in-the-loop simulation test system;

[0010] According to the installation position of the protection device to be checked in the simulation scene, determining the minimum sampling signal required for the normal operation of the protection device to be checked, and establishing a current transformer model that can restore the transient saturation scene;

[0011] Performing a power-on operation on the protection device to be checked, and making the hardware-in-the-loop simulation test system output electrical signals;

[0012] When the protection device acquires correct sampling data, simulating a fault scene in the simulation scene, and determining whether the action result meets the setting value and the action logic through the current signal with transient saturation characteristics calculated by the model and the logical judgment of the protection device.

[0013] As an optional solution of the protection device hardware-in-the-loop test method described in the present application, wherein: the current transformer model comprises a TP-level current transformer and a P-level current transformer.

[0014] As an optional solution of the protection device hardware-in-the-loop test method described in the present application, wherein: the TP-level current transformer is not considered for saturation characteristics.

[0015] As an optional solution of the protection device hardware-in-the-loop test method described in the present application, wherein: a J-A transient saturation model is established for the P-level current transformer.

[0016] As an optional solution of the protection device hardware-in-the-loop test method described in the present application, wherein: the establishment of the J-A transient saturation model comprises initialization of the model and setting of the P-level current transformer parameters.

[0017] Calculating the important parameter magnetization rate differential equation of the transient saturation J-A model;

[0018] Calculating the excitation current differential equation;

[0019] The secondary side of the P-class current transformer with saturation characteristics is updated in real time according to the changed primary current.

[0020] As an alternative of the protection device hardware-in-the-loop test method, the P-class current transformer parameters include the turns ratio, the equivalent cross section of the core, the magnetic permeability in vacuum, the equivalent magnetic chain length of the core, the resistance and leakage reactance of the secondary circuit of the current transformer, the initial excitation current value, and the initial magnetization intensity.

[0021] As an alternative of the protection device hardware-in-the-loop test method, the protection device to be verified is connected to the hardware of the hardware-in-the-loop simulation test system through the current and voltage sampling channels, and the analog quantity AO level of the hardware physical interface board of the hardware-in-the-loop simulation test system is matched.

[0022] The current signal calculated by the current transformer model in the hardware-in-the-loop simulation test system is connected to the current sampling port of the protection device through signal output and amplification.

[0023] The voltage signal calculated by the ideal voltage transformer model in the hardware-in-the-loop simulation test system is connected to the voltage sampling port of the protection device through signal output and amplification.

[0024] The trip outlet signal of the protection device to be verified is connected back to the digital quantity DI channel of the hardware physical interface board of the hardware-in-the-loop simulation test system.

[0025] Another object of the present application is to provide a protection device hardware-in-the-loop test system, which can solve the problem of inaccurate simulation of the nonlinear transient characteristics caused by the transformer core inrush current and the transient saturation characteristics of the current transformer in the existing protection device verification process by constructing a hardware-in-the-loop simulation test system based on the J-A transient saturation theory.

[0026] To solve the above technical problems, the application provides the following technical scheme: a protection device hardware-in-the-loop test system, comprising: a CPU+multi-FPGA simulation test host, an upper computer, a power amplifier, a protection device to be verified, a signal cable, a control cable and an Ethernet cable; the CPU+multi-FPGA simulation test host is used to generate current and voltage signals in a simulation scene, and calculate a fault scene through a simulation algorithm; the upper computer is connected with the CPU+multi-FPGA simulation test host through the Ethernet cable, and is used to set the fault scene and monitor simulation results; the power amplifier amplifies analog signals output by the simulation host, so as to drive an input channel of the protection device to be verified; the signal cable is connected between the power amplifier and the protection device to be verified, and is used to transmit current and voltage signals; the control cable is connected between the protection device to be verified and the simulation test host, and is used to transmit incoming and outgoing signals, and monitor action logic of the protection device; the fault scene is adjusted in real time through the upper computer, and the simulation host outputs required signals to the protection device through the power amplifier for verification.

[0027] A computer device comprises a memory and a processor, the memory stores a computer program, and the processor implements the steps of the protection device hardware-in-the-loop test method as described above when executing the computer program.

[0028] A computer readable storage medium stores a computer program, and the computer program implements the steps of the protection device hardware-in-the-loop test method as described above when executed by a processor.

[0029] The application has the following beneficial effects: the protection device hardware-in-the-loop test method provided by the application restores true value currents in a non-ideal fault state by using real simulation of a current transformer J-A saturation model, and deeply tests working characteristics of a power station relay protection device. Meanwhile, the method is convenient to connect and reliable in principle, and is suitable for requirements of verification of a relay protection device based on an electrical quantity protection principle. The semi-physical test technology is high in universality and safety, and is convenient for field popularization and use. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the application, and for those skilled in the art, other drawings can also be obtained without creative labor based on these drawings.

[0031] Fig. 1 is a hardware-in-the-loop simulation test system structure arrangement diagram in a protection device hardware-in-the-loop test method provided by an embodiment of the application.

[0032] Fig. 2 is a schematic diagram of a simulation scene to be checked in a protection device hardware-in-the-loop test method according to an embodiment of the present application.

[0033] Fig. 3 is a three-phase fault current recording graph of two sides of a transformer in a protection device hardware-in-the-loop test method according to an embodiment of the present application.

[0034] Fig. 4 is a three-phase differential current calculation value and trip signal recording curve graph when the second harmonic braking coefficient is 0.30 in a protection device hardware-in-the-loop test method according to an embodiment of the present application.

[0035] Fig. 5 is a three-phase differential current calculation value and trip signal recording curve graph when the second harmonic braking coefficient is 0.65 in a protection device hardware-in-the-loop test method according to an embodiment of the present application. DETAILED DESCRIPTION

[0036] In order to make the above objectives, features and advantages of the present application more apparent, specific embodiments of the present application will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work should fall within the protection scope of the present application.

[0037] In the following description, many specific details are set forth in order to provide a thorough understanding of the present application. However, the present application can be practiced in other ways different from those described herein, and those of ordinary skill in the art can make similar extensions without departing from the spirit of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0038] Embodiment 1

[0039] Referring to Fig. 1, according to an embodiment of the present application, a protection device hardware-in-the-loop test method is provided, comprising:

[0040] Step 1: Build a simulation primary system in the hardware-in-the-loop simulation test system, that is, the simulation scene to be checked. The elements included are a generator, a transformer, an infinite system, a transmission line, a load impedance, a mutual inductor, etc.

[0041] Step 2: According to the installation position of the protection device to be checked in the simulation scene to be checked, determine the minimum sampling signals required for the normal operation of the protection device to be checked, and establish a current transformer model that can restore the transient saturation scene. The saturation characteristics of the TP-level current transformer are not taken into account, and for the P-level current transformer, a J-A transient saturation model of all P-level mutual inductors in the simulation scene to be checked is established according to the transformation ratio, core cross-sectional area, core size and other parameters.

[0042] Step 3: Connect the peripheral interface of the protection device to be verified, such as the current and voltage sampling channel, with the hardware of the simulated primary system, wherein the current signal is from the calculated value of the current transformer model in step 2), and the voltage signal can use an ideal voltage transformer. Match the analog quantity AIO, digital quantity DIO and other interface devices with the level grade;

[0043] Step 4: Power on the protection device to be verified, and enable the simulated primary system to output continuous and stable electrical signals. After correct sampling readings are observed on the protection device, simulate a fault scene in the simulated scene to be verified. The current signal calculated by the model considering transient saturation characteristics is used for logical judgment of the protection device, and whether the action result meets the setting value and action logic is observed. The relevant process is recorded, then the fault scene in the simulated scene to be verified is changed, and the step 4 process is repeated, otherwise the test is ended.

[0044] The simulated primary system of step 1 has the following characteristics: a CPU + multi-FPGA hardware architecture is used, each FPGA simulation board card is configured with synchronous analog input AI and output AO channels, the maximum sampling rate is not less than 1 MS / s, and the voltage range supports ±10V; high-speed digital input DI and output DO channels are configured. The highest update frequency of a single channel is not less than 10MHz, and the TTL interface standard is adopted; the algorithm model of the verification FPGA can be built and deployed by using the basic modules. The basic modules include: addition, subtraction, multiplication, division, integral module, differential module, logic comparison module, coordinate transformation module, PID module, PLL phase-locked module, etc. The circuit parameters are adjusted online in real time in real-time simulation, and the number of parameters and the number of modifications are not limited; a power amplifier can be used. The structure diagram of the simulated primary system is shown in FIG. 1. The simulated scene to be verified is a pure software model, which has certain man-machine interaction interface during running to trigger faults, observe model running and other basic functions.

[0045] In step 2, for the TP-level current transformer arranged in the simulated scene to be verified, the ratio is converted into an ideal transformer, that is, the primary current divided by the secondary current is the model output current. For the P-level current transformer, the following steps are used for calculation:

[0046] (1) Initialize the model, set the P-level current transformer parameters, including the ratio of turns N, the equivalent cross section A of the core; the magnetic permeability in vacuum state μ0, μ0=4π×10-7T·m / A; the equivalent magnetic chain length of the core l; the resistance R2 and leakage reactance L2 of the secondary circuit of the current transformer. Set the initial excitation current value im(k-1) and the initial magnetization M(k-1), and mark the initial state as the k-1 time for general algorithm process description.

[0047] (2) Calculate the important parameter magnetization rate differential formula of the J-A model considering transient saturation

[0048] Calculate the magnetic field strength H(k) = i m (k-1)·N / l (1)

[0049] Calculate the J-A theory parameter - effective magnetic field strength H e (k) = H(k) + alpha M(k-1) (2)

[0050] Calculate the J-A theory parameter - non-magnetic hysteresis magnetization

[0051] Calculate the J-A theory parameter - non-magnetic hysteresis permeability

[0052] Calculate the J-A theory parameter - permeability

[0053] In the formula, M s , c, K, alpha, a are five key parameters of J-A model, wherein M s is the saturation magnetization of the core material; c is the energy loss coefficient; K is the pinning effect constant; a is the shape parameter; alpha is the magnetic domain wall coupling coefficient, which can be easily obtained from the factory magnetization curve of the ferromagnetic material; M an is the magnetization strength assuming no magnetic hysteresis effect of the ferromagnetic material; the calculation of the direction parameter delta is as follows:

[0054] (3) Calculate the differential of the excitation current:

[0055] (4) Then update the output current of the P-level transformer with saturation characteristics on the secondary side in real time according to the change of the primary current. i2(k) = i1(k) / N-i m (k) (8)

[0056] The step 3 connects the current and voltage sampling channels of the protection device to be verified with the hardware of the simulated primary system, and matches the analog quantity AO level of the hardware physical interface board of the simulated primary system. The current signal calculated by the transformer model in the simulated primary system is connected to the current sampling port of the protection device after signal output and amplification; the voltage signal calculated by the ideal voltage transformer model in the simulated primary system is connected to the voltage sampling port of the protection device after signal output and amplification; the tripping outlet signal of the protection device to be verified is connected back to the digital quantity DI channel of the physical interface board of the simulated primary system, which is used to observe and judge the correctness of the tripping action logic.

[0057] The step 4 simulates the protection device to be checked with the simulated primary system debugging operation, after the signal is observed to be stable, the fault scene is designed according to the test item and the fault is triggered, and whether the protection device to be checked is correctly acted is observed. Whether the action time meets the protection logic. Whether the action value is consistent with the fixed value.

[0058] Then according to the actual demand, multiple tests can be carried out in other scenes.

[0059] Embodiment 2

[0060] Referring to FIG. 1, one embodiment of the present application provides a hardware-in-the-loop simulation test system, which comprises:

[0061] CPU+multi-FPGA simulation test host, host computer, power amplifier, protection device to be checked, signal cable and control cable.

[0062] The system adopts a CPU+multi-FPGA hardware architecture, each FPGA simulation board card is configured with a synchronous analog input AI, an output AO channel, a maximum sampling rate not less than 1MS / s, and a voltage range supporting ±10V; a high-speed digital input DI, an output DO channel. The highest update frequency of a single channel is not less than 10MHz, and the TTL interface standard; the algorithm model of the FPGA can be verified and deployed by using the basic module. The basic module includes: addition, subtraction, multiplication, division, integral module, differential module, logic comparison module, coordinate transformation module, PID module, PLL phase-locked loop and other modules. The circuit parameters are adjusted online in real time in real-time simulation, and the number of parameters and the number of modifications are not limited; a power amplifier can be used.

[0063] The structure diagram of the system 1 is shown in FIG. 1, in which 1 is a CPU+multi-FPGA simulation test host; 2 is a host computer; 3 is a power amplifier; 4 is a protection device to be checked; 5 is a signal cable; 6 is a control cable; and 7 is an Ethernet cable.

[0064] There is a certain man-machine interface in the running, which can trigger faults, observe model running and other basic functions.

[0065] Embodiment 3

[0066] One embodiment of the present application is different from the previous two embodiments:

[0067] If the functions are implemented in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the parts of the prior art that make contributions or parts of the technical solutions can be embodied in the form of a software product, which is stored in a storage medium and includes a number of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.

[0068] The logic and / or steps represented in the flowcharts or otherwise described herein, for example, can be considered as a list of executable instructions for implementing logic functions, which can be embodied in any computer readable medium for use by or in connection with an instruction execution system, apparatus or device, such as a computer-based system, a system including a processor or other system that can fetch instructions from an instruction execution system, apparatus or device and execute the instructions, or in conjunction with these instruction execution systems, apparatus or devices. For the purpose of this specification, "computer readable medium" can be any device that can contain, store, communicate, propagate or transport programs for use by or in connection with an instruction execution system, apparatus or device, or in conjunction with these instruction execution systems, apparatus or devices.

[0069] More specific examples (non-exhaustive list) of computer readable medium include the following: electrical connections having one or more wires (electronic devices), portable computer diskette (magnetic devices), random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM or flash memory), fiber optic devices, and portable compact disk read only memory (CDROM). In addition, the computer readable medium can even be paper or other suitable medium on which the program can be printed, because the program can be obtained electronically, for example, by optical scanning of the paper or other medium, followed by editing, interpreting or otherwise processing the obtained program with the aid of a computer, and then storing it in a computer memory.

[0070] It should be understood that portions of the application can be implemented in hardware, software, firmware, or combinations thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, and in another embodiment, can be implemented using any or a combination of the following which are known in the art: a discrete logic circuit having logic gates for implementing logic functions on data signals, an application specific integrated circuit having appropriate combinational logic gates, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0071] Embodiment 3

[0072] Referring to FIGS. 1-5, for one embodiment of the present application, a protection device hardware-in-the-loop test method is provided, and scientific demonstration is carried out through economic benefit calculation and simulation experiment in order to verify the beneficial effects of the present application.

[0073] The protection device hardware-in-the-loop test method and system based on J-A transient saturation theory described in the present application first builds a simulated primary simulation system in the hardware-in-the-loop simulation test system (this document is referred to as a simulated primary system), that is, a simulation scene to be checked (this document is referred to as a simulation scene to be checked). The elements included can be a generator, a transformer, an infinite system, a transmission line, a load impedance, a mutual inductor, etc., and the hardware composition of the simulated primary system is as shown in FIG. 1. The simulated simulation primary system is as shown in FIG. 2.

[0074] Then, according to the installation position of the protection device to be checked in the simulation scene to be checked, the minimum sampling signal required for the normal operation of the protection device to be checked is determined, and a current transformer model that can be used to restore the transient saturation scene is established. For a P-level current transformer, a P-level mutual inductor J-A transient saturation model is established according to the parameters such as the transformation ratio, the cross-sectional area of the core, and the size of the core. For a TP-level current transformer, an ideal mutual inductor is simulated. The calculation steps of the P-level current transformer J-A transient saturation model are as follows:

[0075] (1) Initialize the model, set the parameters of the P-level current transformer, including the transformation ratio turns N, the equivalent cross section A of the core; the magnetic permeability in vacuum μ0, μ0=4π×10-7T·m / A; the equivalent magnetic flux length of the core l; the resistance R2 and leakage reactance L2 of the secondary circuit of the current transformer. Set the initial excitation current value im(k-1) and the initial magnetization M(k-1), and for the general algorithm flow description, mark the k-1 time as the initial state.

[0076] (2) Calculate the important parameter magnetization rate differential formula of the J-A model considering transient saturation

[0077] The magnetic field strength H(k) = i m (k-1)·N / l (1)

[0078] The J-A theory parameter - effective magnetic field strength H e (k) = H(k) + aM(k-1) (2)

[0079] The J-A theory parameter - non-magnetic hysteresis magnetization strength

[0080] The J-A theory parameter - non-magnetic hysteresis permeability

[0081] The J-A theory parameter - permeability

[0082] In the formula, Ms, c, K, a and a are five key parameters of the J-A model, wherein Ms is the saturation magnetization of the core material; c is the energy loss coefficient; K is the pinning effect constant; a is the shape parameter; a is the magnetic domain wall coupling coefficient, which is easily obtained from the factory magnetization curve of the ferromagnetic material; Man is the magnetization strength assuming no magnetic hysteresis effect of the ferromagnetic material; the calculation of the direction parameter δ is as follows:

[0083] (3) Calculate the excitation current differential formula:

[0084] (4) Then update the output current of the P-level transformer on the secondary side with saturation characteristics in real time according to the change of the primary current. i2(k) = i1(k) / N-i m (k) (8)

[0085] The peripherals interface of the protection device to be verified, such as the current and voltage sampling channel, is connected to the hardware of the simulated primary system, wherein the current signal comes from the mutual inductor model calculation value, and the voltage signal can adopt an ideal voltage transformer. The power amplifier in the simulated primary system can match the analog quantity AIO signal calculated by software and the voltage and current level of the interface of the protection device to be verified, such as the 0-5V line voltage signal output by the simulation system is changed to 0-100V through the power amplifier, and the 0-5V phase current signal output by the simulation system is changed to 0-1A through the power amplifier. The signal of the digital quantity DIO also needs to be matched through the power amplifier before being connected to the actual protection device to be verified.

[0086] After the level matching and the connection are completed, power is supplied to the protection device to be checked, and the simulated primary system can output continuous and stable electrical signals, and correct sampling can be seen on the protection device. Then, a fault scenario is simulated in the simulation scene to be checked, the current signal with transient saturation characteristics calculated by the model is sent to the protection device to be checked for logic judgment, whether the action result is correct is observed, the related process is recorded, then the fault scenario in the simulation scene to be checked is changed, the step 4) is repeated, otherwise the test is ended.

[0087] In this example, a hardware-in-the-loop simulation test is performed on a 330 / 110 kV, 240 MVA double-winding three-phase transformer protection device. According to the factory data, the transformer protection device contains a secondary harmonic braking criterion to avoid unbalanced current such as mutual inductor saturation and transformer excitation inrush, and now the in-depth test is performed. The data such as transformer turns ratio, voltage level, capacity and current transformer ratio in the simulation system are input into the actual protection device, and the corresponding setting value is configured. The P-level mutual inductor of the 330 kV side is 600 / 1, and the secondary load is 7Ω. The P-level current inductor of the 110 kV side is 1200 / 1, and the secondary load is also 7Ω. According to the actual core cross-sectional area and equivalent flux length of the two types of inductors, the J-A parameters describing the non-linear characteristics of the core are used to establish the corresponding current inductor J-A transient saturation model. The key parameters of the J-A model are set as: Ms = 1.8×106, c = 0.1, k = 300, α = 2.5×10-5, a = 100. The key setting values in the transformer protection device are: the "differential starting setting value" is set to 0.3, the "differential ratio braking maximum slope" is set to 0.8, the "inrush blocking function selection" is set to 0 (indicating secondary harmonic braking), and the "secondary harmonic braking coefficient" is selected as 0.30 and 0.65 for comparison test.

[0088] In order to illustrate the benefits of the protection device setting value verification and function test of the present application, a transformer external fault is simulated to illustrate the advancement of the method. A three-phase short-circuit grounding fault is set in the simulation scene to be checked near the 330 kV side, the fault time is 0.7s, and the duration is 0.05s. The protection device trip output signal and three-phase current signal are recorded by the oscillograph. The power impedance parameters of the simulation scene to be checked are set to cause the transient saturation of the P-level current inductor under the fault current, verify the adaptability of the protection device and its setting value to the transient saturation signal, and observe whether the action signal of the protection device is correctly responded.

[0089] Figure 3 shows the three-phase current waveforms calculated by the J-A transient saturation model under the simulation system. In the figure, IA, IB and IC are the current inductor model calculation signals of the 330 kV side, and Ia, Ib and Ic are the current inductor model calculation signals of the 110 kV side.

[0090] Fig. 4 shows the three-phase differential current calculation results and the trip signal recording curve of the transformer protection device when the "second harmonic braking coefficient" is selected as 0.30. Under this setting, although the current transformer is severely distorted and the differential current is obvious, the blocking logic of the protection device correctly blocks, and reliably does not act in the external fault scenario.

[0091] Fig. 5 shows the three-phase differential current calculation results and the trip signal recording curve of the transformer protection device when the "second harmonic braking coefficient" is selected as 0.65. Under this setting, the same transient saturation and the same differential current have caused a misoperation at 0.7339s.

[0092] The results show that the model, test method and system described in the present application can perform hardware-in-the-loop semi-physical simulation testing on the transformer protection device. Compared with the conventional method for checking the protection device, the present method can deeply test the fault scenarios that are difficult to reproduce by conventional methods, and verify the correctness and reliability of the protection device function and its setting value.

[0093] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present application and not to limit it. Although the present application has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present application can be modified or replaced by equivalents without departing from the spirit and scope of the present application, and they should be covered in the scope of the claims of the present application.

Claims

1. A method of testing a protection device hardware in the loop, characterized in that, The method comprises the following steps: constructing a simulation scene in a hardware-in-the-loop simulation test system; determining the minimum sampling signals required for the protection device to be checked to work normally according to the installation position of the protection device to be checked in the simulation scene, establishing a current transformer model capable of restoring the transient saturation scene; performing a power-on operation on the protection device to be checked and making the hardware-in-the-loop simulation test system output electrical signals; when the protection device acquires correct sampling signals, simulating a fault scene in the simulation scene, and determining whether the action result of the protection device meets the setting value and the action logic through the current signal calculated by the model and the logic judgment of the protection device.

2. The protection device hardware-in-the-loop test method of claim 1, wherein: The current transformer model comprises a TP-level current transformer and a P-level current transformer.

3. The protection device hardware-in-the-loop test method of claim 2, wherein: The TP-level current transformer is not considered to have saturation characteristics.

4. The protection device hardware-in-the-loop test method of claim 3, wherein: The P-level current transformer is established with a J-A transient saturation model.

5. The protection device hardware-in-the-loop test method of claim 4, wherein: The establishment of the J-A transient saturation model comprises initializing the model and setting the parameters of the P-level current transformer; calculating the differential formula of the important parameter magnetization rate of the J-A model considering transient saturation; calculating the differential formula of the excitation current; real-time updating the output current of the P-level transformer with saturation characteristics according to the varying primary current.

6. The protection device hardware-in-the-loop test method of claim 5, wherein: The parameters of the P-level current transformer comprise the turns ratio, the equivalent cross section of the core, the magnetic permeability in the vacuum state, the equivalent magnetic flux length of the core, the resistance and leakage reactance of the secondary circuit of the current transformer, the initial excitation current value, and the initial magnetization strength.

7. The protection device hardware-in-the-loop test method of claim 6, wherein: The method comprises the following steps: connecting the current and voltage sampling channels of the protection device to be checked with the hardware of the hardware-in-the-loop simulation test system, and matching the analog quantity AO level of the hardware physical interface board of the hardware-in-the-loop simulation test system; the current signal calculated by the current transformer model in the hardware-in-the-loop simulation test system is connected to the current sampling port of the protection device after signal output and amplification; the voltage signal calculated by the ideal voltage transformer model in the hardware-in-the-loop simulation test system is connected to the voltage sampling port of the protection device after signal output and amplification; 8. A hardware-in-the-loop simulation test system, characterized by, the tripping outlet signal of the protection device to be checked is connected back to the digital quantity DI channel of the hardware physical interface board of the hardware-in-the-loop simulation test system. The method comprises the following steps: a CPU+multi-FPGA simulation test host, a host computer, a power amplifier, a protection device to be checked, a signal cable, a control cable, and an Ethernet cable; the CPU+multi-FPGA simulation test host is used to generate current and voltage signals in a simulation scene and calculate fault scenes through a simulation algorithm; the host computer is connected with the CPU+multi-FPGA simulation test host through an Ethernet cable and is used to set fault scenes and monitor simulation results; the power amplifier amplifies the analog signals output by the simulation host to drive the input channels of the protection device to be checked; the signal cable is connected with the power amplifier and the protection device to be checked and is used to transmit current and voltage signals; the control cable is connected with the protection device to be checked and the simulation test host and is used to transmit incoming and outgoing signals and monitor the action logic of the protection device; the host computer adjusts the fault scene in real time, and the simulation host outputs required signals to the protection device through the power amplifier for verification. 9.A computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the computer device is configured to perform the method according to any one of claims 1-8 when the computer program is executed by the processor. The computer program is executed by the processor to implement the steps of the protection device hardware-in-the-loop test method in any one of claims 1 to 7.

10. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the protection device hardware-in-the-loop test method in any one of claims 1 to 7.

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