Bridging system and computing architecture

Abstract

Disclosed in the present application are a bridging system and a computing architecture in the technical field of computers. The bridging system provided in the present application comprises a root device bridge controller and a slave device bridge controller. The two controllers communicate with each other by using a target bus standard, such that address configuration of the two controllers can be implemented without the aid of a host processor. The communication process does not require the participation of an external CPU, thereby reducing the complexity of chip configurations and communications. While ensuring high-speed data transmission, the present application simplifies and optimizes system architecture, and allows for more flexible overall design, great compatibility, and higher communication efficiency.

Description

A bridging system and computing architecture

[0001] Cross-reference to Related Applications

[0002] This application claims priority to the Chinese patent application No. 202411367256.6, filed on September 29, 2024, and entitled "A bridging system and computing architecture", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present application relates to the field of computer technology, and in particular, to a bridging system and computing architecture. BACKGROUND

[0004] At present, the communication between dual-chip is generally implemented based on a private protocol, and the cost of designing and maintaining the private protocol is relatively high, and the related configuration of the chip needs to be controlled by means of a host. For example, the bus address configuration of a GPU (Graphics Processing Unit) device is processed by a host processor, which increases the complexity of chip configuration and communication. SUMMARY

[0005] Therefore, the purpose of the present application is to provide a bridging system and computing architecture to reduce the complexity of chip configuration and communication. The specific scheme is as follows:

[0006] In a first aspect, the present application provides a bridging system, comprising: a root device bridge controller and a slave device bridge controller; the root device bridge controller and the slave device bridge controller communicate through a target bus standard;

[0007] The root device bridge controller comprises: a target bus configuration module, a request management module and a first address management module;

[0008] The target bus configuration module is configured to configure a slave device to which the slave device bridge controller belongs and a root device to which the root device bridge controller belongs;

[0009] The request management module is configured to respond to a first request packet sent by the slave device bridge controller;

[0010] The first address management module is configured to convert the first request packet from the object bus standard to the target bus standard;

[0011] The slave device bridge controller comprises: a request analysis module, a second address management module, a data mover and an interrupt management module;

[0012] The request analysis module is configured to analyze a second request packet sent by the root device bridge controller;

[0013] The second address management module is configured to convert the second request packet from the target bus standard to the object bus standard.

[0014] The data mover is configured to implement direct memory access according to the analysis result of the second request packet.

[0015] The interrupt management module is configured to manage the interrupt signal between the root device bridge controller and the root device through the target bus standard.

[0016] In some embodiments, the target bus configuration module comprises:

[0017] The slave device configuration unit is configured to perform base address configuration, register configuration and interrupt configuration on the slave device.

[0018] The root device configuration unit is configured to perform base address configuration and register configuration on the root device.

[0019] In some embodiments, the slave device configuration unit is configured to write all 1s to the base address register in the slave device, read the register value from the base address register, take the complement of the read register value and increment it by 1 to obtain the bus space size corresponding to the base address register.

[0020] In some embodiments, the first address management module comprises:

[0021] The first root conversion unit is configured to convert the request based on the object bus standard to the request based on the LITE-based object bus standard.

[0022] The second root conversion unit is configured to convert the request based on the LITE-based object bus standard to the transaction layer data packet based on the target bus standard.

[0023] In some embodiments, the request management module comprises:

[0024] The interrupt request management unit is configured to store the interrupt request by using the register.

[0025] The write request management unit is configured to calculate the corresponding write address according to the write request, and complete the write operation according to the write address.

[0026] The read request management unit is configured to process the read request.

[0027] In some embodiments, the write request management unit comprises:

[0028] The address calculation sub-unit is configured to calculate the write address according to the write request start address, the data length and the first information group in the write request.

[0029] The write length calculation sub-unit is configured to calculate the bus address length according to the write address.

[0030] The write control subunit is configured to complete a corresponding write operation according to the bus address length.

[0031] In some embodiments, the read request management unit includes:

[0032] The cache subunit is configured to cache the read request as a first-in-first-out queue.

[0033] The parsing subunit is configured to parse the read request to obtain read address information.

[0034] The address subunit is configured to parse the read address information to obtain an address resolution result.

[0035] The read control subunit is configured to complete a corresponding read operation according to the address resolution result.

[0036] In some embodiments, the second address management module includes:

[0037] The first slave conversion unit is configured to parse and convert the transaction layer data packet based on the target bus standard.

[0038] The second slave conversion unit is configured to convert to obtain the transaction layer data packet based on the target bus standard.

[0039] The third slave conversion module is configured to implement conversion from the internal bus to the object bus standard.

[0040] In some embodiments, the request parsing module includes:

[0041] The write operation parsing unit is configured to complete a corresponding write operation according to a write descriptor obtained by parsing a write address.

[0042] The read operation parsing unit is configured to complete a corresponding read operation according to a read descriptor obtained by parsing a read address.

[0043] In some embodiments, the write operation parsing unit is specifically configured to: detect whether the write address is legal; if so, calculate a write start address and a data bit width alignment address, splice the write start address and the data bit width alignment address to obtain the write descriptor.

[0044] In some embodiments, the read operation parsing unit is specifically configured to: detect whether the read address is legal; if so, parse the read address to obtain the read descriptor, and complete a corresponding read operation according to the read descriptor.

[0045] In some embodiments, the data mover includes:

[0046] The write mover is configured to encapsulate write data as a transaction layer data packet based on the target bus standard.

[0047] The read mover is configured to output read data to a read data interface based on the object bus standard.

[0048] In some embodiments, the write mover comprises:

[0049] a write descriptor processing unit configured to process write descriptor information of the write data;

[0050] a packet processing unit configured to process write request packet information;

[0051] a write packaging unit configured to package transaction layer data packets based on a target bus standard according to a processing result of the descriptor information and a processing result of the request packet information.

[0052] In some embodiments, the read mover comprises:

[0053] a read descriptor processing unit configured to process read descriptor information of the read data;

[0054] a data parsing and alignment unit configured to complete parsing and alignment of the read data;

[0055] a read cache unit configured to cache the data;

[0056] a mapping unit configured to complete mapping of the data packet to a read data interface based on an object bus standard;

[0057] a read packaging unit configured to complete packaging of the read data.

[0058] In a second aspect, the present application provides a computing architecture, comprising: a root device and a slave device; the root device and the slave device communicate based on the bridge system of any of the above.

[0059] According to the above scheme, the present application provides a bridge system, comprising: a root device bridge controller and a slave device bridge controller; the root device bridge controller and the slave device bridge controller communicate through a target bus standard; wherein the root device bridge controller comprises: a target bus configuration module, a request management module and a first address management module; the target bus configuration module is configured to: configure a slave device to which the slave device bridge controller belongs and a root device to which the root device bridge controller belongs; the request management module is configured to: respond to a first request packet sent by the slave device bridge controller; the first address management module is configured to: convert the first request packet from an object bus standard to a target bus standard; wherein the slave device bridge controller comprises: a request parsing module, a second address management module, a data mover and an interrupt management module; the request parsing module is configured to: parse a second request packet sent by the root device bridge controller; the second address management module is configured to: convert the second request packet from a target bus standard to an object bus standard; the data mover is configured to: realize direct memory access according to a parsing result of the second request packet; the interrupt management module is configured to: manage an interrupt signal between the root device bridge controller through the target bus standard.

[0060] It can be seen that the beneficial effects of the present application are: the root device and the slave device are communicated by using the root device bridge controller and the slave device bridge controller; the root device bridge controller and the slave device bridge controller communicate through the target bus standard; the root device bridge controller comprises a target bus configuration module for configuring the slave device and the root device, a request management module for responding to a first request packet sent by the slave device bridge controller, and a first address management module for converting the first request packet from the object bus standard to the target bus standard; the slave device bridge controller comprises a request analysis module for analyzing a second request packet sent by the root device bridge controller, a second address management module for converting the second request packet from the target bus standard to the object bus standard, a data mover for realizing direct memory access, and an interrupt management module for managing an interrupt signal through the target bus standard. It can be seen that the bridge system provided by the present application is divided into the root device bridge controller and the slave device bridge controller, the two controllers communicate through the target bus standard, the address configuration of the two controllers can be realized without the help of the host processor, the communication process does not need the participation of the external CPU (Central Processing Unit), the complexity of chip configuration and communication is reduced; while ensuring high-speed data transmission, the system architecture is simplified and optimized, the overall design is more flexible, the compatibility is strong, and the communication efficiency is higher.

[0061] Correspondingly, the computing architecture provided by the present application also has the above technical effects. BRIEF DESCRIPTION OF DRAWINGS

[0062] In order to more clearly illustrate the technical solutions of some embodiments of the present application or the prior art, the drawings needed to be used in the embodiment or prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can also obtain other drawings according to the provided drawings without creative labor.

[0063] Fig. 1 is a schematic diagram of a bridge system disclosed by the present application;

[0064] Fig. 2 is a schematic diagram of a PCIe-AXI bridge controller of an RC end disclosed by the present application;

[0065] Fig. 3 is a flow chart of an EP end BAR address configuration method disclosed by the present application;

[0066] Fig. 4 is a schematic diagram of a write operation processing disclosed by the present application;

[0067] Fig. 5 is a schematic diagram of a read operation processing disclosed by the present application;

[0068] Fig. 6 is a schematic diagram of a PCIe-AXI bridge controller of an EP end disclosed by the present application;

[0069] Fig. 7 is a schematic diagram of an AXI write operation according to the present disclosure;

[0070] Fig. 8 is a structural diagram of a write data mover according to the present disclosure;

[0071] Fig. 9 is a structural diagram of a read data mover according to the present disclosure;

[0072] Fig. 10 is a schematic diagram of another bridge system according to the present disclosure;

[0073] Fig. 11 is a structural diagram of an electronic device according to the present disclosure. DETAILED DESCRIPTION

[0074] The technical solutions in some embodiments of the present application will be described clearly and completely below with reference to the drawings of some embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on some embodiments of the present application, all other examples obtained by those skilled in the art without creative labor fall within the scope of the present application.

[0075] At present, the communication between dual-chip is generally implemented based on a private protocol, and the cost of designing and maintaining the private protocol is relatively high, and the related configuration of the chip needs to be controlled by means of a host. For example, the bus address configuration of a GPU device by a host processor increases the complexity of chip configuration and communication. Therefore, the present application provides a bridge communication scheme, which can reduce the complexity of chip configuration and communication.

[0076] Referring to Fig. 1, some embodiments of the present application disclose a bridge system, comprising: a root device bridge controller and a slave device bridge controller; the root device bridge controller and the slave device bridge controller communicate through a target bus standard. The target bus standard can be specifically PCIe (Peripheral Component Interconnect express, a high-speed serial computer expansion bus standard).

[0077] The root device bridge controller comprises: a target bus configuration module, a request management module and a first address management module; the slave device bridge controller comprises: a request analysis module, a second address management module, a data mover and an interrupt management module.

[0078] Further, the functions of the modules in the root device bridge controller are as follows:

[0079] The target bus configuration module is configured to configure the slave device to which the slave device bridge controller belongs and the root device to which the root device bridge controller belongs.

[0080] The request management module is configured to respond to the first request packet sent by the device bridge controller.

[0081] The first address management module is configured to convert the first request packet from an object bus standard to a target bus standard. The object bus standard is specifically an AXI (Advanced eXtensible Interface, a bus protocol).

[0082] When the target bus standard is PCIe and the object bus standard is AXI, the root device bridge controller can serve as a PCIe-AXI bridge controller, and the slave device bridge controller can also serve as a PCIe-AXI bridge controller.

[0083] Further, the functions of the modules in the slave device bridge controller are as follows:

[0084] The request analysis module is configured to analyze the second request packet sent by the root device bridge controller.

[0085] The second address management module is configured to convert the second request packet from the target bus standard to the object bus standard.

[0086] The data mover is configured to implement direct memory access according to the analysis result of the second request packet.

[0087] The interrupt management module is configured to manage the interrupt signal between the root device bridge controller and the slave device bridge controller through the target bus standard.

[0088] In some embodiments, the target bus configuration module includes a slave device configuration unit configured to perform base address configuration, register configuration, and interrupt configuration on the slave device, and a root device configuration unit configured to perform base address configuration and register configuration on the root device. For example, in the form of a CFG0 TLP packet, the main configurations include the BAR bus start address of the slave device, Enable, MPS / MRRS configuration, and MSI interrupt enable and address. The root device configuration space is initialized in an internal APB (Advanced Peripheral Bus) mode, and mainly includes Enable, MPS / MRRS configuration. Among them, MPS (Max Payload Size) represents the maximum value of the effective payload carried in a TLP packet in bytes; MRRS (Max Read Request Size) represents the maximum number of bytes that can be requested to read from the receiving end at a time in a TLP read request packet.

[0089] In some embodiments, the slave configuration unit is configured to: write all 1s to a base address register in the slave device, read the register value from the base address register, and obtain the bus space size corresponding to the base address register by performing a bitwise NOT operation on the read register value and then incrementing the result by 1. For example, write all 1s to the bar base address register, then read the value of the register, and perform a bitwise NOT operation on the returned result and then increment the result by 1 to obtain the preset space size of the current bar. If the current bar space is 32 bits, 32-bit preset addresses are written; if the current bar space is 64 bits, it is further determined whether the current bar space size exceeds 32 bits. If the current bar space size does not exceed 32 bits, the start addresses of the current bar and the next bar (combined as a 64-bit bar) can be directly set. Otherwise, all 1s are further written to the next bar (high 32 bits) and the written value is read to obtain the 64-bit preset space size of the entire bar. Finally, the start addresses of the low 32-bit bar and the high 32-bit bar are set in sequence. If the current bar is not enabled (i.e., the value read after all 1s are written to the bar is all 0s), the bar is directly skipped for initialization of the next bar. This process is repeated until the last bar.

[0090] In some embodiments, the first address management module includes: a first root conversion unit configured to convert a request based on an object bus standard to a request based on a LITE (Light Industrial Terminal Equipment) object bus standard, including conversion of data bit width, address, and burst storage, etc. A second root conversion unit is configured to convert a request based on the LITE object bus standard to a transaction layer data packet based on a target bus standard. For example, the conversion of AXI LITE interface and TLP (Transaction Layer Packet) packet and the conversion of AXI address range and BAR space are performed. The conversion formula is: (INPUT_ADDR-CH_RANGE_L)+BAR base address, INPUT_ADDR is the AXI address, CH_RANGE_L is the low address of the corresponding BAR range, and BAR base address is the BAR base address output by the EP initialization module. AXI-LITE is a lightweight AXI protocol, which is a type of AXI4 protocol.

[0091] In some embodiments, the request management module includes: an interrupt request management unit configured to store interrupt requests using registers; a write request management unit configured to calculate a corresponding write address according to a write request and complete a write operation according to the write address; and a read request management unit configured to process a read request.

[0092] In some embodiments, the write request management unit comprises: an address calculation subunit configured to calculate a write address according to a write request start address, a data length, and the first information group in the write request; for example, the AXI write start address and end address are calculated according to the start address, the FBE (First DW Byte Enable), the LBE (Last DW Byte Enable), and the length LENGTH of the TLP packet. A write length calculation subunit is configured to calculate a bus address length according to the write address; for example, the AXI write length is calculated according to the calculated start address and end address. A write control subunit is configured to complete a corresponding write operation according to the bus address length; specifically, the logical control of the AXI write address and write data is completed under the control of a state machine according to the address length information. The FBE and the LBE respectively indicate whether the data bytes in the first DW (Double Word) and the last DW in the TLP are valid, and each bit indicates one byte; one DW represents four bytes.

[0093] In some embodiments, the read request management unit comprises: a cache subunit configured to cache the read request as a first-in-first-out queue; an analysis subunit configured to analyze the read request to obtain read address information; an address subunit configured to analyze the read address information to obtain an address analysis result; and a read control subunit configured to complete a corresponding read operation according to the address analysis result.

[0094] In some embodiments, the second address management module comprises: a first slave conversion unit configured to analyze and convert a transaction layer data packet based on a target bus standard, including: reception of a TLP packet, 32bit / 64bit Mwr (DMA write), Mrd (BMA read) protocol analysis, and conversion of a local data bus. A second slave conversion unit is configured to convert a transaction layer data packet based on a target bus standard, including: conversion of the local data bus to an internal APB bus, conversion of the APB bus to a TLP packet, and address conversion; and a third slave conversion module configured to realize conversion of an internal bus to an object bus standard, for example, to complete conversion of the internal APB bus to an AXI bus.

[0095] In some embodiments, the request analysis module comprises:

[0096] The write operation analysis unit is configured to complete corresponding write operation according to a write descriptor obtained by analyzing a write address. For example, the AXI write address is subjected to legality judgment, and it is judged whether it is in the preset range of each channel. If the AXI write address is in the preset range of each channel, corresponding conversion is performed according to the formula, and the output start address is aligned according to the large data bit width. The data channel is first subjected to a beat processing, and then the corresponding byte offset and byte count are calculated. If the byte count does not match the burst length Aw_len of the AXI write address channel transmitted by the address channel or the address is not in the range of each channel, the AXI response signal Bresp returns abnormal information, and data movement is not performed. Otherwise, the start byte offset address and the large data bit width alignment address are spliced to obtain the write descriptor start address, the data is sent to the large cache after being subjected to beat cache, and the data stream is written under the control of the state machine.

[0097] The read operation analysis unit is configured to complete corresponding read operation according to a read descriptor obtained by analyzing a read address. Specifically, the read address is subjected to legality judgment and corresponding address conversion, and the read descriptor length needs to be converted from Arlen to Byte length unit.

[0098] In some embodiments, the write operation analysis unit is specifically configured to: detect whether the write address is legal; if legal, calculate a write start address and a data bit width alignment address, and splice the write start address and the data bit width alignment address to obtain a write descriptor.

[0099] In some embodiments, the read operation analysis unit is specifically configured to: detect whether the read address is legal; if legal, analyze the read address to obtain a read descriptor, and complete corresponding read operation according to the read descriptor.

[0100] In some embodiments, the data mover comprises: a write mover configured to encapsulate write data into transaction layer packets based on a target bus standard. For example, according to a descriptor output by AXI write resolution and a preset max_payload (i.e., MPS), data cached by the AXI write resolution is encapsulated into a TLP packet and sent to a PCIe module. The read mover is configured to output read data to a read data interface based on the target bus standard. For example, according to a read descriptor output by AXI read resolution and a preset max_read_req_size (i.e., MRRS), a plurality of TLP packet read requests (4K, including max_read_req_size and RCB boundary) are obtained by splitting and tag management is performed, wherein each Non-Posted operation that needs to return a completion has a separate tag. Finally, a CplD (return packet) from the PCIe module is parsed, cached and output to an AXI read data port. RCB (Read Completion Boundary) is the maximum aligned byte boundary of a data packet that can be returned when reading a PCIe memory. CplD (Completion with data TLP) specifically refers to a read completion packet with data.

[0101] In some embodiments, the write mover comprises: a write descriptor processing unit configured to process write descriptor information of write data; a packet processing unit configured to process write request packet information; and a write encapsulation unit configured to encapsulate, according to a processing result of the descriptor information and a processing result of the request packet information, a transaction layer packet based on a target bus standard.

[0102] In some embodiments, the read mover comprises: a read descriptor processing unit configured to process read descriptor information of read data; a data parsing and alignment unit configured to complete parsing and alignment of the read data; a read cache unit configured to cache the data; a mapping unit configured to complete mapping of the data packet to a read data interface based on a target bus standard; and a read encapsulation unit configured to complete encapsulation of the read data.

[0103] It can be seen that some embodiments of the application utilize a root device bridge controller and a slave device bridge controller to enable the root device and the slave device to communicate; wherein the root device bridge controller and the slave device bridge controller communicate through a target bus standard; and the root device bridge controller comprises a target bus configuration module configured to configure the slave device and the root device, a request management module configured to respond to a first request packet sent by the slave device bridge controller, and a first address management module configured to convert the first request packet from an object bus standard to the target bus standard; and the slave device bridge controller comprises a request analysis module configured to analyze a second request packet sent by the root device bridge controller, a second address management module configured to convert the second request packet from the target bus standard to the object bus standard, a data mover configured to implement direct memory access, and an interrupt management module configured to manage an interrupt signal through the target bus standard. It can be seen that the bridge system provided by the application is divided into two parts, the root device bridge controller and the slave device bridge controller, and the two controllers communicate through the target bus standard, without the need for a host processor to realize address configuration of the two controllers, and the communication process does not need to involve an external CPU, thereby reducing the complexity of chip configuration and communication; while ensuring high-speed data transmission, the system architecture is simplified and optimized, the overall design is more flexible, the compatibility is strong, and the communication efficiency is higher.

[0104] It should be noted that PCIe is the third generation of high-performance general-purpose IO bus, which is used for interconnection of peripheral devices in computer and communication platform applications, and can realize serial point-to-point double-channel high-bandwidth transmission. PCIe adopts a tree topology structure, which generally consists of a root device component (Root Complex), a switching device (Switch) and a terminal slave device (End Point). The Root Complex is a bridge between CPU instructions and PCIe TLP packets, and is used to complete mutual decoding of the two. The main purpose of the Switch is to expand the PCIe bus, which generally has one upstream port and multiple downstream ports. The Endpoint is a leaf node of the PCIe tree structure.

[0105] The AXI protocol is the most important part of the AMBA (Advanced Microcontroller Bus Architecture) 3.0 protocol proposed by ARM Company, and is an on-chip bus with high performance, high bandwidth and low delay. The AXI4 protocol supports three types of interfaces: AXI4, AXI4-LITE and AXI4-Stream. Among them, AXI4 is a high-performance memory-mapped interface, which is used to access memory and other high-speed data transmission scenarios that need to specify addresses. AXI4-LITE is a simplified version of the AXI4 interface, which is used to access some low-speed peripherals. AXI4-Stream is a high-speed data stream transmission interface, which is used for continuous data reading and writing between master and slave devices without address.

[0106] Generally, the PCIe hard core provided by the FPGA (Field-Programmable Gate Array) can be instantiated as a Root Complex or an Endpoint, and the interface provided for the user is an AXI-Stream interface, which is used to send and receive TLP packets. The FPGA local memory interface generally adopts a common AXI4 interface, and if the data interaction between the local memory and the remote memory is implemented, the address conversion between the AXI domain and the PCI domain needs to be completed.

[0107] The PCIe-AXI bridge controller can realize the AXI interface communication of the RC end and the EP end based on the PCIe protocol. The RC end AXI MASTER can read and write the storage space corresponding to the BAR address of the EP end, and the EP end AXI MASTER reads and writes the local storage space of the RC end in a large data amount in a DMA (Direct Memory Access) mode. Specifically, the RTL (Register Transfer Level) design can be completely adopted, so as to facilitate the transplantation on various FPGA platforms, and the design is flexible and efficient, and matches multiple design scenarios. The PCIe-AXI bridge controller mainly completes the mutual conversion between the PCIe transaction layer TLP packet and the AXI read-write request. The EP end can use the memory space of the RC end as if it uses the local memory. The RC end can access the BAR space of the EP end as if it accesses the local memory.

[0108] Based on the above, some embodiments of the application realize the PCIe-AXI bridge controller based on the FPGA design, which includes two parts of the RC end PCIe-AXI bridge controller and the EP end PCIe-AXI bridge controller.

[0109] The RC end PCIe-AXI bridge controller can refer to FIG. 2, and mainly includes three parts of the PCIe configuration space initialization (that is, a target bus configuration module), the BAR read-write management (that is, a first address management module), and the Mwr / Mrd read-write management (a request management module). The PCIe configuration space initialization completes the EP Bar space base address configuration, the RC and EP MPS / MRRS configuration, and the EP end MSI interrupt enable and address configuration. The BAR read-write management completes the conversion (including address space conversion) of the AXI read-write request to the TLP packet. The Mwr / Mrd read-write management completes the processing of the request from the EP end Mrd / Mwr / MSI.

[0110] PCIe configuration space initialization is divided into EP and RC control separately. EP configuration space initialization takes CFG0 TLP package form, mainly configuring BAR start address, Enable, MPS / MRRS configuration and MSI interrupt enable and address; while RC configuration space initialization takes internal APB bus form, mainly including Enable, MPS / MRRS configuration.

[0111] The configuration of EP end BAR start address needs to judge the address space size of each BAR. Firstly, write all 1s to the bar base address register, then read the value of the register, and the returned result is negated and added 1, which is the preset space size of the current bar. If the current bar space is 32 bits, write 32-bit preset address; if the current bar space is 64 bits, further judge whether the current bar space size exceeds 32 bits, if it does not exceed 32 bits, the start address of the current bar and the next bar (combined as a 64-bit bar) can be directly set, otherwise, further write all 1s to the next bar (high 32 bits) and read the written value, and then get the 64-bit preset space size of the entire bar, and finally set the start address of the low 32-bit and high 32-bit bar in turn; if the current bar is not enabled (i.e. the value read after writing all 1s to the bar is all 0s), directly skip the initialization of the next bar, and so on, until the last bar. The specific configuration flow chart is shown in Figure 3.

[0112] BAR read-write management mainly includes AXI2AXILITE (i.e. the first root conversion unit) and AXILITE2TLP (i.e. the second root conversion unit). AXI2AXILITE completes the conversion of AXI to AXILITE interface, including data bit width, address and burst storage conversion, divided into AXI read adaptation module and AXI write adaptation module. AXILITE2TLP completes the conversion of AXILITE interface and TLP package and the conversion of AXI address range and BAR space, the conversion formula is (INPUT_ADDR-CH_RANGE_L)+BAR base address, INPUT_ADDR is AXI address, CH_RANGE_L is the low address of the corresponding BAR range, and BAR base address is the BAR base address output by the EP initialization module.

[0113] Mwr / Mrd management mainly processes and responds to Mwr / Mrd requests from EP. Among them, Mwr includes MSI interrupt request and data write request. MSI interrupt write request is parsed and saved in internal APB register.

[0114] The Mwr data write request includes four modules of Rx_ctrl (receive control), Cal_len (length calculation), Addr_ctrl (address management) and Data_ctrl (data management). The Rx_ctrl calculates the AXI write start address, end address according to the start address, FBE, LBE and LENGTH of the TLP packet. The Cal_len then calculates the AXI write length according to the start address and end address calculated by the Rx_ctrl. The Addr_ctrl and Data_ctrl complete the logical control of the AXI write address and write data under the control of the state machine according to the address length information. Details are shown in FIG. 4.

[0115] The Mrd data read request includes four modules of FIFO buffer (i.e. buffer subunit), Fork (analysis and splitting subunit), Axim2s (read address data management, corresponding address subunit) and CplD Tx (return packet sending, corresponding read control subunit). The FIFO buffer is from the Mrd TLP request (tentatively 32) of the EP. The Fork is used for analyzing the information of the source address, length, FBE, LBE, TAG and Request_id of the TLP packet and copying two-way output. One way is given to the AXI read address data processing module Axim2s, and the other way is given to the CplD packaging sending module CplD Tx. The Axim2s module mainly completes address analysis, alignment and AXI read address and read data logical control. The CplD Tx module completes data packet phase alignment and packaging. Details are shown in FIG. 5. The Request_id field includes the bus number Bus Number, device number Device Number and function number Function Number of the PCIe device generating the TLP message.

[0116] The design block diagram of the EP end PCIe-AXI bridge controller is shown in FIG. 6, which mainly includes four parts of BAR read-write management (corresponding to the second address management module), AXI read-write analysis (corresponding to the request analysis module), read-write data mover and interrupt management. The BAR read-write management mainly completes the conversion of the TLP (Transaction Layer Packet) packet read-write request to the AXI read-write control (including address space conversion). The AXI read-write analysis mainly completes the conversion of the AXI read-write instruction to the read-write descriptor, write data buffer analysis and address space conversion. The read-write data mover mainly completes the DMA read-write logical control and TLP packet header packaging. The interrupt management mainly completes the management of the traditional interrupt and MSI interrupt reporting.

[0117] The BAR read-write management mainly includes three parts of TLP2LB (corresponding to the first slave conversion unit), LB2TLP (corresponding to the second slave conversion unit) and APB2AXIMM (corresponding to the third slave conversion module). The TLP2LB mainly completes the reception of the TLP package, the 32bit / 64bit Mwr, the Mrd protocol analysis and the conversion of the local data bus. The LB2TLP mainly completes the conversion of the local data bus to the internal APB bus, the conversion of the APB bus to the TLP package and the address conversion. The APB2AXIMM mainly completes the conversion of the internal APB bus to the AXI bus, and supports the byte mask. The PCIe Bar is converted into the AXI domain, and a maximum of bar0-bar5 is supported. The bar space size is configured on the hard core module, and the offset address can be set according to the requirement when each path is mapped to the AXI domain.

[0118] The AXI write analysis completes the conversion of the AXI write command to the write descriptor and the AXI write data buffering and analysis (wstrb and write address start byte offset). First, the AXI write address is judged for legality, whether it is in the preset range of each path. If the AXI write address is in the preset range of each path, the corresponding conversion is performed according to the formula. At this time, the output start address is aligned according to the large data width. The data channel is first processed by a beat, and then the corresponding byte offset and byte count are calculated. If the byte count does not match the Aw_len input by the address channel or the address is not in the range of each channel, the Bresp returns an exception information, and no data moving is performed. Otherwise, the start byte offset address and the large data width alignment address are spliced to calculate the write descriptor start address. The data is sent to the large cache after being buffered by the beat, and the data stream is written under the control of the state machine. The specific process is shown in FIG. 7.

[0119] The AXI read analysis is relatively simple. Only the legality of the read address is judged and the corresponding address conversion is performed. The read descriptor length needs to be converted from Arlen to Byte length unit.

[0120] The write data mover mainly encapsulates the data buffered by the AXI write analysis into a TLP package and sends it to the PCIe module according to the descriptor output by the AXI write analysis and the preset max_payload. The write data mover mainly includes three modules of mwr_ctrl (write control management), axim2s (data stream analysis) and tx_mw (sending management). The mwr_ctrl completes the analysis, splitting (4K and max_payload boundary) and FBE, LBE analysis of the write descriptor. The Axim2s completes the analysis of the package header, the package start position: keep_start_site and the length of keep keep_len. The mwr_ctrl completes the data package alignment and TLP package encapsulation according to the output information of the above two modules. The specific process is shown in FIG. 8.

[0121] The read data mover mainly splits a read descriptor output according to AXI read analysis and a preset max_read_req_size to obtain a plurality of TLP package read requests (4K, including max_read_req_size and RCB boundaries), and performs Tag management, finally analyzes, caches and outputs CplD from the PCIe module to the AXI read data port. The read data mover mainly includes five parts of Mrd_ctrl (read control management), Rx_cpld (return packet analysis), Mem_cpld (data caching and processing), Axis2m (interface conversion) and Tx_mrd (sending management). Mrd_ctrl completes descriptor splitting management, Tag management and recycling. Rx_cpld completes CplD analysis and data alignment. Mem_cpld completes data caching, tag disorder processing and data packet splicing. Axis2m completes the mapping of the data packet to the AXI read data channel interface. Tx_mrd completes the encapsulation of the read descriptor information into the Mrd TLP package, as shown in FIG. 9.

[0122] The interrupt management module supports traditional interrupts INTX (Interrupt eXternal, external interrupt) and MSI (Message Signal Interrupt, message signal interrupt), and the interrupt type can be defined in the header file to automatically generate the corresponding module. The MSI supports 32-bit and 64-bit addresses, and a maximum of 32 interrupts. The MSI interrupt can adopt a standardized TLP package form, or can be directly connected to the interrupt management interface of the PCIe module.

[0123] In some embodiments of the present application, a PCIe-AXI bridge controller is designed based on a programmable logic device FPGA as a hardware implementation. The design is completely implemented in RTL, facilitating porting to various platforms. The design block diagram is shown in FIG. 10. Among them, the RC end can automatically / manual configure the EP bar space starting address, MSI interrupt configuration register, support double AXI address 64bit, data bit width arbitrary configuration (32 integer multiple), RC and EP MPS / MRRS according to the maximum value supported by each other automatic configuration (128-4096), only need to modify the peripheral matching interface can adapt to various FPGA platform. Various address conversion parameterized control, or can be modified through the internal APB bus flexibly; the overall design is flexible and efficient. Based on the PCIe-AXI bridge controller, the RC end and the EP end can realize AXI interface communication based on the PCIe protocol. The RC end AXI MASTER can read and write the BAR address corresponding storage space of the EP end, and the EP end AXI MASTER can read and write the local storage space of the RC end in the form of DMA. The present application is completely designed in RTL, without introducing any third-party chip, facilitating porting to various platforms. The present application realizes chip interconnection based on the PCIe protocol, and the internal bus adopts standardized AXI protocol, with strong universality; greatly simplifies the system architecture, while ensuring high bandwidth and low delay.

[0124] The following describes a computing architecture provided by some embodiments of the present application. The computing architecture described below can be referred to with other embodiments described herein.

[0125] Some embodiments of the present application disclose a computing architecture, comprising: a root device and a slave device; the root device and the slave device communicate based on the bridge system of any of the above embodiments.

[0126] In some embodiments, the bridge system comprises: a root device bridge controller and a slave device bridge controller; the root device bridge controller and the slave device bridge controller communicate through the target bus standard.

[0127] Among them, the root device bridge controller comprises: a target bus configuration module, a request management module and a first address management module; the target bus configuration module is used for: configuring the slave device to which the slave device bridge controller belongs and the root device to which the root device bridge controller belongs; the request management module is used for: responding to the first request packet sent by the slave device bridge controller; the first address management module is used for: converting the first request packet from the object bus standard to the target bus standard;

[0128] The slave device bridge controller comprises a request resolving module, a second address management module, a data mover and an interrupt management module. The request resolving module is configured to resolve a second request packet sent by the root device bridge controller. The second address management module is configured to convert the second request packet from a target bus standard to an object bus standard. The data mover is configured to implement direct memory access according to a resolving result of the second request packet. The interrupt management module is configured to manage an interrupt signal between the root device bridge controller and the slave device bridge controller through the target bus standard.

[0129] In some embodiments, the target bus configuration module comprises a slave device configuration unit configured to configure a base address, registers and interrupts of the slave device, and a root device configuration unit configured to configure a base address and registers of the root device.

[0130] In some embodiments, the slave device configuration unit is configured to write all 1s to a base address register of the slave device, read a register value from the base address register, take a bitwise NOT of the read register value and increment the bitwise NOT result by 1 to obtain a bus space size corresponding to the base address register.

[0131] In some embodiments, the first address management module comprises a first root conversion unit configured to convert a request based on the object bus standard to a request based on the LITE-based object bus standard, and a second root conversion unit configured to convert the request based on the LITE-based object bus standard to a transaction layer data packet based on the target bus standard.

[0132] In some embodiments, the request management module comprises an interrupt request management unit configured to store an interrupt request by using a register, a write request management unit configured to calculate a corresponding write address according to a write request and complete a write operation according to the write address, and a read request management unit configured to process a read request.

[0133] In some embodiments, the write request management unit comprises an address calculation subunit configured to calculate a write address according to a write request start address, a data length and a first information group in the write request, a write length calculation subunit configured to calculate a bus address length according to the write address, and a write control subunit configured to complete a corresponding write operation according to the bus address length.

[0134] In some embodiments, the read request management unit comprises a cache subunit configured to cache a read request as a first-in-first-out queue, a resolving subunit configured to resolve the read request to obtain read address information, an address subunit configured to resolve the read address information to obtain an address resolving result, and a read control subunit configured to complete a corresponding read operation according to the address resolving result.

[0135] In some embodiments, the second address management module comprises: a first slave conversion unit configured to parse and convert the transaction layer packet based on the target bus standard; a second slave conversion unit configured to convert the transaction layer packet based on the target bus standard; and a third slave conversion unit configured to implement conversion from the internal bus to the object bus standard.

[0136] In some embodiments, the request parsing module comprises: a write operation parsing unit configured to complete a corresponding write operation according to a write descriptor obtained by parsing a write address; and a read operation parsing unit configured to complete a corresponding read operation according to a read descriptor obtained by parsing a read address.

[0137] In some embodiments, the write operation parsing unit is specifically configured to: detect whether the write address is legal; if the write address is legal, calculate a write start address and a data bit width alignment address, splice the write start address and the data bit width alignment address to obtain the write descriptor.

[0138] In some embodiments, the read operation parsing unit is specifically configured to: detect whether the read address is legal; if the read address is legal, parse the read address to obtain the read descriptor, and complete a corresponding read operation according to the read descriptor.

[0139] In some embodiments, the data mover comprises: a write mover configured to encapsulate write data into a transaction layer packet based on the target bus standard; and a read mover configured to output read data to a read data interface based on the object bus standard.

[0140] In some embodiments, the write mover comprises: a write descriptor processing unit configured to process write descriptor information of the write data; a packet processing unit configured to process write request packet information; and a write encapsulation unit configured to encapsulate the transaction layer packet based on the target bus standard according to a processing result of the descriptor information and a processing result of the request packet information.

[0141] In some embodiments, the read mover comprises: a read descriptor processing unit configured to process read descriptor information of the read data; a data parsing and alignment unit configured to complete parsing and alignment of the read data; a read cache unit configured to cache the data; a mapping unit configured to complete mapping of the data packet to the read data interface based on the object bus standard; and a read encapsulation unit configured to complete encapsulation of the read data.

[0142] In some embodiments, the more specific working processes of the various modules and units in the embodiments of the present application can refer to the corresponding contents disclosed in the foregoing embodiments, which will not be described herein.

[0143] It can be seen that the bridge system of some embodiments of the present application is divided into a root device bridge controller and a slave device bridge controller, the two controllers communicate with each other using a target bus standard, the address configuration of the two controllers can be realized without the help of a host processor, the communication process does not need to involve an external CPU, the complexity of chip configuration and communication is reduced, while ensuring high-speed data transmission, the system architecture is simplified and optimized, the overall design is more flexible, the compatibility is strong, and the communication efficiency is higher.

[0144] An electronic device provided by some embodiments of the present application is introduced below, and the electronic device described below can be referred to with other embodiments described herein. The electronic device of some embodiments of the present application can be any functional module described in the above embodiments.

[0145] Referring to FIG. 11, some embodiments of the present application disclose an electronic device, comprising:

[0146] The memory 1101 is configured to save a computer program.

[0147] The processor 1102 is configured to execute the computer program to realize the method functions realized by any functional module described in the above embodiments.

[0148] An electronic device provided by some embodiments of the present application is introduced below, and the electronic device described below can be referred to with other embodiments described herein. The electronic device of some embodiments of the present application can be any functional module described in the above embodiments.

[0149] A non-volatile storage medium is configured to save a computer program, wherein the computer program is executed by a processor to realize the method functions realized by any functional module described in the above embodiments. The non-volatile storage medium is a computer-readable non-volatile storage medium, which is a carrier for resource storage and can be a read-only memory, a random access memory, a magnetic disk or an optical disk, etc. The resources stored on the non-volatile storage medium include an operating system, a computer program and data, etc. The storage mode can be temporary storage or permanent storage.

[0150] A computer program product provided by some embodiments of the present application is introduced below, and the computer program product described below can be referred to with other embodiments described herein.

[0151] A computer program product comprises a computer program / instruction, which is executed by a processor to realize the method functions realized by any functional module described in the above embodiments.

[0152] Each embodiment in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same or similar parts of each embodiment can be referred to each other.

[0153] The steps of a method or algorithm described in connection with the embodiments disclosed herein can be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module can reside in random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disk, a removable disk, a CD-ROM, or any other form of non-transitory storage medium known in the art. The term "non-transitory" simply means a computer-readable medium that does not include a transient signal.

[0154] The principles and implementations of the present application have been described in relation to specific examples, which are presented only by way of illustration and for purposes of description and should not be construed as limiting the present application.

Claims

1. A bridging system, characterized in that The application relates to a root device bridge controller and a slave device bridge controller. The root device bridge controller and the slave device bridge controller communicate through a target bus standard; The root device bridge controller comprises a target bus configuration module, a request management module and a first address management module; The target bus configuration module is configured to configure a slave device to which the slave device bridge controller belongs and a root device to which the root device bridge controller belongs; The request management module is configured to respond to a first request packet sent by the slave device bridge controller; The first address management module is configured to convert the first request packet from an object bus standard to a target bus standard; The slave device bridge controller comprises a request analysis module, a second address management module, a data mover and an interrupt management module; The request analysis module is configured to analyze a second request packet sent by the root device bridge controller; The second address management module is configured to convert the second request packet from a target bus standard to an object bus standard; The data mover is configured to realize direct memory access according to an analysis result of the second request packet; The interrupt management module is configured to manage an interrupt signal with the root device bridge controller through a target bus standard. The target bus configuration module comprises:

2. The bridging system of claim 1, wherein, A slave device configuration unit configured to perform base address configuration, register configuration and interrupt configuration on the slave device; A root device configuration unit configured to perform base address configuration and register configuration on the root device. The slave device configuration unit is configured to write all 1s to a base address register in the slave device, read a register value from the base address register, take the complement of the read register value and increment by one to obtain a bus space size corresponding to the base address register.

3. The bridging system of claim 2, wherein, The first address management module comprises:

4. The bridging system of claim 1, wherein, A first root conversion unit configured to convert a request based on an object bus standard into a request based on an object bus standard of LITE; A second root conversion unit configured to convert a request based on an object bus standard of LITE into a transaction layer data packet based on a target bus standard. The first root conversion unit is specifically configured to perform conversion of at least data bit width, address and burst storage.

5. The bridging system of claim 4, wherein, The request management module comprises:

6. The bridging system of claim 1, wherein, An interrupt request management unit configured to store an interrupt request by using a register; A write request management unit configured to calculate a corresponding write address according to a write request and complete a write operation according to the write address; A read request management unit configured to process a read request. The write request management unit comprises:

7. The bridging system of claim 6, wherein, An address calculation subunit configured to calculate the write address according to a write request start address, a data length and a first information group in the write request; A write length calculation subunit configured to calculate a bus address length according to the write address; A write control subunit configured to complete a corresponding write operation according to the bus address length. The read request management unit comprises:

8. The bridging system of claim 6, wherein, A cache subunit configured to cache a read request as a first-in-first-out queue; An analysis subunit configured to analyze the read request to obtain read address information; ​ An address subunit configured to parse the read address information to obtain an address resolution result; A read control subunit configured to complete a corresponding read operation according to the address resolution result.

9. The bridging system of claim 1, wherein, The second address management module comprises: A first slave conversion unit configured to parse and convert a transaction layer data packet based on a target bus standard; A second slave conversion unit configured to convert to obtain a transaction layer data packet based on a target bus standard; A third slave conversion module configured to implement conversion from an internal bus to an object bus standard.

10. The bridging system of claim 1, wherein, The request analysis module comprises: A write operation analysis unit configured to complete a corresponding write operation according to a write descriptor obtained by analyzing a write address; A read operation analysis unit configured to complete a corresponding read operation according to a read descriptor obtained by analyzing a read address.

11. The bridging system of claim 10, wherein, The write operation analysis unit is specifically configured to: detect whether the write address is legal; if legal, calculate a write start address and a data bit width alignment address, and splice the write start address and the data bit width alignment address to obtain the write descriptor.

12. The bridging system of claim 11, wherein, The write operation analysis unit is specifically configured to determine that the write address is legal if the write address is within a preset range of each channel.

13. The bridging system of claim 10, wherein, The read operation analysis unit is specifically configured to: detect whether the read address is legal, if legal, analyze the read address to obtain the read descriptor, and complete a corresponding read operation according to the read descriptor.

14. The bridging system of claim 1, wherein, The data mover comprises: A write mover configured to encapsulate write data into a transaction layer data packet based on a target bus standard; A read mover configured to output read data to a read data interface based on an object bus standard.

15. The bridging system of claim 14, wherein, The write mover comprises: A write descriptor processing unit configured to process write descriptor information of write data; A packet processing unit configured to process write request packet information; A write encapsulation unit configured to encapsulate to obtain a transaction layer data packet based on a target bus standard according to a processing result of the descriptor information and a processing result of the request packet information.

16. The bridging system of claim 14, wherein, The read mover comprises: A read descriptor processing unit configured to process read descriptor information of read data; A data analysis and alignment unit configured to complete analysis and alignment of read data; A read cache unit configured to cache data; A mapping unit configured to complete mapping of a data packet to a read data interface based on an object bus standard; A read encapsulation unit configured to complete encapsulation of read data.

17. The bridging system of claim 1, wherein, The target bus standard is a high-speed peripheral component interconnect standard.

18. The bridging system of claim 1, wherein, The object bus standard is a high-level extensible interface.

19. The bridging system of claim 1, wherein, The interrupt management module comprises an external interrupt and a message signal interrupt.

20. A computing architecture characterized by, Comprise: A root device and a slave device; the root device and the slave device communicate based on the bridge system of any one of claims 1 to 19.

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