Display substrate and manufacturing method therefor, and display apparatus

Abstract

A display substrate and a manufacturing method therefor, and a display apparatus. The display substrate comprises a driving structure layer and a light-emitting structure layer that are arranged on a base substrate, the driving structure layer comprises a plurality of circuit units, and the light-emitting structure layer comprises a plurality of first light-emitting devices; the circuit units at least include first circuit units and second circuit units, each of the first circuit units and the second circuit units comprises a pixel driving circuit, the pixel driving circuits of the first circuit units are connected to the first light-emitting devices, while the pixel driving circuits of the second circuit units are not connected to the first light-emitting devices; and the at least one of the second circuit units further comprises at least one transverse connection line extending in a first direction and at least one vertical connection line extending in a second direction, wherein the transverse connection line is connected to the vertical connection line to form a mesh-like interconnected structure, and the first direction intersects the second direction.

Description

Display substrate, preparation method thereof and display device

[0001] The present application claims priority to the Chinese patent application No. 202411355755.3, filed on September 26, 2024, and entitled "Display substrate, preparation method thereof and display device", the content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of display, in particular to a display substrate, a preparation method thereof and a display device. BACKGROUND

[0003] Organic light emitting diode (OLED) and quantum dot light emitting diode (QLED) are active light emitting display devices, which have the advantages of self-luminous, wide viewing angle, high contrast, low power consumption, extremely high response speed, lightness, flexibility, low cost, etc. With the continuous development of display technology, flexible display devices with OLED or QLED as light emitting devices and controlled by thin film transistors (TFT) have become the mainstream products in the current display field. SUMMARY

[0004] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0005] In one aspect, the present disclosure provides a display substrate, comprising a first display area and a second display area, the first display area at least partially surrounding the second display area, the first display area being configured to display images, and the second display area being configured to display images and transmit light; the first display area comprises a driving structure layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate, the driving structure layer comprises a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, and the light-emitting structure layer comprises a plurality of first light-emitting devices; the circuit units at least include first circuit units and second circuit units, the first circuit units and the second circuit units each include a pixel driving circuit, the pixel driving circuit of the first circuit units is connected with the first light-emitting devices, and the pixel driving circuit of the second circuit units is not connected with the first light-emitting devices; at least one second circuit unit further comprises at least one horizontal connection line extending along a first direction and at least one vertical connection line extending along a second direction, the horizontal connection line is connected with the vertical connection line to form a meshed communication structure, and the first direction and the second direction intersect.

[0006] In an exemplary embodiment, in at least one first circuit unit, the pixel driving circuit at least includes a storage capacitor, a first reset transistor, a second reset transistor, and a first light-emitting control transistor, a first electrode of the first reset transistor is connected with a first initial signal line through a fifth connection electrode, a second electrode of the first reset transistor is connected with a first electrode plate of the storage capacitor through a first connection electrode, a first electrode of the first light-emitting control transistor is connected with a second electrode plate of the storage capacitor through a third connection electrode, a first electrode of the second reset transistor is connected with a second initial signal line through a sixth connection electrode, the third connection electrode is connected with a first power supply line, and a plurality of the second electrode plates in at least one unit row form a horizontal power supply signal line; in at least one second circuit unit, the vertical connection line includes the first connection electrode, the third connection electrode, and the fifth connection electrode, the first connection electrode is connected with the third connection electrode and the fifth connection electrode respectively, the third connection electrode is connected with the horizontal connection line of the present unit row, and the fifth connection electrode is connected with the horizontal connection line of the previous unit row.

[0007] In an exemplary embodiment, the at least one second circuit unit further comprises an eleventh connection electrode, a twelfth connection electrode, a thirteenth connection electrode and a fourteenth connection electrode; the eleventh connection electrode is arranged between and connected with the first connection electrode and the third connection electrode; the twelfth connection electrode is arranged between and connected with the first connection electrode and the fifth connection electrode; the thirteenth connection electrode is arranged between and connected with the third connection electrode and the transverse connection line of the unit row; and the fourteenth connection electrode is arranged between and connected with the fifth connection electrode and the transverse connection line of the previous unit row.

[0008] In an exemplary embodiment, the transverse connection line comprises a first transverse connection line, and the vertical connection line comprises a first vertical connection line; the fifth connection electrode in the first vertical connection line is connected with the first initial signal line; and the first initial signal line and the first transverse connection line form a transverse double-line structure for transmitting a first initial signal.

[0009] In an exemplary embodiment, in the at least one first circuit unit, the pixel driving circuit further comprises a data writing transistor, a second connection electrode, a data connection electrode and a data signal line; the second connection electrode is connected with a first electrode of the data writing transistor; the data connection electrode is connected with the second connection electrode; and the data signal line is connected with the data connection electrode; and in the at least one second circuit unit, the second circuit unit further comprises a first data connection block; the first data connection block is connected with the second connection electrode and the first initial signal line respectively.

[0010] In an exemplary embodiment, in the at least one second circuit unit, the second circuit unit further comprises a first vertical wire and a second vertical wire; the first vertical wire is connected with the data connection electrode; the second vertical wire is connected with the first vertical wire; the first vertical connection line, the first vertical wire and the second vertical wire form a vertical three-line structure for transmitting a first initial signal; and the transverse double-line structure and the vertical three-line structure form a plurality of first meshed communication structures.

[0011] In an exemplary embodiment, in the at least one second circuit unit, the third connection electrode is not connected with the first power supply line.

[0012] In an exemplary embodiment, the horizontal connection line comprises a second horizontal connection line, and the vertical connection line comprises a second vertical connection line; the at least one second circuit unit further comprises a fifteenth connection electrode, which is arranged between and connected with the fifth connection electrode and the sixth connection electrode respectively; and the second initial signal line and the second horizontal connection line form a horizontal double-line structure for transmitting the second initial signal.

[0013] In an exemplary embodiment, in the at least one first circuit unit, the pixel driving circuit further comprises a data writing transistor, a second connection electrode, a data connection electrode, a data signal line, and a second data connection block, the second connection electrode is connected with the first electrode of the data writing transistor, the data connection electrode is connected with the second connection electrode, the data signal line is connected with the data connection electrode, and the second data connection block is connected with the sixth connection electrode; and the at least one second circuit unit further comprises a third data connection block, which is connected with the second data connection block and the data connection electrode respectively.

[0014] In an exemplary embodiment, the at least one second circuit unit further comprises a first vertical wire and a second vertical wire, the first vertical wire is connected with the data connection electrode, the second vertical wire is connected with the first vertical wire, the second vertical connection line, the first vertical wire, and the second vertical wire form a vertical three-line structure for transmitting the second initial signal, and the horizontal double-line structure and the vertical three-line structure form a plurality of second meshed communication structures.

[0015] In an exemplary embodiment, in the at least one second circuit unit, the third connection electrode is not connected with the first power supply line, and the fifth connection electrode is not connected with the first initial signal line.

[0016] In an exemplary embodiment, the horizontal connection line comprises a third horizontal connection line, and the vertical connection line comprises a third vertical connection line, and the third connection electrode in the third vertical connection line is connected with the first power supply line, and the horizontal power supply signal line and the third horizontal connection line form a horizontal double-line structure for transmitting the first power supply signal.

[0017] In an exemplary embodiment, in the at least one first circuit unit, the pixel driving circuit further comprises a data writing transistor, a second connection electrode, a data connection electrode, and a data signal line, the second connection electrode is connected with the first electrode of the data writing transistor, the data connection electrode is connected with the second connection electrode, and the data signal line is connected with the data connection electrode; and the at least one second circuit unit further comprises a power supply connection block, which is connected with the data connection electrode and the first power supply line respectively.

[0018] In an exemplary embodiment, the at least one second circuit unit further comprises a first vertical wire and a second vertical wire, the first vertical wire is connected with the data connection electrode, the second vertical wire is connected with the first vertical wire, the first power supply line, the third vertical connection line, the first vertical wire and the second vertical wire form a vertical four-wire structure for transmitting a first power supply signal, and the horizontal two-wire structure and the vertical four-wire structure form a plurality of third meshed communication structures.

[0019] In an exemplary embodiment, in the at least one second circuit unit, the fifth connection electrode is not connected with the first initial signal line.

[0020] In an exemplary embodiment, the horizontal connection line comprises a first horizontal connection line, a second horizontal connection line and / or a third horizontal connection line, the vertical connection line comprises a first vertical connection line, a second vertical connection line and / or a third vertical connection line, and the meshed communication structure comprises a first meshed communication structure, a second meshed communication structure and / or a third meshed communication structure.

[0021] In another aspect, the present disclosure further provides a display device comprising the aforementioned display substrate.

[0022] In yet another aspect, the present disclosure further provides a manufacturing method of a display substrate, the display substrate comprising a first display area and a second display area, the first display area at least partially surrounding the second display area, the first display area being configured to perform image display, and the second display area being configured to perform image display and transmit light; the manufacturing method comprising:

[0023] forming a driving structure layer on the substrate, and forming a light-emitting structure layer on the driving structure layer;

[0024] The driving structure layer of the first display area comprises a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, and the light-emitting structure layer of the first display area comprises a plurality of first light-emitting devices; the circuit units at least comprise first circuit units and second circuit units, the first circuit units and the second circuit units each comprise a pixel driving circuit, the pixel driving circuit of the first circuit unit is connected with the first light-emitting device, and the pixel driving circuit of the second circuit unit is not connected with the first light-emitting device; at least one second circuit unit further comprises at least one horizontal connection line extending along a first direction and at least one vertical connection line extending along a second direction, the horizontal connection line is connected with the vertical connection line to form a meshed communication structure, and the first direction and the second direction intersect.

[0025] Other aspects can become apparent after reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0026] The accompanying drawings are used to provide an understanding of the technical scheme of the present disclosure, and constitute a part of the specification, and are used together with embodiments of the present disclosure to explain the technical scheme of the present disclosure, and do not constitute a limitation on the technical scheme of the present disclosure.

[0027] FIG. 1 is a structural schematic diagram of a display device;

[0028] FIG. 2 is a structural schematic diagram of a display substrate;

[0029] FIG. 3 is a plan structural schematic diagram of a display area in a display substrate;

[0030] FIG. 4 is a cross-sectional structural schematic diagram of a display area in a display substrate;

[0031] FIG. 5 is an equivalent circuit diagram of a pixel driving circuit;

[0032] FIG. 6 is a structural schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0033] FIG. 7 is a schematic diagram of a pixel driving circuit and a light emitting device connected according to an exemplary embodiment of the present disclosure;

[0034] FIG. 8 is a structural schematic diagram of a first display area according to an exemplary embodiment of the present disclosure;

[0035] FIGS. 9A and 9B are structural schematic diagrams of a first meshed communication structure according to an exemplary embodiment of the present disclosure;

[0036] FIG. 10 is a schematic diagram of a display substrate after forming a semiconductor layer pattern according to the present disclosure;

[0037] FIGS. 11A and 11B are schematic diagrams of a display substrate after forming a first conductive layer pattern according to the present disclosure;

[0038] FIGS. 12A and 12B are schematic diagrams of a display substrate after forming a second conductive layer pattern according to the present disclosure;

[0039] FIG. 13 is a schematic diagram of a display substrate after forming a fourth insulating layer pattern according to the present disclosure;

[0040] FIGS. 14A and 14B are schematic diagrams of a display substrate after forming a third conductive layer pattern according to the present disclosure;

[0041] FIG. 15 is a schematic diagram of a display substrate after forming a fifth insulating layer and a first planar layer pattern according to the present disclosure;

[0042] FIGS. 16A and 16B are schematic diagrams of a display substrate after forming a fourth conductive layer pattern according to the present disclosure;

[0043] FIG. 17 is a schematic view of a display substrate after forming a second planarization layer pattern according to the present disclosure;

[0044] FIGS. 18A and 18B are schematic views of a display substrate after forming a fifth conductive layer pattern according to the present disclosure;

[0045] FIG. 19 is a schematic view of another first display area according to an exemplary embodiment of the present disclosure;

[0046] FIGS. 20A and 20B are schematic views of a second meshed connection structure according to an exemplary embodiment of the present disclosure;

[0047] FIG. 21 is a schematic view of another display substrate after forming a fourth insulating layer pattern according to the present disclosure;

[0048] FIGS. 22A and 22B are schematic views of another display substrate after forming a third conductive layer pattern according to the present disclosure;

[0049] FIG. 23 is a schematic view of another display substrate after forming a fifth insulating layer and a first planarization layer pattern according to the present disclosure;

[0050] FIGS. 24A and 24B are schematic views of another display substrate after forming a fourth conductive layer pattern according to the present disclosure;

[0051] FIG. 25 is a schematic view of another first display area according to an exemplary embodiment of the present disclosure;

[0052] FIGS. 26A and 26B are schematic views of a third meshed connection structure according to an exemplary embodiment of the present disclosure;

[0053] FIGS. 27A and 27B are schematic views of another display substrate after forming a third conductive layer pattern according to the present disclosure;

[0054] FIG. 28 is a schematic view of another display substrate after forming a fifth insulating layer and a first planarization layer pattern according to the present disclosure;

[0055] FIGS. 29A and 29B are schematic views of another display substrate after forming a fourth conductive layer pattern according to the present disclosure;

[0056] FIG. 30 is a schematic view of another first display area according to an exemplary embodiment of the present disclosure;

[0057] FIG. 31 is a schematic view of another first display area according to an exemplary embodiment of the present disclosure;

[0058] FIG. 32 is a schematic view of another first display area according to an exemplary embodiment of the present disclosure;

[0059] FIG. 33 is a schematic view of another first display area according to an exemplary embodiment of the present disclosure.

[0060] Explanation of reference signs: 11-first active layer; 12-second active layer; 13-third active layer; 14-fourth active layer; 15-fifth active layer; 16-sixth active layer; 17-seventh active layer; 21-first scan signal line; 22-second scan signal line; 23-emitting signal line; 31-first plate; 32-second plate; 33-opening; 34-plate connecting strip; 41-first initial signal line; 42-second initial signal line; 43-first shielding electrode; 44-second shielding electrode; 51-first connecting electrode; 52-second connecting electrode; 53-third connecting electrode; 54-fourth connecting electrode; 55-fifth connecting electrode; 56-sixth connecting electrode; 61-eleventh connecting electrode; 62-twelfth connecting electrode; 63-thirteenth connecting electrode; 64-fourteenth connecting electrode; 65-fifteenth connecting electrode; 66-first data connecting block; 67-second data connecting block; 68-third data connecting block; 71-first power line; 72-second power line; 73-data signal line; 74-data connecting electrode; 75-first anode connecting electrode; 76-second anode connecting electrode; 81-first horizontal connecting line; 82-second horizontal connecting line; 83-third horizontal connecting line; 91-first vertical connecting line; 92-second vertical connecting line; 93-third vertical connecting line; 100-display area; 101-substrate; 102-driving structure layer; 103-emitting structure layer; 104-encapsulation structure layer; 110-first vertical wire; 120-second vertical wire; 200-bonding area; 300-bezel area. DETAILED DESCRIPTION

[0061] In order to make the objects, technical solutions and advantages of the present disclosure clearer, the following will be used to specifically explain the embodiments of the present disclosure with reference to the drawings. It should be noted that the embodiments can be implemented in a variety of different forms. Those skilled in the art can easily understand that the modes and contents can be changed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be combined with each other arbitrarily without conflict.

[0062] The proportions of the drawings in the present disclosure can be used as a reference in the actual process, but are not limited thereto. For example, the width-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are also not limited to the number shown in the drawings. The drawings described in the present disclosure are only schematic structural diagrams, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.

[0063] In the present specification, ordinal numbers such as "first", "second", "third", and the like are provided to avoid confusion of components, and are not intended to be limited in terms of quantity.

[0064] In the present specification, for the convenience of explanation, words indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to explain the positional relationship of the components with reference to the drawings, and are only for the convenience of describing the present specification and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction of describing each component. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0065] In the present specification, unless specifically defined and limited otherwise, the terms "mount", "connected", "connected" should be broadly understood. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate, or the communication between two elements. Those skilled in the art can understand the specific meaning of the above terms in the present disclosure according to the specific circumstances.

[0066] In this specification, a transistor means an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and the source electrode (a source electrode terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that, in this specification, the channel region means a region where current flows mainly.

[0067] In this specification, the first terminal can be a drain electrode and the second terminal can be a source electrode, or the first terminal can be a source electrode and the second terminal can be a drain electrode. The functions of the "source electrode" and the "drain electrode" are sometimes interchanged with each other in the case of using a transistor whose polarity is reversed or in the case where the direction of current flowing in a circuit is changed, and the like. Therefore, in this specification, the "source electrode" and the "drain electrode" can be interchanged with each other, and the "source terminal" and the "drain terminal" can be interchanged with each other.

[0068] In this specification, "electrically connected" includes the case where components are connected through an element having some function of electricity. The element having some function of electricity is not particularly limited as long as electric signals can be transmitted and received between components to be connected. Examples of the element having some function of electricity include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, and another element having some function.

[0069] In this specification, "parallel" means a state where an angle formed by two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus includes a state where the angle is greater than or equal to -5° and less than or equal to 5°. In addition, "perpendicular" means a state where an angle formed by two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus includes a state where the angle is greater than or equal to 85° and less than or equal to 95°.

[0070] In this specification, a "film" and a "layer" can be interchanged with each other. For example, a "conductive layer" can be replaced with a "conductive film". Similarly, an "insulating film" can be replaced with an "insulating layer".

[0071] In this specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon is not necessarily a strict one and can be an approximate triangle, rectangle, trapezoid, pentagon, or hexagon. There can be some small deformation due to a tolerance, a rounded corner, a rounded side, or the like. In the present disclosure, "about" means that a value is not strictly limited to a certain value, and a value within a range of a process and measurement error is allowed.

[0072] FIG. 1 is a structural schematic diagram of a display device. As shown in FIG. 1, the display device can include a timing controller, a data driver, a scan driver, a light emitting driver, and a pixel array, the timing controller is connected with the data driver, the scan driver, and the light emitting driver respectively, the data driver is connected with a plurality of data signal lines (D1 to Dn) respectively, the scan driver is connected with a plurality of scan signal lines (S1 to Sm) respectively, and the light emitting driver is connected with a plurality of light emitting signal lines (E1 to Eo) respectively. The pixel array can include a plurality of sub-pixels Pxij, i and j can be natural numbers, at least one sub-pixel Pxij can include a circuit unit and a light emitting unit, the circuit unit can include at least a pixel driving circuit, the pixel driving circuit is connected with the scan signal line, the light emitting signal line, and the data signal line respectively, and the light emitting unit can include a light emitting device connected with the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller can provide a gray value and a control signal suitable for the specification of the data driver to the data driver, can provide a clock signal, a scan start signal, and the like suitable for the specification of the scan driver to the scan driver, and can provide a clock signal, an emission stop signal, and the like suitable for the specification of the light emitting driver to the light emitting driver. The data driver can generate data voltages to be provided to the data signal lines D1, D2, D3, …, and Dn using the gray value and the control signal received from the timing controller. For example, the data driver can sample the gray value using the clock signal, and apply data voltages corresponding to the gray value to the data signal lines D1 to Dn in units of a pixel row. n can be a natural number. The scan driver can generate scan signals to be provided to the scan signal lines S1, S2, S3, …, and Sm by receiving the clock signal, the scan start signal, and the like from the timing controller. For example, the scan driver can sequentially provide the scan signal having an on-level pulse to the scan signal lines S1 to Sm. For example, the scan driver can be configured in the form of a shift register, and can generate the scan signal in a manner that sequentially transfers the scan start signal provided in the form of an on-level pulse to a next stage circuit under the control of the clock signal. m can be a natural number. The light emitting driver can generate emission signals to be provided to the light emitting signal lines E1, E2, E3, …, and Eo by receiving the clock signal, the emission stop signal, and the like from the timing controller. For example, the light emitting driver can sequentially provide the emission signal having an off-level pulse to the light emitting signal lines E1 to Eo. For example, the light emitting driver can be configured in the form of a shift register, and can generate the emission signal in a manner that sequentially transfers the emission stop signal provided in the form of an off-level pulse to a next stage circuit under the control of the clock signal. o can be a natural number. In an exemplary embodiment, the pixel array can be disposed on a display substrate.

[0073] FIG. 2 is a structural schematic diagram of a display substrate. As shown in FIG. 2, the display substrate can include a display area 100, a binding area 200 located on one side of the display area 100, and a frame area 300 located on the other side of the display area 100. In an exemplary embodiment, the display area 100 can be a flat area including a plurality of sub-pixels Pxij constituting a pixel array, the plurality of sub-pixels Pxij being configured to display dynamic pictures or still images, and the display area 100 can be referred to as an active area (AA). In an exemplary embodiment, the display substrate can adopt a flexible substrate, and thus the display substrate can be deformable, for example, curled, bent, folded, or rolled up.

[0074] In an exemplary embodiment, the binding area 200 can include, in sequence along a direction away from the display area, an outgoing line area, a bending area, a driving chip area, and a binding pin area, the outgoing line area being connected to the display area 100 and including at least data outgoing lines. The bending area can be connected to the outgoing line area and can include at least a composite insulating layer provided with a groove configured to bend the binding area to the back of the display area. The driving chip area can include an integrated circuit (IC) configured to be connected to the plurality of data outgoing lines. The binding pin area can include a bonding pad configured to be connected to an external flexible printed circuit (FPC).

[0075] In an exemplary embodiment, the frame area 300 can include, in sequence along a direction away from the display area 100, a circuit area, a power line area, a crack dam area, and a cutting area. The circuit area can be connected to the display area 100 and can include at least a gate drive circuit connected to a scanning signal line and a light-emitting signal line in the display area 100. The power line area can be connected to the circuit area and can include at least a frame power lead extending along a direction parallel to an edge of the display area and connected to a cathode in the display area 100. The crack dam area can be connected to the power line area and can include at least a plurality of cracks provided on a composite insulating layer. The cutting area can be connected to the crack dam area and can include at least a cutting groove provided on the composite insulating layer, the cutting groove being configured to be cut by a cutting device along the cutting groove after all film layers of the display substrate are prepared.

[0076] In an exemplary embodiment, the outgoing line area in the binding area 200 and the power line area in the frame area 300 can be provided with an isolation dam, the isolation dam extending along a direction parallel to an edge of the display area and forming a ring structure surrounding the display area 100, the edge of the display area being an edge of the display area on one side of the binding area or the frame area.

[0077] FIG. 3 is a schematic diagram of a planar structure of a display region in a display substrate. As shown in FIG. 3, the display region can include a plurality of pixel units P arranged in a matrix manner, and at least one pixel unit P can include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4. Each sub-pixel can include a circuit unit and a light-emitting unit, and the circuit unit can include at least a pixel driving circuit. The pixel driving circuit is connected to a scan signal line, a light-emitting signal line, and a data signal line, respectively, and is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting unit. The light-emitting unit can include a light-emitting device connected to the pixel driving circuit of the sub-pixel where the light-emitting device is located, and the light-emitting device is configured to emit light with a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel where the light-emitting device is located.

[0078] In an example embodiment, the first sub-pixel P1 can be a red sub-pixel (R) that emits red light, the second sub-pixel P2 can be a blue sub-pixel (B) that emits blue light, the third sub-pixel P3 can be a first green sub-pixel (G1) that emits green light, and the fourth sub-pixel P4 can be a second green sub-pixel (G2) that emits green light. In an example embodiment, the shape of the sub-pixel can be rectangular, diamond, pentagonal, or hexagonal, and the four sub-pixels can be arranged in an RGBG manner.

[0079] In other example embodiments, the pixel unit P can include three sub-pixels arranged in a horizontal parallel manner or a vertical parallel manner, and the present disclosure does not limit the arrangement of the three sub-pixels.

[0080] FIG. 4 is a schematic diagram of a cross-sectional structure of a display region in a display substrate. As shown in FIG. 4, in a plane perpendicular to the display substrate, the display region can include a driving structure layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on a side of the driving structure layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on a side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the first display area can include other film layers, such as a touch structure layer, and the present disclosure does not limit the film layers.

[0081] In an example embodiment, the substrate 101 can be a flexible substrate or can be a rigid substrate. The driving structure layer 102 can include a plurality of circuit units, each of which can include at least a pixel driving circuit composed of a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 can include a plurality of light-emitting units, each of which can include a light-emitting device that can include at least an anode, an organic light-emitting layer, and a cathode, the anode being connected to the pixel driving circuit, the organic light-emitting layer being connected to the anode, and the cathode being connected to the organic light-emitting layer, the organic light-emitting layer emitting light of a corresponding color under the driving of the anode and the cathode. The encapsulating structure layer 104 can include a first encapsulating layer, a second encapsulating layer, and a third encapsulating layer stacked together, the first encapsulating layer and the third encapsulating layer can be made of inorganic material, and the second encapsulating layer can be made of organic material, the second encapsulating layer being disposed between the first encapsulating layer and the third encapsulating layer to form an inorganic material / organic material / inorganic material stacked structure, which can prevent external water vapor from entering the light-emitting structure layer 103.

[0082] FIG. 5 is an equivalent circuit diagram of a pixel driving circuit. In an example embodiment, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. As shown in FIG. 5, the pixel driving circuit can include 7 transistors (first transistor T1 to seventh transistor T7) and 1 storage capacitor C, and the pixel driving circuit is connected to 7 signal lines (first scan signal line S1, second scan signal line S2, light-emitting signal line EM, first initial signal line INIT1, second initial signal line INIT2, data signal line DATA, and first power supply line VDD).

[0083] In an example embodiment, the pixel driving circuit can include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first terminal of the storage capacitor C, respectively. The second node N2 is connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5, respectively. The third node N3 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, respectively. The fourth node N4 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, respectively.

[0084] In an example embodiment, the first terminal of the storage capacitor C is connected to the first node N1, and the second terminal of the storage capacitor C is connected to the first power supply line VDD.

[0085] In an example embodiment, the gate electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is connected to the first node N1.

[0086] In an example embodiment, the gate electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the first node N1, and the second electrode of the second transistor T2 is connected to the third node N3.

[0087] In an example embodiment, the gate electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3.

[0088] In an example embodiment, the gate electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line DATA, and the second electrode of the fourth transistor T4 is connected to the second node N2.

[0089] In an example embodiment, the gate electrode of the fifth transistor T5 is connected to the emission signal line EM, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2.

[0090] In an example embodiment, the gate electrode of the sixth transistor T6 is connected to the emission signal line EM, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the fourth node N4.

[0091] In an example embodiment, the gate electrode of the seventh transistor T7 is connected to the first scan signal line S1, the first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the fourth node N4.

[0092] In an example embodiment, the first electrode of the light emitting device EL is connected to the fourth node N4, and the second electrode of the light emitting device EL is connected to the second power supply line VSS. The light emitting device EL can be an OLED including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked, or can be a QLED including a first electrode (anode), a quantum dot light emitting layer, and a second electrode (cathode) stacked.

[0093] In an example embodiment, the first power supply line VDD is configured to provide a constant first power supply signal to the pixel driving circuit, the second power supply line VSS is configured to provide a constant second power supply signal to the light emitting device, and the first power supply signal is a high-level signal and the second power supply signal is a low-level signal. The first initial voltage signal and the second initial voltage signal can be constant voltage signals, which are not limited in the present disclosure.

[0094] In an example embodiment, the first transistor T1 to the seventh transistor T7 in the pixel driving circuit can be P-type transistors, or can be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the seventh transistor T7 can include P-type transistors and N-type transistors.

[0095] In an example embodiment, the first transistor T1 to the seventh transistor T7 can be low-temperature polysilicon thin film transistors, or can be oxide thin film transistors, or can be low-temperature polysilicon thin film transistors and oxide thin film transistors. The active layer of the low-temperature polysilicon thin film transistor adopts low-temperature polysilicon (LTPS), and the active layer of the oxide thin film transistor adopts oxide semiconductor (Oxide). The low-temperature polysilicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantage of low leakage current. Integrating the low-temperature polysilicon thin film transistor and the oxide thin film transistor on one display substrate forms an LTPO (Low Temperature Polycrystalline + Oxide) display substrate, which can take advantage of both and can achieve low-frequency driving, reduce power consumption, and improve display quality.

[0096] For products such as smart terminals, it is often necessary to set up front cameras, fingerprint sensors, or light sensors, etc. To improve the screen ratio, the display device usually adopts the method of opening holes on the display substrate to form an under-display camera area (UDC), and places the camera and other sensors in the under-display camera area of the display substrate to realize the camera full screen (FDC) technology. The under-display camera area not only has a certain transmittance, but also has display function.

[0097] The exemplary embodiments of the present disclosure provide a display substrate, comprising a first display area and a second display area, the first display area at least partially surrounding the second display area, the first display area being configured to display images, and the second display area being configured to display images and transmit light; the first display area comprises a driving structure layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate, the driving structure layer comprises a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, and the light-emitting structure layer comprises a plurality of first light-emitting devices; the circuit units at least comprise first circuit units and second circuit units, the first circuit units and the second circuit units each comprise a pixel driving circuit, the pixel driving circuit of the first circuit units is connected with the first light-emitting devices, and the pixel driving circuit of the second circuit units is not connected with the first light-emitting devices; at least one second circuit unit further comprises at least one horizontal connection line extending along a first direction and at least one vertical connection line extending along a second direction, the horizontal connection line is connected with the vertical connection line to form a meshed communication structure, and the first direction and the second direction intersect.

[0098] In the exemplary embodiments, in at least one first circuit unit, the pixel driving circuit at least comprises a storage capacitor, a first reset transistor, a second reset transistor, and a first light-emitting control transistor, a first electrode of the first reset transistor is connected with a first initial signal line through a fifth connection electrode, a second electrode of the first reset transistor is connected with a first electrode plate of the storage capacitor through a first connection electrode, a first electrode of the first light-emitting control transistor is connected with a second electrode plate of the storage capacitor through a third connection electrode, a first electrode of the second reset transistor is connected with a second initial signal line through a sixth connection electrode, the third connection electrode is connected with a first power supply line, and a plurality of the second electrode plates in at least one unit row form a horizontal power supply signal line; in at least one second circuit unit, the vertical connection line comprises the first connection electrode, the third connection electrode, and the fifth connection electrode, the first connection electrode is connected with the third connection electrode and the fifth connection electrode respectively, the third connection electrode is connected with the horizontal connection line of the present unit row, and the fifth connection electrode is connected with the horizontal connection line of the previous unit row.

[0099] In the exemplary embodiments, the horizontal connection line comprises a first horizontal connection line, the vertical connection line comprises a first vertical connection line, the fifth connection electrode in the first vertical connection line is connected with the first initial signal line, and the first initial signal line and the first horizontal connection line form a horizontal double-line structure for transmitting a first initial signal.

[0100] In an exemplary embodiment, the horizontal connection lines include a second horizontal connection line, and the vertical connection lines include a second vertical connection line; the at least one second circuit unit further includes a fifteenth connection electrode disposed between and connected with the fifth connection electrode and the sixth connection electrode; and the second initial signal line and the second horizontal connection line form a horizontal double-line structure for transmitting a second initial signal.

[0101] In an exemplary embodiment, the horizontal connection lines include a third horizontal connection line, and the vertical connection lines include a third vertical connection line; the third connection electrode in the third vertical connection line is connected with the first power supply line; and the horizontal power supply signal line and the third horizontal connection line form a horizontal double-line structure for transmitting a first power supply signal.

[0102] In an exemplary embodiment, the horizontal connection lines include a first horizontal connection line, a second horizontal connection line and / or a third horizontal connection line, and the vertical connection lines include a first vertical connection line, a second vertical connection line and / or a third vertical connection line; and the meshed communication structure includes a first meshed communication structure, a second meshed communication structure and / or a third meshed communication structure.

[0103] FIG. 6 is a structural schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure. As shown in FIG. 6, the display substrate can include a display area 100, a binding area 200 located on one side of the display area 100, and a frame area 300 located on the other side of the display area 100. The display area 100 can include at least a first display region 100A and a second display region 100B, and the first display region 100A can at least partially surround the second display region 100B. The first display region 100A is configured to display images and can be referred to as a normal display region. The second display region 100B is configured to display images and transmit light, and the transmitted light is received by an optical device. The second display region 100B can be referred to as an under-screen camera display region or a light-transmitting display region, and the position of the second display region 100B can correspond to the position of the optical device. In a direction perpendicular to the display substrate, the display area can include at least a driving structure layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate.

[0104] In an example embodiment, the driving structure layer of the first display area 100A can include a plurality of circuit repeating units. The circuit repeating unit is a basic unit constituting the driving structure layer of the first display area 100A, and the driving structure layer of the first display area 100A can be constituted by repeatedly and continuously arranging the circuit repeating units along the first direction X and the second direction Y. A plurality of circuit repeating units arranged in sequence along the first direction X can be referred to as a repeating row, a plurality of circuit repeating units arranged in sequence along the second direction Y can be referred to as a repeating column, and the first direction X and the second direction Y intersect. The light-emitting structure layer of the first display area 100A can include a plurality of light-emitting repeating units. The light-emitting repeating unit is a basic unit constituting the light-emitting structure layer of the first display area 100A, and the light-emitting structure layer of the first display area 100A can be constituted by repeatedly and continuously arranging the light-emitting repeating units along the first direction X and the second direction Y.

[0105] In an example embodiment, in the first display area 100A, the positions of the plurality of circuit repeating units and the plurality of light-emitting repeating units can be substantially corresponding, the orthographic projection of at least one circuit repeating unit on the substrate has a first area, the orthographic projection of at least one light-emitting repeating unit on the substrate has a second area, and the ratio of the first area to the second area can be about 0.95 to 1.05, that is, the area of the orthographic projection of the circuit repeating unit on the substrate and the area of the orthographic projection of the light-emitting repeating unit on the substrate can be substantially the same.

[0106] In an example embodiment, the driving structure layer of the first display area 100A can be arranged in a compression mode, and the light-emitting structure layer of the first display area 100A can be arranged in a normal (non-compression) mode. For example, in the normal mode, one circuit repeating unit can be arranged with M circuit units, and one light-emitting repeating unit can be arranged with M first light-emitting units. In the compression mode, the number of circuit units arranged in the circuit repeating unit can be increased by using lateral compression, that is, one circuit unit is inserted into the area previously arranged with M circuit units, so that one circuit repeating unit can include M+1 circuit units arranged in sequence along the first direction X. Since the light-emitting structure layer is arranged in the normal mode, the light-emitting repeating unit still includes M first light-emitting devices arranged in sequence along the first direction X, and the area occupied by the M+1 circuit units is substantially the same as the area occupied by the M first light-emitting units. In an example embodiment, M can be a positive integer greater than or equal to 2, for example, M can be 2, 4, or 7.

[0107] In an example embodiment, for the pixel arrangement of the RGBG of the present disclosure, M is equal to 4, that is, the display substrate of the present disclosure adopts a 4-insert-1 structure.

[0108] In an example embodiment, the at least one circuit unit can at least include a pixel driving circuit, the at least one first light emitting unit can at least include a first light emitting device, and the area of the M+1 pixel driving circuits in one circuit repeating unit orthogonally projected on the substrate can be substantially the same as the area of the M first light emitting devices in one light emitting repeating unit orthogonally projected on the substrate.

[0109] In an example embodiment, the circuit unit in the present disclosure refers to a region divided according to the pixel driving circuit, and the light emitting unit in the present disclosure refers to a region divided according to the light emitting device. In an example embodiment, the position of the light emitting unit orthogonally projected on the substrate can correspond to the position of the circuit unit orthogonally projected on the substrate, or the position of the light emitting unit orthogonally projected on the substrate can not correspond to the position of the circuit unit orthogonally projected on the substrate.

[0110] In an example embodiment, the plurality of circuit units arranged in sequence along the first direction X can be referred to as a unit row, the plurality of circuit units arranged in sequence along the second direction Y can be referred to as a unit column, and the plurality of unit rows and the plurality of unit columns form an array of circuit units arranged in an array.

[0111] In an example embodiment, the plurality of pixel driving circuits in the at least one circuit repeating unit can have substantially the same size. The plurality of first light emitting devices in the at least one light emitting repeating unit can have substantially the same size. In the present disclosure, the size of the pixel driving circuit refers to the size of the pixel driving circuit orthogonally projected on the substrate, and the size of the light emitting device refers to the size of the light emitting device orthogonally projected on the substrate. When the pixel driving circuit and the light emitting device orthogonally projected on the substrate are rectangular, the size can include any one or more of the following: the length of the first direction X orthogonally projected, the length of the second direction Y orthogonally projected, and the area orthogonally projected. When the pixel driving circuit and the light emitting device orthogonally projected on the substrate are circular or elliptical, the size can include any one or more of the following: the radius orthogonally projected, the major axis and the minor axis orthogonally projected, and the area orthogonally projected.

[0112] In an example embodiment, the driving structure layer of the second display area 100B can include a plurality of insulating layers, the light emitting structure layer of the second display area 100B can include a plurality of second light emitting units, and the second light emitting unit can at least include a second light emitting device, i.e., the second display area 100B does not have a pixel driving circuit, but only has a light emitting device. Since the second display area 100B does not have a pixel driving circuit, the second light emitting device of the second display area 100B needs to be connected to the pixel driving circuit in the first display area 100A through the anode connection line.

[0113] In the exemplary embodiments, the size of the second light emitting device in the second display area 100B can be substantially the same as the size of the first light emitting device in the first display area 100A, and the arrangement of the plurality of second light emitting devices in the second display area 100B can be substantially the same as the arrangement of the plurality of first light emitting devices in the first display area 100A.

[0114] In the exemplary embodiments, in the at least one circuit repeating unit, the M+1 circuit units can include M first circuit units and 1 second circuit unit, or can include M first circuit units and 1 third circuit unit. The pixel driving circuit in the first circuit unit is configured to provide a driving signal to the first light emitting device in the first display area 100A, the pixel driving circuit in the second circuit unit is a dummy pixel circuit, and the pixel driving circuit in the third circuit unit is configured to provide a driving signal to the second light emitting device in the second display area 100B.

[0115] FIG. 7 is a schematic diagram of a connection between a pixel driving circuit and a light emitting device according to an exemplary embodiment of the present disclosure. As shown in FIG. 7, the driving structure layer of the first display area 100A can include a plurality of pixel driving circuits, and the driving structure layer of the second display area 100B is not provided with a pixel driving circuit. The light emitting structure layer of the first display area 100A can include a plurality of first light emitting devices F1, and the light emitting structure layer of the second display area 100B can include a plurality of second light emitting devices F2.

[0116] In the exemplary embodiments, the circuit repeating unit in the first display area 100A away from the second display area 100B region can include 4 first circuit units Q1 and 1 second circuit unit Q2 arranged in sequence along the first direction X, and the circuit repeating unit in the first display area 100A close to the second display area 100B region can include 4 first circuit units Q1 and 1 third circuit unit Q3 arranged in sequence along the first direction X. The first circuit unit Q1, the second circuit unit Q2 and the third circuit unit Q3 all include a pixel driving circuit, and the size of the pixel driving circuit in the first circuit unit Q1, the second circuit unit Q2 and the third circuit unit Q3 can be substantially the same.

[0117] In an example embodiment, the pixel driving circuit in the at least one first circuit unit Q1 is directly connected with the at least one first light emitting unit F1 in the first display area 100A, the orthogonal projection of the pixel driving circuit in the at least one first circuit unit Q1 on the substrate at least partially overlaps with the orthogonal projection of the at least one first light emitting unit F1 on the substrate, and the pixel driving circuit in the first circuit unit Q1 is configured to provide a driving signal to the connected first light emitting unit F1 to drive the corresponding first light emitting unit F1 to emit light. In some examples, the pixel driving circuit in the plurality of first circuit units Q1 and the plurality of first light emitting units F1 can be in a one-to-one relationship, or can be in a one-to-many relationship, or can be in a many-to-one relationship, which is not limited in the present disclosure.

[0118] In an example embodiment, the pixel driving circuit in the at least one third circuit unit Q3 is connected with the at least one second light emitting unit F2 in the second display area 100B through the anode connection line AL, the orthogonal projection of the pixel driving circuit in the at least one third circuit unit Q3 on the substrate does not overlap with the orthogonal projection of the at least one second light emitting unit F2 on the substrate, and the pixel driving circuit in the third circuit unit Q3 is configured to provide a driving signal to the connected second light emitting unit F2 to drive the corresponding second light emitting unit F2 to emit light. In some examples, the pixel driving circuit in the plurality of third circuit units Q3 and the plurality of second light emitting units F2 can be in a one-to-one relationship, or can be in a one-to-many relationship, or can be in a many-to-one relationship, which is not limited in the present disclosure.

[0119] In an example embodiment, the pixel driving circuit in the at least one second circuit unit Q2 is neither connected with the first light emitting unit F1 in the first display area 100A nor connected with the second light emitting unit F2 in the second display area 100B.

[0120] In an example embodiment, the first circuit unit Q1 can be referred to as a normal circuit unit, and the second circuit unit Q2 and the third circuit unit Q3 can be referred to as an inserted circuit unit. The pixel driving circuit in the first circuit unit Q1 providing a driving signal to the first light emitting unit F1 in the first display area can be referred to as a normal pixel circuit, the pixel driving circuit in the second circuit unit Q2 neither connected with the first light emitting unit F1 nor connected with the second light emitting unit F2 can be referred to as a dummy pixel circuit, and the pixel driving circuit in the third circuit unit Q3 providing a driving signal to the second light emitting unit F2 in the second display area can be referred to as an inserted pixel circuit.

[0121] In an example embodiment, the plurality of first circuit units arranged in sequence along the second direction Y can be referred to as normal unit columns, and the plurality of second circuit units (or the plurality of second circuit units and the at least one third circuit unit) arranged in sequence along the second direction Y can be referred to as inserted unit columns. Four normal unit columns can be provided between two inserted unit columns adjacent in the first direction X, forming a 4-in-1 structure.

[0122] In an example embodiment, the plurality of third circuit units can be provided at a position of the first display region close to the second display region, and the plurality of second circuit units can be provided at a position of the first display region away from the second display region, which is not limited in the present disclosure.

[0123] In an example embodiment, the position of the second display region 100B in the first display region 100A is not limited, and the second display region 100B can be located in an upper region or a lower region of the first display region 100A, or can be located at an edge of the first display region 100A. The resolutions of the first display region 100A and the second display region 100B can be the same or different, which is not limited in the present disclosure.

[0124] In an example embodiment, in a plane parallel to the display substrate, the shape of the second display region 100B can be any one or more of a rectangle, a polygon, a circle, and an ellipse. The optical device can be an optical sensor such as a fingerprint identification device, a camera, or a 3D imaging device. When the shape of the second display region 100B is a circle, the diameter of the circle can be about 3 mm to 5 mm. When the shape of the second display region 100B is a rectangle, the side length of the rectangle can be about 3 mm to 5 mm, which is not limited in the present disclosure.

[0125] FIG. 8 is a schematic structural diagram of a first display region according to an example embodiment of the present disclosure, illustrating the structure of 16 circuit units of 2 unit rows (an Mth unit row and an (M+1)th unit row) and 8 unit columns (an Nth unit column to an (N+7)th unit column) in the first display region. Among them, the Nth unit column, the (N+2)th unit column to the (N+5)th unit column, and the (N+7)th unit column are normal unit columns, and the circuit units in these unit columns are first circuit units. The (N+1)th unit column and the (N+6)th unit column are inserted unit columns, and the circuit units in these unit columns are second circuit units. As shown in FIG. 8, in a plane parallel to the display substrate, the driving structure layer of the first display region can include a plurality of first circuit units and a plurality of second circuit units, and at least one first circuit unit or at least one second circuit unit can include a pixel driving circuit.

[0126] In the example embodiment, the pixel driving circuit of the at least one first circuit unit can be connected with the first scan signal line 21, the second scan signal line 22, the light emitting signal line 23, the first initial signal line 41, the second initial signal line 42, the first power supply line 71 and the data signal line 73 respectively. The first scan signal line 21, the second scan signal line 22 and the light emitting signal line 23 are configured to provide the first scan signal, the second scan signal and the light emitting control signal to the pixel driving circuit respectively, the first initial signal line 41 and the second initial signal line 42 are configured to provide the first initial signal and the second initial signal to the pixel driving circuit respectively, the first power supply line 71 is configured to provide the first power supply signal to the pixel driving circuit, and the data signal line 73 is configured to provide the data signal to the pixel driving circuit. The plurality of signal lines connected with the pixel driving circuit can be located within the corresponding circuit unit.

[0127] In the example embodiment, the first scan signal line 21, the second scan signal line 22, the light emitting signal line 23, the first initial signal line 41 and the second initial signal line 42 can be in the shape of a straight line or a broken line with the main part extending along the first direction X, and the first power supply line 71 and the data signal line 73 can be in the shape of a straight line or a broken line with the main part extending along the second direction Y.

[0128] In the present disclosure, A extending along the direction of B means that A can include a main part and a secondary part connected with the main part, the main part is in the shape of a line, a line segment or a bar, the main part extends along the direction of B, and the length of the main part extending along the direction of B is greater than the length of the secondary part extending along other directions. In the following description, A extending along the direction of B means that the main part of A extends along the direction of B. In the example embodiment, the first direction X can be the unit row direction, and the second direction Y can be the unit column direction.

[0129] In the example embodiment, the pixel driving circuit of the at least one first circuit unit can include at least a storage capacitor and a plurality of transistors. The storage capacitor can include a first plate and a second plate stacked, and the plurality of transistors can include a first transistor T1 as a first reset transistor, a second transistor T2 as a compensation transistor, a third transistor T3 as a driving transistor, a fourth transistor T4 as a data writing transistor, a fifth transistor T5 as a first light emitting control transistor, a sixth transistor T6 as a second light emitting control transistor, and a seventh transistor T7 as a second reset transistor.

[0130] In the example embodiment, the gate electrode of the first transistor T1 is connected with the second scan signal line 22, the first electrode of the first transistor T1 is connected with the first initial signal line 41, and the second electrode of the first transistor T1 is connected with the first electrode of the second transistor T2 and the first electrode plate of the storage capacitor (also the gate electrode of the third transistor T3) respectively. The gate electrode of the second transistor T2 is connected with the first scan signal line 21, the second electrode of the second transistor T2 is connected with the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6 respectively. The gate electrode of the fourth transistor T4 is connected with the first scan signal line 21, the first electrode of the fourth transistor T4 is connected with the data signal line 73, and the second electrode of the fourth transistor T4 is connected with the first electrode of the third transistor T3 and the second electrode of the fifth transistor T5 respectively. The gate electrode of the fifth transistor T5 is connected with the light-emitting signal line 23, and the first electrode of the fifth transistor T5 is connected with the first power supply line 71. The gate electrode of the sixth transistor T6 is connected with the light-emitting signal line 23, and the second electrode of the sixth transistor T6 is connected with the second electrode of the seventh transistor T7. The gate electrode of the seventh transistor T7 is connected with the first scan signal line 21, and the first electrode of the seventh transistor T7 is connected with the second initial signal line 42.

[0131] In the example embodiment, the at least one first circuit unit can further include a second power supply line 72. The second power supply line 72 can have a shape of a straight line or a broken line extending along the second direction Y, and the second power supply line 72 is configured to be connected with the cathode in the light-emitting device.

[0132] In the example embodiment, the driving structure layer of the first display area can further include at least one first horizontal connection line 81 and at least one first vertical connection line 91. The first initial signal line 41 and the first vertical connection line 91 form a first meshed communication structure on the display substrate, and the first horizontal connection line 81 and the first vertical connection line 91 form another first meshed communication structure on the display substrate.

[0133] FIGS. 9A and 9B are schematic structural diagrams of a first meshed communication structure according to an example embodiment of the present disclosure. As shown in FIGS. 8 and 9A, the first vertical connection line 91 can have a shape of a broken line extending along the second direction Y, and can be arranged in the plurality of second circuit units in at least one insertion unit column. For example, the first vertical connection line 91 can be arranged in the N+1th unit column and the N+6th unit column respectively.

[0134] In the example embodiment, the first circuit unit and the second circuit unit can further include the first horizontal connection line 81. The first horizontal connection line 81 can have a shape of a straight line or a broken line extending along the first direction X, and in at least one unit row, the first horizontal connection line 81 can be continuously arranged in the plurality of first circuit units and the plurality of second circuit units.

[0135] In the example embodiment, the pixel driving circuit in the first circuit unit and the second circuit unit can further include a first connection electrode 51, a third connection electrode 53, and a fifth connection electrode 55. One end of the first connection electrode 51 is connected with the second electrode of the first transistor T1 and the first electrode of the second transistor T2, and the other end of the first connection electrode 51 is connected with the first plate of the storage capacitor, i.e., the second electrode of the first transistor T1 and the first electrode of the second transistor T2 are connected with the first plate of the storage capacitor through the first connection electrode 51. One end of the third connection electrode 53 is connected with the first electrode of the fifth transistor T5, and the other end of the third connection electrode 53 is connected with the second plate of the storage capacitor, i.e., the first electrode of the fifth transistor T5 is connected with the second plate of the storage capacitor through the third connection electrode 53. One end of the fifth connection electrode 55 is connected with the first electrode of the first transistor T1, and the other end of the fifth connection electrode 55 is connected with the first initial signal line 41, i.e., the first electrode of the first transistor T1 is connected with the first initial signal line 41 through the fifth connection electrode 55.

[0136] In the example embodiment, in at least one first circuit unit, the first connection electrode 51, the third connection electrode 53, and the fifth connection electrode 55 are arranged in isolation. In at least one second circuit unit, the first vertical connection line 91 can include the first connection electrode 51, the third connection electrode 53, and the fifth connection electrode 55, the first connection electrode 51 is connected with the third connection electrode 53 and the fifth connection electrode 55 respectively, the third connection electrode 53 is connected with the first horizontal connection line 81 of the current unit row, and the fifth connection electrode 55 is connected with the first horizontal connection line 81 of the previous unit row.

[0137] In the example embodiment, at least one second circuit unit can further include an eleventh connection electrode 61, a twelfth connection electrode 62, a thirteenth connection electrode 63, and a fourteenth connection electrode 64. The eleventh connection electrode 61 can be arranged between and connected with the first connection electrode 51 and the third connection electrode 53 respectively. The twelfth connection electrode 62 can be arranged between and connected with the first connection electrode 51 and the fifth connection electrode 55 respectively. The thirteenth connection electrode 63 can be arranged between and connected with the third connection electrode 53 and the first horizontal connection line 81 of the current unit row respectively. The fourteenth connection electrode 64 can be arranged between and connected with the fifth connection electrode 55 and the first horizontal connection line 81 of the previous unit row respectively.

[0138] In the example embodiment, since the first connection electrode 51 and the third connection electrode 53 are connected to each other through the eleventh connection electrode 61, the third connection electrode 53 is connected to the thirteenth connection electrode 63, and the first connection electrode 51 and the fifth connection electrode 55 are connected to each other through the twelfth connection electrode 62, the fifth connection electrode 55 is connected to the fourteenth connection electrode 64, thus forming the first vertical connection line 91 extending along the second direction Y in the second circuit unit.

[0139] In the example embodiment, in at least one of the second circuit units, the fourteenth connection electrode 64, the fifth connection electrode 55, the twelfth connection electrode 62, the first connection electrode 51, the eleventh connection electrode 61, the third connection electrode 53, and the thirteenth connection electrode 63 can be an integrated structure connected to each other.

[0140] In the example embodiment, since the thirteenth connection electrode 63 of the present unit row and the fourteenth connection electrode 64 of the next unit row are connected to the same first horizontal connection line 81, not only the connection of the first vertical connection lines 91 in one unit column is achieved, but also the first horizontal connection line 81 extending along the first direction X and the first vertical connection line 91 extending along the second direction Y form a first meshed connection structure. Since the fifth connection electrode 55 in the first vertical connection line 91 is connected to the first initial signal line 41, the first initial signal line 41 extending along the first direction X and the first vertical connection line 91 extending along the second direction Y form another first meshed connection structure.

[0141] In the example embodiment, the first power supply line 71 can have a shape of a straight line or a broken line with a main body part extending along the second direction Y, and can be provided in the first circuit unit and the second circuit unit. In at least one of the first circuit units, the first power supply line 71 can be connected to the third connection electrode 53. In at least one of the second circuit units, the first power supply line 71 is not connected to the third connection electrode 53.

[0142] As shown in FIGS. 8 and 9B, in the example embodiment, at least one of the first circuit units or at least one of the second circuit units can further include a second connection electrode 52 connected to the first electrode of the fourth transistor T4 and a data connection electrode 74 connected to the second connection electrode 52.

[0143] In the example embodiment, in at least one of the first circuit units, the data signal line 73 is connected to the data connection electrode 74.

[0144] In the exemplary embodiment, the at least one second circuit unit can further include a first data connection block 66 connected to the second connection electrode 52 on one side and to the first initial signal line 41 on the other side.

[0145] In the exemplary embodiment, the at least one second circuit unit can further include a first vertical line 110 and a second vertical line 120, which can have a shape of a straight line or a broken line extending in the second direction Y along the main body portion.

[0146] In the exemplary embodiment, the first vertical line 110 in the at least one second circuit unit is connected to the data connection electrode 74. Since the data connection electrode 74 is connected to the second connection electrode 52, the second connection electrode 52 is connected to the first initial signal line 41 through the first data connection block 66, and thus the first vertical line 110 and the first initial signal line 41 have the same potential.

[0147] In the exemplary embodiment, the second vertical line 120 in the at least one second circuit unit can be connected to the first vertical line 110 through at least one line connection line 120-1, and thus the second vertical line 120 and the first vertical line 110 have the same potential.

[0148] In the exemplary embodiment, the first initial signal line 41 extending in the first direction X and the first horizontal connection line 81 form a horizontal double line structure for transmitting the first initial signal, the first vertical connection line 91, the first vertical line 110, and the second vertical line 120 extending in the second direction Y form a vertical triple line structure for transmitting the first initial signal, and the horizontal double line structure and the vertical triple line structure form a plurality of first meshed communication structures for transmitting the first initial signal in a meshed form.

[0149] In the exemplary embodiment, the first vertical line 110 in the second circuit unit can have substantially the same position and shape as the data signal line 73 in the first circuit unit, except that the data signal line 73 is connected to a data lead line for transmitting a data signal after extending to the bonding area, whereas the first vertical line 110 is provided only in the display area.

[0150] In the exemplary embodiment, the second vertical line 120 in the second circuit unit can have substantially the same position and shape as the second power supply line 72 in the first circuit unit, except that the second power supply line 72 can be connected to a power supply lead line for transmitting a second power supply signal after extending to the bonding area or the upper bezel area, whereas the second vertical line 120 is provided only in the display area.

[0151] In the exemplary embodiments, in a direction perpendicular to the display substrate, the driving structure layer of the first region can include a plurality of conductive layers, which can at least include a first gate metal layer (a first conductive layer), a second gate metal layer (a second conductive layer) disposed on a side of the first gate metal layer away from the base, a first source-drain metal layer (a third conductive layer) disposed on a side of the second gate metal layer away from the base, a second source-drain metal layer (a fourth conductive layer) disposed on a side of the first source-drain metal layer away from the base, and a third source-drain metal layer (a fifth conductive layer) disposed on a side of the second source-drain metal layer away from the base. The first scan signal line 21, the second scan signal line 22, the light-emitting signal line 23, and the first plate of the storage capacitor can be disposed in the first gate metal layer, the first initial signal line 41, the second initial signal line 42, and the second plate of the storage capacitor can be disposed in the second gate metal layer, the first horizontal connection line 81 and the first vertical connection line 91 can be disposed in the first source-drain metal layer, the first power supply line 71 can be disposed in the second source-drain metal layer, the second power supply line 72, the data signal line 73, the first vertical wire 110, and the second vertical wire 120 can be disposed in the third source-drain metal layer.

[0152] The preparation process of the display substrate is exemplarily illustrated below by the present exemplary embodiments. The "patterning process" in the present disclosure includes, for metal materials, inorganic materials, or transparent conductive materials, deposition of a film layer, coating photoresist on the film layer, mask exposure, development, etching, stripping of photoresist, etc., and for organic materials, coating of organic materials, mask exposure, development, etc. The deposition can adopt any one or more of sputtering, evaporation, chemical vapor deposition, the coating can adopt any one or more of spraying, spin coating, and inkjet printing, the etching can adopt any one or more of dry etching and wet etching, and the present disclosure does not make any limitation. The "film" refers to a film of a certain material made on a substrate by deposition, coating, or other processes. If the "film" does not need to be patterned during the entire production process, the "film" can also be referred to as a "layer". If the "film" needs to be patterned during the entire production process, it is referred to as a "film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are disposed in the same layer" in the present disclosure means that A and B are formed at the same time by the same patterning process. The "thickness" of the film layer refers to the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0153] In an example embodiment, taking 16 circuit units of 2 unit rows (Mth unit row and M+1th unit row) and 8 unit columns (Nth unit column to N+7th unit column) as an example, the preparation process of the substrate can include the following operations. Among them, the Nth unit column, the N+2th unit column to the N+5th unit column, and the N+7th unit column are normal unit columns, the circuit units in these unit columns are first circuit units, and the N+1th unit column and the N+6th unit column are inserted unit columns, and the circuit units in these unit columns are second circuit units.

[0154] (11) Forming a semiconductor layer pattern. In an example embodiment, forming a semiconductor layer pattern can include sequentially depositing a first insulating thin film and a semiconductor thin film on a substrate, patterning the semiconductor thin film by a patterning process, forming a first insulating layer disposed on the substrate, and a semiconductor layer pattern disposed on the first insulating layer, as shown in FIG. 10.

[0155] In an example embodiment, the semiconductor layer pattern of each circuit unit (i.e., each first circuit unit and each second circuit unit, hereinafter the same) in the first display area can include at least a first active layer 11 of a first transistor T1 to a seventh active layer 17 of a seventh transistor T7, and the first active layer 11 to the seventh active layer 17 can be an integrated structure connected to each other.

[0156] In an example embodiment, in the second direction Y, the first active layer 11, the second active layer 12, and the fourth active layer 14 can be located on the side opposite to the second direction Y of the third active layer 13, and the fifth active layer 15, the sixth active layer 16, and the seventh active layer 17 can be located on the side of the second direction Y of the third active layer 13.

[0157] In an example embodiment, the shape of the third active layer 13 can be an “Ω” shape, the shape of the first active layer 11 can be an “n” shape, the shape of the second active layer 12, the fifth active layer 15, and the sixth active layer 16 can be an “L” shape, and the shape of the fourth active layer 14 and the seventh active layer 17 can be an “I” shape.

[0158] In the example embodiment, the first active layer 11 to the seventh active layer 17 can each include a first region, a second region, and a channel region between the first region and the second region. In the example embodiment, the second region 11-2 of the first active layer and the first region 12-1 of the second active layer can be connected to each other, and the second region 11-2 of the first active layer can serve as the first region 12-1 of the second active layer. The first region 13-1 of the third active layer, the second region 14-2 of the fourth active layer, and the second region 15-2 of the fifth active layer can be connected to each other, and the first region 13-1 of the third active layer can serve as the second region 14-2 of the fourth active layer and the second region 15-2 of the fifth active layer. The second region 12-2 of the second active layer, the second region 13-2 of the third active layer, and the first region 16-1 of the sixth active layer can be connected to each other, and the second region 12-2 of the second active layer can serve as the second region 13-2 of the third active layer and the first region 16-1 of the sixth active layer. The second region 16-2 of the sixth active layer and the second region 17-2 of the seventh active layer can be connected to each other, and the second region 16-2 of the sixth active layer can serve as the second region 17-2 of the seventh active layer. The first region 11-1 of the first active layer, the first region 14-1 of the fourth active layer, the first region 15-1 of the fifth active layer, and the first region 17-1 of the seventh active layer can be separately provided.

[0159] In the example embodiment, the first region 17-1 of the seventh active layer in the circuit unit in the present process can be provided in the circuit unit in the next unit row. For example, the first region 17-1 of the seventh active layer of the circuit unit in the M-1th unit row can be provided in the circuit unit in the Mth unit row. For another example, the first region 17-1 of the seventh active layer of the circuit unit in the Mth unit row can be provided in the circuit unit in the M+1th unit row.

[0160] In the example embodiment, the position and shape of the semiconductor layer in the plurality of circuit units in one unit row can be substantially the same, and the position and shape of the semiconductor layer in the plurality of circuit units in one unit column can be substantially the same.

[0161] In the example embodiment, in the present process, the semiconductor layer in the second display region is etched to form the first insulating layer provided on the substrate.

[0162] In the example embodiment, the semiconductor layer can be polycrystalline silicon (p-Si), i.e., the third transistor to the seventh transistor are LTPS transistors. In the example embodiment, the patterning of the semiconductor thin film by the patterning process can include: first forming an amorphous silicon (a-si) thin film on the first insulating thin film, performing dehydrogenation treatment on the amorphous silicon thin film, performing crystallization treatment on the amorphous silicon thin film after the dehydrogenation treatment to form a polycrystalline silicon thin film. Subsequently, the polycrystalline silicon thin film is patterned to form a semiconductor layer pattern.

[0163] (12) forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern can include: sequentially depositing a second insulating thin film and a first conductive thin film on the substrate on which the aforementioned pattern is formed, patterning the first conductive thin film by a patterning process, forming a second insulating layer covering the semiconductor layer, and forming the first conductive layer pattern on the second insulating layer, as shown in FIGS. 11A and 11B, which is a plan view of the first conductive layer in FIG. 11A. In an exemplary embodiment, the first conductive layer can be referred to as a first gate metal (GATE1) layer.

[0164] In an exemplary embodiment, the first conductive layer pattern of each circuit unit in the first display area can include at least a first scan signal line 21, a second scan signal line 22, a light emitting signal line 23, and a first plate 31 of a storage capacitor.

[0165] In an exemplary embodiment, the first plate 31 of the storage capacitor can have a rectangular shape, and a corner of the rectangular shape can be provided with a chamfer or a groove. A normal projection of the first plate 31 on the substrate at least partially overlaps a normal projection of the third active layer on the substrate. The first plate 31 can simultaneously serve as a lower plate of the storage capacitor and a gate electrode of the third transistor T3.

[0166] In an exemplary embodiment, the first scan signal line 21 can have a straight line shape or a polygonal line shape extending along the first direction X, and can be disposed on a side of the first plate 31 opposite to the second direction Y. An area where the first scan signal line 21 overlaps the fourth active layer can serve as a gate electrode of the fourth transistor T4, thereby enabling the first scan signal line 21 to control the on or off of the fourth transistor T4.

[0167] In an exemplary embodiment, the first scan signal line 21 of each circuit unit can be provided with a gate block 21-1, which can have a strip shape extending along the second direction Y. A first end of the gate block 21-1 can be connected to a side of the first scan signal line 21 close to the first plate 31, and a second end of the gate block 21-1 can extend toward the side close to the first plate 31. An area where the first scan signal line 21 and the gate block 21-1 overlap the second active layer can serve as a gate electrode of the second transistor T2 of the dual-gate structure, thereby enabling the first scan signal line 21 to control the on or off of the second transistor T2.

[0168] In an exemplary embodiment, in at least one unit row, the first scan signal line 21 and the gate blocks 21-1 of the plurality of circuit units can be an integrated structure connected to each other.

[0169] In the example embodiment, the second scan signal line 22 can be in the shape of a straight line or a broken line extending along the first direction X, and can be arranged on the side of the first plate 31 away from the first scan signal line 21. The region where the second scan signal line 22 overlaps the first active layer in the circuit unit can serve as the gate electrode of the first transistor T1 of the double-gate structure in the circuit unit, so that the second scan signal line 22 can control the on or off of the first transistor T1 in the circuit unit. The region where the second scan signal line 22 overlaps the seventh active layer in the circuit unit in the previous unit row can serve as the gate electrode of the seventh transistor T7 in the circuit unit in the previous unit row, so that the second scan signal line 22 can control the on or off of the seventh transistor T7 in the circuit unit in the previous unit row.

[0170] In the example embodiment, the first transistor T1 in the present unit row and the seventh transistor T7 in the previous unit row are controlled by the same second scan signal line in the present unit row. In the example embodiment, in terms of timing control, the second scan signal line in the present unit row can be equivalent to the first scan signal line in the previous unit row. The present disclosure can effectively reduce the number of scan signal lines by arranging the second scan signal line in the present unit row to control the first transistor T1 in the present unit row and the seventh transistor T7 in the previous unit row, which is conducive to reducing the size of the circuit unit and improving the display resolution.

[0171] In the example embodiment, the light-emitting signal line 23 can be in the shape of a straight line or a broken line extending along the first direction X, and can be arranged on the side of the first plate 31 in the second direction Y. The region where the light-emitting signal line 23 overlaps the fifth active layer can serve as the gate electrode of the fifth transistor T5, and the region where the light-emitting signal line 23 overlaps the sixth active layer can serve as the gate electrode of the sixth transistor T6, so that the light-emitting signal line 23 can control the on or off of the fifth transistor T5 and the sixth transistor T6.

[0172] In the example embodiment, the positions and shapes of the first conductive layers in the plurality of circuit units in one unit row can be substantially the same, and the positions and shapes of the first conductive layers in the plurality of circuit units in one unit column can be substantially the same.

[0173] In the example embodiment, in the present process, the first conductive layer in the second display area is etched to form a second insulating layer arranged on the first insulating layer.

[0174] (13) forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern can include: sequentially depositing a third insulating thin film and a second conductive thin film on the substrate on which the aforementioned pattern is formed, patterning the second conductive thin film by a patterning process, forming a third insulating layer covering the first conductive layer pattern, and forming the second conductive layer pattern on the third insulating layer, as shown in FIGS. 12A and 12B, which is a plan view of the second conductive layer in FIG. 12A. In an exemplary embodiment, the second conductive layer can be referred to as a second gate metal (GATE2) layer.

[0175] In an exemplary embodiment, the second conductive layer pattern of each circuit unit in the first display area at least includes: a second plate 32 of a storage capacitor, a first initial signal line 41, a second initial signal line 42, a first shield electrode 43, and a second shield electrode 44.

[0176] In an exemplary embodiment, the second plate 32 of the storage capacitor can have a rectangular shape, and a corner of the rectangular shape can be provided with a chamfer or a groove. A normal projection of the second plate 32 on the substrate at least partially overlaps a normal projection of the first plate 31 on the substrate. The second plate 32 can serve as an upper plate of the storage capacitor, and the first plate 31 and the second plate 32 constitute the storage capacitor.

[0177] In an exemplary embodiment, the second plate 32 is provided with an opening 33, and the opening 33 can have a rectangular shape and can be located in a middle region of the second plate 32, so that the second plate 32 has a ring shape. The opening 33 exposes the third insulating layer covering the first plate 31, and a normal projection of the first plate 31 on the substrate contains a normal projection of the opening 33 on the substrate. In an exemplary embodiment, the opening 33 is configured to accommodate a seventh via hole formed subsequently, the seventh via hole is located in the opening 33 and exposes the first plate 31, so that a first connection electrode formed subsequently is connected to the first plate 31.

[0178] In an exemplary embodiment, the second plate 32 can be provided with a plate connection strip 34. The plate connection strip 34 can have a strip shape extending along the first direction X, and the plate connection strip 34 can be provided on one side of the second plate 32 in the first direction X or on the side opposite to the first direction X. A first end of the plate connection strip 34 is connected to the second plate 32 in the present circuit unit, and a second end of the plate connection strip 34 is connected to the second plate 32 in an adjacent circuit unit in the first direction X.

[0179] In the example embodiment, the second plate 32 and the plate connecting strip 34 in the two adjacent circuit units in one unit row can be an integrated structure connected with each other. For example, the second plate 32 in the Nth unit column and the second plate 32 in the N+1th unit column are connected with each other through the plate connecting strip 34, forming an integrated structure connected with each other. Since the second plate 32 in each circuit unit is connected with the first power supply line formed subsequently, by forming the second plates 32 of the adjacent circuit units into an integrated structure connected with each other, the second plates of the integrated structure can be reused as the horizontal power supply signal line, which can ensure that the multiple second plates in one unit row have the same potential, and is beneficial to improve the uniformity of the panel, avoid display defects of the display substrate, and ensure the display effect of the display substrate.

[0180] In the example embodiment, the first initial signal line 41 can be in a linear or zigzag shape extending along the first direction X, and can be arranged between the first scan signal line 21 and the second scan signal line 22. The first initial signal line 41 can be provided with a first initial connecting block 41-1, which can be in a block shape (e.g., a rectangular shape). The first end of the first initial connecting block 41-1 is connected to the side of the first initial signal line 41 away from the second plate 32, and the second end of the first initial connecting block 41-1 extends away from the second plate 32. The first initial connecting block 41-1 is configured to be connected to the first region of the first active layer through a fifth connecting electrode formed subsequently.

[0181] In the example embodiment, the first initial signal line 41 and the first initial connecting block 41-1 in at least one circuit unit can be an integrated structure connected with each other.

[0182] In the example embodiment, the second initial signal line 42 can be in a linear or zigzag shape extending along the first direction X, and can be arranged on the side of the second scan signal line 22 away from the first scan signal line 21. The second initial signal line 42 can be provided with a second initial connecting block 42-1, which can be in a block shape (e.g., a rectangular shape) and connected to the second initial signal line 42. The second initial connecting block 42-1 is configured to be connected to the first region of the seventh active layer through a sixth connecting electrode formed subsequently.

[0183] In the example embodiment, the orthographic projection of the second initial signal line 42 on the substrate at least partially overlaps the orthographic projection of the first active layer between the two gate electrodes in the first transistor T1 on the substrate. The second initial signal line 42 can shield the node between the two gate electrodes in the first transistor T1, avoid the influence of the data voltage jump on the first transistor T1, reduce the influence of the data voltage jump on the normal operation of the pixel driving circuit, and improve the display effect.

[0184] In an exemplary embodiment, in at least one circuit unit, the second initial signal line 42 and the second initial connection block 42-1 can be an integrated structure connected to each other.

[0185] In an exemplary embodiment, the first shielding electrode 43 can be in a block shape (e.g., a rectangular shape), and can be arranged on the side of the second plate 32 close to the first scan signal line 21. The first end of the first shielding electrode 43 is connected to the side of the second plate 32 close to the first scan signal line 21, and the second end of the first shielding electrode 43 extends toward the side close to the first scan signal line 21. The orthogonal projection of the first shielding electrode 43 on the substrate at least partially overlaps the orthogonal projection of the second active layer between the two gate electrodes in the second transistor T2 on the substrate. In an exemplary embodiment, the first shielding electrode 43 is configured to shield the node between the two gate electrodes in the second transistor T2, to avoid the influence of the data voltage jump on the second transistor T2, to reduce the influence of the data voltage jump on the normal operation of the pixel driving circuit, and to improve the display effect.

[0186] In an exemplary embodiment, in at least one circuit unit, the second plate 32 and the first shielding electrode 43 can be an integrated structure connected to each other.

[0187] In an exemplary embodiment, the second shielding electrode 44 can be in a strip shape extending along the second direction Y, and can be arranged on the side of the first initial signal line 41 close to the first scan signal line 21. The first end of the second shielding electrode 44 is connected to the side of the first initial signal line 41 close to the first scan signal line 21, and the second end of the second shielding electrode 44 extends toward the side close to the first scan signal line 21. In the first direction X, the second shielding electrode 44 can be located between the first region of the second active layer (also the second region of the first active layer) and the first region of the fourth active layer. In an exemplary embodiment, the second shielding electrode 44 is configured as a shielding structure between the first node and the data write-through hole, to block the influence of the data voltage jump on the first node of the pixel driving circuit, to reduce the influence of the data voltage jump on the normal operation of the pixel driving circuit, and to improve the display effect.

[0188] In an exemplary embodiment, in at least one circuit unit, the first initial signal line 41 and the second shielding electrode 44 can be an integrated structure connected to each other.

[0189] In an exemplary embodiment, the positions and shapes of the second conductive layers in the plurality of circuit units in one unit row can be substantially the same, and the positions and shapes of the second conductive layers in the plurality of circuit units in one unit column can be substantially the same.

[0190] In an exemplary embodiment, in the present process, the second conductive layer in the second display area is etched away, to form a third insulating layer arranged on the second insulating layer.

[0191] (14) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern can include: on the substrate on which the aforementioned patterns are formed, depositing a fourth insulating thin film, patterning the fourth insulating thin film using a patterning process, forming a fourth insulating layer covering the second conductive layer, the fourth insulating layer being provided with a plurality of vias, as shown in FIG. 13.

[0192] In an exemplary embodiment, the plurality of vias of each circuit unit in the first display area can include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, and a tenth via V10.

[0193] In an exemplary embodiment, the first via V1 has a footprint on the substrate within the footprint of the first region of the first active layer on the substrate, the second insulating layer, the third insulating layer, and the fourth insulating layer within the first via V1 are etched away, exposing the surface of the first region of the first active layer, and the first via V1 is configured to allow the fifth connection electrode formed subsequently to connect with the first region of the first active layer through the via.

[0194] In an exemplary embodiment, the second via V2 has a footprint on the substrate within the footprint of the second region of the first active layer (also the first region of the second active layer) on the substrate, the second insulating layer, the third insulating layer, and the fourth insulating layer within the second via V2 are etched away, exposing the surface of the second region of the first active layer (also the first region of the second active layer), and the second via V2 is configured to allow the first connection electrode formed subsequently to connect with the second region of the first active layer (also the first region of the second active layer) through the via.

[0195] In an exemplary embodiment, the third via V3 has a footprint on the substrate within the footprint of the first region of the fourth active layer on the substrate, the second insulating layer, the third insulating layer, and the fourth insulating layer within the third via V3 are etched away, exposing the surface of the first region of the fourth active layer, and the third via V3 is configured to allow the second connection electrode formed subsequently to connect with the first region of the fourth active layer through the via. In an exemplary embodiment, the third via V3 serves as a data write via of the present disclosure.

[0196] In an exemplary embodiment, the fourth via V4 has a footprint on the substrate within the footprint of the first region of the fifth active layer on the substrate, the second insulating layer, the third insulating layer, and the fourth insulating layer within the fourth via V4 are etched away, exposing the surface of the first region of the fifth active layer, and the fourth via V4 is configured to allow the third connection electrode formed subsequently to connect with the first region of the fifth active layer through the via.

[0197] In an example embodiment, the fifth via V5 is configured such that the second insulating layer, the third insulating layer and the fourth insulating layer within the fifth via V5 are etched away, exposing the surface of the second region of the sixth active layer (also the second region of the seventh active layer), and the fifth via V5 is configured to enable a fourth connection electrode formed subsequently to connect with the second region of the sixth active layer (also the second region of the seventh active layer) through the via.

[0198] In an example embodiment, the sixth via V6 is configured such that the second insulating layer, the third insulating layer and the fourth insulating layer within the sixth via V6 are etched away, exposing the surface of the first region of the seventh active layer, and the sixth via V6 is configured to enable a sixth connection electrode formed subsequently to connect with the first region of the seventh active layer through the via.

[0199] In an example embodiment, the seventh via V7 is configured such that the third insulating layer and the fourth insulating layer within the seventh via V7 are etched away, exposing the surface of the first plate 31, and the seventh via V7 is configured to enable a first connection electrode formed subsequently to connect with the first plate 31 through the via.

[0200] In an example embodiment, the eighth via V8 is configured such that the fourth insulating layer within the eighth via V8 is etched away, exposing the surface of the second plate 32, and the eighth via V8 is configured to enable a third connection electrode formed subsequently to connect with the second plate 32 through the via.

[0201] In an example embodiment, the ninth via V9 is configured such that the fourth insulating layer within the ninth via V9 is etched away, exposing the surface of the first initial connection block 41-1, and the ninth via V9 is configured to enable a fifth connection electrode formed subsequently to connect with the first initial connection block 41-1 through the via.

[0202] In an example embodiment, the tenth via V10 is configured such that the fourth insulating layer within the tenth via V10 is etched away, exposing the surface of the second initial connection block 42-1, and the tenth via V10 is configured to enable a sixth connection electrode formed subsequently to connect with the second initial connection block 42-1 through the via.

[0203] In an example embodiment, the at least one second circuit unit can further include an eleventh via V11. A projection of the eleventh via V11 on the substrate is within a projection of the first initial signal line 41 on the substrate, a fourth insulating layer within the eleventh via V11 is etched to expose a surface of the first initial signal line 41, and the eleventh via V11 is configured to allow a subsequently formed initial connection electrode to connect to the first initial signal line 41 through the via.

[0204] In an example embodiment, in the present process, a fourth insulating layer is formed on the third insulating layer in the second display area.

[0205] (15) Forming a third conductive layer pattern. In an example embodiment, forming the third conductive layer can include: on the substrate on which the aforementioned pattern is formed, depositing a third conductive thin film, and patterning the third conductive thin film using a patterning process to form a third conductive layer disposed on the fourth insulating layer, as shown in FIGS. 14A and 14B, where FIG. 14B is a plan view of the third conductive layer in FIG. 14A. In an example embodiment, the third conductive layer can be referred to as a first source-drain metal (SD1) layer.

[0206] In an example embodiment, the third conductive layer of each circuit unit in the first display area at least includes: a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55, a sixth connection electrode 56, and a first lateral connection line 81.

[0207] In an example embodiment, the first connection electrode 51 can have a shape of a strip extending along the second direction Y, a first end of the first connection electrode 51 is connected to the second region of the first active layer (also the first region of the second active layer) through the second via V2, and a second end of the first connection electrode 51 is connected to the first plate 31 through the seventh via V7. Since the first plate 31 serves as the gate electrode of the third transistor T3, the first connection electrode 51 realizes the interconnection between the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first plate 31 of the storage capacitor, forming the first node N1 of the pixel driving circuit.

[0208] In an example embodiment, the second connection electrode 52 can have a shape of a block (e.g., a rectangle), and the second connection electrode 52 is connected to the first region of the fourth active layer through the third via V3, and is configured to be connected to a subsequently formed data connection electrode.

[0209] In an example embodiment, the third connection electrode 53 can have a strip shape extending along the second direction Y, a first end of the third connection electrode 53 is connected to the first region of the fifth active layer through the fourth via V4, a second end of the third connection electrode 53 is connected to the second plate 32 through the eighth via V8, and the third connection electrode 53 is configured to be connected to the first power line formed subsequently. In an example embodiment, the third connection electrode 53 realizes the interconnection between the first electrode of the fifth transistor T5 and the second plate 32 of the storage capacitor, and the first electrode of the fifth transistor T5 and the second plate 32 of the storage capacitor have the same potential.

[0210] In an example embodiment, the fourth connection electrode 54 can have a block shape (e.g., a rectangular shape), the fourth connection electrode 54 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the fifth via V5, and the fourth connection electrode 54 is configured to be connected to the first anode connection electrode formed subsequently.

[0211] In an example embodiment, the fifth connection electrode 55 can have a ring shape (e.g., a rectangular ring) structure, which can include at least a first side and a third side extending along the first direction X, and a second side and a fourth side extending along the second direction Y, the first side can be disposed on one side of the third side in the second direction Y, the second side can be disposed on one side of the fourth side in the first direction X, and the first side, the second side, the third side and the fourth side are sequentially connected. One end of the first side is connected to the first region of the first active layer through the first via V1, and the other end of the first side is connected to the first initial connection block 41-1 through the ninth via V9. Since the first initial connection block 41-1 is connected to the first initial signal line 41, the fifth connection electrode 55 realizes that the first initial signal line 41 writes the first initial signal to the first electrode of the first transistor T1.

[0212] In an example embodiment, the sixth connection electrode 56 can have a strip shape extending along the second direction Y, a first end of the sixth connection electrode 56 is connected to the first region of the seventh active layer through the sixth via V6, and a second end of the sixth connection electrode 56 is connected to the second initial connection block 42-1 through the tenth via V10. Since the second initial connection block 42-1 is connected to the second initial signal line 42, the sixth connection electrode 56 realizes that the second initial signal line 42 writes the second initial signal to the first electrode of the seventh transistor T7.

[0213] In an example embodiment, the first lateral connection line 81 can have a straight line shape or a broken line shape extending along the first direction X, and can be located between the light-emitting signal line 23 of the current unit row and the second initial signal line 42 of the next unit row.

[0214] In the example embodiment, the third conductive layer of the at least one second circuit unit can further include an eleventh connection electrode 61, a twelfth connection electrode 62, a thirteenth connection electrode 63, and a fourteenth connection electrode 64.

[0215] In the example embodiment, the eleventh connection electrode 61 can have a strip shape extending along the first direction X, can be disposed between the first connection electrode 51 and the third connection electrode 53, and can have a first end connected to the first connection electrode 51 and a second end connected to the third connection electrode 53.

[0216] In the example embodiment, the twelfth connection electrode 62 can have a strip shape extending along the second direction Y, can be disposed between the first connection electrode 51 and the fifth connection electrode 55, and can have a first end connected to the first connection electrode 51 and a second end connected to the fifth connection electrode 55.

[0217] In the example embodiment, the thirteenth connection electrode 63 can have a strip shape extending along the second direction Y, can be disposed between the third connection electrode 53 and the first transverse connection line 81 of the present unit row, and can have a first end connected to the third connection electrode 53 and a second end connected to the first transverse connection line 81 of the present unit row. In the example embodiment, the thirteenth connection electrode 63 realizes the connection between the third connection electrode 53 and the first transverse connection line 81.

[0218] In the example embodiment, the fourteenth connection electrode 64 can have a strip shape extending along the second direction Y, can be disposed between the third side of the fifth connection electrode 55 of the present unit row and the first transverse connection line 81 of the previous unit row, and can have a first end connected to the third side of the fifth connection electrode 55 of the present unit row and a second end connected to the first transverse connection line 81 of the previous unit row, thus realizing the connection between the fifth connection electrode 55 of the present unit row and the first transverse connection line 81 of the previous unit row.

[0219] In the example embodiment, the first connection electrode 51 and the third connection electrode 53 are connected to each other through the eleventh connection electrode 61, the third connection electrode 53 is connected to the thirteenth connection electrode 63, the first connection electrode 51 and the fifth connection electrode 55 are connected to each other through the twelfth connection electrode 62, and the fifth connection electrode 55 is connected to the fourteenth connection electrode 64, thus forming a first vertical connection line 91 extending along the second direction Y in the second circuit unit, and the first vertical connection line 91 is connected to the first node N1 of the pixel driving circuit in the second circuit unit.

[0220] In the example embodiment, the fourteenth connection electrode 64, the fifth connection electrode 55, the twelfth connection electrode 62, the first connection electrode 51, the eleventh connection electrode 61, the third connection electrode 53, and the thirteenth connection electrode 63 in the at least one second circuit unit can be an integrated structure connected to each other.

[0221] In the example embodiment, since the thirteenth connection electrode 63 of the present unit row and the fourteenth connection electrode 64 of the next unit row are connected to the same first horizontal connection line 81, not only the connection of the plurality of first vertical connection lines 91 in one unit column is achieved, but also the first horizontal connection line 81 extending along the first direction X and the first vertical connection line 91 extending along the second direction Y form a first meshed communication structure formed by the third conductive layer. Since the fifth connection electrode 55 in the first vertical connection line 91 is connected to the first initial signal line 41, the first initial signal line 41 extending along the first direction X and the first vertical connection line 91 extending along the second direction Y form another first meshed communication structure formed by the second conductive layer and the third conductive layer, respectively. In this way, both of the two first meshed communication structures are meshed structures for transmitting the first initial signal, which can effectively reduce the resistance of the first initial signal line, reduce the voltage drop of the first initial signal, effectively improve the uniformity of the first initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance.

[0222] In the example embodiment, the first display area adopts a compression mode to arrange the circuit units, and the pixel driving circuit has a large wiring density, and the static electricity generated in the process is easy to accumulate, which causes damage and short circuit of the transistors in the pixel driving circuit. For example, the first scan signal line, the second scan signal line, and the light-emitting signal line are all longer signal lines in the first conductive layer, and the first initial signal line and the second initial signal line are both longer signal lines in the second conductive layer. If there is no way to transfer other signal lines, the static electricity is easy to accumulate on these longer signal lines. The present disclosure forms two first meshed communication structures for transmitting the first initial signal in the second conductive layer and the third conductive layer, which can transfer the static electricity of the longer signal lines in the first conductive layer and the second conductive layer to the third conductive layer and release it from the third conductive layer, effectively eliminating the accumulation of static electricity generated in the process, effectively avoiding damage and short circuit of the transistors in the pixel driving circuit, and improving the product quality.

[0223] In the example embodiment, the first initial signal line 41 and the first horizontal connection line 81 extending along the first direction X form a horizontal double-line structure for transmitting the first initial signal, which can further reduce the resistance of the first initial signal line and reduce the voltage drop of the first initial signal.

[0224] In the example embodiment, the third conductive layer of the at least one second circuit unit can further include a first data connection block 66. The first data connection block 66 can be in a block shape (e.g., a rectangular shape), can be disposed on the side of the second connection electrode 52 close to the first initial signal line 41, and can be connected to the second connection electrode 52. The first data connection block 66 can be connected to the first initial signal line 41 through an eleventh via V11.

[0225] In the example embodiment, the second connection electrode 52 and the first data connection block 66 in the at least one second circuit unit can be an integrated structure connected to each other.

[0226] In some other embodiments, for a display substrate in a Fanout in Panel (FIP) structure, the unit row can further include a first data connection line, a first end of the first data connection line being connected to the data signal line, and a second end of the first data connection line being connected to a second data connection line. The first data connection line and the first lateral connection line can be disposed in the same layer and formed synchronously through a same patterning process. A first break can be disposed between the first data connection line and the first lateral connection line disposed in the same unit row, and the first break is configured to realize mutual insulation between the first data connection line and the first lateral connection line.

[0227] In the example embodiment, in the present process, the third conductive layer in the second display area is etched away.

[0228] (16) Forming a fifth insulating layer and a first planar layer pattern. In the example embodiment, forming the fifth insulating layer and the first planar layer pattern can include: on the substrate on which the aforementioned patterns are formed, first depositing a fifth insulating thin film, then coating a first planar thin film, and patterning the fifth insulating thin film and the first planar thin film through a patterning process to form a fifth insulating layer covering the third conductive layer pattern and a first planar layer disposed on the fifth insulating layer, the fifth insulating layer and the first planar layer being provided with a plurality of vias, as shown in FIG. 15.

[0229] In the example embodiment, the plurality of vias in each circuit unit in the first display area at least include a twenty-first via V21, a twenty-second via V22, and a twenty-third via V23.

[0230] In the example embodiment, the orthographic projection of the twenty-first via V21 on the substrate is within the range of the orthographic projection of the second connection electrode 52 on the substrate. The fifth insulating layer and the first planar layer in the twenty-first via V21 are removed to expose the surface of the second connection electrode 52. The twenty-first via V21 is configured to enable a subsequently formed data connection electrode to be connected to the second connection electrode 52 through the via.

[0231] In an exemplary embodiment, the second twenty-two via hole V22 is configured to connect the first power line formed later with the third connection electrode 53 through the via hole.

[0232] In an exemplary embodiment, the second twenty-two via hole V22 can be provided only in the first circuit unit. Since the third connection electrode 53 in the second circuit unit constitutes the first vertical connection line and is connected with the first horizontal connection line, the second twenty-two via hole V22 is not provided in the second circuit unit, i.e. the first power line formed later is not connected with the third connection electrode 53 in the second circuit unit.

[0233] In an exemplary embodiment, the second twenty-three via hole V23 is configured to connect the first anode connection electrode formed later with the fourth connection electrode 54 through the via hole.

[0234] In an exemplary embodiment, in the present process, the fifth insulating layer provided on the fourth insulating layer and the first planar layer provided on the fifth insulating layer are formed in the second display area.

[0235] In some other embodiments, the display substrate can not be provided with the fifth insulating layer, which is not limited in the present disclosure.

[0236] (17) forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer can include: on the substrate on which the aforementioned pattern is formed, depositing a fourth conductive thin film, patterning the fourth conductive thin film by using a patterning process, and forming the fourth conductive layer provided on the first planar layer, as shown in FIG. 16A and FIG. 16B, which is a plan view of the fourth conductive layer in FIG. 16A. In an exemplary embodiment, the fourth conductive layer can be referred to as a second source-drain metal (SD2) layer.

[0237] In an exemplary embodiment, the fourth conductive layer of each circuit unit in the first display area at least includes: the first power line 71, the data connection electrode 74, and the first anode connection electrode 75.

[0238] In an exemplary embodiment, the first power line 71 can be in a shape of a straight line or a broken line with a main body extending along the second direction Y. In the first circuit unit, the first power line 71 is connected to the third connection electrode 53 through the twenty-second via V22. Since the third connection electrode 53 is connected to the first area of the fifth active layer and the second plate 32 respectively through the via, the first power line 71 can write the first power signal to the second plate 32 of the storage capacitor and the first plate of the fifth transistor T5 respectively. Since the first vertical connection line is formed in the second circuit unit, the first power line 71 in the second circuit unit is not connected to the third connection electrode 53 in the second circuit unit.

[0239] In an exemplary embodiment, the plurality of first power lines 71 can extend to the binding area or the upper frame area and be connected to the power lead wire for transmitting the first power signal.

[0240] In an exemplary embodiment, the first power line 71 can be a broken line with variable width, and the orthographic projection of the first power line 71 on the substrate at least partially overlaps the orthographic projection of the first connection electrode 51 on the substrate. Since the first connection electrode 51 is the first node N1 of the pixel driving circuit, the first power line 71 with constant potential can shield the first node N1, avoid the influence of data voltage jump on the first node N1, improve the working stability of the pixel driving circuit, and improve the display effect.

[0241] In an exemplary embodiment, the orthographic projection of the first power line 71 on the substrate can contain the orthographic projection of the first connection electrode 51 on the substrate.

[0242] In an exemplary embodiment, the data connection electrode 74 can be in a shape of a block (such as a rectangle), the data connection electrode 74 is connected to the second connection electrode 52 through the twenty-first via V21, and the data connection electrode 74 is configured to be connected to the data signal line or the first vertical trace formed subsequently.

[0243] In an exemplary embodiment, the first anode connection electrode 75 can be in a shape of a block (such as a rectangle), the first anode connection electrode 75 is connected to the fourth connection electrode 54 through the twenty-third via V23, and the first anode connection electrode 75 is configured to be connected to the second anode connection electrode formed subsequently.

[0244] In an exemplary embodiment, in this process, the fourth conductive layer in the second display area is etched.

[0245] (18) forming a second planar layer pattern. In an exemplary embodiment, forming the second planar layer pattern can include: on the substrate on which the aforementioned patterns are formed, coating a second planar film, patterning the second planar film using a patterning process, forming a second planar layer covering the fourth conductive layer pattern, the second planar layer being provided with a plurality of vias, as shown in FIG. 17.

[0246] In an exemplary embodiment, the plurality of vias in each circuit unit in the first display area includes at least a thirty-first via V31 and a thirty-second via V32.

[0247] In an exemplary embodiment, the thirty-first via V31 has a projection on the substrate within the projection of the data connection electrode 74 on the substrate, the second planar layer in the thirty-first via V31 is removed to expose the surface of the data connection electrode 74, and the thirty-first via V31 is configured to allow a data signal line or a first vertical trace formed subsequently to connect with the data connection electrode 74 through the via.

[0248] In an exemplary embodiment, the thirty-second via V32 has a projection on the substrate within the projection of the first anode connection electrode 75 on the substrate, the second planar layer in the thirty-second via V32 is removed to expose the surface of the first anode connection electrode 75, and the thirty-second via V32 is configured to allow a second anode connection electrode formed subsequently to connect with the first anode connection electrode 75 through the via.

[0249] In an exemplary embodiment, in this process, the second display area forms a second planar layer provided on the first planar layer.

[0250] (19) forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer can include: on the substrate on which the aforementioned patterns are formed, depositing a fifth conductive film, patterning the fourth conductive film using a patterning process, forming a fifth conductive layer provided on the first planar layer, as shown in FIGS. 18A and 18B, FIG. 18B being a plan view of the fifth conductive layer in FIG. 18A. In an exemplary embodiment, the fifth conductive layer can be referred to as a third source-drain metal (SD3) layer.

[0251] In an exemplary embodiment, the fifth conductive layer of each first circuit unit in the first display area includes at least the second power line 72, the data signal line 73, and the second anode connection electrode 76, and the fifth conductive layer of each second circuit unit in the first display area includes at least the second anode connection electrode 76, the first vertical trace 110, and the second vertical trace 120.

[0252] In the example embodiment, the shape of the second power line 72 in the first circuit unit can be a straight line or a broken line with the main body extending along the second direction Y, and the second power line 72 is configured to be connected with the cathode of the light emitting device. In the example embodiment, a plurality of second power lines 72 can extend to the binding area or the upper frame area, and be connected with the power lead wire for transmitting the second power signal, so as to realize the SIP (SIP: S in Panel) structure of the second power line, effectively reduce the resistance of the second power line, reduce the voltage drop of the second power signal, effectively improve the uniformity of the second power signal in the display substrate, effectively improve the display uniformity, improve the display quality and display effect, and reduce the frame width, improve the screen ratio, and facilitate the realization of the full-screen display.

[0253] In the example embodiment, the shape of the data signal line 73 in the first circuit unit can be a straight line or a broken line with the main body extending along the second direction Y, and the data signal line 73 is connected with the data connection electrode 74 through the thirty-first via V31. Since the data connection electrode 74 in the first circuit unit is connected with the second connection electrode 52 through the via, and the second connection electrode 52 is connected with the first area of the fourth active layer through the via, the data signal line 73 can write the data signal to the first electrode of the fourth transistor T4 in the first circuit unit.

[0254] In the example embodiment, the shape of the second anode connection electrode 76 can be a block shape (such as a rectangular shape), and the second anode connection electrode 76 is connected with the first anode connection electrode 75 through the thirty-second via V32. The second anode connection electrode 76 in the first circuit unit is configured to be connected with the anode in the first display area 100A formed subsequently. Since the first anode connection electrode 75 in the first circuit unit is connected with the fourth connection electrode 54 through the via, and the fourth connection electrode 54 is connected with the second area of the sixth active layer (also the second area of the seventh active layer) through the via, the pixel driving circuit in the first circuit unit can output the driving current to the light emitting device in the first display area 100A. The second anode connection electrode 76 in the second circuit unit is configured as a dummy electrode, which is neither connected with the anode in the first display area 100A nor connected with the anode in the second display area 100B.

[0255] In the exemplary embodiment, the first vertical trace 110 in the second circuit unit can be in a straight line shape or a broken line shape with the main part extending along the second direction Y, and the first vertical trace 110 is connected to the data connection electrode 74 through the thirty-first via V31. Since the data connection electrode 74 is connected to the second connection electrode 52 through the via, the second connection electrode 52 is not only connected to the first region of the fourth active layer through the via, but also connected to the first data connection block 66 which is connected to the first initial signal line 41 through the via, so that the first vertical trace 110 and the first initial signal line 41 have the same potential, which not only avoids the floating of the first vertical trace 110, but also realizes that the first vertical trace 110 can write the first initial signal to the first electrode of the fourth transistor T4 in the second circuit unit.

[0256] In the exemplary embodiment, the first vertical connection line formed in the second circuit unit is connected to the first node N1 of the pixel driving circuit in the second circuit unit, and the disclosure can effectively avoid the short circuit between the first node N1 and the second node N2 when the fourth transistor T4 is turned on by writing the first initial signal to the first electrode of the fourth transistor T4 in the second circuit unit.

[0257] In the exemplary embodiment, the position and shape of the first vertical trace 110 in the second circuit unit can be substantially the same as the position and shape of the data signal line 73 in the first circuit unit, except that the data signal line 73 is connected to the data lead wire for transmitting the data signal after extending to the binding area, while the first vertical trace 110 is only arranged in the display area.

[0258] In the exemplary embodiment, the second vertical trace 120 in the second circuit unit can be in a straight line shape or a broken line shape with the main part extending along the second direction Y. In at least one second circuit unit, the first vertical trace 110 and the second vertical trace 120 can be connected to each other through at least one trace connection line 120-1. The trace connection line 120-1 can be in a straight line shape or a broken line shape with the main part extending along the first direction X, the first end of the trace connection line 120-1 is connected to the first vertical trace 110, and the second end of the trace connection line 120-1 is connected to the second vertical trace 120.

[0259] In the exemplary embodiment, in at least one insertion unit column, the first vertical trace 110, the second vertical trace 120 and the trace connection line 120-1 can be an integrated structure connected to each other.

[0260] In the exemplary embodiment, the position and shape of the second vertical trace 120 in the second circuit unit can be substantially the same as the position and shape of the second power supply line 72 in the first circuit unit, except that the second power supply line 72 can be connected with a power supply lead wire transmitting the second power supply signal after extending to the binding area or the upper frame area, while the second vertical trace 120 is only arranged in the display area.

[0261] In the exemplary embodiment, since the first vertical connection line 91 and the first vertical trace 110 transmit the first initial signal, the second vertical trace 120 is connected with the first vertical trace 110, thus the second vertical trace 120 also transmits the first initial signal, the first vertical connection line 91, the first vertical trace 110 and the second vertical trace 120 extending along the second direction Y form a vertical three-wire structure transmitting the first initial signal, which can further reduce the resistance of the first initial signal line and reduce the voltage drop of the first initial signal.

[0262] In the exemplary embodiment, the horizontal two-wire structure composed of the first initial signal line 41 and the first horizontal connection line 81 and the vertical three-wire structure composed of the first vertical connection line 91, the first vertical trace 110 and the second vertical trace 120 can form a plurality of first meshed communication structures, which can maximally reduce the resistance of the first initial signal line and maximally reduce the voltage drop of the first initial signal.

[0263] In some other embodiments, for the display substrate of the FIP structure, the normal unit column can further include a second data connection line, a first end of the second data connection line is connected with the first data connection line, and a second end of the second data connection line is connected with a data lead-out wire after extending to the binding area. The second data connection line and the second power supply line can be arranged in the same layer and formed synchronously through the same patterning process, and a second break can be arranged between the second data connection line and the second power supply line arranged in the same unit column, and the second break is configured to realize mutual insulation between the second data connection line and the second power supply line.

[0264] In the exemplary embodiment, in the present process, the fifth conductive layer in the second display area is etched away.

[0265] The subsequent preparation process can include forming a third planar layer, the third planar layer is provided with an anode via hole, the anode via hole exposes the surface of the second anode connection electrode, and the anode via hole is configured to enable the subsequent anode to be connected with the second anode connection electrode through the via hole.

[0266] Thus far, the driving structure layer of the present embodiment is prepared on the substrate. The driving structure layer of the first display area can include, in sequence, a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer, a first planar layer, a fourth conductive layer, a second planar layer, a fifth conductive layer, and a third planar layer on the substrate. The semiconductor layer can include at least an active layer of a plurality of transistors, the first conductive layer can include at least a first scan signal line, a second scan signal line, a light-emitting signal line, and a first plate of a storage capacitor, the second conductive layer can include at least a first initial signal line, a second initial signal line, and a second plate of the storage capacitor, the third conductive layer can include at least a first horizontal connection line, a first vertical connection line, and a plurality of connection electrodes, the fourth conductive layer can include at least a first power supply line, and the fifth conductive layer can include at least a data signal line, a second power supply line, a first vertical trace, and a second vertical trace.

[0267] In an exemplary embodiment, the substrate can be a flexible substrate, or can be a rigid substrate. The rigid substrate can include, but is not limited to, one or more of glass, quartz, and the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate can include, in sequence on a glass carrier plate, a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer. The materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the like, and the materials of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), or the like, for improving the water-oxygen resistance of the substrate. The first and second inorganic material layers are also referred to as barrier layers, and the material of the semiconductor layer can be amorphous silicon (a-si).

[0268] In the example embodiment, the first, second, third, fourth and fifth insulating layers can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can be a single layer, multiple layers or a composite layer. The shielding layer, the first, second, third, fourth and fifth conductive layers can be a metal material such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) or molybdenum (Mo), or can be an alloy material composed of metals such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single layer structure or a multiple composite structure such as Ti / Al / Ti. The first, second and third planar layers can be an organic material such as resin or polyimide.

[0269] In the example embodiment, after the driving structure layer is prepared, a light-emitting structure layer can be prepared on the driving structure layer, and an encapsulation structure layer can be prepared on the light-emitting structure layer, which will not be described herein.

[0270] The example embodiment of the present disclosure provides a display substrate. By forming a first horizontal connection line extending along a first direction X and a first vertical connection line extending along a second direction Y in a display area, and the first horizontal connection line and the first vertical connection line forming a first meshed communication structure for transmitting a first initial signal, the resistance of the first initial signal line can be effectively reduced, the voltage drop of the first initial signal can be reduced, the uniformity of the first initial signal in the display substrate can be effectively improved, the display uniformity can be effectively improved, and the display quality and display performance are improved.

[0271] The example embodiment of the present disclosure forms a horizontal double-line structure for transmitting the first initial signal in the second and third conductive layers, and forms a vertical three-line structure for transmitting the first initial signal in the third and fifth conductive layers. The horizontal double-line structure and the vertical three-line structure can form a plurality of first meshed communication structures, which can maximally reduce the resistance of the first initial signal line and maximally reduce the voltage drop of the first initial signal.

[0272] The example embodiment of the present disclosure forms the first meshed communication structure for transmitting the first initial signal, which can transfer the static electricity of the longer signal line in the first and second conductive layers to the third conductive layer and discharge the static electricity from the third conductive layer, effectively eliminating the accumulation of static electricity generated in the process, effectively avoiding the damage and short circuit of the transistor in the pixel driving circuit, and improving the product quality. In addition, forming the first meshed communication structure on the display substrate can also effectively improve the hole mura phenomenon.

[0273] The circuit unit is arranged in a compression mode, the first display area adopts a 4-in-1 structure, which can not only reduce the circuit difference of each area and avoid adverse effects such as screen-off watermark caused by the circuit difference, but also has a reasonable structure layout and will not affect the transmittance.

[0274] The second power line is arranged in the display area to achieve the SIP structure, which can effectively reduce the resistance of the second power line, reduce the voltage drop of the second power signal, effectively improve the uniformity of the second power signal in the display substrate, effectively improve the display uniformity, improve the display quality and display quality, reduce the frame width, improve the screen-to-body ratio, and facilitate the realization of the full-screen display.

[0275] The first vertical trace is connected with the first initial signal line, which can not only avoid the floating of the first vertical trace in the second circuit unit, but also effectively avoid the short circuit between nodes in the pixel driving circuit.

[0276] The preparation process of the embodiment of the present disclosure can be well compatible with the existing preparation process, and the process is simple to implement, high in production efficiency, low in production cost, and high in yield.

[0277] FIG. 19 is a structural schematic diagram of another first display area according to an example embodiment of the present disclosure. In the example embodiment, the main structure of the display substrate of the present embodiment is basically the same as that of the display substrate shown in FIG. 8, except that the driving structure layer of the first display area further includes at least one second horizontal connection line 82 and at least one second vertical connection line 92, the second initial signal line 42 and the second vertical connection line 92 form a second mesh communication structure on the display substrate, and the second horizontal connection line 82 and the second vertical connection line 92 form another second mesh communication structure on the display substrate.

[0278] FIGS. 20A and 20B are structural schematic diagrams of a second mesh communication structure according to an example embodiment of the present disclosure. As shown in FIGS. 19 and 20A, the shape of the second horizontal connection line 82 can be a straight line or a polyline extending along the first direction X, and the second horizontal connection line 82 can be continuously arranged in a plurality of first circuit units and a plurality of second circuit units in at least one unit row. The shape of the second vertical connection line 92 can be a polyline extending along the second direction Y, and the second vertical connection line 92 can be arranged in a plurality of second circuit units of at least one insertion unit column. For example, the second vertical connection line 92 can be arranged in the N+1th unit column and the N+6th unit column, respectively.

[0279] In the exemplary embodiment, the first circuit unit and the second circuit unit can further include a sixth connection electrode 56, one end of which is connected to the first electrode of the seventh transistor T7, and the other end of which is connected to the second initial signal line 42.

[0280] In the exemplary embodiment, the at least one second circuit unit can further include a first connection electrode 51, a third connection electrode 53, a fifth connection electrode 55, an eleventh connection electrode 61, a twelfth connection electrode 62, a thirteenth connection electrode 63, and a fourteenth connection electrode 64, which are substantially the same as those of the embodiment shown in FIG. 8, except that the thirteenth connection electrode 63 connects the third connection electrode 53 and the second horizontal connection line 82, and the fourteenth connection electrode 64 connects the fifth connection electrode 55 of the present unit row and the second horizontal connection line 82 of the previous unit row, thereby forming a second vertical connection line 92 extending in the second direction Y in the second circuit unit.

[0281] In the exemplary embodiment, the at least one second circuit unit can further include a fifteenth connection electrode 65. The fifteenth connection electrode 65 can be disposed between and connected to the fifth connection electrode 55 and the sixth connection electrode 56.

[0282] In the exemplary embodiment, since the thirteenth connection electrode 63 of the present unit row and the fourteenth connection electrode 64 of the next unit row are connected to the same second horizontal connection line 82, not only the plurality of second vertical connection lines 92 in one unit column are connected to each other, but also the second horizontal connection line 82 extending in the first direction X and the second vertical connection line 92 extending in the second direction Y form one second meshed communication structure. Since the fifth connection electrode 55 in the first vertical connection line 91 is connected to the sixth connection electrode 56 through the fifteenth connection electrode 65, and the sixth connection electrode 56 is connected to the second initial signal line 42, the second initial signal line 42 extending in the first direction X and the second vertical connection line 92 extending in the second direction Y form another second meshed communication structure.

[0283] In the exemplary embodiment, in the at least one first circuit unit, the first power supply line 71 can be connected to the third connection electrode 53. In the at least one second circuit unit, the first power supply line 71 is not connected to the third connection electrode 53.

[0284] As shown in FIGS. 19 and 20B, the at least one first circuit unit can further include a second data connection block 67 connected with the sixth connection electrode 56. The at least one second circuit unit can further include a third data connection block 68 connected with the data connection electrode 74, and the third data connection block 68 is connected with the second data connection block 67 through a via.

[0285] In the exemplary embodiment, the first vertical wire 110 in the second circuit unit is connected with the data connection electrode 74 through a via. Since the data connection electrode 74 is connected with the third data connection block 68, the third data connection block 68 is connected with the second data connection block 67 through a via, and the second data connection block 67 is connected with the sixth connection electrode 56, and the sixth connection electrode 56 is connected with the second initial signal line 42, the first vertical wire 110 and the second initial signal line 42 have the same potential. Since the second vertical wire 120 is connected with the first vertical wire 110 through the wire connection line 120-1, the second vertical wire 120 and the first vertical wire 110 have the same potential.

[0286] In the exemplary embodiment, the second initial signal line 42 and the second horizontal connection line 82 extending along the first direction X form a horizontal double-line structure for transmitting the second initial signal, the second vertical connection line 92, the first vertical wire 110 and the second vertical wire 120 extending along the second direction Y form a vertical three-line structure for transmitting the second initial signal, and the horizontal double-line structure and the vertical three-line structure form a plurality of second meshed communication structures for transmitting the second initial signal in a meshed manner.

[0287] In the exemplary embodiment, the preparation process of the substrate can include the following operations.

[0288] (21) The semiconductor layer, the first conductive layer and the second conductive layer are sequentially formed, and the formation process and the formed semiconductor layer, the first conductive layer and the second conductive layer are substantially the same as those of the embodiment shown in FIG. 8.

[0289] (24) The fourth insulating layer pattern is formed, and the formation process and the formed fourth insulating layer pattern are substantially the same as those of the embodiment shown in FIG. 8, except that the second vertical connection line is formed in the second circuit unit in the subsequent process, and the second vertical connection line is connected with the second initial signal line, so that the second circuit unit is not provided with the ninth via V9, i.e., the fifth connection electrode of the second circuit unit formed subsequently is not connected with the first initial connection block 41-1. In addition, the eleventh via is not formed on the fourth insulating layer in the embodiment, as shown in FIG. 21.

[0290] (25) forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer can include: depositing a third conductive thin film on the substrate on which the aforementioned patterns are formed, patterning the third conductive thin film by using a patterning process, and forming the third conductive layer disposed on the fourth insulating layer, as shown in FIGS. 22A and 22B, which is a plan view of the third conductive layer in FIG. 22A.

[0291] In an exemplary embodiment, the third conductive layer of each circuit unit in the first display area can include at least: a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55, a sixth connection electrode 56, and a second horizontal connection line 82, the structures of the first connection electrode 51 to the sixth connection electrode 56 being substantially the same as those in the embodiment shown in FIG. 8.

[0292] In an exemplary embodiment, the second horizontal connection line 82 can have a linear shape or a zigzag shape extending along the first direction X, and can be located between the light emitting signal line 23 of the present unit row and the second initial signal line 42 of the next unit row.

[0293] In an exemplary embodiment, the third conductive layer of at least one second circuit unit can further include an eleventh connection electrode 61, a twelfth connection electrode 62, a thirteenth connection electrode 63, and a fourteenth connection electrode 64, the structures of the eleventh connection electrode 61 to the fourteenth connection electrode 64 being substantially the same as those in the embodiment shown in FIG. 8, except that the thirteenth connection electrode 63 connects the third connection electrode 53 and the second horizontal connection line 82, and the fourteenth connection electrode 64 connects the fifth connection electrode 55 of the present unit row and the second horizontal connection line 82 of the previous unit row, thereby forming a second vertical connection line 92 extending along the second direction Y in the second circuit unit, and the second vertical connection line 92 is connected to the first node N1 of the pixel driving circuit in the second circuit unit.

[0294] In an exemplary embodiment, the third conductive layer of at least one second circuit unit can further include a fifteenth connection electrode 65. The fifteenth connection electrode 65 can have a strip shape extending along the first direction X, and can be disposed between the fifth connection electrode 55 and the sixth connection electrode 56, with a first end of the fifteenth connection electrode 65 connected to the fifth connection electrode 55 and a second end of the fifteenth connection electrode 65 connected to the sixth connection electrode 56.

[0295] In the example embodiment, since the thirteenth connection electrode 63 of the present unit row and the fourteenth connection electrode 64 of the next unit row are connected with the same second horizontal connection line 82, not only the interconnection of the plurality of second vertical connection lines 92 in one unit column is achieved, but also the second horizontal connection line 82 extending along the first direction X and the second vertical connection line 92 extending along the second direction Y form a second meshed communication structure, which is formed by the third conductive layer. Since the fifth connection electrode 55 in the first vertical connection line 91 is connected with the sixth connection electrode 56 through the fifteenth connection electrode 65, and the sixth connection electrode 56 is connected with the second initial signal line 42, the second initial signal line 42 extending along the first direction X and the second vertical connection line 92 extending along the second direction Y form another second meshed communication structure, which is formed by the second conductive layer and the third conductive layer. In this way, both of the two second meshed communication structures are meshed structures for transmitting the second initial signal, which can effectively reduce the resistance of the second initial signal line, reduce the voltage drop of the second initial signal, effectively improve the uniformity of the second initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance.

[0296] In the example embodiment, by forming the two second meshed communication structures for transmitting the second initial signal in the second conductive layer and the third conductive layer, the static electricity of the longer signal line in the first conductive layer and the second conductive layer can be transferred to and released from the third conductive layer, which effectively eliminates the accumulation of static electricity generated in the process, effectively avoids the damage and short circuit of the transistor in the pixel driving circuit, and improves the product quality.

[0297] In the example embodiment, the second initial signal line 42 extending along the first direction X and the second horizontal connection line 82 form a horizontal double-line structure for transmitting the second initial signal, which can further reduce the resistance of the second initial signal line and reduce the voltage drop of the second initial signal.

[0298] In the example embodiment, the third conductive layer of the at least one first circuit unit can further include a second data connection block 67. The second data connection block 67 can be in the shape of a block (such as a rectangle), which can be arranged on the side of the sixth connection electrode 56 away from the fifth connection electrode 55 and connected with the sixth connection electrode 56. The first data connection block 66 is configured to be connected with the third data connection block formed subsequently.

[0299] In the example embodiment, in the at least one first circuit unit, the sixth connection electrode 56 and the second data connection block 67 can be an integrated structure connected with each other.

[0300] In the exemplary embodiments, the second data connection block 67 can be arranged in the first circuit unit on the first direction X side of the second circuit unit. For example, for the N+1 unit column as the insertion unit column, the second data connection block 67 can be arranged in at least one first circuit unit of the N+2 unit column. For another example, for the N+6 unit column as the insertion unit column, the second data connection block 67 can be arranged in at least one first circuit unit of the N+7 unit column.

[0301] (26) The fifth insulating layer and the first planar layer pattern are formed, the forming process and the formed fifth insulating layer and the first planar layer pattern are basically the same as those of the embodiment shown in FIG. 8, except that the fifth insulating layer and the first planar layer are further provided with the twenty-fourth via hole V24, as shown in FIG. 23.

[0302] In the exemplary embodiments, the orthogonal projection of the twenty-fourth via hole V24 on the substrate is within the orthogonal projection range of the second data connection block 67 on the substrate, the fifth insulating layer and the first planar layer in the twenty-fourth via hole V24 are removed to expose the surface of the second data connection block 67, and the twenty-fourth via hole V24 is configured to allow the third data connection block formed subsequently to connect with the second data connection block 67 through the via hole.

[0303] In the exemplary embodiments, the twenty-second via hole V22 can be arranged only in the first circuit unit. Since the third connection electrode 53 in the second circuit unit constitutes the second vertical connection line and is connected with the second horizontal connection line, the second circuit unit is not provided with the twenty-second via hole V22, i.e., the first power supply line formed subsequently is not connected with the third connection electrode 53 in the second circuit unit.

[0304] (27) The fourth conductive layer pattern is formed, the forming process and the formed fourth conductive layer pattern are basically the same as those of the embodiment shown in FIG. 8, except that the fourth conductive layer of at least one second circuit unit can further include a third data connection block 68, as shown in FIG. 24A and FIG. 24B, wherein FIG. 24B is a plan view of the fourth conductive layer in FIG. 24A.

[0305] In the exemplary embodiments, the third data connection block 68 arranged in the second circuit unit can have a block shape (e.g., a rectangular shape), can be arranged on the side of the data connection electrode 74 close to the second data connection block 67 and connected with the data connection electrode 74, and the third data connection block 68 is connected with the second data connection block 67 through the twenty-fourth via hole V24.

[0306] In the exemplary embodiments, in at least one second circuit unit, the data connection electrode 74 and the third data connection block 68 can be an integrated structure connected with each other.

[0307] In the exemplary embodiment, the first power line 71 in the second circuit unit is not connected to the third connection electrode 53 in the second circuit unit because the second vertical connection line is formed in the second circuit unit.

[0308] (28) The second planar layer and the fifth conductive layer pattern are sequentially formed, and the forming process and the formed second planar layer and the fifth conductive layer pattern are substantially the same as those of the embodiment shown in FIG. 8, as shown in FIG. 19.

[0309] In the exemplary embodiment, the first vertical trace 110 in the second circuit unit is connected to the data connection electrode 74 through the via. Since the data connection electrode 74 is connected to the third data connection block 68, the third data connection block 68 is connected to the second data connection block 67 through the via, the second data connection block 67 is connected to the sixth connection electrode 56, and the sixth connection electrode 56 is connected to the second initial signal line 42, the first vertical trace 110 and the second initial signal line 42 have the same potential, which not only avoids floating of the first vertical trace 110, but also realizes that the first vertical trace 110 can write the second initial signal to the first electrode of the fourth transistor T4 in the second circuit unit. The disclosure can effectively avoid the short circuit between the first node N1 and the second node N2 when the fourth transistor T4 is turned on by writing the second initial signal to the first electrode of the fourth transistor T4 in the second circuit unit.

[0310] In the exemplary embodiment, the second vertical trace 120 is connected to the first vertical trace 110 through the trace connection line 120-1, so that the second vertical trace 120 and the first vertical trace 110 have the same potential. In this way, the second vertical connection line 92 extending along the second direction Y, the first vertical trace 110 and the second vertical trace 120 form a vertical three-wire structure for transmitting the second initial signal, which can further reduce the resistance of the second initial signal line and reduce the voltage drop of the second initial signal.

[0311] In the exemplary embodiment, the horizontal double-wire structure composed of the second initial signal line 42 and the second horizontal connection line 82 and the vertical three-wire structure composed of the second vertical connection line 92, the first vertical trace 110 and the second vertical trace 120 can form a plurality of second mesh communication structures, which can maximize the reduction of the resistance of the second initial signal line and the voltage drop of the second initial signal.

[0312] The display substrate provided by the embodiment of the present disclosure can effectively reduce the resistance of the second initial signal line, reduce the voltage drop of the second initial signal, effectively improve the uniformity of the second initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance.

[0313] The embodiment of the present disclosure can form a horizontal double-line structure for transmitting the second initial signal in the second conductive layer and the third conductive layer, and form a vertical three-line structure for transmitting the second initial signal in the third conductive layer and the fifth conductive layer. The horizontal double-line structure and the vertical three-line structure can form a plurality of second meshed communication structures, which can maximally reduce the resistance of the second initial signal line and maximally reduce the voltage drop of the second initial signal.

[0314] The embodiment of the present disclosure can form a second meshed communication structure for transmitting the second initial signal, so that the static electricity of the longer signal line in the first conductive layer and the second conductive layer can be transferred to the third conductive layer and discharged from the third conductive layer. The embodiment of the present disclosure can effectively eliminate the static electricity accumulated in the process, effectively avoid the damage and short circuit of the transistor in the pixel driving circuit, and improve the product quality. In addition, the second meshed communication structure formed on the display substrate can also effectively improve the hole mura phenomenon.

[0315] The embodiment of the present disclosure can connect the first vertical wire with the second initial signal line, which can not only avoid the floating of the first vertical wire in the second circuit unit, but also effectively avoid the short circuit between the nodes in the pixel driving circuit.

[0316] FIG. 25 is a structural schematic diagram of another display substrate according to an embodiment of the present disclosure. In the embodiment, the main structure of the display substrate is basically the same as that of the display substrate described above, except that the driving structure layer of the first display area further includes at least one third horizontal connection line 83 and at least one third vertical connection line 93. The third horizontal connection line 83 and the first power line 71 form a third meshed communication structure on the display substrate, and the third horizontal connection line 83 and the third vertical connection line 93 form another third meshed communication structure on the display substrate.

[0317] FIGS. 26A and 26B are structural diagrams of a third meshed connection structure according to an exemplary embodiment of the present disclosure. As shown in FIGS. 25 and 26A, the third horizontal connection line 83 can have a shape of a straight line or a broken line extending along the first direction X, and the third horizontal connection line 83 can be continuously provided in the plurality of first circuit units and the plurality of second circuit units in at least one unit row. The third vertical connection line 93 can have a shape of a broken line extending along the second direction Y, and can be provided in the plurality of second circuit units of at least one insertion unit column. For example, the third vertical connection line 93 can be provided in the N+lth unit column and the N+6th unit column, respectively.

[0318] In the exemplary embodiment, the at least one second circuit unit can further include the first connection electrode 51, the third connection electrode 53, the fifth connection electrode 55, the eleventh connection electrode 61, the twelfth connection electrode 62, the thirteenth connection electrode 63, and the fourteenth connection electrode 64, and the above-described structure can be substantially the same as that of the embodiment shown in FIG. 8, except that the thirteenth connection electrode 63 connects the third connection electrode 53 and the third horizontal connection line 83, and the fourteenth connection electrode 64 connects the fifth connection electrode 55 of the present unit row and the third horizontal connection line 83 of the previous unit row, thereby forming the third vertical connection line 93 extending along the second direction Y in the second circuit unit.

[0319] In the exemplary embodiment, since the thirteenth connection electrode 63 of the present unit row and the fourteenth connection electrode 64 of the next unit row are connected to the same third horizontal connection line 83, not only the plurality of third vertical connection lines 93 in one unit column are connected to each other, but also the third horizontal connection line 83 extending along the first direction X and the third vertical connection line 93 extending along the second direction Y form one third meshed connection structure. Since the third connection electrode 53 in the third vertical connection line 93 is connected to the first power supply line 71, the third horizontal connection line 83 extending along the first direction X and the first power supply line 71 extending along the second direction Y form another third meshed connection structure.

[0320] In the exemplary embodiment, since the second electrode plate and the electrode plate connection bar in the second conductive layer form the horizontal power supply signal line 30, the horizontal power supply signal line 30 can form yet another third meshed connection structure with the third vertical connection line 93.

[0321] In the exemplary embodiment, the first power supply line 71 is connected not only to the third connection electrode 53 in the first circuit unit, but also to the third connection electrode 53 in the second circuit unit.

[0322] As shown in FIG. 25 and FIG. 26B, the at least one second circuit unit can further include a power connection block 71-1 connected with the first power line 71 and the data connection electrode 74, respectively.

[0323] In the exemplary embodiment, the first vertical wire 110 in the second circuit unit is connected with the data connection electrode 74 through a via. Since the data connection electrode 74 is connected with the first power line 71 through the power connection block 71-1, the first vertical wire 110 and the first power line 71 have the same potential. Since the second vertical wire 120 is connected with the first vertical wire 110 through the wire connection line 120-1, the second vertical wire 120 and the first vertical wire 110 have the same potential.

[0324] In the exemplary embodiment, the lateral power signal line 30 and the third lateral connection line 83 extending along the first direction X form a lateral double-line structure for transmitting the first power signal, the first power line 71, the third vertical connection line 93, the first vertical wire 110 and the second vertical wire 120 extending along the second direction Y form a vertical four-line structure for transmitting the first power signal, and the lateral double-line structure and the vertical four-line structure form a plurality of third meshed communication structures for transmitting the first power signal in a meshed manner.

[0325] In the exemplary embodiment, the preparation process of the substrate can include the following operations.

[0326] (31) to (34) sequentially form the semiconductor layer, the first conductive layer, the second conductive layer and the fourth insulating layer pattern, the forming process and the formed semiconductor layer, the first conductive layer, the second conductive layer and the fourth insulating layer pattern are basically the same as those of the embodiment shown in FIG. 8, except that the second circuit unit is not provided with the ninth via V9 since the third vertical connection line is formed in the second circuit unit in the subsequent process and the third vertical connection line is configured to be connected with the first power line. In addition, the fourth insulating layer of the present embodiment is not formed with the eleventh via.

[0327] (35) form a third conductive layer pattern. In the exemplary embodiment, forming the third conductive layer can include: on the substrate formed with the aforementioned patterns, depositing a third conductive thin film, patterning the third conductive thin film by using a patterning process, and forming the third conductive layer disposed on the fourth insulating layer, as shown in FIG. 27A and FIG. 27B, wherein FIG. 27B is a plan view of the third conductive layer in FIG. 27A.

[0328] In the example embodiment, the third conductive layer of each circuit unit in the first display area at least includes: a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55, a sixth connection electrode 56, and a third lateral connection line 83, the structures of the first connection electrode 51 to the sixth connection electrode 56 are basically the same as those of the embodiment shown in FIG. 8.

[0329] In the example embodiment, the third lateral connection line 83 can be in a straight line shape or a broken line shape extending along the first direction X, and can be located between the light emitting signal line 23 of the current unit row and the first power supply line 71 of the next unit row.

[0330] In the example embodiment, the third conductive layer of at least one second circuit unit can further include an eleventh connection electrode 61, a twelfth connection electrode 62, a thirteenth connection electrode 63, and a fourteenth connection electrode 64, the structures of the above are basically the same as those of the embodiment shown in FIG. 8, except that the thirteenth connection electrode 63 realizes the connection between the third connection electrode 53 and the third lateral connection line 83, and the fourteenth connection electrode 64 realizes the connection between the fifth connection electrode 55 of the current unit row and the third lateral connection line 83 of the previous unit row, thereby forming a third vertical connection line 93 extending along the second direction Y in the second circuit unit, and the third vertical connection line 93 is connected with the first node N1 of the pixel driving circuit in the second circuit unit.

[0331] In the example embodiment, since the thirteenth connection electrode 63 of the current unit row and the fourteenth connection electrode 64 of the next unit row are connected with the same third lateral connection line 83, not only the mutual connection of multiple third vertical connection lines 93 in one unit column is realized, but also the third lateral connection line 83 extending along the first direction X and the third vertical connection line 93 extending along the second direction Y form a third meshed communication structure, which is formed by the third conductive layer. Since the third connection electrode 53 in the third vertical connection line 93 is connected with the first power supply line formed subsequently, the third lateral connection line 83 extending along the first direction X and the first power supply line extending along the second direction Y form another third meshed communication structure, which is formed by the third conductive layer and the fourth conductive layer. In this way, both of the two third meshed communication structures are meshed structures for transmitting the first power supply signal, which can effectively reduce the resistance of the first power supply line, reduce the voltage drop of the first power supply signal, effectively improve the uniformity of the first power supply signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance.

[0332] In the exemplary embodiments, the present disclosure can transfer the static electricity of the longer signal line in the first conductive layer and the second conductive layer to the third conductive layer and discharge the static electricity from the third conductive layer by forming the plurality of third meshed communication structures in the second conductive layer and the third conductive layer to transmit the first power signal, effectively eliminating the accumulation of static electricity generated in the process, effectively avoiding the damage and short circuit of the transistor in the pixel driving circuit, and improving the product quality.

[0333] In the exemplary embodiments, the third vertical connection line 93 can extend to the binding area or the upper frame area and be connected with the power supply lead wire transmitting the first power signal, which can effectively prevent the occurrence of process static electricity. The present disclosure can make the static electricity be led out from the display area to the upper frame and the binding area through the meshed communication structure by setting the third vertical connection line to access the first power signal at the upper frame and the binding area, which can further eliminate the accumulation of static electricity generated in the process.

[0334] (36) The fifth insulating layer and the first planar layer pattern are formed, and the forming process and the formed fifth insulating layer and the first planar layer pattern are basically the same as those of the embodiment shown in FIG. 8, except that the twenty-second via hole V22 can be arranged in the first circuit unit and the second circuit unit, that is, the subsequently formed first power line is connected with the third connection electrode 53 in the first circuit unit and the second circuit unit, as shown in FIG. 28.

[0335] (37) The fourth conductive layer pattern is formed, and the forming process and the formed fourth conductive layer pattern are basically the same as those of the embodiment shown in FIG. 8, except that the fourth conductive layer of at least one second circuit unit can further include a power supply connection block 71-1, as shown in FIGS. 29A and 29B, wherein FIG. 29B is a plan view of the fourth conductive layer in FIG. 29A.

[0336] In the exemplary embodiments, the first power line 71 can be connected with the third connection electrode 53 in the first circuit unit and the second circuit unit through the twenty-second via hole V22.

[0337] In the exemplary embodiments, the power supply connection block 71-1 arranged in the second circuit unit can be in the shape of a block (such as a rectangle), which can be arranged between the first power line 71 and the data connection electrode 74, the first end of the power supply connection block 71-1 is connected with the data connection electrode 74, and the second end of the power supply connection block 71-1 is connected with the first power line 71.

[0338] In the exemplary embodiments, in at least one second circuit unit, the first power line 71, the power supply connection block 71-1, and the data connection electrode 74 can be an integrated structure connected with each other.

[0339] (38) The second planar layer and the fifth conductive layer pattern are sequentially formed, and the forming process and the formed second planar layer and the fifth conductive layer pattern are substantially the same as those of the embodiment shown in FIG. 8, as shown in FIG. 25.

[0340] In the example embodiment, the first vertical trace 110 in the second circuit unit is connected with the data connection electrode 74 through the via. Since the data connection electrode 74 is connected with the first power line 71 through the power connection block 71-1, the first vertical trace 110 and the first power line 71 have the same potential, which not only avoids floating of the first vertical trace 110, but also realizes that the first vertical trace 110 can write the first power signal to the first electrode of the fourth transistor T4 in the second circuit unit.

[0341] In the example embodiment, since the second vertical trace 120 is connected with the first vertical trace 110 through the trace connection line 120-1, the second vertical trace 120 and the first vertical trace 110 have the same potential. In this way, the first power line 71 extending along the second direction Y, the third vertical connection line 93, the first vertical trace 110 and the second vertical trace 120 form a vertical four-wire structure for transmitting the first power signal, which can further reduce the resistance of the first power signal line and reduce the voltage drop of the first power signal.

[0342] In the example embodiment, the horizontal double-wire structure of the horizontal power signal line 30 and the third horizontal connection line 83 and the vertical four-wire structure composed of the first power line 71, the third vertical connection line 93, the first vertical trace 110 and the second vertical trace 120 can constitute a plurality of third mesh communication structures, which can maximize the reduction of the resistance of the first power signal line and maximize the reduction of the voltage drop of the first power signal.

[0343] The example embodiment of the present disclosure provides a display substrate, by forming the third horizontal connection line extending along the first direction X and the third vertical connection line extending along the second direction Y in the display area, and the third horizontal connection line and the third vertical connection line form a mesh third mesh communication structure for transmitting the first power signal, which can effectively reduce the resistance of the first power signal line, reduce the voltage drop of the first power signal, effectively improve the uniformity of the first power signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance.

[0344] The example embodiment of the present disclosure forms a horizontal double-wire structure for transmitting the first power signal in the second conductive layer and the third conductive layer, forms a vertical four-wire structure for transmitting the first power signal in the third conductive layer, the fourth conductive layer and the fifth conductive layer respectively, and the horizontal double-wire structure and the vertical four-wire structure can constitute a plurality of third mesh communication structures, which can maximize the reduction of the resistance of the first power signal line and maximize the reduction of the voltage drop of the first power signal.

[0345] The third meshed communication structure for transmitting the first power signal can transfer and release the static electricity of the longer signal line in the first conductive layer and the second conductive layer to and from the third conductive layer, effectively eliminating the static electricity accumulation generated in the process, effectively avoiding the damage and short circuit of the transistor in the pixel driving circuit, and improving the product quality.

[0346] The second vertical wire of the second circuit unit is connected with the first power line, which can not only avoid the floating of the second vertical wire in the second circuit unit, but also effectively avoid the short circuit between the nodes in the pixel driving circuit.

[0347] FIG. 30 is a structural schematic diagram of another first display area according to an exemplary embodiment of the present disclosure. In the exemplary embodiment, the main structure of the display substrate of the present embodiment is basically the same as that of the aforementioned display substrate, except that the first meshed communication structure and the second meshed communication structure are formed on the display substrate at the same time.

[0348] As shown in FIG. 30, the driving structure layer of the first display area can further include at least one first horizontal connection line 81, at least one second horizontal connection line 82, at least one first vertical connection line 91, and at least one second vertical connection line 92. The first initial signal line 41 and the first vertical connection line 91 form a first meshed communication structure on the display substrate, the first horizontal connection line 81 and the first vertical connection line 91 form another first meshed communication structure on the display substrate, the second initial signal line 42 and the second vertical connection line 92 form a second meshed communication structure on the display substrate, and the second horizontal connection line 82 and the second vertical connection line 92 form another second meshed communication structure on the display substrate.

[0349] In the exemplary embodiment, the first horizontal connection line 81 and the second horizontal connection line 82 can be disposed in the same layer and formed synchronously by the same patterning process. In at least one unit row, the first horizontal connection line 81 and the second horizontal connection line 82 can be alternately disposed in the first direction X, and a first break K1 is disposed between adjacent first horizontal connection lines 81 and second horizontal connection lines 82 in the first direction X, which is configured to realize the mutual insulation between the first horizontal connection line 81 and the second horizontal connection line 82. For example, the first horizontal connection line 81 extending along the first direction X can be disposed in the N+1th unit column to the N+5th unit column, and the second horizontal connection line 82 extending along the first direction X can be disposed in the N+6th unit column to the N+10th unit column.

[0350] In the example embodiment, the first vertical connection lines 91 and the second vertical connection lines 92 can be arranged in the same layer and formed synchronously by the same patterning process. The first vertical connection lines 91 and the second vertical connection lines 92 can be arranged in different insertion unit columns respectively, and the first vertical connection lines 91 and the second vertical connection lines 92 can be arranged alternately in the first direction X. For example, the first vertical connection lines 91 extending along the second direction Y can be arranged in the N+1th unit column, and the second vertical connection lines 92 extending along the second direction Y can be arranged in the N+6th unit column.

[0351] In the example embodiment, the driving structure layer of the first display area can further include first vertical wires and second vertical wires, which can have substantially the same structure as the foregoing embodiments, and thus will not be described herein.

[0352] In the example embodiment, in the region of the N+1th to N+5th unit columns, the first initial signal lines 41 and the first horizontal connection lines 81 extending along the first direction X form horizontal double-line structures for transmitting the first initial signals, the first vertical connection lines 91, the first vertical wires and the second vertical wires extending along the second direction Y form vertical three-line structures for transmitting the first initial signals, and the horizontal double-line structures and the vertical three-line structures form a plurality of first meshed communication structures for transmitting the first initial signals in a meshed manner.

[0353] In the example embodiment, in the region of the N+6th to N+10th unit columns, the second initial signal lines 42 and the second horizontal connection lines 82 extending along the first direction X form horizontal double-line structures for transmitting the second initial signals, the second vertical connection lines 92, the first vertical wires and the second vertical wires extending along the second direction Y form vertical three-line structures for transmitting the second initial signals, and the horizontal double-line structures and the vertical three-line structures form a plurality of second meshed communication structures for transmitting the second initial signals in a meshed manner.

[0354] In an example embodiment, the first meshed communication structure and the second meshed communication structure can be arranged in units of repeating columns. For example, the first meshed communication structure can be arranged in repeating columns including the N+lth unit column to the N+5th unit column, the second meshed communication structure can be arranged in repeating columns including the N+6th unit column to the N+10th unit column, and the first meshed communication structure and the second meshed communication structure are arranged alternately in the first direction X. For another example, the first meshed communication structure can be arranged in repeating columns including the N+lth unit column to the N+5th unit column, the first meshed communication structure can be arranged in repeating columns including the N+6th unit column to the N+10th unit column, the second meshed communication structure can be arranged in repeating columns including the N+11th unit column to the N+15th unit column, and the second meshed communication structure can be arranged in repeating columns including the N+16th unit column to the N+20th unit column, and the first meshed communication structure, the first meshed communication structure, the second meshed communication structure, and the second meshed communication structure are arranged alternately in the first direction X, which is not limited in the present disclosure.

[0355] The present embodiment can effectively reduce the resistance of the first initial signal line and the second initial signal line, reduce signal voltage drop, effectively improve display uniformity, and improve display quality and display performance by forming the first meshed communication structure for transmitting the first initial signal and the second meshed communication structure for transmitting the second initial signal in the display area.

[0356] FIG. 31 is a structural schematic diagram of another first display area according to an example embodiment of the present disclosure. In an example embodiment, the main structure of the display substrate of the present embodiment is basically the same as that of the display substrate shown in FIG. 30, except that the first meshed communication structure and a third meshed communication structure are formed on the display substrate.

[0357] As shown in FIG. 31, the driving structure layer of the first display area can further include at least one first horizontal connection line 81, at least one third horizontal connection line 83, at least one first vertical connection line 91, and at least one third vertical connection line 93. The first initial signal line 41 and the first vertical connection line 91 form a first meshed communication structure on the display substrate, the first horizontal connection line 81 and the first vertical connection line 91 form another first meshed communication structure on the display substrate, the third horizontal connection line 83 and the first power supply line 71 form a third meshed communication structure on the display substrate, and the third horizontal connection line 83 and the third vertical connection line 93 form another third meshed communication structure on the display substrate.

[0358] In the example embodiment, the first lateral connection line 81 and the third lateral connection line 83 can be arranged in the same layer and formed synchronously by the same patterning process. In at least one unit row, the first lateral connection line 81 and the third lateral connection line 83 can be arranged alternately in the first direction X, and a first break K1 is arranged between adjacent first lateral connection lines 81 and third lateral connection lines 83 in the first direction X, and the first break K1 is configured to realize mutual insulation between the first lateral connection line 81 and the third lateral connection line 83. For example, the first lateral connection line 81 extending along the first direction X can be arranged in the N+1th unit column to the N+5th unit column, and the third lateral connection line 83 extending along the first direction X can be arranged in the N+6th unit column to the N+10th unit column.

[0359] In the example embodiment, the first vertical connection line 91 and the third vertical connection line 93 can be arranged in the same layer and formed synchronously by the same patterning process. The first vertical connection line 91 and the third vertical connection line 93 can be arranged in different insertion unit columns respectively, and the first vertical connection line 91 and the third vertical connection line 93 can be arranged alternately in the first direction X. For example, the first vertical connection line 91 extending along the second direction Y can be arranged in the N+1th unit column, and the third vertical connection line 93 extending along the second direction Y can be arranged in the N+6th unit column.

[0360] In the example embodiment, the driving structure layer of the first display area can further include a first vertical wire and a second vertical wire, and the structures thereof can be substantially the same as those of the foregoing embodiments, which will not be described herein again.

[0361] In the example embodiment, in the region of the N+1th unit column to the N+5th unit column, the first initial signal line 41 extending along the first direction X and the first lateral connection line 81 form a lateral double-line structure for transmitting the first initial signal, the first vertical connection line 91, the first vertical wire and the second vertical wire extending along the second direction Y form a vertical three-line structure for transmitting the first initial signal, and the lateral double-line structure and the vertical three-line structure form a plurality of first meshed communication structures for transmitting the first initial signal in a meshed manner.

[0362] In the example embodiment, in the region of the N+6th unit column to the N+10th unit column, the lateral power signal line 30 extending along the first direction X and the third lateral connection line 83 form a lateral double-line structure for transmitting the first power signal, the first power line 71, the third vertical connection line 93, the first vertical wire and the second vertical wire extending along the second direction Y form a vertical four-line structure for transmitting the first power signal, and the lateral double-line structure and the vertical four-line structure form a plurality of third meshed communication structures for transmitting the first power signal in a meshed manner.

[0363] In an example embodiment, the first meshed interconnection structure and the third meshed interconnection structure can be arranged in units of repeating columns. For example, the first meshed interconnection structure can be arranged in repeating columns including the N+lth unit column to the N+5th unit column, the third meshed interconnection structure can be arranged in repeating columns including the N+6th unit column to the N+10th unit column, and the first meshed interconnection structure and the third meshed interconnection structure are arranged alternately in the first direction X. For another example, the first meshed interconnection structure can be arranged in repeating columns including the N+lth unit column to the N+5th unit column, the first meshed interconnection structure can be arranged in repeating columns including the N+6th unit column to the N+10th unit column, the third meshed interconnection structure can be arranged in repeating columns including the N+11th unit column to the N+15th unit column, and the third meshed interconnection structure can be arranged in repeating columns including the N+16th unit column to the N+20th unit column, and the first meshed interconnection structure, the first meshed interconnection structure, the third meshed interconnection structure, and the third meshed interconnection structure are arranged alternately in the first direction X, which is not limited in the present disclosure.

[0364] The embodiment of the present disclosure can effectively reduce the resistance of the first initial signal line and the first power line, reduce the signal voltage drop, effectively improve the display uniformity, and improve the display quality and display performance by forming the first meshed interconnection structure for transmitting the first initial signal and the third meshed interconnection structure for transmitting the first power signal in the display area.

[0365] FIG. 32 is a structural schematic diagram of another first display area according to an example embodiment of the present disclosure. In an example embodiment, the main structure of the display substrate of the present embodiment is basically the same as that of the display substrate shown in FIG. 30, except that the second meshed interconnection structure and the third meshed interconnection structure are formed on the display substrate at the same time.

[0366] As shown in FIG. 32, the driving structure layer of the first display area can further include at least one second horizontal connection line 82, at least one third horizontal connection line 83, at least one second vertical connection line 92, and at least one third vertical connection line 93. The second initial signal line 42 and the second vertical connection line 92 form a second meshed interconnection structure on the display substrate, the second horizontal connection line 82 and the second vertical connection line 92 form another second meshed interconnection structure on the display substrate, the third horizontal connection line 83 and the first power line 71 form a third meshed interconnection structure on the display substrate, and the third horizontal connection line 83 and the third vertical connection line 93 form another third meshed interconnection structure on the display substrate.

[0367] In the example embodiment, the second lateral connection line 82 and the third lateral connection line 83 can be arranged in the same layer and formed synchronously by the same patterning process. In at least one unit row, the second lateral connection line 82 and the third lateral connection line 83 can be arranged alternately in the first direction X, and a first break K1 is arranged between adjacent second lateral connection line 82 and third lateral connection line 83 in the first direction X, and the first break K1 is configured to realize mutual insulation between the second lateral connection line 82 and the third lateral connection line 83. For example, the second lateral connection line 82 extending along the first direction X can be arranged in the N+1th unit column to the N+5th unit column, and the third lateral connection line 83 extending along the first direction X can be arranged in the N+6th unit column to the N+10th unit column.

[0368] In the example embodiment, the second vertical connection line 92 and the third vertical connection line 93 can be arranged in the same layer and formed synchronously by the same patterning process. The second vertical connection line 92 and the third vertical connection line 93 can be arranged in different insertion unit columns respectively, and the second vertical connection line 92 and the third vertical connection line 93 can be arranged alternately in the first direction X. For example, the second vertical connection line 92 extending along the second direction Y can be arranged in the N+1th unit column, and the third vertical connection line 93 extending along the second direction Y can be arranged in the N+6th unit column.

[0369] In the example embodiment, the driving structure layer of the first display area can further include a first vertical trace and a second vertical trace, which can have substantially the same structure as the foregoing embodiments, and will not be described herein.

[0370] In the example embodiment, in the region of the N+1th unit column to the N+5th unit column, the second initial signal line 42 extending along the first direction X and the second lateral connection line 82 form a lateral double-line structure for transmitting the second initial signal, the second vertical connection line 92 extending along the second direction Y, the first vertical trace and the second vertical trace form a vertical three-line structure for transmitting the second initial signal, and the lateral double-line structure and the vertical three-line structure form a plurality of second meshed communication structures for transmitting the second initial signal in a meshed manner.

[0371] In the example embodiment, in the region of the N+6th unit column to the N+10th unit column, the lateral power signal line 30 extending along the first direction X and the third lateral connection line 83 form a lateral double-line structure for transmitting the first power signal, the first power line 71 extending along the second direction Y, the third vertical connection line 93, the first vertical trace and the second vertical trace form a vertical four-line structure for transmitting the first power signal, and the lateral double-line structure and the vertical four-line structure form a plurality of third meshed communication structures for transmitting the first power signal in a meshed manner.

[0372] In an example embodiment, the second meshed communication structure and the third meshed communication structure can be arranged in units of repeating columns. For example, the second meshed communication structure can be arranged in repeating columns including the N+1th unit column to the N+5th unit column, the third meshed communication structure can be arranged in repeating columns including the N+6th unit column to the N+10th unit column, and the second meshed communication structure and the third meshed communication structure are arranged alternately in the first direction X. For another example, the second meshed communication structure can be arranged in repeating columns including the N+1th unit column to the N+5th unit column, the second meshed communication structure can be arranged in repeating columns including the N+6th unit column to the N+10th unit column, the third meshed communication structure can be arranged in repeating columns including the N+11th unit column to the N+15th unit column, the third meshed communication structure can be arranged in repeating columns including the N+16th unit column to the N+20th unit column, and the second meshed communication structure, the second meshed communication structure, the third meshed communication structure, and the third meshed communication structure are arranged alternately in the first direction X, which is not limited in the present disclosure.

[0373] The embodiment of the present disclosure can effectively reduce the resistance of the second initial signal line and the first power line, reduce the signal voltage drop, effectively improve the display uniformity, and improve the display quality and display performance by forming the second meshed communication structure for transmitting the second initial signal and the third meshed communication structure for transmitting the first power signal in the display area.

[0374] FIG. 33 is a structural schematic diagram of another first display area according to an example embodiment of the present disclosure. In an example embodiment, the main structure of the display substrate of the present embodiment is basically the same as the main structure of the display substrate shown in the foregoing, except that the first meshed communication structure, the second meshed communication structure, and the third meshed communication structure are formed on the display substrate at the same time.

[0375] As shown in FIG. 33, the driving structure layer of the first display area can further include at least one first horizontal connection line 81, at least one second horizontal connection line 82, at least one third horizontal connection line 83, at least one first vertical connection line 91, at least one second vertical connection line 92, and at least one third vertical connection line 93. The first initial signal line 41 and the first vertical connection line 91 form a first meshed communication structure on the display substrate, and the first horizontal connection line 81 and the first vertical connection line 91 form another first meshed communication structure on the display substrate. The second initial signal line 42 and the second vertical connection line 92 form a second meshed communication structure on the display substrate, and the second horizontal connection line 82 and the second vertical connection line 92 form another second meshed communication structure on the display substrate. The third horizontal connection line 83 and the first power line 71 form a third meshed communication structure on the display substrate, and the third horizontal connection line 83 and the third vertical connection line 93 form another third meshed communication structure on the display substrate.

[0376] In the example embodiment, the first, second and third lateral connection lines 81, 82 and 83 can be disposed in the same layer and formed synchronously by the same patterning process. In at least one unit row, the first, second and third lateral connection lines 81, 82 and 83 can be periodically arranged in the first direction X, and a first break K1 is disposed between adjacent first and second lateral connection lines 81 and 82 in the first direction X, a first break K1 is disposed between adjacent second and third lateral connection lines 82 and 83 in the first direction X, and a first break K1 is disposed between adjacent third and first lateral connection lines 83 and 81 in the first direction X, and the first break K1 is configured to realize mutual insulation between adjacent lateral connection lines. For example, the first lateral connection lines 81 extending along the first direction X can be disposed in the N+1th to N+5th unit columns, the second lateral connection lines 82 extending along the first direction X can be disposed in the N+6th to N+10th unit columns, and the third lateral connection lines 83 extending along the first direction X can be disposed in the N+11th to N+15th unit columns.

[0377] In the example embodiment, the first, second and third vertical connection lines 91, 92 and 93 can be disposed in the same layer and formed synchronously by the same patterning process. The first, second and third vertical connection lines 91, 92 and 93 can be respectively disposed in different insertion unit columns, and periodically arranged in the first direction X. For example, the first vertical connection lines 91 extending along the second direction Y can be disposed in the N+1th unit column, the second vertical connection lines 92 extending along the second direction Y can be disposed in the N+6th unit column, and the third vertical connection lines 93 extending along the second direction Y can be disposed in the N+11th unit column.

[0378] In the example embodiment, the driving structure layer of the first display area can further include first and second vertical wires, and the structures thereof can be substantially the same as those of the foregoing embodiments, which will not be described herein again.

[0379] In the example embodiment, in the region of the N+1th to N+5th unit columns, the first initial signal lines 41 and the first lateral connection lines 81 extending along the first direction X form a lateral double-line structure for transmitting the first initial signal, the first vertical connection lines 91, the first and second vertical wires extending along the second direction Y form a vertical three-line structure for transmitting the first initial signal, and the lateral double-line structure and the vertical three-line structure form a plurality of first meshed communication structures for transmitting the first initial signal in a meshed manner.

[0380] In the exemplary embodiment, in the region of the N+6th to N+10th unit columns, the second initial signal lines 42 and the second horizontal connection lines 82 extending along the first direction X form a horizontal double-line structure for transmitting the second initial signal, the second vertical connection lines 92, the first vertical traces and the second vertical traces extending along the second direction Y form a vertical three-line structure for transmitting the second initial signal, and the horizontal double-line structure and the vertical three-line structure form a plurality of second meshed communication structures for transmitting the second initial signal in a meshed manner.

[0381] In the exemplary embodiment, in the region of the N+11th to N+15th unit columns, the horizontal power signal lines 30 and the third horizontal connection lines 83 extending along the first direction X form a horizontal double-line structure for transmitting the first power signal, the first power lines 71, the third vertical connection lines 93, the first vertical traces and the second vertical traces extending along the second direction Y form a vertical four-line structure for transmitting the first power signal, and the horizontal double-line structure and the vertical four-line structure form a plurality of third meshed communication structures for transmitting the first power signal in a meshed manner.

[0382] In the exemplary embodiment, the first meshed communication structures, the second meshed communication structures and the third meshed communication structures can be arranged in units of repeating columns. For example, the first meshed communication structures can be arranged in the repeating columns including the N+1st to N+5th unit columns, the second meshed communication structures can be arranged in the repeating columns including the N+6th to N+10th unit columns, and the third meshed communication structures can be arranged in the repeating columns including the N+11th to N+15th unit columns, and the first meshed communication structures, the second meshed communication structures and the third meshed communication structures are periodically arranged along the first direction X, which is not limited in the present disclosure.

[0383] The embodiments of the present disclosure can effectively reduce the resistance of the first initial signal lines, the second initial signal lines and the first power lines, reduce the signal voltage drop, effectively improve the display uniformity, and improve the display quality and display performance by forming the first meshed communication structures for transmitting the first initial signal, the second meshed communication structures for transmitting the second initial signal and the third meshed communication structures for transmitting the first power signal in the display region.

[0384] The foregoing structures and the preparation process thereof are merely exemplary, and in the exemplary embodiment, the corresponding structures can be changed, and the patterning process can be increased or reduced according to actual needs.

[0385] In the exemplary embodiment, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as an OLED, a quantum dot display (QLED), a light-emitting diode display (Micro LED or Mini LED), a quantum dot light-emitting diode display (QDLED) and the like, which is not limited in the present disclosure.

[0386] The present disclosure also provides a preparation method of a display substrate for manufacturing the display substrate provided in the above embodiments. In an exemplary embodiment, the display substrate includes a first display area and a second display area, the first display area at least partially surrounds the second display area, the first display area is configured to display images, and the second display area is configured to display images and transmit light; the preparation method can include:

[0387] forming a driving structure layer on the substrate, and forming a light-emitting structure layer on the driving structure layer;

[0388] The driving structure layer of the first display area includes a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, and the light-emitting structure layer of the first display area includes a plurality of first light-emitting devices; the circuit units at least include first circuit units and second circuit units, the first circuit units and the second circuit units each include a pixel driving circuit, the pixel driving circuit of the first circuit units is connected with the first light-emitting devices, and the pixel driving circuit of the second circuit units is not connected with the first light-emitting devices; at least one second circuit unit further includes at least one horizontal connection line extending along a first direction and at least one vertical connection line extending along a second direction, the horizontal connection line is connected with the vertical connection line to form a meshed communication structure, and the first direction and the second direction intersect.

[0389] The present disclosure also provides a display device including the display substrate described above. The display device can be any product or component with display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc., and the embodiments of the present disclosure are not limited thereto.

[0390] Although the embodiments of the present disclosure are disclosed as above, it should be noted that the above embodiments are merely exemplary and not restrictive. Therefore, the present disclosure is not limited to what is specifically shown and described herein. Various modifications, substitutions, and omissions can be made to the embodiments without departing from the scope of the present disclosure.

Claims

1. A display substrate, comprising a first display area and a second display area, the first display area at least partially surrounding the second display area, the first display area being configured to display an image, and the second display area being configured to display an image and transmit light; the first display area comprising a driving structure layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate, the driving structure layer comprising a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, and the light-emitting structure layer comprising a plurality of first light-emitting devices; the circuit units at least comprising a first circuit unit and a second circuit unit, the first circuit unit and the second circuit unit each comprising a pixel driving circuit, the pixel driving circuit of the first circuit unit being connected to the first light-emitting device, and the pixel driving circuit of the second circuit unit not being connected to the first light-emitting device; at least one second circuit unit further comprising at least one horizontal connection line extending along a first direction and at least one vertical connection line extending along a second direction, the horizontal connection line being connected to the vertical connection line to form a meshed communication structure, and the first direction and the second direction intersecting. 2.The display substrate of claim 1, wherein, In at least one first circuit unit, the pixel driving circuit at least comprises a storage capacitor, a first reset transistor, a second reset transistor and a first light-emitting control transistor, a first electrode of the first reset transistor being connected to a first initial signal line through a fifth connection electrode, a second electrode of the first reset transistor being connected to a first electrode plate of the storage capacitor through a first connection electrode, a first electrode of the first light-emitting control transistor being connected to a second electrode plate of the storage capacitor through a third connection electrode, a first electrode of the second reset transistor being connected to a second initial signal line through a sixth connection electrode, the third connection electrode being connected to a first power supply line, and a plurality of the second electrode plates in at least one unit row forming a horizontal power supply signal line; in at least one second circuit unit, the vertical connection line comprises the first connection electrode, the third connection electrode and the fifth connection electrode, the first connection electrode being connected to the third connection electrode and the fifth connection electrode respectively, the third connection electrode being connected to the horizontal connection line of the present unit row, and the fifth connection electrode being connected to the horizontal connection line of the previous unit row. 3.The display substrate of claim 2, wherein, The at least one second circuit unit further comprises an eleventh connection electrode, a twelfth connection electrode, a thirteenth connection electrode and a fourteenth connection electrode; the eleventh connection electrode is arranged between and connected with the first connection electrode and the third connection electrode; the twelfth connection electrode is arranged between and connected with the first connection electrode and the fifth connection electrode; the thirteenth connection electrode is arranged between and connected with the third connection electrode and the transverse connection line of the unit row; and the fourteenth connection electrode is arranged between and connected with the fifth connection electrode and the transverse connection line of the previous unit row. 4.The display substrate of claim 2, wherein, The transverse connection line comprises a first transverse connection line, and the vertical connection line comprises a first vertical connection line; the fifth connection electrode in the first vertical connection line is connected with the first initial signal line; and the first initial signal line and the first transverse connection line form a transverse double-line structure for transmitting a first initial signal. 5.The display substrate of claim 4, wherein, In the at least one first circuit unit, the pixel driving circuit further comprises a data writing transistor, a second connection electrode, a data connection electrode and a data signal line; the second connection electrode is connected with a first electrode of the data writing transistor; the data connection electrode is connected with the second connection electrode; and the data signal line is connected with the data connection electrode; and in the at least one second circuit unit, the first data connection block is connected with the second connection electrode and the first initial signal line respectively. 6.The display substrate of claim 5, wherein, In the at least one second circuit unit, the first vertical wire is connected with the data connection electrode, and the second vertical wire is connected with the first vertical wire; the first vertical connection line, the first vertical wire and the second vertical wire form a vertical three-line structure for transmitting a first initial signal; and the transverse double-line structure and the vertical three-line structure form a plurality of first meshed communication structures. 7.The display substrate of claim 4, wherein, In the at least one second circuit unit, the third connection electrode is not connected with the first power supply line. 8.The display substrate of claim 2, wherein, The transverse connection line comprises a second transverse connection line, and the vertical connection line comprises a second vertical connection line; the at least one second circuit unit further comprises a fifteenth connection electrode arranged between and connected with the fifth connection electrode and the sixth connection electrode; and the second initial signal line and the second transverse connection line form a transverse double-line structure for transmitting a second initial signal. 9.The display substrate of claim 8, wherein, The pixel driving circuit in the at least one first circuit unit further comprises a data writing transistor, a second connection electrode, a data connection electrode, a data signal line, and a second data connection block, the second connection electrode is connected with a first electrode of the data writing transistor, the data connection electrode is connected with the second connection electrode, the data signal line is connected with the data connection electrode, and the second data connection block is connected with the sixth connection electrode; and the at least one second circuit unit further comprises a third data connection block, the third data connection block is connected with the second data connection block and the data connection electrode respectively. 10.The display substrate of claim 9, wherein, The at least one second circuit unit further comprises a first vertical wire and a second vertical wire, the first vertical wire is connected with the data connection electrode, and the second vertical wire is connected with the first vertical wire, the second vertical connection line, the first vertical wire, and the second vertical wire form a vertical three-wire structure for transmitting a second initial signal, and the horizontal double-wire structure and the vertical three-wire structure form a plurality of second meshed communication structures. 11.The display substrate of claim 8, wherein, In the at least one second circuit unit, the third connection electrode is not connected with the first power supply line, and the fifth connection electrode is not connected with the first initial signal line. 12.The display substrate of claim 2, wherein, The horizontal connection line comprises a third horizontal connection line, the vertical connection line comprises a third vertical connection line, the third connection electrode in the third vertical connection line is connected with the first power supply line, and the horizontal power supply signal line and the third horizontal connection line form a horizontal double-wire structure for transmitting a first power supply signal. 13.The display substrate of claim 12, wherein, The pixel driving circuit in the at least one first circuit unit further comprises a data writing transistor, a second connection electrode, a data connection electrode, and a data signal line, the second connection electrode is connected with a first electrode of the data writing transistor, the data connection electrode is connected with the second connection electrode, and the data signal line is connected with the data connection electrode; and the at least one second circuit unit further comprises a power supply connection block, the power supply connection block is connected with the data connection electrode and the first power supply line respectively. 14.The display substrate of claim 13, wherein, The at least one second circuit unit further comprises a first vertical wire and a second vertical wire, the first vertical wire is connected with the data connection electrode, and the second vertical wire is connected with the first vertical wire, the first power supply line, the third vertical connection line, the first vertical wire, and the second vertical wire form a vertical four-wire structure for transmitting a first power supply signal, and the horizontal double-wire structure and the vertical four-wire structure form a plurality of third meshed communication structures. 15.The display substrate of claim 12, wherein, In the at least one second circuit unit, the fifth connection electrode is not connected with the first initial signal line. 16.The display substrate according to any one of claims 1 to 15, wherein The horizontal connection line comprises a first horizontal connection line, a second horizontal connection line, and / or a third horizontal connection line, the vertical connection line comprises a first vertical connection line, a second vertical connection line, and / or a third vertical connection line, and the meshed communication structure comprises a first meshed communication structure, a second meshed communication structure, and / or a third meshed communication structure.

17. A display device comprising the display substrate according to any one of claims 1 to 16. 18.A method for manufacturing a display substrate, the display substrate comprising a first display area and a second display area, the first display area at least partially surrounding the second display area, the first display area configured to display an image, and the second display area configured to display an image and transmit light; the method comprising: forming a driving structure layer on a base, and forming a light-emitting structure layer on the driving structure layer; the driving structure layer of the first display area comprises a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, and the light-emitting structure layer of the first display area comprises a plurality of first light-emitting devices; the circuit units at least comprise a first circuit unit and a second circuit unit, the first circuit unit and the second circuit unit each comprise a pixel driving circuit, the pixel driving circuit of the first circuit unit is connected with the first light-emitting device, and the pixel driving circuit of the second circuit unit is not connected with the first light-emitting device; at least one second circuit unit further comprises at least one horizontal connection line extending along a first direction and at least one vertical connection line extending along a second direction, the horizontal connection line is connected with the vertical connection line to form a meshed communication structure, and the first direction and the second direction intersect.

Images