Array substrate, manufacturing method therefor, display panel and display apparatus

Abstract

An array substrate. The array substrate comprises a substrate, a heating electrode disposed on one side of the substrate, a first insulating layer and a second insulating layer, the substrate comprising a first region and a second region; the orthographic projection of the heating electrode on the substrate is located in the first region and does not coincide with the second region; the first insulating layer is disposed on the side of the heating electrode close to the substrate and is in contact with the heating electrode; the second insulating layer is disposed on the side of the heating electrode away from the substrate and is in contact with the heating electrode; the thickness of at least one of the first insulating layer and the second insulating layer in the first region is greater than the thickness thereof in the second region.

Description

Array substrate, preparation method thereof, display panel and display device

[0001] This application claims priority to Chinese Patent Application No. 202411393291.5, filed on September 30, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure relates to the technical field of display, and in particular, to an array substrate, a preparation method thereof, a display panel and a display device. BACKGROUND

[0003] With the continuous development of display technology, display devices have been widely applied (such as vehicle-mounted display panels). Common display devices include liquid crystal display devices (LCD). A liquid crystal display device can include an array substrate, a color film substrate, and a liquid crystal layer between the array substrate and the color film substrate. The liquid crystal display device drives the rotation of liquid crystal molecules in the liquid crystal layer by applying an electric field to the liquid crystal layer between the array substrate and the color film substrate, to change the orientation of the liquid crystal molecules in the liquid crystal layer, and then adjust the light transmittance of the liquid crystal layer. In the case of low temperature (such as below -20℃), the viscosity of the liquid crystal molecules in the liquid crystal layer increases, which results in slow response speed of the liquid crystal display panel, and may cause problems such as ghosting when switching display pictures or playing videos. In the case of lower temperature (such as below -30℃), the liquid crystal molecules in the liquid crystal layer may crystallize, resulting in the display panel being unable to display normally. How to improve the reliability of the liquid crystal display panel working in a low temperature environment is an important problem to be solved for the liquid crystal display device at present. SUMMARY

[0004] In one aspect, an array substrate is provided. The array substrate includes a substrate, a heating electrode disposed on one side of the substrate, a first insulating layer, and a second insulating layer. The substrate includes a first region and a second region. A projection of the heating electrode on the substrate is located in the first region and does not overlap with the second region. The first insulating layer is disposed on a side of the heating electrode close to the substrate and in contact with the heating electrode. The second insulating layer is disposed on a side of the heating electrode away from the substrate and in contact with the heating electrode. At least one of the first insulating layer and the second insulating layer has a thickness in the first region greater than a thickness in the second region.

[0005] In some embodiments, a projection of the first insulating layer onto the substrate is located in the first region and does not overlap the second region. A projection of the second insulating layer onto the substrate is located in the first region and the second region, and a thickness of the second insulating layer in the first region is equal to a thickness of the second insulating layer in the second region.

[0006] In some embodiments, the first insulating layer includes a first sub-portion and a second sub-portion. A projection of the first sub-portion onto the substrate is located in the first region and covers a projection of the heating electrode onto the substrate. A projection of the second sub-portion onto the substrate is located in the second region and does not overlap a projection of the heating electrode onto the substrate. A thickness of the first sub-portion is greater than a thickness of the second sub-portion. A projection of the second insulating layer onto the substrate is located in the first region and the second region, and a thickness of the second insulating layer in the first region is equal to a thickness of the second insulating layer in the second region.

[0007] In some embodiments, in a cross section of the first insulating layer and the heating electrode perpendicular to an extending direction of the heating electrode, the first insulating layer includes a trapezoid located in a first region, a boundary of the heating electrode is close to the substrate, and a boundary of the trapezoid is located in a range away from the substrate.

[0008] In some embodiments, the first insulating layer includes a first sub-portion and a second sub-portion. A projection of the first sub-portion onto the substrate is located in the first region and covers a projection of the heating electrode onto the substrate. A projection of the second sub-portion onto the substrate is located in the second region and does not overlap a projection of the heating electrode onto the substrate. A thickness of the first sub-portion is greater than a thickness of the second sub-portion. A projection of the second insulating layer onto the substrate is located in the first region and does not overlap the second region.

[0009] In some embodiments, a thickness of the first sub-portion is H1, a thickness of the second sub-portion is H2,

[0010] In some embodiments, the array substrate further comprises a thin film transistor. The thin film transistor is disposed between the substrate and the first insulating layer, and comprises a gate, a semiconductor pattern, a source pattern and a drain pattern. The semiconductor pattern is disposed on a side of the gate away from the substrate, the source pattern and the drain pattern are disposed on a side of the semiconductor pattern away from the substrate, and the source pattern and the drain pattern have a space therebetween. The second sub-portion covers a projection of the thin film transistor on the substrate. A portion of the second sub-portion is between the source pattern and the drain pattern, and contacts the semiconductor pattern.

[0011] In some embodiments, a projection of the first insulating layer on the substrate is located in the first region and does not overlap the second region. A projection of the second insulating layer on the substrate is located in the first region and does not overlap the second region.

[0012] In some embodiments, an included angle between a sidewall of the first insulating layer and a reference surface is less than or equal to 50°; the reference surface is parallel to the substrate.

[0013] In some embodiments, a projection of the first insulating layer on the substrate is located in the first region and does not overlap the second region. A projection of the second insulating layer on the substrate is located in the first region and does not overlap the second region.

[0014] In some embodiments, the second insulating layer covers a surface of the heating electrode away from the substrate and a sidewall of the heating electrode.

[0015] In some embodiments, a surface of the heating electrode contacting the first insulating layer is a first surface, a surface of the first insulating layer contacting the heating electrode is a second surface, the first surface is located in the second surface, and a boundary of the first surface has a space from a boundary of the second surface.

[0016] In some embodiments, in a projection of the second insulating layer and the heating electrode on the substrate, the second insulating layer covers the heating electrode, and a first space between a boundary of the second insulating layer and a boundary of the heating electrode is greater than or equal to 0.5 μm.

[0017] In some embodiments, an included angle between a sidewall of the second insulating layer and a reference surface is less than or equal to 50°; the reference surface is parallel to the substrate.

[0018] In some embodiments, the second insulating layer is proximate to a boundary of the surface of the substrate, and coincides with a boundary of the first insulating layer distal to the surface of the substrate.

[0019] In some embodiments, the heating electrode comprises a first electrode, a second electrode and a plurality of auxiliary electrodes. The first electrode extends along a first direction and comprises a first end and a second end. The second electrode extends along the first direction and is arranged side by side with the first electrode. The second electrode comprises a third end on the same side as the first end and a fourth end on the same side as the second end. The first end and the third end are electrically connected to a power supply of different polarity, and the second end is electrically connected to the fourth end. The plurality of auxiliary electrodes are arranged between the first electrode and the second electrode and are spaced apart along the first direction. The two ends of the auxiliary electrodes are respectively connected to the first electrode and the second electrode. The resistance of the plurality of auxiliary electrodes gradually decreases in a direction away from the first end and the third end.

[0020] In some embodiments, the plurality of auxiliary electrodes comprise the same material and are arranged in the same layer as the first electrode and the second electrode. The line width of the plurality of auxiliary electrodes gradually decreases in a direction away from the first end and the third end.

[0021] In some embodiments, the plurality of auxiliary electrodes are equally spaced apart along the first direction.

[0022] In some embodiments, the array substrate further comprises a plurality of data signal lines. The plurality of data signal lines are spaced apart along the first direction and each extends along a second direction. The auxiliary electrode has a projection on the substrate that at least partially overlaps with a projection of the data signal line on the substrate. The second direction intersects the first direction.

[0023] In some embodiments, the distance between two adjacent auxiliary electrodes is D1, the distance between two adjacent data signal lines is D2, and D1 = N x D2, where N is a positive integer.

[0024] In some embodiments, the first electrode and the second electrode each comprise an electrode trace that extends along the first direction.

[0025] In some embodiments, the first electrode and the second electrode each comprise a plurality of electrode traces arranged in parallel. The plurality of electrode traces are spaced apart along a second direction and each extends along the first direction. The ends of the plurality of electrode traces along the first direction are connected to each other. The plurality of auxiliary electrodes are connected to the two electrode traces that are closest to the first electrode and the second electrode, respectively.

[0026] In some embodiments, the first electrode and the second electrode each comprise a plurality of electrode traces arranged in parallel, the plurality of electrode traces are spaced apart along a second direction and each extend along the first direction, and ends of the plurality of electrode traces along the first direction are connected to each other. The auxiliary electrode is electrically connected to a number of the electrode traces belonging to the first electrode and the second electrode respectively.

[0027] In another aspect, a method for manufacturing an array substrate is provided. The method includes forming a first insulating layer on one side of a substrate. A heating electrode is formed on a side of the first insulating layer distal to the substrate; the substrate comprises a first region and a second region, a footprint of the heating electrode on the substrate is located within the first region and does not overlap with the second region. A second insulating layer is formed on a side of the heating electrode distal to the substrate. At least one of the first insulating layer and the second insulating layer is subjected to a patterning process, so that the one or both of the first insulating layer and the second insulating layer subjected to the patterning process has a thickness within the first region greater than a thickness within the second region.

[0028] In some embodiments, the patterning process on at least one of the first insulating layer and the second insulating layer comprises patterning the first insulating layer after the heating electrode is formed and before the second insulating layer is formed. The method includes forming a first insulating layer on one side of a substrate; a footprint of the first insulating layer on the substrate is located within the first region and the second region. A conductive layer is formed on a side of the first insulating layer distal to the substrate; a footprint of the conductive layer on the substrate covers the first region and the second region. A first mask layer is formed on a side of the conductive layer distal to the substrate; a footprint of the first mask layer on the substrate covers the first region and exposes the second region. The conductive layer is subjected to a patterning process with the first mask layer as a mask to remove a portion of the conductive layer located within the second region, forming the heating electrode. The first insulating layer is subjected to a patterning process with the first mask layer as a mask, so that the first insulating layer has a thickness within the first region greater than a thickness within the second region. A second insulating layer is formed on a side of the heating electrode distal to the substrate; a footprint of the second insulating layer on the substrate is located within the first region and the second region, and the second insulating layer has a thickness within the first region equal to a thickness within the second region.

[0029] In some embodiments, the patterning at least one of the first insulating layer and the second insulating layer comprises: patterning the second insulating layer after the second insulating layer is formed. The preparation method comprises: forming the first insulating layer on one side of the substrate; a footprint of the first insulating layer on the substrate is located in the first region and the second region. Forming the heating electrode on a side of the first insulating layer away from the substrate; a footprint of the heating electrode on the substrate covers the first region and does not overlap with the second region. Forming the second insulating layer on a side of the heating electrode and the first insulating layer away from the substrate. Forming the second mask layer on a side of the second insulating layer away from the substrate; a footprint of the second mask layer on the substrate is located in the first region and covers the footprint of the heating electrode on the substrate, a boundary of the footprint of the second mask layer on the substrate has a spacing with a boundary of the footprint of the heating electrode on the substrate. Patterning the second insulating layer using the second mask layer as a mask, removing a region of the second insulating layer not covered by the second mask layer, and the second insulating layer covers a surface of the heating electrode away from the substrate and a sidewall of the heating electrode.

[0030] In some embodiments, the forming the heating electrode on a side of the first insulating layer away from the substrate comprises: forming a conductive layer on a side of the first insulating layer away from the substrate. Forming a first mask layer on a side of the conductive layer away from the substrate using a metal mask plate. Patterning the conductive layer using the first mask layer as a mask to form the heating electrode. The forming the second mask layer on a side of the second insulating layer away from the substrate comprises: forming a photoresist layer on a side of the second insulating layer away from the substrate; a footprint of the photoresist layer on the substrate covers the first region and the second region. Performing a weak exposure process on the photoresist layer using the metal mask plate. Developing the photoresist layer to form the second mask layer.

[0031] In some embodiments, after the patterning of the second insulating layer, the preparation method further comprises: patterning the first mask layer using the second mask layer as a mask.

[0032] In some embodiments, before the patterning of the first insulating layer, the first insulating layer comprises a first sub-portion and a third sub-portion, a footprint of the first sub-portion on the substrate is located in the first region, and a footprint of the third sub-portion on the substrate is located in the second region. The patterning of the first insulating layer comprises: removing the third sub-portion; a footprint of the first insulating layer on the substrate does not overlap with the second region.

[0033] In some embodiments, before the first insulating layer is patterned, the first insulating layer includes a third sub-portion, a projection of the third sub-portion on the substrate is located in the second region. The patterning of the first insulating layer according to the second mask layer includes: removing part of the third sub-portion, and retaining part of the third sub-portion to form a second sub-portion.

[0034] In another aspect, a display panel is provided. The display panel includes the array substrate described in any of the above embodiments, and a color film substrate and a liquid crystal layer. The color film substrate is arranged opposite to the array substrate, and the liquid crystal layer is arranged between the array substrate and the color film substrate.

[0035] In yet another aspect, a display device is provided. The display device includes the display panel described above, and a backlight module. The backlight module is arranged on a light-out side of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings needed to be used in some embodiments of the present disclosure. Obviously, the drawings described in the following description are only the drawings of some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual time sequence, etc. of the products involved in the embodiments of the present disclosure.

[0037] FIG. 1 is a structural diagram of a display device according to some embodiments;

[0038] FIG. 2 is a structural diagram of a display panel according to some embodiments;

[0039] FIG. 3 is a planar structural layout of an array substrate according to some embodiments;

[0040] FIG. 4 is a structural diagram of an array substrate according to some embodiments;

[0041] FIG. 5 is another structural diagram of an array substrate according to some embodiments;

[0042] FIG. 6 is yet another structural diagram of an array substrate according to some embodiments;

[0043] FIG. 7 is yet another structural diagram of an array substrate according to some embodiments;

[0044] FIG. 8 is yet another structural diagram of an array substrate according to some embodiments;

[0045] FIG. 9 is another planar structural diagram of an array substrate according to some embodiments;

[0046] FIG. 10 is another plan view of an array substrate according to some embodiments;

[0047] FIG. 11 is an equivalent circuit diagram of an array substrate according to some embodiments;

[0048] FIG. 12 to FIG. 24 are another plan view of an array substrate according to some embodiments;

[0049] FIG. 25 to FIG. 37 are process step diagrams of an array substrate according to some embodiments. DETAILED DESCRIPTION

[0050] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings. It should be apparent that the described embodiments are only a part of the embodiments of the present disclosure, and not all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0051] Unless otherwise required by context, the term “comprise” and other forms of the term “comprise”, such as “comprises” and “comprising”, are used in an open, inclusive sense, that is, as “including, but not limited to”. In the description of the specification, the terms “one embodiment”, “some embodiments”, “exemplary embodiments”, “example”, “specific example” or “some examples” are intended to mean that a particular feature, structure, material, or characteristic included in at least one embodiment or example of the present disclosure. The illustrative representation of the above terms does not necessarily mean the same embodiment or example. In addition, the specific features, structures, materials or characteristics described can be included in any one or more embodiments or examples in any appropriate manner.

[0052] Hereinafter, the terms “first” and “second” are used only for descriptive purposes, and cannot be understood to indicate or imply relative importance or implicitly indicate the number of indicated technical features. Therefore, the features defined with “first” and “second” can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise stated, the meaning of “a plurality of” is two or more.

[0053] In describing some embodiments, "connected" and "coupled" and their derivatives can be used. Connect can be used to indicate that two members are in direct contact and coupled can be used to indicate that two members are in either direct or indirect contact. The use of "connected" and "coupled" herein, and in the following claims is not limited to direct or physical connections, but can include an electrical connection, whether direct or indirect; and it can include use of different methods to connect or couple devices. The embodiments disclosed herein are not intended to be limited to content described herein.

[0054] "at least one of A, B, and C" has the same meaning as "at least one of A, B, or C" and includes the following combinations: only A, only B, only C, A and B, A and C, B and C, and A and B and C.

[0055] "A and / or B" includes the following combinations: A alone, B alone, and A and B together.

[0056] The use of "adapted to" or "configured to" herein is meant as open and inclusive language that does not foreclose devices adapted to or configured to perform additional tasks or steps. Additionally, the use of "based on" is meant to be open and inclusive, in that a process, step, calculation, or other action "based on" one or more recited conditions or values may, in practice, be based on additional conditions or values beyond those recited.

[0057] As used herein, "about," "substantially," or "approximately" refers to the recited value and to values within an acceptable range of deviation of the recited value, as determined by one of ordinary skill in the art considering the measurement in question and the error intended to be introduced to the particular quantity being measured.

[0058] As used herein, "parallel," "perpendicular," and "equal" include the recited condition and conditions that are approximately the recited condition, where the range of approximation is within an acceptable range of deviation, as determined by one of ordinary skill in the art considering the measurement in question and the error intended to be introduced to the particular quantity being measured. For example, "parallel" includes absolute parallel and near parallel, where the acceptable range of deviation for near parallel can be, for example, within 5°; "perpendicular" includes absolute perpendicular and near perpendicular, where the acceptable range of deviation for near perpendicular can also be, for example, within 5°. "Equal" includes absolute equality and near equality, where the acceptable range of deviation for near equality can be, for example, a difference between the two that is less than or equal to 5% of either.

[0059] It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate or intervening layers can also be present.

[0060] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are schematic and are not intended to be as actual views of individual layers and regions of devices and structures. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of exemplary embodiments.

[0061] Referring to FIG. 1, embodiments of the disclosure provide a display device, and the display device 1000 is a product having an image display function. Exemplarily, the display device 1000 can be any device displaying whether moving (e.g., video) or fixed (e.g., still image) and whether text or image.

[0062] Exemplarily, the display device 1000 can be any product or component having a display function, such as a television, a notebook computer, a tablet computer, a personal digital assistant (PDA), a mobile phone (cell phone), a watch, a clock, a calculator, a GPS receiver / navigator, a camera, a display panel of a camera view (e.g., a display panel of a rearview camera in a vehicle), a wearable device, an augmented reality (AR) device, a virtual reality (VR) device, a mixed reality (MR) device, an in-vehicle display panel, a flight display panel, and the like.

[0063] In some embodiments, the display device 1000 can be a liquid crystal display (LCD) in terms of a light emitting type of the display device 1000. The display device 1000 can be a flat display device or a curved display device, and the like in terms of a form of the display device 1000. The display device 1000 can be rectangular, circular, or any other shape in terms of a shape of the display device 1000. Hereinafter, some embodiments of the disclosure will be schematically described by taking a rectangular and flat liquid crystal display device as an example, but embodiments of the disclosure are not limited thereto, and any other display device can be considered as long as the same technical idea is applied.

[0064] In some embodiments, the display device 1000 can include a display panel 1100 (may also be referred to as a display panel) and a driving circuit board (not shown in the figure). The driving circuit board may, for example, include a timing controller (TCON), a power management chip (DC / DC), and an adjustable resistance voltage dividing circuit (generating Vcom), and the like driving circuit, and the driving circuit board can also include other circuit structures, which are not listed one by one here. The driving circuit board is electrically connected with the display panel 1100, for transmitting control signals to the display panel 1100, and then driving the display panel 1100 to realize image display. In addition, the display device 1000 can also include other structures, such as the display device 1000 can also include touch structure, under-screen camera, and under-screen fingerprint recognition sensor, etc., so that the display device 1000 can realize touch, shooting, video recording or fingerprint recognition and other different functions, and other structures of the display device 1000 are not listed one by one here.

[0065] Referring to FIG. 2, in the case of a liquid crystal display device, the display device 1000 can also include a backlight module 1200 disposed on the backlight side of the display panel 1100. Exemplarily, the backlight module 1200 can be a direct backlight module or a side-in backlight module, etc., and the backlight module 1200 is used to provide a light source for the display panel 1100. The display panel 1100 includes a plurality of sub-pixels, and the amount of light passing through the display panel 1100 can be adjusted for each sub-pixel, so that each sub-pixel displays the same or different gray scale to achieve the purpose of image display.

[0066] Continuing to refer to FIG. 2, in the case of a liquid crystal display panel, the display panel 1100 can include an array substrate 100 and a color film substrate 200 disposed opposite each other, and a liquid crystal layer 300 disposed between the array substrate 100 and the color film substrate 200, wherein the color film substrate 200 can also be referred to as a counter substrate or an encapsulation substrate. Of course, the structure of the display panel 1100 is not limited to this, and the display panel 1100 can also include other structures as long as the same technical idea is adopted. For example, the display panel 1100 can also include a first alignment film (not shown in the figure) disposed on the side of the array substrate 100 close to the liquid crystal layer 300, and a second alignment film (not shown in the figure) disposed on the side of the color film substrate 200 close to the liquid crystal layer 300, etc.

[0067] The color film substrate 200 can include a filter portion and a black matrix. The filter portion is configured to filter light incident on the color film substrate 200, so that each sub-pixel emits light of one color (such as red, green, or blue). Different sub-pixels can emit light of the same or different colors, so that the display panel 1100 can realize color display. The black matrix is configured to cover the transistors and signal lines on the array substrate, so as to improve the contrast of the display panel.

[0068] The liquid crystal layer 300 includes liquid crystal molecules. The liquid crystal molecules have the characteristics of high viscosity and easy crystallization at low temperatures (such as below -20°C). Generally, a liquid crystal display panel can only work normally in an ambient temperature range of -20°C to +70°C. If the working ambient temperature of the liquid crystal display panel is lower than -20°C, the display panel may have problems such as long response time (slow response speed), ghosting when switching display screens or playing videos or animations, and even crystallization of the liquid crystal molecules, which may cause the display panel to fail to display normally. However, in some fields such as vehicle display and aerospace military, the working ambient temperature of the liquid crystal display panel may be lower than -20°C, for example, -30°C, -40°C, -45°C, and the like. Therefore, it is a research focus of the liquid crystal display panel to expand the working temperature range of the liquid crystal display panel and enable the liquid crystal display panel to work normally in a lower temperature environment.

[0069] The related art provides a liquid crystal display panel that can be heated and can heat the liquid crystal display panel in a low-temperature environment. The liquid crystal display panel includes a heating plate attached to the outside of the liquid crystal display panel. The heating plate transmits heat to the liquid crystal layer through the air and the array substrate in sequence. However, the heat conduction process is slow and energy-consuming, the heating efficiency is low, and the energy consumption is high.

[0070] To solve at least one of the above technical problems, with reference to FIGS. 3 and 4, some embodiments of the present disclosure provide an array substrate 100. The array substrate 100 includes a substrate 10, a heating electrode 20 disposed on one side of the substrate 10, a first insulating layer 30, and a second insulating layer 40. The heating electrode 20 is configured to generate heat when working, so as to heat the array substrate 100 and further heat the liquid crystal molecules in the liquid crystal layer. In this way, the heating electrode 20 can be integrated in the array substrate 100, the heat transmission path can be shortened, the heating efficiency of the array substrate and the display panel can be improved, and the heat loss of the heating electrode 20 can be reduced, thereby reducing the power consumption of the heating electrode 20.

[0071] In addition, the substrate 10 includes a first region 11 and a second region 12, and a positive projection of the heating electrode 20 on the substrate 10 is located in the first region 11 and does not overlap the second region 12. In other words, the first region 11 and the second region 12 on the substrate 10 can be defined by the positive projection of the heating electrode 20 on the substrate 10, for example, the positive projection of the heating electrode 20 on the substrate 10 occupies the first region 11, and of course, the range of the first region 11 can be slightly larger than the positive projection of the heating electrode 20 on the substrate 10. The regions of the substrate 10 other than the first region 11 are the second region 12.

[0072] The first insulating layer 30 is arranged on the side of the heating electrode 20 close to the substrate 10 and in contact with the heating electrode 20, and the second insulating layer 40 is arranged on the side of the heating electrode 20 away from the substrate 10 and in contact with the heating electrode 20. That is, the first insulating layer 30 and the second insulating layer 40 are respectively the insulating layers in direct contact with the heating electrode 20 on both sides of the heating electrode 20. The first insulating layer 30 and the second insulating layer 40 can cover the heating electrode 20 to avoid short circuit between the heating electrode 20 and other conductive structures (such as data signal lines DL, gate lines GL, pixel electrodes 52 and common electrodes 51) of the array substrate 100.

[0073] Exemplarily, the first insulating layer 30 and the second insulating layer 40 can both be inorganic insulating layers, which can be, for example, a passivation layer PVX. The materials of the first insulating layer 30 and the second insulating layer 40 can include any one of inorganic insulating materials such as silicon nitride (SiNx, x>0), silicon oxynitride (SiON) and silicon oxide (SiOx, x>0), and can also include a single-layer or multi-layer structure containing the above inorganic insulating materials. The materials of the first insulating layer 30 and the second insulating layer 40 can be the same or different. In addition, the thickness of the first insulating layer 30 and the second insulating layer 40 can be, for example, 100-1000 nm. For example, the thickness of the first insulating layer 30 and the second insulating layer 40 can be, for example, 100-1000 nm. Or and so on, and the embodiments of the present disclosure will not list them one by one. Among them, the thickness of the first insulating layer 30 and the second insulating layer 40 can be equal or different, which will not be listed one by one here.

[0074] The applicant has found that the shrinkage stress of the first insulating layer 30 and the second insulating layer 40 is large, which may cause the shrinkage stress of the array substrate 100 to be large. For example, after the array substrate 100 undergoes an annealing process, a large deviation in the critical dimension (Total Pitch; TP for short) of the conductive layer in the array substrate 100 may occur. The TP can be used to measure the precision of a pattern formed on a substrate. That is, there is a large difference between the TP design layout of the conductive layer in the array substrate 100 and the actual TP (Final TP) layout of the conductive layer finally formed in the array substrate. Moreover, due to the large shrinkage stress on the array substrate, the risk of warping of the four corners of the array substrate is large.

[0075] To overcome the above technical problems, in the embodiments of the present disclosure, as shown in FIGS. 4-8, the thickness of at least one of the first insulating layer 30 and the second insulating layer 40 in the first region 11 is greater than the thickness in the second region 12. That is, the thickness of at least one of the first insulating layer 30 and the second insulating layer 40 in the portion of the orthographic projection on the substrate 10 located in the first region 11 is greater than the thickness of the portion of the orthographic projection on the substrate 10 located in the second region 12. In this way, at least one of the first insulating layer 30 and the second insulating layer 40 does not uniformly extend over the entire array substrate 100. For example, the portion of the first insulating layer 30 and / or the second insulating layer 40 whose orthographic projection on the substrate 10 does not cover the heating electrode 20 can be thinned or removed by a patterning process such as etching. In this way, the thickness of the first insulating layer 30 and / or the second insulating layer 40 in the region (second region 12) outside the heating electrode 20 as a whole can be reduced, thereby reducing the shrinkage stress generated by the first insulating layer 30 and the second insulating layer 40, which is conducive to reducing the Final TP deviation of the array substrate 100 after the annealing process, and is also conducive to reducing the risk of warping of the array substrate 100. In addition, since the thickness of the first insulating layer 30 and / or the second insulating layer 40 in the second region 12 is reduced, the depth of the first via V1 can be reduced, thereby reducing the etching time of the first via V1 and reducing the size (area of the orthographic projection on the substrate 10) of the first via V1. In this way, it is conducive to improving the aperture ratio of the array substrate 100, thereby improving the light extraction efficiency of the array substrate 100.

[0076] In embodiments of the present disclosure, when describing the "portion of the first insulating layer 30 (or the second insulating layer 40) in the first region 11 (or the second region 12)", it refers to the portion of the first insulating layer 30 (or the second insulating layer 40) whose orthogonal projection on the substrate 10 is located in the first region 11. Similarly, when describing the "thickness of the first insulating layer 30 (or the second insulating layer 40) in the first region 11 (or the second region 12)", it refers to the thickness of the portion of the first insulating layer 30 (or the second insulating layer 40) whose orthogonal projection on the substrate 10 is located in the first region 11.

[0077] In addition, in embodiments of the present disclosure, when describing the thickness of a film layer, it refers to the thickness of the film layer at the position where the surface on which the film layer is located is parallel to the substrate; at this time, the film layer is neither at the position of a via nor on a surface that is undulating. That is, the thickness of the film layer at the position of a via and at the position of an undulating surface can vary, for example, at the position of a via of the film layer, the film layer is completely removed so the thickness is 0, and at the position of an undulating surface, the thickness can be smaller or larger. For example, as shown in FIG. 4, when describing the thickness of the second insulating layer 40 in the first region 11, it can refer to the dimension of the portion of the second insulating layer 40 that is in contact with the upper surface of the heating electrode 20 in the direction perpendicular to the substrate 10. For example, when describing the thickness of the second insulating layer 40 in the second region 12, it cannot refer to the thickness of the second insulating layer 40 at the first via V1. For another example, the portion of the second insulating layer 40 that is in contact with the sidewall of the first insulating layer 30 is on an undulating surface (a surface that is not parallel to the substrate 10), and the dimension of the second insulating layer 40 at this position in the direction perpendicular to the surface on which it is located will be smaller (compared to the thickness of the portion of the second insulating layer 40 that is in contact with the upper surface of the heating electrode 20).

[0078] In some embodiments, the thickness of the first insulating layer 30 in the first region 11 can be greater than the thickness of the first insulating layer 30 in the second region 12, and the thickness of the second insulating layer 40 in the first region 11 can be equal to the thickness of the second insulating layer 40 in the second region 12 (as shown in FIGS. 4 and 5). Alternatively, the thickness of the first insulating layer 30 in the first region 11 can be greater than the thickness of the first insulating layer 30 in the second region 12, and the thickness of the second insulating layer 40 in the first region 11 can be greater than the thickness of the second insulating layer 40 in the second region 12 (as shown in FIGS. 6 and 7). Alternatively, the thickness of the first insulating layer 30 in the first region 11 can be equal to the thickness of the first insulating layer 30 in the second region 12, and the thickness of the second insulating layer 40 in the first region 11 can be greater than the thickness of the second insulating layer 40 in the second region 12 (as shown in FIG. 8).

[0079] In some embodiments, as shown in FIG. 3 and FIG. 4, the orthographic projection of the first insulating layer 30 on the substrate 10 is located in the first region 11 and does not overlap with the second region 12. That is, the orthographic projection of the first insulating layer 30 on the substrate 10 does not cover the second region 12, and the thickness of the portion of the first insulating layer 30 located in the second region 12 is 0. Exemplarily, the portion of the first insulating layer 30 located in the second region 12 can be removed by a patterning process. In this way, the thickness of the first insulating layer 30 in the first region 11 is greater than that in the second region 12. Moreover, the orthographic projection of the second insulating layer 40 on the substrate 10 is located in the first region 11 and the second region 12, and the thickness of the second insulating layer 40 in the first region 11 is equal to that in the second region 12. That is, the second insulating layer 40 extends substantially over the entire array substrate 100, and the thickness of the second insulating layer 40 is uniform, except for the first via V1 penetrating through the second insulating layer 40 and the relief change caused by the surface on which the second insulating layer 40 is located; and the second insulating layer 40 is not subjected to a patterning process to thin or remove the portion thereof located in the second region 12. The above arrangement can reduce the thickness of the first insulating layer 30 in the region (the second region 12) other than the heating electrode 20, thereby reducing the shrinkage stress suffered by the first insulating layer 30, which is conducive to reducing the Final TP deviation of the array substrate 100 after the annealing process, and is also conducive to reducing the risk of warping of the array substrate 100. In addition, since the thickness of the first insulating layer 30 in the second region 12 is reduced, the first via V1 only needs to penetrate through the third insulating layer 53 and the second insulating layer 40, so the depth of the first via V1 can be reduced, thereby reducing the etching time of the first via V1 and reducing the size (the area of the orthographic projection on the substrate 10) of the first via V1, which is conducive to improving the aperture ratio of the array substrate 100, thereby improving the light extraction efficiency of the array substrate 100.

[0080] Exemplarily, in the case where the first insulating layer 30 and the second insulating layer 40 are in the structure as shown in FIG. 4, the first region 11 can be defined by the orthographic projection of the first insulating layer 30 on the substrate 10, for example, the region where the orthographic projection of the first insulating layer 30 on the substrate 10 is located is the first region 11, and the other regions are the second region 12.

[0081] Continuing to refer to FIGS. 3 and 4, the array substrate 100 can further include a plurality of gate lines GL, a gate insulating layer GI, a semiconductor pattern ACT, and a source-drain conductive layer arranged in sequence away from the substrate 10 between the substrate 10 and the film layer where the first insulating layer 30 is located; the source-drain conductive layer includes a plurality of data signal lines DL and a drain pattern D. The plurality of gate lines GL extend along the first direction X and are spaced apart along the second direction Y, the plurality of data signal lines DL extend along the second direction Y and are spaced apart along the first direction X, and the plurality of gate lines GL and the plurality of data signal lines DL cross each other to form a grid structure, and one grid defines one sub-pixel.

[0082] As shown in FIG. 4, the array substrate 100 can further include a thin film transistor TFT, which can be a bottom-gate transistor. The thin film transistor TFT includes a gate G integrally arranged with the gate line GL, the semiconductor pattern ACT, a source pattern S integrally arranged with the data signal line DL, and the drain pattern D arranged in the same layer as the source pattern S. The array substrate 100 can further include a common electrode 51, a third insulating layer 53, and a pixel electrode 52 located away from the substrate 10 on the side of the second insulating layer 40. The pixel electrode 52 can be connected to the drain pattern D through a first via V1.

[0083] As shown in FIG. 4, in some embodiments, in the case that the orthographic projection of the first insulating layer 30 on the substrate 10 does not cover the second region 12, the included angle a between the side wall 33 (hereinafter referred to as the first side wall 33) formed by the first insulating layer 30 and a reference surface parallel to the substrate 10 (such as the upper surface of the substrate 10) is less than or equal to 50°. That is, the slope angle a of the first side wall 33 formed by the first insulating layer 30 is less than or equal to 50°. In this way, it is beneficial to reduce the slope of the second insulating layer 40 at the first side wall 33 of the first insulating layer 30 and reduce the risk of climbing fracture of the subsequently formed common electrode 51 and pixel electrode 52 at the position where the first side wall 33 of the first insulating layer 30 is located. Exemplarily, the included angle a between the first side wall 33 formed by the first insulating layer 30 and the reference surface is 25°, 30°, 35°, 37°, 40°, or 45°, and the like, and the embodiments of the present disclosure will not list them one by one.

[0084] Referring to FIG. 5, in some embodiments, the first insulating layer 30 includes a first sub-portion 31 and a second sub-portion 32. The first sub-portion 31 has a footprint on the substrate 10 located in the first region 11 and covers the footprint of the heating electrode 20 on the substrate 10. The second sub-portion 32 has a footprint on the substrate 10 located in the second region 12 and does not overlap with the footprint of the heating electrode 20 on the substrate 10. The thickness H1 of the first sub-portion 31 is greater than the thickness H2 of the second sub-portion 32. That is, the first insulating layer 30 extends over the entire array substrate 100, but the thickness H1 of the first insulating layer 30 in the first region 11 is greater than the thickness H2 in the second region 12. The second insulating layer 40 has a footprint on the substrate 10 located in the first region 11 and the second region 12, and the thickness of the second insulating layer 40 in the first region 11 is equal to the thickness in the second region 12. That is, the second insulating layer 40 extends substantially over the entire array substrate 100, and the thickness of the second insulating layer 40 is uniform, except for the thickness of the via hole penetrating through the second insulating layer 40 and the uneven topography caused by the surface of the second insulating layer 40. The second insulating layer 40 is not subjected to a patterning process to thin or remove the portion thereof in the second region 12. The above arrangement can reduce the thickness of the first insulating layer 30 in the region (second region 12) other than the heating electrode 20, thereby reducing the shrinkage stress of the first insulating layer 30, which is beneficial to reduce the Final TP deviation of the array substrate 100 after the annealing process, and is also beneficial to reduce the risk of warping of the array substrate 100. In addition, since the thickness of the first insulating layer 30 in the second region 12 is reduced, the first via hole V1 only needs to penetrate through the third insulating layer 53, the second insulating layer 40, and the second sub-portion 32 of the first insulating layer 30, so that the thickness penetrated by the first via hole V1 can be reduced, thereby reducing the etching time of the first via hole V1, reducing the size (the area of the footprint on the substrate 10) of the first via hole V1, and improving the aperture ratio of the array substrate 100, thereby improving the light extraction efficiency of the array substrate 100.

[0085] For example, in the case where the first insulating layer 30 and the second insulating layer 40 are in the structure as shown in FIG. 5, the first region 11 can be defined by the footprint of the first sub-portion 31 of the first insulating layer 30 on the substrate 10, for example, the region where the footprint of the first sub-portion 31 on the substrate 10 is located is the first region 11.

[0086] For example, the portion of the first insulating layer 30 in the second region 12 can be partially removed by a patterning process, such as by controlling the etching speed and etching time to avoid completely etching the first insulating layer 30 in the second region 12, so as to avoid damage to other film layers and structures close to the substrate 10 side of the first insulating layer 30 during etching.

[0087] As shown in FIG. 5, the array substrate 100 includes a thin film transistor TFT disposed between the substrate 10 and the first insulating layer 30, the thin film transistor TFT including a gate G, a semiconductor pattern ACT, a source pattern S and a drain pattern D. The semiconductor pattern ACT is disposed on a side of the gate G away from the substrate 10, the source pattern S and the drain pattern D are disposed on a side of the semiconductor pattern ACT away from the substrate 10, and the source pattern S and the drain pattern D have a second interval D3 therebetween. A normal projection of the second sub-portion 32 of the first insulating layer 30 on the substrate 10 covers a normal projection of the thin film transistor TFT on the substrate 10, so that the second sub-portion 32 can protect the thin film transistor TFT and reduce damage to the thin film transistor TFT in the process of patterning the first insulating layer. The second sub-portion 32 is partially between the source pattern S and the drain pattern D and contacts a surface of the semiconductor pattern ACT away from the substrate 10. In this way, the second sub-portion 32 can protect the semiconductor pattern ACT and avoid damage to the semiconductor pattern ACT and the source pattern S and the drain pattern D in the process of etching the first insulating layer 30.

[0088] As shown in FIG. 5, in some embodiments, the thickness H2 of the second sub-portion 32 is less than one-half of the thickness H1 of the first sub-portion 31, i.e. In this way, not only can the thickness H2 of the second sub-portion 32 be greatly reduced to reduce the shrinkage stress of the first insulating layer 30, thereby reducing the Final TP deviation of the array substrate 100 after the annealing process and reducing the risk of warping of the array substrate 100, but also the second sub-portion 32 can cover other film layers (semiconductor pattern ACT) on a side of the first insulating layer 30 close to the substrate 10 to avoid damage to the other film layers (semiconductor pattern ACT). Exemplarily, the thickness H1 of the first sub-portion 31 can be The thickness H2 of the second sub-portion 32 can be Exemplarily, the thickness H1 of the first sub-portion 31 can be or and so on, the thickness H2 of the second sub-portion 32 can be or and so on, the thickness H2 of the second sub-portion 32 can be or

[0089] As shown in FIG. 5, in some embodiments, in the case where the first insulating layer 30 includes the first sub-portion 31 and the second sub-portion 32, the included angle a between the first sidewall 33 formed by the first insulating layer 30 (the first sub-portion 31) and a reference surface parallel to the substrate 10 (such as the upper surface of the substrate 10) is less than or equal to 50°. That is, the slope angle a of the first sidewall 33 formed by the first sub-portion 31 is less than or equal to 50°. In this way, it is beneficial to reduce the slope of the second insulating layer 40 at the first sidewall 33 of the first insulating layer 30, and reduce the risk of the subsequently formed common electrode 51 and pixel electrode 52 being broken by climbing at the position where the first sidewall 33 of the first insulating layer 30 is located. Exemplarily, the included angle a between the first sidewall 33 formed by the first sub-portion 31 and the reference surface can be 25°, 30°, 37°, 40°, or 45°, and the like, and the embodiments of the present disclosure will not list them one by one.

[0090] In some embodiments, as shown in FIG. 4 and FIG. 5, in the cross section of the first insulating layer 30 and the heating electrode 20 perpendicular to the extension direction of the heating electrode (such as the cross section shown in FIG. 4 and FIG. 5), the first insulating layer 30 includes a trapezoid located in the first area 11, that is, the part of the first insulating layer 30 located in the first area 11 is in a trapezoidal structure. In the above-mentioned cross section, the heating electrode 20 is close to the boundary (lower boundary) of the substrate 10, and is located in the range where the trapezoid is away from the boundary (upper side) of the substrate 10, in other words, the lower surface of the heating electrode 20 is located in the range of the upper surface of the trapezoidal part (the part located in the first area 11) of the first insulating layer 30. Specifically, the boundary of the heating electrode 20 close to the substrate 10 can completely coincide with the boundary of the trapezoid away from the substrate 10, that is, the lower surface of the heating electrode 20 completely coincides with the upper surface of the trapezoidal part of the first insulating layer 30; or, at least one end of the boundary of the heating electrode 20 close to the substrate 10 can have a spacing with the boundary of the trapezoid away from the substrate 10, that is, at least part of the boundary of the lower surface of the heating electrode 20 has a spacing with the boundary of the upper surface of the trapezoidal part of the first insulating layer 30. Exemplarily, in the preparation process of the array substrate 100, the first insulating layer 30 can be patterned (etched) by taking the heating electrode 20 as a mask, or the first insulating layer 30 and the heating electrode 20 can be patterned by using the same mask layer, which is beneficial to reduce the preparation difficulty and preparation cost of the array substrate 100.

[0091] Referring to FIG. 6, in some embodiments, the first insulating layer 30 includes a first sub-portion 31 and a second sub-portion 32. The orthogonal projection of the first sub-portion 31 on the substrate 10 is located in the first region 11 and covers the orthogonal projection of the heating electrode 20 on the substrate 10. The orthogonal projection of the second sub-portion 32 on the substrate 10 is located in the second region 12 and does not overlap with the orthogonal projection of the heating electrode 20 on the substrate 10. The thickness H1 of the first sub-portion 31 is greater than the thickness H2 of the second sub-portion 32. That is, although the first insulating layer 30 extends over the entire array substrate 100, the thickness H1 of the first insulating layer 30 in the first region 11 is greater than the thickness H2 in the second region 12. The orthogonal projection of the second insulating layer 40 on the substrate 10 is located in the first region 11 and does not overlap with the second region 12, that is, the orthogonal projection of the second insulating layer 40 on the substrate 10 does not cover the second region 12, and the thickness of the portion of the second insulating layer 40 located in the second region 12 is 0. Exemplarily, the portion of the second insulating layer 40 located in the second region 12 can be removed by a patterning process. At this time, the thickness of the second insulating layer 40 in the first region 11 is greater than the thickness in the second region 12. This arrangement can reduce the thickness of the first insulating layer 30 and the second insulating layer 40 in the region (the second region 12) outside the heating electrode 20, thereby reducing the shrinkage stress suffered by the first insulating layer 30 and the second insulating layer 40, which is conducive to reducing the Final TP deviation of the array substrate 100 after the annealing process, and is also conducive to reducing the risk of warping of the array substrate 100. In addition, since the thickness of the first insulating layer 30 and the second insulating layer 40 in the second region 12 is reduced, the first via V1 only needs to penetrate the third insulating layer 53 and the second sub-portion 32 of the first insulating layer 30, so the depth of the first via V1 can be reduced, thereby reducing the etching time of the first via V1 and reducing the size (the area of the orthogonal projection on the substrate 10) of the first via V1. In this way, it is conducive to improving the aperture ratio of the array substrate 100, thereby improving the light extraction efficiency of the array substrate 100.

[0092] Exemplarily, in the case where the first insulating layer 30 and the second insulating layer 40 are structures as shown in FIG. 6, the first region 11 can be defined by the orthogonal projection of the first sub-portion 31 of the first insulating layer 30 on the substrate 10, for example, the region where the orthogonal projection of the first sub-portion 31 on the substrate 10 is located is the first region 11.

[0093] Exemplarily, the second insulating layer 40 in the second region 12 can be removed and the first insulating layer 30 in the second region 12 can be partially removed by the same patterning process, for example, by controlling the etching speed and etching time. The first insulating layer 30 in the second region 12 can be avoided to be etched completely to avoid damage to other film layers and structures close to the substrate 10 side of the first insulating layer 30 during etching.

[0094] As shown in FIG. 6, the array substrate 100 includes a thin film transistor TFT disposed between the substrate 10 and the first insulating layer 30, the thin film transistor TFT including a gate G, a semiconductor pattern ACT, a source pattern S, and a drain pattern D. The source pattern S and the drain pattern D have a third interval D3 therebetween. A portion of the second sub-portion 32 of the first insulating layer 30 is located within the third interval D3 between the source pattern S and the drain pattern D and contacts the semiconductor pattern ACT away from the surface of the substrate 10. The first insulating layer 30 can protect the semiconductor pattern ACT from damage during etching of the first insulating layer 30.

[0095] As shown in FIG. 6, in some embodiments, the thickness H2 of the second sub-portion 32 is less than one-half of the thickness H1 of the first sub-portion 31, i.e. In this way, not only can the thickness H2 of the second sub-portion 32 be greatly reduced, reducing the shrinkage stress of the first insulating layer 30 to reduce the Final TP deviation of the array substrate 100 after the annealing process and reduce the risk of warping of the array substrate 100, but also the second sub-portion 32 can cover other film layers (such as the semiconductor pattern ACT) on the side of the first insulating layer 30 close to the substrate 10, avoiding damage to the other film layers.

[0096] For example, the thickness H1 of the first sub-portion 31 can be The thickness H2 of the second sub-portion 32 can be For example, the thickness H1 of the first sub-portion 31 can be Or Or Or Embodiments of the present disclosure do not list all of the above.

[0097] As shown in FIG. 6, in some embodiments, after the second insulating layer 40 is removed from the second region 12, the second insulating layer 40 can still cover the surface of the heating electrode 20 away from the substrate 10 and the sidewall of the heating electrode 20. In this way, the second insulating layer 40 and the first insulating layer 30 can completely cover the heating electrode 20 to avoid shorting between the heating electrode 20 and other conductive structures (such as the common electrode 51 and the pixel electrode 52) of the array substrate 100.

[0098] With reference back to FIG. 6, in some embodiments, the surface of the heating electrode 20 in contact with the first insulating layer 30 is a first surface 201, the surface of the first insulating layer 30 in contact with the heating electrode 20 is a second surface 34, the first surface 201 is located within the second surface 34, and the boundary of the first surface 201 and the boundary of the second surface 34 have a first interval D4. That is, the edge of the first insulating layer 30 extends beyond the boundary of the heating electrode 20, and the first insulating layer 30 and the heating electrode 20 can form a step structure together, which is conducive to the deposition of the second insulating layer 40 on the sidewalls of the first insulating layer 30 and the heating electrode 20, reduces the risk of breakage of the second insulating layer 40 on the sidewalls of the first insulating layer 30 and the heating electrode 20, and is conducive to the deposition of the first electrode 51 and the second electrode 52 on the surface of the second insulating layer 40.

[0099] With reference back to FIG. 6, in some embodiments, in the orthogonal projection of the second insulating layer 40 and the heating electrode 20 on the substrate 10, the second insulating layer 40 covers the heating electrode 20, and the boundary of the second insulating layer 40 and the boundary of the heating electrode 20 have a first interval D4, which is greater than or equal to 0.5 μm. This is conducive to the complete coverage of the heating electrode 20 by the second insulating layer 40, ensures that the second insulating layer 40 completely covers the surface of the heating electrode 20, and reduces the risk of short circuit between the heating electrode 20 and the common electrode 51 and the pixel electrode 52. Exemplarily, the first interval D4 can be 0.5 μm, 0.6 μm, 0.75 μm, 1.0 μm, or 1.5 μm, etc., and the embodiments of the present disclosure will not list them one by one.

[0100] In addition, as shown in FIG. 6, in some embodiments, when the thicknesses of the first insulating layer 30 and the second insulating layer 40 in the first region 11 are both greater than the thicknesses of the first insulating layer 30 and the second insulating layer 40 in the second region 12, respectively, the boundary of the upper surface of the first insulating layer 30 in the first region 11 coincides with the boundary of the lower surface of the second insulating layer 40. In this way, the first insulating layer 30 and the second insulating layer 40 can be patterned by the same etching process, which is conducive to simplifying the preparation process of the first insulating layer 30 and the second insulating layer 40 and reducing the preparation cost of the first insulating layer 30 and the second insulating layer 40.

[0101] As shown in FIG. 6, the included angle a between the first sidewall 33 formed by the first insulating layer 30 (the first sub-portion 31) and the reference surface is less than or equal to 50°, in other words, the slope angle a of the first sidewall 33 formed by the first sub-portion 31 is less than or equal to 50°. In addition, in the case where the second insulating layer 40 removes the portion within the second region 12, the included angle b between the sidewall (hereinafter referred to as the second sidewall 41) formed by the second insulating layer 40 and the reference surface is less than or equal to 50°, that is, the slope angle b of the second sidewall 41 formed by the second insulating layer 40 is less than or equal to 50°. In this way, it is beneficial to reduce the slope of the first sidewall 33 and the second sidewall 41, and reduce the risk of the subsequent common electrode 51 and pixel electrode 52 from being broken by climbing at the first sidewall 33 and the second sidewall 41.

[0102] Exemplarily, the included angle a between the first sidewall 33 formed by the first insulating layer 30 and the reference surface can be 25°, 30°, 35°, 37°, 40° or 45°, etc. Exemplarily, the included angle b between the second sidewall 41 formed by the second insulating layer 40 and the reference surface can be 25°, 25°, 30°, 37°, 40° or 45°, etc., and the embodiments of the present disclosure will not list them one by one. Among them, the included angle a between the first sidewall 33 and the reference surface can be equal to or different from the included angle b between the second sidewall 41 and the reference surface. Among them, the first insulating layer 30 and the second insulating layer 40 are patterned by the same etching process, and the materials of the first insulating layer 30 and the second insulating layer 40 are the same, so that the included angle a between the first sidewall 33 and the reference surface can be equal to the included angle b between the second sidewall 41 and the reference surface.

[0103] Referring to FIG. 7, in some embodiments, the orthogonal projection of the first insulating layer 30 on the substrate 10 is located in the first region 11 and does not overlap the second region 12. And the orthogonal projection of the second insulating layer 40 on the substrate 10 is located in the first region 11 and does not overlap the second region 12. That is, neither the orthogonal projection of the first insulating layer 30 nor the orthogonal projection of the second insulating layer 40 on the substrate 10 covers the second region 12, and the thickness of the portion of the first insulating layer 30 and the second insulating layer 40 located in the second region 12 is 0. In this way, the thickness of the first insulating layer 30 and the second insulating layer 40 in the first region 11 is greater than the thickness in the second region 12. The thickness of the first insulating layer 30 and the second insulating layer 40 in the region (the second region 12) other than the heating electrode 20 can be greatly reduced, thereby reducing the shrinkage stress suffered by the first insulating layer 30 and the second insulating layer 40, which is conducive to reducing the Final TP deviation of the array substrate 100 after the annealing process, and reducing the risk of warping of the array substrate 100. In addition, since the thickness of the first insulating layer 30 and the second insulating layer 40 in the second region 12 is reduced, the depth of the first via V1 can be reduced, thereby reducing the etching time of the first via V1 and reducing the size (the area of the orthogonal projection on the substrate 10) of the first via V1. In this way, it is conducive to improving the aperture ratio of the array substrate 100, thereby improving the light extraction efficiency of the array substrate 100.

[0104] Exemplarily, the second insulating layer 40 and the first insulating layer 30 in the second region 12 can be removed by the same patterning process, such as by controlling the etching speed and etching time.

[0105] Exemplarily, in the case where the first insulating layer 30 and the second insulating layer 40 are in the structure as shown in FIG. 7, the first region 11 can be defined by the orthogonal projection of the first insulating layer 30 on the substrate 10, such as the region where the orthogonal projection of the first insulating layer 30 on the substrate 10 is located.

[0106] As shown in FIG. 7, in some embodiments, after the second insulating layer 40 removes the portion in the second region 12, the second insulating layer 40 can still cover the surface of the heating electrode 20 away from the substrate 10 and the sidewall of the heating electrode 20. In this way, the second insulating layer 40 and the first insulating layer 30 can completely wrap the heating electrode 20 to avoid short circuit between the heating electrode 20 and other conductive structures (such as the data signal line DL, the gate line GL, the common electrode 51 and the pixel electrode 52) of the array substrate 100.

[0107] Continuing to refer to FIG. 7, in some embodiments, the surface of the heating electrode 20 in contact with the first insulating layer 30 is a first surface 201, the surface of the first insulating layer 30 in contact with the heating electrode 20 is a second surface 34, the first surface 201 is located within the second surface 34, and the boundary of the first surface 201 and the boundary of the second surface 34 have a first interval D4. In this way, it is beneficial to deposit the second insulating layer 40 on the sidewalls of the first insulating layer 30 and the heating electrode 20, reduce the risk of breaking the second insulating layer 40 on the sidewalls of the first insulating layer 30 and the heating electrode 20, and facilitate the deposition of the first electrode 51 and the second electrode 52 on the surface of the second insulating layer 40.

[0108] As shown in FIG. 7, in the orthogonal projection of the second insulating layer 40 and the heating electrode 20 on the substrate 10, the second insulating layer 40 covers the heating electrode 20, and the boundary of the second insulating layer 40 and the boundary of the heating electrode 20 have a first interval D4, which is greater than or equal to 0.5 μm. In this way, it is beneficial to completely cover the heating electrode 20 with the second insulating layer 40, ensure that the second insulating layer 40 completely covers the surface of the heating electrode 20, and reduce the risk of short circuit between the heating electrode 20 and the common electrode 51 and the pixel electrode 52. Exemplarily, the first interval D4 can be 0.5 μm, 0.6 μm, 0.75 μm, 1.0 μm, or 1.5 μm, etc., and the embodiments of the present disclosure will not list them one by one.

[0109] As shown in FIG. 7, the included angle α between the first sidewall 33 of the first insulating layer 30 and the reference surface is less than or equal to 50°, in other words, the slope angle α of the first sidewall 33 is less than or equal to 50°. In addition, in the case where the second insulating layer 40 removes the part in the second region 12, the included angle β between the second sidewall 41 of the second insulating layer 40 and the reference surface is less than or equal to 50°, that is, the slope angle β of the second sidewall 41 is less than or equal to 50°. In this way, it is beneficial to reduce the slope of the first sidewall 33 and the second sidewall 41, and reduce the risk of climbing and breaking of the subsequently formed common electrode 51 and pixel electrode 52 at the first sidewall 33 and the second sidewall 41.

[0110] In addition, as shown in FIG. 7, in the case where the thicknesses of the first insulating layer 30 and the second insulating layer 40 in the first region 11 are both greater than the thicknesses of the first insulating layer 30 and the second insulating layer 40 in the second region 12, respectively, the boundary of the upper surface of the first insulating layer 30 in the first region 11 coincides with the boundary of the lower surface of the second insulating layer 40. In this way, the first insulating layer 30 and the second insulating layer 40 can be patterned by the same etching process, which is beneficial to simplify the preparation process of the first insulating layer 30 and the second insulating layer 40, and reduce the preparation cost of the first insulating layer 30 and the second insulating layer 40.

[0111] Referring to FIG. 8, in some embodiments, the orthographic projection of the first insulating layer 30 on the substrate 10 is located within the first region 11 and the second region 12, and the thickness of the first insulating layer 30 within the first region 11 is equal to the thickness of the first insulating layer 30 within the second region 12. The orthographic projection of the second insulating layer 40 on the substrate 10 is located within the first region 11 and does not overlap the second region 12. That is, the first insulating layer 30 extends substantially across the entire array substrate 100, and the thickness of the first insulating layer 30 is uniform, except for the through hole penetrating through the first insulating layer 30 and the relief topography variation caused by the surface on which the first insulating layer 30 is located. The first insulating layer 30 is not subjected to a patterning process to thin or remove the portion of the first insulating layer 30 within the second region 12. The orthographic projection of the second insulating layer 40 on the substrate 10 does not cover the second region 12, and the thickness of the portion of the second insulating layer 40 within the second region 12 is 0. The portion of the second insulating layer 40 within the second region 12 can be removed by a patterning process, such that the thickness of the second insulating layer 40 within the first region 11 is greater than the thickness of the second insulating layer 40 within the second region 12. In this way, the thickness of the second insulating layer 40 in the region (the second region 12) other than the heating electrode 20 can be reduced, and thus the shrinkage stress of the second insulating layer 40 can be reduced, which is conducive to reducing the Final TP deviation of the array substrate 100 after the annealing process, and is also conducive to reducing the risk of warping of the array substrate 100. In addition, since the thickness of the second insulating layer 40 within the second region 12 is reduced, the first through hole V1 only needs to penetrate through the third insulating layer 53 and the first insulating layer 30, and thus the depth of the first through hole V1 can be reduced, the etching time of the first through hole V1 can be reduced, and the size (the area of the orthographic projection on the substrate 10) of the first through hole V1 can be reduced, which is conducive to improving the aperture ratio of the array substrate 100, and thus improving the light extraction efficiency of the array substrate 100.

[0112] For example, in the case where the first insulating layer 30 and the second insulating layer 40 are in the structure as shown in FIG. 8, the first region 11 can be defined by the orthographic projection of the second insulating layer 40 on the substrate 10, for example, the region where the orthographic projection of the second insulating layer 40 on the substrate 10 is located is the first region 11.

[0113] As shown in FIG. 8, in some embodiments, in the case where the second insulating layer 40 removes the portion within the second region 12, the second insulating layer 40 can still cover the surface of the heating electrode 20 away from the substrate 10 and the sidewall of the heating electrode 20, so that the second insulating layer 40 and the first insulating layer 30 can completely wrap the heating electrode 20 to avoid short circuit between the heating electrode 20 and other conductive structures (such as the data signal line DL, the gate line GL, the common electrode 51 and the pixel electrode 52) of the array substrate 100.

[0114] Continuously referring to FIG. 8, in the orthographic projection of the second insulating layer 40 and the heating electrode 20 on the substrate 10, the second insulating layer 40 covers the heating electrode 20, and there is a first interval D4 between the boundary of the second insulating layer 40 and the boundary of the heating electrode 20, the first interval D4 is greater than or equal to 0.5 μm. It is beneficial for the second insulating layer 40 to completely cover the heating electrode 20, to ensure that the second insulating layer 40 completely covers the surface of the heating electrode 20, and to reduce the risk of short circuit between the heating electrode 20 and the common electrode 51 and the pixel electrode 52. Exemplarily, the first interval D4 can be 0.5 μm, 0.6 μm, 0.75 μm, 1.0 μm, or 1.5 μm, etc., and the embodiments of the present disclosure will not list them one by one.

[0115] As shown in FIG. 8, in the case that the second insulating layer 40 removes the part in the second region 12, the included angle β between the second sidewall 41 formed by the second insulating layer 40 and the reference surface is less than or equal to 50°, that is, the slope angle β of the second sidewall 41 is less than or equal to 50°. In this way, it is beneficial to reduce the slope of the second sidewall 41 and reduce the risk of climbing fracture of the subsequently formed common electrode 51 and pixel electrode 52 at the first sidewall 33 and the second sidewall 41. Exemplarily, the included angle β between the second sidewall 41 formed by the second insulating layer 40 and the reference surface can be 25°, 25°, 30°, 37°, 40°, or 45°, etc., and the embodiments of the present disclosure will not list them one by one.

[0116] In some embodiments, referring to FIG. 9, the heating electrode 20 can include a first electrode 21 and a second electrode 22. The first electrode 21 and the second electrode 22 both extend along the first direction X. The first electrode 21 includes a first end 211 and a second end 212 located at both ends of the first direction X. The second electrode 22 is arranged side by side with the first electrode 21, and the second electrode 22 includes a third end 221 located at the same side as the first end 211, and a fourth end 222 located at the same side as the second end 212. The first end 211 and the third end 221 are electrically connected with the power supply of different polarities, and the second end 212 and the fourth end 222 are electrically connected. In this way, one side of the first electrode 21 and the second electrode 22 is electrically connected with the power supply, and the other side is connected through the connecting electrode 24, and the first electrode 21 and the second electrode 22 and the power supply of opposite polarities can form a current loop. When the heating electrode 20 works, the first electrode 21 and the second electrode 22 can generate heat to heat the array substrate 100, the array substrate 100 transmits the heat to the liquid crystal layer, improves the temperature of the liquid crystal molecules in the liquid crystal layer, reduces the viscosity, and enables the display panel to work at a lower ambient temperature.

[0117] Exemplarily, the array substrate 100 can include a plurality of heating electrodes 20 arranged along the second direction Y, one heating electrode 20 refers to a first electrode 21 and a second electrode 22 electrically connected with one positive voltage terminal V+ and one negative voltage terminal V-, and can constitute one current loop. The first electrode 21 and the second electrode 22 are alternately distributed in the second direction Y; the array substrate 100 can include a display area AA and a peripheral area BB surrounding the display area AA. The first electrode 21 and the second electrode 22 extend to the peripheral area BB at both ends along the first direction X, respectively. One of the first end 211 and the third end 221 is used to connect the voltage terminal with positive polarity (positive voltage terminal V+), and the other is used to connect the voltage terminal with negative polarity (negative voltage terminal V-). In the embodiments of the present application, the first end 211 is connected with the positive voltage terminal V+ with positive polarity, and the third end 221 is connected with the negative voltage terminal V- with negative polarity, which is exemplarily described. Of course, the embodiments of the present disclosure are not limited thereto, and can be connected in other suitable manners. The first electrode 21 and the second electrode 22 refer to at least one electrode trace 202 connected with the voltage terminal with the same polarity and adjacent to each other in the second direction Y.

[0118] Wherein, the positive voltage terminal V+ and the negative voltage terminal V- can be electrically connected with an external power supply through a chip on film (Chip On Film; COF) to provide power for the positive voltage terminal V+ and the negative voltage terminal V-. For example, a constant voltage power supply can be provided for the positive voltage terminal V+ and the negative voltage terminal V- to provide a constant voltage. The array substrate can further include a gate driving circuit, which is located on the side of the peripheral area away from the COF, or in other words, the COF and the gate driving circuit are located on opposite sides of the display area AA.

[0119] Referring to FIG. 10, in some embodiments, based on the structure of the heating electrode 20 shown in FIG. 9, the heating electrode 20 can further include a plurality of auxiliary electrodes 23. The plurality of auxiliary electrodes 23 are arranged between the first electrode 21 and the second electrode 22 and are spaced apart along the first direction X. The auxiliary electrodes 23 can extend along the second direction Y, and the two ends of the auxiliary electrodes 23 along the second direction Y are connected to the first electrode 21 and the second electrode 22, respectively. Along the direction away from the first end 211 and the third end 221 (the direction from left to right in FIG. 10, hereinafter referred to as the third direction X'), the resistance of the plurality of auxiliary electrodes 23 gradually decreases. Along the third direction X', the voltage difference between the first electrode 21 and the second electrode 22 gradually decreases, and the resistance of the plurality of auxiliary electrodes 23 gradually decreases. For example, by calculating the resistance of each auxiliary electrode 23, the heating power of the heating electrode 20 at different positions on the array substrate 100 can be the same. In this way, it is beneficial to improve the uniformity of the heat generation of the heating electrode 20 at different positions along the third direction X', the temperature change at different positions on the array substrate 100 is more uniform, and the uniformity of the temperature rise of the display panel at different positions is improved. In addition, by increasing the auxiliary electrodes 23, it is also beneficial to increase the coverage density of the heating electrode 20, thereby improving the overall heating efficiency of the heating electrode 20 and improving the heating efficiency of the array substrate and the display panel.

[0120] For example, by increasing the auxiliary electrodes 23 and calculating the resistance of each auxiliary electrode 23, the average temperature rise rate of the display panel can be greater than or equal to a first threshold value, and the temperature range (the difference between the highest temperature and the lowest temperature) at different positions of the display panel can be less than a second threshold value. For example, the first threshold value can be 6 ℃ / min, 10 ℃ / min, 15 ℃ / min, or 20 ℃ / min, and the second threshold value can be 10 ℃, 9 ℃, 7 ℃, or 5 ℃. Embodiments of the present disclosure do not list them one by one.

[0121] In addition, in the case where the heating electrode 20 includes the first electrode 21, the second electrode 22, and the auxiliary electrode 23, the positions where the first electrode 21, the second electrode 22, and the auxiliary electrode 23 are located are all considered as the first region. That is, at least one of the first electrode 21, the second electrode 22, and the auxiliary electrode 23, the thickness of the first insulating layer 30 and / or the second insulating layer 40 is greater than the thickness of the corresponding film layer in the second region (a region other than the first electrode 21, the second electrode 22, and the auxiliary electrode 23). The specific arrangement of the first insulating layer 30 and the second insulating layer 40 can be referred to the above, and will not be described here. In addition, the thickness of the first insulating layer 30 and / or the second insulating layer 40 at the positions of the first electrode 21 and the second electrode 22 can be equal to the thickness of the corresponding film layer at the position of the auxiliary electrode 23.

[0122] Exemplarily, the resistance of each auxiliary electrode 23 can be obtained by calculation in the embodiments of the present disclosure.

[0123] As shown in FIG. 11, the connections of the auxiliary electrode 23 with the first electrode 21 and the second electrode 22 are defined as node X and node X' respectively, and there are N nodes in total in FIG. 11. The resistance of the auxiliary electrode 23 arranged between the node X and the node X' is equivalent to R X . Meanwhile, the resistance between the node X-1 and the node X is equivalent to R XL , the resistance between the node X-1' and the node X' is equivalent to R XR , the resistance between the node 1' and the negative voltage terminal V- is equivalent to R 1R , and the resistance between the node 1 and the positive voltage terminal V+ is equivalent to R 1L . It is assumed that R 1R = R 1L , the equivalent resistance for connecting the first electrode 21 and the second electrode 22 farthest from the first end 211 is R (N+1) , and the equivalent resistances between the node N and the node N' are R (N+1)L and R (N+1)R respectively; in addition, it is assumed that the voltage difference between the positive voltage terminal V+ and the negative voltage terminal V- is U. For convenience of description, the equivalent resistance between the node X and the node X' is defined as R 节点X , and it is easy to know that the calculation formula of R 节点X is as follows:

[0124] The voltage between the node X and the node X' is defined as U 节点X , and it is easy to know that the calculation formula of U 节点X is as follows:

[0125] The heating power of the auxiliary electrode 23 between the node X and the node X' is defined as P RX , and it is easy to know that the calculation formula of P RX is as follows:

[0126] In addition, the heating power of the resistances R XL and R XR needs to be calculated, and since R XL = R XR , it is easy to know that P RXL = P RXR .

[0127] It is easy to know that:

[0128] The resistance R XL , the resistance R XRand resistance R X The corresponding area is area X, and the sum of the heating power of area X is:

[0129] Suppose the heating power of area 1, area 2, area 3, …, area N in the entire array substrate is the same: P1=P2=P3=…=P X-1 =P X =P X+1 =…=P N =P N+1 (5)

[0130] In the actual preparation process of the array substrate, a plurality of auxiliary electrodes 23, for example, 10 auxiliary electrodes 23, can be arranged equidistantly between the first electrode 21 and the second electrode 22. The resistance R XL and the resistance R XR can be calculated according to the resistivity, film thickness, and line width of the actual heating electrode 21. Then, according to the actual process capability of the exposure machine of the production line used in the array substrate preparation process, and the film thickness of the heating electrode 20, the range of the resistance R X of the auxiliary electrode 23 between the node N and the node N' can be designed in advance, and then the actual value of the resistance Rx of each auxiliary electrode 23 can be calculated according to the above formula (5) by exhaustive method. In this way, the heating power in each area can be made consistent, which is beneficial to improve the uniformity of temperature rise in each area of the array substrate, and further improve the uniformity of temperature rise at different positions of the display panel.

[0131] In some embodiments, the plurality of auxiliary electrodes 23, the first electrode 21, and the second electrode 22 are made of the same material and are arranged in the same layer. For example, the plurality of auxiliary electrodes 23, the first electrode 21, and the second electrode 22 can be integrally prepared by using the same material and the same film forming process, which is beneficial to reduce the preparation cost of the heating electrode 20, thereby reducing the preparation cost of the array substrate and the display panel. In addition, along the direction X+ away from the first end 211 and the third end 221, the line width of the plurality of auxiliary electrodes 23 gradually decreases. In the case where the plurality of auxiliary electrodes 23, the first electrode 21, and the second electrode 22 are made of the same material, the resistivity and thickness of the plurality of auxiliary electrodes 23 are substantially the same. According to the resistance calculation formula R=ρ×L×S, S is the interface area of the auxiliary electrode 23. Among them, the resistivity ρ, length L, and thickness of each auxiliary electrode 23 are respectively corresponding to each other, and the resistance value of each auxiliary electrode 23 can be adjusted by adjusting the width of the auxiliary electrode 23, so that the resistance of the plurality of auxiliary electrodes 23 gradually decreases along the direction X+ away from the first end 211 and the third end 221.

[0132] In some embodiments, as shown in FIGS. 10 and 12, the plurality of auxiliary electrodes 23 in the same heating electrode 20 can be distributed equidistantly along the first direction X, so that the area between the first electrode 21 and the second electrode 22 can be divided into a plurality of areas with equal areas by the plurality of auxiliary electrodes 23, which is conducive to the calculation of the resistance of the auxiliary electrode 23 and the improvement of the uniformity of the heat generation of the heating electrode 20 at different positions of the third direction X', thereby improving the uniformity of the temperature rise of the display panel at different positions.

[0133] As shown in FIGS. 10 and 12, the array substrate 100 further comprises a plurality of data lines DL, which are distributed equidistantly along the first direction X and extend along the second direction Y. The auxiliary electrode 23 has a projection on the substrate 10, which at least partially overlaps with the projection of the data signal line DL on the substrate 10. In this way, the influence of the auxiliary electrode 23 on the light-emitting efficiency of the array substrate 100 can be greatly reduced.

[0134] In some embodiments, as shown in FIGS. 10 and 12, the distance between two adjacent auxiliary electrodes 23 is D1, the distance between two adjacent data signal lines DL is D2, and D1=N×D2, where N is a positive integer. That is, an auxiliary electrode 23 is arranged every N data lines DL, which is conducive to the arrangement of the auxiliary electrode 23 opposite to the data line DL to reduce the influence of the auxiliary electrode 23 on the light-emitting efficiency of the array substrate. Exemplarily, the value of N can be 1, 2, 3, 4, 5, etc., and the embodiments of the present disclosure will not be enumerated one by one.

[0135] In some embodiments, as shown in FIGS. 10 and 12, the first electrode 21 and the second electrode 22 each comprise an electrode trace 202 extending along the first direction X, that is, the heating electrode 20 can be a "1U" structure. Exemplarily, an electrode trace 202 can be arranged on one side of each gate line GL along the second direction Y, and an electrode trace 202 can be arranged between two adjacent gate lines GL. In this way, the distribution density of the electrode trace 202 can be greatly improved, thereby improving the heating efficiency and the heating uniformity of the array substrate 100 at different positions. For example, the heating substrate can be heated to a higher temperature in a shorter time, and the temperature rise speed at different positions is the same or substantially the same.

[0136] In one example, as shown in FIG. 10, and along the first direction X, the distance between two adjacent auxiliary electrodes 23 is equal to the distance between two adjacent data lines DL (D1=D2), or in other words, one auxiliary electrode 23 is provided corresponding to each data line DL. In one example, as shown in FIG. 12, and along the first direction X, the distance between two adjacent auxiliary electrodes 23 is equal to twice the distance between two adjacent data lines DL (D1=N×2D2), or in other words, one auxiliary electrode 23 is provided corresponding to every two data lines DL.

[0137] It should be noted that in all the embodiments of the present disclosure, "one electrode trace 202" refers to one trace extending along the first direction X on the heating electrode 20. The heating electrode 20 (such as the first electrode 21 and the second electrode 22) can further include a plurality of electrode traces 202 arranged in parallel.

[0138] In other embodiments, as shown in FIGS. 13-16, the first electrode 21 and the second electrode 22 each include a plurality of electrode traces 202 arranged in parallel, the plurality of electrode traces 202 are spaced apart along the second direction Y and each extend along the first direction X, and the ends of the plurality of electrode traces 202 along the first direction X are connected to each other. In this way, the number of heating electrodes 20 can be reduced, and thus the number of positive voltage terminals V+ and negative voltage terminals V- can be reduced, and the difficulty of power supply of the heating electrode 20 can be reduced. The plurality of auxiliary electrodes 23 are connected to the two electrode traces 202 belonging to the first electrode 21 and the second electrode 22 respectively and closest to the plurality of auxiliary electrodes 23.

[0139] For example, as shown in FIG. 13, the first electrode 21 and the second electrode 22 can each include four electrode traces 202 arranged in parallel, that is, the heating electrode 20 is a "4U" structure. The two ends of the plurality of auxiliary electrodes 23 along the second direction Y are connected to the two electrode traces 202 belonging to the first electrode 21 and the second electrode 22 respectively and closest to the plurality of auxiliary electrodes 23. And along the first direction X, the distance between two adjacent auxiliary electrodes 23 is equal to the distance between two adjacent data lines DL, or in other words, one auxiliary electrode 23 is provided corresponding to each data line DL.

[0140] For example, as shown in FIG. 14, the first electrode 21 and the second electrode 22 can each include four electrode traces 202 arranged in parallel, and the two ends of the plurality of auxiliary electrodes 23 along the second direction Y are connected to the two electrode traces 202 belonging to the first electrode 21 and the second electrode 22 respectively and closest to the plurality of auxiliary electrodes 23. And along the first direction X, the distance between two adjacent auxiliary electrodes 23 is equal to twice the distance between two adjacent data lines DL, or in other words, one auxiliary electrode 23 is provided corresponding to every two data lines DL.

[0141] Exemplarily, as shown in FIG. 15, the first electrode 21 and the second electrode 22 can respectively include 8 electrode wires 202 arranged in parallel, that is, the heating electrode 20 is in a "8U" structure. The plurality of auxiliary electrodes 23 are connected to the two electrode wires 202 belonging to the first electrode 21 and the second electrode 22 respectively and closest to the two electrode wires 202 at both ends along the second direction Y. And along the first direction X, the distance between the adjacent two auxiliary electrodes 23 is equal to the distance between the adjacent data lines DL, or in other words, one auxiliary electrode 23 is arranged corresponding to each data line DL.

[0142] Exemplarily, as shown in FIG. 16, the first electrode 21 and the second electrode 22 can respectively include 8 electrode wires 202 arranged in parallel, and the plurality of auxiliary electrodes 23 are connected to the two electrode wires 202 belonging to the first electrode 21 and the second electrode 22 respectively and closest to the two electrode wires 202 at both ends along the second direction Y. Along the first direction X, the distance between the adjacent two auxiliary electrodes 23 is equal to twice the distance between the adjacent data lines DL, or in other words, one auxiliary electrode 23 is arranged corresponding to every two data lines DL.

[0143] It should be noted that the embodiments of the present disclosure include but are not limited to the structures shown in FIGS. 13-16, for example, the first electrode 21 and the second electrode 22 can respectively include 2, 4, 6, 8 or any other number of electrode wires 202 arranged in parallel, and one auxiliary electrode 23 can be arranged corresponding to every 1, 2, 4 or other suitable number of data lines.

[0144] In other embodiments, referring to FIGS. 17-24, the first electrode 21 and the second electrode 22 respectively include a plurality of electrode wires 202 arranged in parallel, the plurality of electrode wires 202 are spaced apart along the second direction Y and all extend along the first direction X, and the ends of the plurality of electrode wires 202 along the first direction X are connected to each other. In this way, the number of heating electrodes 20 can be reduced, and thus the number of positive voltage terminals V+ and negative voltage terminals V- can be reduced, and the difficulty of power supply of the heating electrode 20 can be reduced. The plurality of auxiliary electrodes 23 can be connected to the plurality of electrode wires 202 belonging to the first electrode 21 and the second electrode 22 respectively and equal in number. In this way, the auxiliary electrode 23 covers a larger area, which is conducive to further improving the heating uniformity of different positions in the array substrate and improving the consistency of the temperature rise rate at different positions in the array substrate.

[0145] Exemplarily, as shown in FIG. 17, the first electrode 21 and the second electrode 22 can respectively include 4 electrode traces 202 arranged in parallel, that is, the heating electrode 20 is in a "4U" structure. The plurality of auxiliary electrodes 23 are respectively connected with two electrode traces 202 belonging to the first electrode 21 and the second electrode 22, for example, the plurality of auxiliary electrodes 23 are electrically connected with the two electrode traces 202 on the lower side of the first electrode 21 and the two electrode traces 202 on the upper side of the second electrode 22. In addition, and along the first direction X, the distance between two adjacent auxiliary electrodes 23 is equal to the distance between two adjacent data lines DL, or in other words, one auxiliary electrode 23 is arranged corresponding to each data line DL.

[0146] Exemplarily, as shown in FIG. 18, the first electrode 21 and the second electrode 22 can respectively include 4 electrode traces 202 arranged in parallel, and the plurality of auxiliary electrodes 23 are electrically connected with all the electrode traces 202 included by the first electrode 21 and the second electrode 22, so that the heating electrode 20 can form a mesh structure. In addition, and along the first direction X, the distance between two adjacent auxiliary electrodes 23 is equal to the distance between two adjacent data lines DL, or in other words, one auxiliary electrode 23 is arranged corresponding to each data line DL.

[0147] Exemplarily, as shown in FIG. 19, the first electrode 21 and the second electrode 22 can respectively include 4 electrode traces 202 arranged in parallel, and the plurality of auxiliary electrodes 23 are electrically connected with the two electrode traces 202 on the lower side of the first electrode 21 and the two electrode traces 202 on the upper side of the second electrode 22. In addition, and along the first direction X, the distance between two adjacent auxiliary electrodes 23 is equal to twice the distance between two adjacent data lines DL, or in other words, one auxiliary electrode 23 is arranged corresponding to each two data lines DL.

[0148] Exemplarily, as shown in FIG. 20, the first electrode 21 and the second electrode 22 can respectively include 4 electrode traces 202 arranged in parallel, and the plurality of auxiliary electrodes 23 are electrically connected with all the electrode traces 202 included by the first electrode 21 and the second electrode 22, so that the heating electrode 20 can form a mesh structure. In addition, and along the first direction X, the distance between two adjacent auxiliary electrodes 23 is equal to twice the distance between two adjacent data lines DL, or in other words, one auxiliary electrode 23 is arranged corresponding to each two data lines DL.

[0149] Exemplarily, as shown in FIG. 21, the first electrode 21 and the second electrode 22 can respectively include 8 electrode traces 202 arranged in parallel, that is, the heating electrode 20 is in an "8U" structure. The plurality of auxiliary electrodes 23 are respectively connected with four electrode traces 202 belonging to the first electrode 21 and the second electrode 22, for example, the plurality of auxiliary electrodes 23 are electrically connected with the four electrode traces 202 on the lower side of the first electrode 21 and the four electrode traces 202 on the upper side of the second electrode 22. In addition, along the first direction X, the distance between adjacent two auxiliary electrodes 23 is equal to the distance between adjacent data lines DL, or in other words, one auxiliary electrode 23 is arranged corresponding to each data line DL.

[0150] Exemplarily, as shown in FIG. 22, the first electrode 21 and the second electrode 22 can respectively include 8 electrode traces 202 arranged in parallel, and the plurality of auxiliary electrodes 23 are electrically connected with all the electrode traces 202 included by the first electrode 21 and the second electrode 22, so that the heating electrode 20 can form a mesh structure. In addition, along the first direction X, the distance between adjacent two auxiliary electrodes 23 is equal to the distance between adjacent data lines DL, or in other words, one auxiliary electrode 23 is arranged corresponding to each data line DL.

[0151] Exemplarily, as shown in FIG. 23, the first electrode 21 and the second electrode 22 can respectively include 8 electrode traces 202 arranged in parallel, and the plurality of auxiliary electrodes 23 are electrically connected with the four electrode traces 202 on the lower side of the first electrode 21 and the four electrode traces 202 on the upper side of the second electrode 22. In addition, along the first direction X, the distance between adjacent two auxiliary electrodes 23 is equal to twice the distance between adjacent data lines DL, or in other words, one auxiliary electrode 23 is arranged corresponding to every two data lines DL.

[0152] Exemplarily, as shown in FIG. 24, the first electrode 21 and the second electrode 22 can respectively include 8 electrode traces 202 arranged in parallel, and the plurality of auxiliary electrodes 23 are electrically connected with all the electrode traces 202 included by the first electrode 21 and the second electrode 22, so that the heating electrode 20 can form a mesh structure. In addition, along the first direction X, the distance between adjacent two auxiliary electrodes 23 is equal to twice the distance between adjacent data lines DL, or in other words, one auxiliary electrode 23 is arranged corresponding to every two data lines DL.

[0153] It should be noted that the embodiments of the present disclosure include but are not limited to the structures shown in FIGS. 17-24, for example, the first electrode 21 and the second electrode 22 can respectively include 2, 4, 6, 8 or any other number of electrode traces 202 arranged in parallel, and the auxiliary electrode 23 can be connected with one or more electrode traces among the plurality of electrode traces, in addition, one auxiliary electrode 23 can be arranged corresponding to every 1, 2, 3, 4 or any other suitable number of data lines.

[0154] Some other embodiments of the present disclosure also provide a preparation method of the array substrate 100, which can be used to prepare the array substrate 100 described in any of the above embodiments. The preparation method of the array substrate 100 can include S100-S400. The sequence of steps S100-S400 is not unique and can be exchanged or combined in a suitable order.

[0155] S100, forming a first insulating layer 30 on one side of the substrate 10.

[0156] Exemplarily, before the step S100, the preparation method of the array substrate 100 can further include sequentially preparing a gate layer, a gate insulating layer, an active layer and a source-drain layer on the substrate 10 by processes such as film forming, photolithography, etching and the like. The gate layer can include a gate line GL and a gate electrode G; the material of the gate insulating layer can include silicon nitride; the active layer can include a semiconductor pattern ACT, and the material of the active layer can be metal oxide or a-Si, etc.

[0157] Exemplarily, the first insulating layer 30 formed by the above step S100 can be a continuous whole layer structure, for example, the first insulating layer 30 is a film layer structure without patterning treatment, which can be patterned in subsequent processes. The preparation process of the first insulating layer 30 can include but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and the material of the first insulating layer 30 can include any one of inorganic insulating materials such as silicon nitride (SiNx, x>0), silicon oxynitride (SiON) and silicon oxide (SiOx, x>0), or can include a single layer or multi-layer structure containing the above inorganic insulating materials. The thickness of the first insulating layer 30 can be 0.1-1000 nm, preferably 1-500 nm.

[0158] S200, forming a heating electrode 20 on the side of the first insulating layer 30 away from the substrate 10.

[0159] The substrate 10 includes a first region 11 and a second region 12, and the orthographic projection of the heating electrode 11 on the substrate 10 is located in the first region 11 and does not coincide with the second region 12.

[0160] Exemplarily, a whole layer of conductive layer can be formed by a process of magnetron sputtering, and then the conductive layer is patterned to obtain the heating electrode by processes including photolithography and etching.

[0161] In the case that the heating electrode 20 comprises an auxiliary electrode, the first electrode, the second electrode and the auxiliary electrode can be simultaneously prepared in the step S200. That is, the auxiliary electrode is made of the same material as the first electrode and the second electrode and is arranged in the same layer as the first electrode and the second electrode.

[0162] S300, forming a second insulating layer 40 on the side of the heating electrode 20 away from the substrate 10.

[0163] Exemplarily, the second insulating layer 40 formed in the step S300 can be a continuous whole layer structure. For example, the second insulating layer 40 can be a film layer structure without being subjected to a patterning process, which can be subjected to a patterning process in the subsequent process. The preparation process of the second insulating layer 40 can include, but is not limited to, CVD, PVD and ALD. The material of the second insulating layer 40 can include any one of inorganic insulating materials such as silicon nitride (SiNx, x>0), silicon oxynitride (SiON) and silicon oxide (SiOx, x>0), and can also include a single layer or a multi-layer structure comprising the above inorganic insulating materials. The thickness of the second insulating layer 40 can be 0.1-10 μm, for example, 0.5-5 μm.

[0164] S400, performing a patterning process on at least one of the first insulating layer 30 and the second insulating layer 40, so that the one or both of the first insulating layer 30 and the second insulating layer 40 subjected to the patterning process has a thickness greater in the first region 11 than in the second region 12. In this way, at least one of the first insulating layer 30 and the second insulating layer 40 subjected to the patterning process does not uniformly extend over the entire array substrate 100, which can reduce the thickness of the first insulating layer 30 and / or the second insulating layer 40 in the region (the second region 12) outside the heating electrode 20 as a whole, thereby reducing the shrinkage stress generated by the first insulating layer 30 and the second insulating layer 40, which is conducive to reducing the Final TP deviation of the array substrate 100 after the annealing process, and is also conducive to reducing the risk of warping of the array substrate 100.

[0165] The step S400 can be performed between the steps S200 and S300 to perform the patterning process on the first insulating layer 30 and not on the second insulating layer. Alternatively, the step S400 can be performed after the step S300 to perform the patterning process on the second insulating layer 40, or simultaneously perform the patterning process on the second insulating layer 40 and the first insulating layer 30.

[0166] In some embodiments, the patterning at least one of the first insulating layer 30 and the second insulating layer 40 in step S400 includes: patterning the first insulating layer 30 after forming the heating electrode 20 in step S200 and before forming the second insulating layer 40 in step S300. Referring to FIGS. 25-32, the method for manufacturing the array substrate includes:

[0167] S100, referring to FIG. 25, forming the first insulating layer 30 on one side of the substrate 10.

[0168] The first insulating layer 30 has a projection on the substrate 10 in the first region 11 and the second region 12. Alternatively, the first insulating layer 30 extends uniformly across the entire array substrate. At this time, the first insulating layer 30 does not represent the final structure, which can be patterned in the subsequent manufacturing process. The preparation process, material and thickness of the first insulating layer 30 are described above, which will not be repeated here. The first region 11 can be a region for forming the heating electrode 20 later, i.e., a region where the heating electrode 20 has a projection on the substrate 10, and the second region 12 refers to other regions except the first region 11.

[0169] Exemplarily, as shown in FIG. 25, the first insulating layer 30 includes a first sub-portion 31 and a third sub-portion 35, the first sub-portion 31 has a projection on the substrate 10 in the first region 11, and the third sub-portion 35 has a projection on the substrate 10 in the second region 12. The first sub-portion 31 and the third sub-portion 35 are different parts of the first insulating layer 30 artificially distinguished for the convenience of description, which can be indistinguishable in structure and material, and there can be no obvious boundary between them in the actual structure; and the first sub-portion 31 refers to the part of the first insulating layer 30 directly below the heating electrode 20 formed in the subsequent process, and the rest is the third portion 33.

[0170] Step S200 of forming the heating electrode 20 on the side of the first insulating layer 30 away from the substrate 10 can include steps S210-S230.

[0171] S210, referring to FIG. 26, forming a conductive layer 20' on the side of the first insulating layer 30 away from the substrate 10.

[0172] Exemplarily, the conductive layer 20' can be formed on one side of the substrate 10 by a magnetron sputtering process, and the conductive layer 20' has a projection on the substrate 10 covering the first region 11 and the second region 12. Alternatively, the conductive layer 20' extends uniformly across the entire array substrate, and at this time, the conductive layer 20' does not represent the final structure, which can be patterned in the subsequent manufacturing process.

[0173] S220, referring to FIG. 27, a first mask layer 61 is formed on the side of the conductive layer 20' away from the substrate 10.

[0174] The first mask layer 61 covers the first area 11 in orthographic projection on the substrate 10, and exposes the second area 12. The forming process of the first mask layer 61 can include, but is not limited to, coating, exposure and development.

[0175] S230, referring to FIG. 28, the conductive layer 20' is patterned with the first mask layer 61 as a mask, and the part of the conductive layer 20' in the second area 12 is removed to form a heating electrode 20.

[0176] Exemplarily, the conductive layer 20' can be etched by a wet etching process to remove the area not covered by the first mask layer 61, and the area covered by the first mask layer 61 is reserved to form the heating electrode 20.

[0177] S400, referring to FIG. 29, the first insulating layer 30 is patterned with the first mask layer 61 as a mask.

[0178] In the above step S400, the thickness of the first insulating layer 30 in the first area 11 can be greater than that in the second area 12. In this way, the thickness of the first insulating layer 30 in the area (the second area 12) outside the heating electrode 20 can be reduced, and the shrinkage stress of the first insulating layer 30 can be reduced, which is beneficial to reduce the Final TP deviation of the array substrate 100 after the annealing process, and is also beneficial to reduce the risk of warping of the array substrate 100. After the above step S400, the first mask layer 61 can be removed (as shown in FIG. 29).

[0179] In each embodiment of the preparation method of the array substrate of the present disclosure, some parameters (such as the slope of the sidewall of the first insulating layer 30 and the second insulating layer 40) of the first insulating layer 30 and the second insulating layer 40 in the preparation process can refer to the description of the array substrate above, and will not be described one by one below.

[0180] In some embodiments, the above step S400 can include one of S410 and S420, that is, the above step S400 can be divided into two ways of S410 and S420.

[0181] S410, as shown in FIG. 29, the third sub-portion 35 is removed.

[0182] In the step S410, the first insulating layer 30 in the second area 12 is removed, and at least part of the first insulating layer 30 in the second area 12 is reserved. In this way, the first insulating layer 30 can extend over the entire array substrate, but the thickness of the first insulating layer 30 in the first area 11 can be greater than the thickness of the first insulating layer 30 in the second area 12. For example, the thickness of the first insulating layer 30 can be controlled by controlling the etching time and etching rate, so as to reserve the part of the first insulating layer 30 in the second area 12 to form the second sub-portion 32.

[0183] In the step S420, referring to FIG. 30, part of the third sub-portion 35 is removed, and part of the third sub-portion 35 is reserved to form the second sub-portion 32.

[0184] In the step S410, the first insulating layer 30 in the second area 12 is removed, and at least part of the first insulating layer 30 in the second area 12 is reserved. In this way, the first insulating layer 30 can extend over the entire array substrate, but the thickness of the first insulating layer 30 in the first area 11 can be greater than the thickness of the first insulating layer 30 in the second area 12. For example, the thickness of the first insulating layer 30 can be controlled by controlling the etching time and etching rate, so as to reserve the part of the first insulating layer 30 in the second area 12 to form the second sub-portion 32.

[0185] In this way, the thickness of the first insulating layer 30 in the area (the second area 12) other than the heating electrode 20 can be reduced, and the shrinkage stress of the first insulating layer 30 can be reduced, which is beneficial to reduce the Final TP deviation of the array substrate 100 after the annealing process, and is also beneficial to reduce the risk of warping of the array substrate 100. In addition, the second sub-portion 32 can protect the semiconductor pattern ACT from being damaged in the process of etching the first insulating layer 30.

[0186] In the step S300, referring to FIGS. 31 and 32, the second insulating layer 40 is formed on the side of the heating electrode 20 away from the substrate 10.

[0187] The second insulating layer 40 is formed on the substrate 10, and the second insulating layer 40 has a thickness in the first area 11 and a thickness in the second area 12. The thickness of the second insulating layer 40 in the first area 11 is equal to the thickness of the second insulating layer 40 in the second area 12. That is, the second insulating layer 40 formed in the step S300 is a continuous whole layer structure, for example, the second insulating layer 40 can be a film layer structure without patterning treatment. The preparation process of the second insulating layer 40 can include but is not limited to CVD, PVD and ALD, and the material of the second insulating layer 40 can include any one of inorganic insulating materials such as silicon nitride (SiNx, x>0), silicon oxynitride (SiON) and silicon oxide (SiOx, x>0), and can also include a single layer or a multi-layer structure containing the above inorganic insulating materials. The thickness of the second insulating layer 40 can be 0.1-10 μm, for example, 0.5-5 μm.

[0188] In the case where the first insulating layer 30 in the second region 12 is removed entirely as shown in Fig. 29, a structure as shown in Fig. 31 can be formed after the step S300, and an array substrate as shown in Fig. 4 can be formed after the pixel electrode and the common electrode are prepared successively. In the case where the first insulating layer 30 in the second region 12 is removed partially and at least a part (the second sub-portion 32) in the second region 12 is reserved as shown in Fig. 30, a structure as shown in Fig. 32 can be formed after the step S300, and an array substrate as shown in Fig. 5 can be formed after the pixel electrode and the common electrode are prepared successively.

[0189] In other embodiments, the step S400 of patterning at least one of the first insulating layer 30 and the second insulating layer 40 includes patterning the second insulating layer 40 after the step S300 of forming the second insulating layer. In this case, the method of preparing the array substrate includes:

[0190] S100, as shown in Fig. 25, forming the first insulating layer 30 on one side of the substrate 10.

[0191] The first insulating layer 30 extends uniformly over the entire array substrate, i.e. the orthographic projection of the first insulating layer 30 on the substrate 10 covers the first region 11 and the second region 12. The first insulating layer 30 formed in this case does not represent the final structure, and can be patterned in the subsequent preparation process. The preparation process, material and thickness of the first insulating layer 30 are described above, and will not be described here again.

[0192] S200, forming the heating electrode 20 on the side of the first insulating layer 30 away from the substrate 10. Exemplarily, the step S200 of forming the heating electrode 20 on the side of the first insulating layer 30 away from the substrate 10 can include steps S210-S230.

[0193] S210, as shown in Fig. 26, forming a conductive layer 20' on the side of the first insulating layer 30 away from the substrate 10.

[0194] Exemplarily, the conductive layer 20' can be formed on the side of the substrate 10 by a process of magnetron sputtering, and the orthographic projection of the conductive layer 20' on the substrate 10 covers the first region 11 and the second region 12. In other words, the conductive layer 20' extends uniformly over the entire array substrate, and the conductive layer 20' does not represent the final structure, and can be patterned in the subsequent preparation process.

[0195] S220, as shown in Fig. 27, forming a first mask layer 61 on the side of the conductive layer 20' away from the substrate 10 by using a metal mask plate (not shown).

[0196] The first mask layer 61 covers the first area 11 in the orthographic projection on the substrate 10, and exposes the second area 12. The forming process of the first mask layer 61 can include, but is not limited to, coating, exposure and development.

[0197] S230, referring to FIG. 28, the conductive layer 20' is patterned with the first mask layer 61 as a mask, and the part of the conductive layer 20' located in the second area 12 is removed, to form the heating electrode 20.

[0198] Exemplarily, the conductive layer 20' can be etched by a wet etching process to remove the area not covered by the first mask layer 61, and to retain the area covered by the first mask layer 61 to form the heating electrode 20.

[0199] S300, referring to FIG. 33, the second insulating layer 40 is formed on the side of the heating electrode 20 and the first insulating layer 30 away from the substrate 10.

[0200] The second insulating layer 40 formed by the above step S300 can be a continuous whole layer structure, for example, the second insulating layer 40 can be a film layer structure without being patterned, which can be patterned in the subsequent process. The preparation process of the second insulating layer 40 can include, but is not limited to, CVD, PVD and ALD, and the material of the second insulating layer 40 can include any one of inorganic insulating materials such as silicon nitride (SiNx, x>0), silicon oxynitride (SiON) and silicon oxide (SiOx, x>0), and can also include a single layer or multi-layer structure containing the above inorganic insulating materials. The thickness of the second insulating layer 40 can be

[0201] S400, the second insulating layer 40 is patterned. Exemplarily, the step S400 of patterning the second insulating layer 40 can include step S430 and step S440.

[0202] S430, referring to FIG. 34, the second mask layer 62 is formed on the side of the second insulating layer 40 away from the substrate.

[0203] The orthographic projection of the second mask layer 62 on the substrate 10 is located in the first area 11, and covers the orthographic projection of the heating electrode 20 on the substrate 10. The boundary of the orthographic projection of the second mask layer 62 on the substrate 10 has a first interval D4 with the boundary of the orthographic projection of the heating electrode 20 on the substrate 10.

[0204] Exemplarily, the above step S430 can include steps S431-S433.

[0205] S431, a photoresist layer is formed on the side of the second insulating layer 40 away from the substrate 10.

[0206] Exemplarily, the photoresist layer can be formed by a coating process, and a normal projection of the photoresist layer on the substrate covers the first region and the second region, that is, the photoresist layer is a film layer extending on the entire array substrate.

[0207] S432, a weak exposure process is performed on the photoresist layer by using the same metal mask plate as that for forming the first mask layer.

[0208] Through the above step S432, a photoresist pattern slightly larger than the heating electrode can be obtained, and the number of mask plates used can be reduced, thereby reducing the preparation cost of the array substrate. Moreover, since the same mask plate is used and the second mask layer is formed by weak exposure, the second insulating layer (as shown in FIG. 35) formed can completely cover the sidewall and top surface of the heating electrode, thereby effectively avoiding the risk of disconnection between the heating electrode and the pixel electrode and the common electrode formed subsequently.

[0209] S433, the photoresist layer is developed to form the second mask layer.

[0210] S440, referring to FIG. 35, the second insulating layer 40 is patterned by taking the second mask layer 62 as a mask.

[0211] In the above step S440, the region of the second insulating layer 40 not covered by the second mask layer 62 can be removed, and the remaining second insulating layer 40 can cover the surface of the heating electrode 20 away from the substrate 10 and the sidewall of the heating electrode 20.

[0212] Exemplarily, the second insulating layer 40 can be patterned by a wet etching process or a dry etching process.

[0213] In some embodiments, after the above step S400, the pixel electrode and the common electrode can be prepared on the side of the second insulating layer 40 away from the substrate 10, to form an array substrate as shown in FIG. 8.

[0214] In another embodiment, after the above step S440, the preparation method further includes a step S450.

[0215] S450, the first insulating layer 30 is patterned by taking the second mask layer 62 as a mask.

[0216] Exemplarily, in the case where the first insulating layer 30 and the second insulating layer 40 comprise the same material, the above step S450 and the step S440 can be completed synchronously, for example, by performing a once etching process to pattern the second insulating layer 40 and the first insulating layer 30 at the same time.

[0217] In some embodiments, the step S450 can include one of S451 and S452, i.e., the step S450 can be performed in two ways as S451 and S452.

[0218] S451, as shown in FIG. 36, the third sub-portion 35 is removed.

[0219] In the step S410, the first insulating layer 30 within the second region 12 is removed, for example, the first insulating layer 30 within the second region 12 can be removed by over-etching the first insulating layer 30 by controlling the etching time and etching rate, at this time, the orthographic projection of the first insulating layer 30 on the substrate 10 does not overlap with the second region 12. In addition, after the step S451, the array substrate 100 as shown in FIG. 7 can be formed after the pixel electrode and the common electrode are prepared.

[0220] S452, as shown in FIG. 37, the third sub-portion 35 is partially removed, and the remaining third sub-portion 35 forms the second sub-portion 32.

[0221] In the step S410, the first insulating layer 30 within the second region 12 is removed, and at least part of the first insulating layer 30 within the second region 12 is retained, so that the first insulating layer 30 can extend over the entire array substrate, but the thickness of the first insulating layer 30 within the first region 11 is greater than that within the second region 12. For example, the thickness of the first insulating layer 30 within the second region 12 can be controlled by controlling the etching time and etching rate, so that the first insulating layer 30 within the second region 12 is retained to form the second sub-portion 32. In addition, after the step S452, the array substrate 100 as shown in FIG. 6 can be formed after the pixel electrode and the common electrode are prepared.

[0222] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto, any person skilled in the art can think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

An array substrate, comprising: a substrate and a heating electrode provided on one side of the substrate, the substrate comprising a first region and a second region, a projection of the heating electrode on the substrate being located in the first region and not overlapping the second region; a first insulating layer provided on a side of the heating electrode close to the substrate and in contact with the heating electrode; a second insulating layer provided on a side of the heating electrode away from the substrate and in contact with the heating electrode; wherein at least one of the first insulating layer and the second insulating layer has a thickness in the first region greater than a thickness in the second region. The array substrate according to claim 1, wherein a projection of the first insulating layer on the substrate is located in the first region and does not overlap the second region; a projection of the second insulating layer on the substrate is located in the first region and the second region, and the thickness of the second insulating layer in the first region is equal to the thickness of the second insulating layer in the second region. The array substrate according to claim 1, wherein the first insulating layer comprises a first sub-portion and a second sub-portion; a projection of the first sub-portion on the substrate is located in the first region and covers the projection of the heating electrode on the substrate; a projection of the second sub-portion on the substrate is located in the second region and does not overlap the projection of the heating electrode on the substrate; the thickness of the first sub-portion is greater than the thickness of the second sub-portion; a projection of the second insulating layer on the substrate is located in the first region and the second region, and the thickness of the second insulating layer in the first region is equal to the thickness of the second insulating layer in the second region. The array substrate according to claim 2 or 3, wherein in a cross section of the first insulating layer and the heating electrode perpendicular to an extending direction of the heating electrode, the first insulating layer comprises a trapezoid located in the first region, a boundary of the heating electrode close to the substrate being located in a range of a boundary of the trapezoid away from the substrate. The array substrate according to claim 1, wherein the first insulating layer comprises a first sub-portion and a second sub-portion; a projection of the first sub-portion on the substrate is located in the first region and covers the projection of the heating electrode on the substrate; a projection of the second sub-portion on the substrate is located in the second region and does not overlap the projection of the heating electrode on the substrate; the thickness of the first sub-portion is greater than the thickness of the second sub-portion; a projection of the second insulating layer on the substrate is located in the first region and does not overlap the second region. The array substrate according to claim 3 or 5, wherein, The first sub-portion has a thickness H1 and the second sub-portion has a thickness H2, The array substrate according to claim 6, further comprising: a thin film transistor provided between the substrate and the first insulating layer, comprising a gate, a semiconductor pattern, a source pattern and a drain pattern; the semiconductor pattern is provided on a side of the gate away from the substrate, the source pattern and the drain pattern are provided on a side of the semiconductor pattern away from the substrate, and there is a gap between the source pattern and the drain pattern; The second sub-portion is located between the source pattern and the drain pattern and is in contact with the semiconductor pattern. The array substrate according to claim 1, wherein The first insulating layer has a thickness in the first region that is equal to a thickness in the second region. The second insulating layer has a thickness in the first region that is equal to a thickness in the second region. The array substrate according to any one of claims 2-8, wherein An angle between a sidewall of the first insulating layer and a reference plane is less than or equal to 50°; the reference plane is parallel to the substrate. The array substrate according to claim 1, wherein The first insulating layer has a thickness in the first region that is equal to a thickness in the second region. The second insulating layer has a thickness in the first region that is equal to a thickness in the second region. The array substrate according to claim 5, 8 or 10, wherein The second insulating layer covers a surface of the heating electrode that is away from the substrate and a sidewall of the heating electrode. The array substrate according to claim 11, wherein A surface of the heating electrode that is in contact with the first insulating layer is a first surface, a surface of the first insulating layer that is in contact with the heating electrode is a second surface, the first surface is located in the second surface, and a boundary of the first surface has a spacing from a boundary of the second surface. The array substrate according to claim 11, wherein In a projection of the second insulating layer and the heating electrode on the substrate, the second insulating layer covers the heating electrode, and a boundary of the second insulating layer has a first spacing from a boundary of the heating electrode, the first spacing is greater than or equal to 0.5 μm. The array substrate according to claim 13, wherein An angle between a sidewall of the second insulating layer and a reference plane is less than or equal to 50°; the reference plane is parallel to the substrate. The array substrate according to claim 11, wherein A boundary of the second insulating layer that is close to a surface of the substrate coincides with a boundary of the first insulating layer that is away from the surface of the substrate. The array substrate according to any one of claims 1 to 15, wherein The heating electrode comprises: A first electrode extends along a first direction and comprises a first end and a second end; A second electrode extends along the first direction and is arranged side by side with the first electrode, the second electrode comprises a third end that is located on a same side as the first end, and a fourth end that is located on a same side as the second end; the first end and the third end are electrically connected to a power supply with different polarities, and the second end and the fourth end are electrically connected; and The array substrate according to claim 14, wherein The first electrode comprises a first portion and a second portion, the first portion is located in the first region, the second portion is located in the second region, and the first portion and the second portion are electrically connected to each other. The array substrate according to claim 14, wherein The second electrode comprises a third portion and a fourth portion, the third portion is located in the first region, the fourth portion is located in the second region, and the third portion and the fourth portion are electrically connected to each other. A plurality of auxiliary electrodes are arranged between the first electrode and the second electrode and are spaced apart along the first direction, two ends of the auxiliary electrodes are connected to the first electrode and the second electrode respectively, and the resistance of the plurality of auxiliary electrodes gradually decreases in a direction away from the first end and the third end. The array substrate according to claim 16, wherein The plurality of auxiliary electrodes comprise the same material as the first electrode and the second electrode and are arranged in the same layer, and the line width of the plurality of auxiliary electrodes gradually decreases in a direction away from the first end and the third end. The array substrate according to claim 16 or 17, wherein The plurality of auxiliary electrodes are equally spaced apart along the first direction. The array substrate according to claim 18, further comprising: A plurality of data signal lines are spaced apart along the first direction and each extends along a second direction; The second direction intersects the first direction; The auxiliary electrode has a projection on the substrate that at least partially overlaps a projection of the data signal line on the substrate. The array substrate according to claim 19, wherein: The distance between two adjacent auxiliary electrodes is D1, the distance between two adjacent data signal lines is D2, and D1 = NxD2, where N is a positive integer. The array substrate according to any one of claims 16-20, wherein The first electrode and the second electrode each comprise an electrode trace that extends along the first direction. The array substrate according to any one of claims 16-20, wherein The first electrode and the second electrode each comprise a plurality of electrode traces arranged in parallel, the plurality of electrode traces are spaced apart along a second direction and each extends along the first direction, and ends of the plurality of electrode traces along the first direction are connected to each other; The plurality of auxiliary electrodes are connected to two closest electrode traces belonging to the first electrode and the second electrode respectively. The array substrate according to any one of claims 16-20, wherein The first electrode and the second electrode each comprise a plurality of electrode traces arranged in parallel, the plurality of electrode traces are spaced apart along a second direction and each extends along the first direction, and ends of the plurality of electrode traces along the first direction are connected to each other; The auxiliary electrode is connected to an equal number of electrode traces belonging to the first electrode and the second electrode respectively. A method for manufacturing an array substrate, comprising: forming a first insulating layer on one side of a substrate; forming a heating electrode on a side of the first insulating layer away from the substrate; The substrate comprises a first region and a second region, a projection of the heating electrode on the substrate is located in the first region and does not overlap the second region; forming a second insulating layer on a side of the heating electrode away from the substrate; and forming a plurality of auxiliary electrodes on a side of the second insulating layer away from the substrate. At least one of the first and second insulating layers is patterned so that the thickness of the patterned one or both of the first and second insulating layers is greater in the first region than in the second region. The manufacturing method of claim 24, wherein The patterning of at least one of the first and second insulating layers includes patterning the first insulating layer after the heating electrode is formed and before the second insulating layer is formed; The manufacturing method includes: forming a first insulating layer on one side of the substrate; the orthographic projection of the first insulating layer on the substrate is located in the first region and the second region; forming a conductive layer on the side of the first insulating layer away from the substrate; the orthographic projection of the conductive layer on the substrate covers the first region and the second region; forming a first mask layer on the side of the conductive layer away from the substrate; the orthographic projection of the first mask layer on the substrate covers the first region and exposes the second region; patterning the conductive layer using the first mask layer as a mask to remove the portion of the conductive layer located in the second region, forming the heating electrode; patterning the first insulating layer using the first mask layer as a mask so that the thickness of the first insulating layer in the first region is greater than in the second region; forming a second insulating layer on the side of the heating electrode away from the substrate; the orthographic projection of the second insulating layer on the substrate is located in the first region and the second region, and the thickness of the second insulating layer in the first region is equal to the thickness of the second insulating layer in the second region. The manufacturing method of claim 24, wherein The patterning of at least one of the first and second insulating layers includes patterning the second insulating layer after the second insulating layer is formed; the manufacturing method includes: forming a first insulating layer on one side of the substrate; the orthographic projection of the first insulating layer on the substrate is located in the first region and the second region; forming a heating electrode on the side of the first insulating layer away from the substrate; the orthographic projection of the heating electrode on the substrate covers the first region and does not overlap the second region; forming a second insulating layer on the side of the heating electrode and the first insulating layer away from the substrate; forming a second mask layer on the side of the second insulating layer away from the substrate; the orthographic projection of the second mask layer on the substrate is located in the first region and covers the orthographic projection of the heating electrode on the substrate, and the boundary of the orthographic projection of the second mask layer on the substrate has a spacing from the boundary of the orthographic projection of the heating electrode on the substrate; patterning the second insulating layer using the second mask layer as a mask to remove the region of the second insulating layer not covered by the second mask layer, the second insulating layer covering the surface of the heating electrode away from the substrate and the sidewall of the heating electrode. The manufacturing method of claim 26, wherein The forming the heating electrode on a side of the first insulating layer away from the substrate comprises: forming a conductive layer on a side of the first insulating layer away from the substrate; forming a first mask layer on a side of the conductive layer away from the substrate by using a metal mask plate; performing a patterning process on the conductive layer by using the first mask layer as a mask to form the heating electrode; The forming the second mask layer on a side of the second insulating layer away from the substrate comprises: forming a photoresist layer on a side of the second insulating layer away from the substrate; a normal projection of the photoresist layer on the substrate covers the first region and the second region; performing a weak exposure process on the photoresist layer by using the metal mask plate; developing the photoresist layer to form the second mask layer. The preparation method according to claim 26, wherein, after the patterning process on the second insulating layer, the preparation method further comprises: performing a patterning process on the first mask layer by using the second mask layer as a mask. The production method according to claim 25 or 26, wherein Before the patterning process on the first insulating layer, the first insulating layer comprises a first sub-portion and a third sub-portion, a normal projection of the first sub-portion on the substrate is located in the first region, and a normal projection of the third sub-portion on the substrate is located in the second region; The patterning process on the first insulating layer comprises: removing the third sub-portion; and a normal projection of the first insulating layer on the substrate does not coincide with the second region. The production method according to claim 25 or 26, wherein Before the patterning process on the first insulating layer, the first insulating layer comprises a third sub-portion, and a normal projection of the third sub-portion on the substrate is located in the second region; The patterning process on the first insulating layer according to the second mask layer comprises: removing part of the third sub-portion, and a part of the third sub-portion remaining forms a second sub-portion. A display panel comprises: The array substrate according to any one of claims 1-23; A color filter substrate is arranged opposite to the array substrate; A liquid crystal layer is arranged between the array substrate and the color filter substrate. A display device comprises: The display panel according to claim 31; A backlight module is arranged on a backlight side of the display panel.

Images