Uncooled infrared focal plane array readout integrated circuit, and detector

Abstract

An uncooled infrared focal plane array readout integrated circuit (200), and a detector. The readout integrated circuit (200) comprises a pixel circuit module (10) and a readout integrated circuit bias module (30). The pixel circuit module (10) comprises a pixel resistor (13), a correction voltage terminal (VEB), a first node (N1), a pixel bias sub-module (12), and a correction sub-module (11), wherein the pixel bias sub-module (12) is connected to the pixel resistor (13), and the correction sub-module (11) is connected to the correction voltage terminal (VEB), so as to correct a deviation of an output result from the readout integrated circuit (200) caused by a resistance deviation of the pixel resistor (13). The readout integrated circuit bias module (30) comprises a working resistor (R), a bias voltage provision module (33), and a feedback module (32), wherein a connection terminal of the bias voltage provision module (33) is connected to the feedback module (32), and an output end thereof is connected to one end of the working resistor (R); the other end of the working resistor (R) is connected to the first node (N1); the voltage of the bias voltage provision module (33) fluctuates with at least one of a correction voltage (Veb) and a target temperature of the pixel resistor (13); and the feedback module (32) generates a feedback current (I0) which corresponds to the voltage (Vd) of the first node (N1), and provides the feedback current (I0) to the bias voltage provision module (33).

Description

Uncooled infrared focal plane array readout circuit and detector TECHNICAL FIELD

[0001] The present application relates to the technical field of uncooled infrared focal plane array detector, and particularly relates to an uncooled infrared focal plane array readout circuit and detector. BACKGROUND

[0002] The uncooled infrared focal plane array (UFPA) readout integrated circuit (ROIC) can integrate and convert the weak electrical signal generated by the uncooled detector array and then output. Generally, the uncooled infrared focal plane array readout circuit includes a bias module connected with the infrared sensitive pixel and providing the bias voltage required for the corresponding infrared sensitive pixel, a correction sub-module connected with the infrared sensitive pixel, and an integration module, and an analog-digital conversion module connected with the integration module. For different infrared sensitive pixels in the uncooled infrared focal plane array, the corresponding correction sub-module corrects the deviation of the readout circuit output caused by the resistance deviation between different pixel resistors. However, the configuration of different correction voltages for different pixel correction sub-modules will affect the readout effect of the readout circuit. SUMMARY

[0003] The present application provides an uncooled infrared focal plane array readout circuit and detector to improve the stability of the response rate of the uncooled infrared focal plane array readout circuit.

[0004] The present application provides an uncooled infrared focal plane array readout circuit, which includes: a pixel circuit module including a pixel resistor, a correction voltage end, a first node, a pixel bias sub-module and a correction sub-module connected to the first node, wherein the pixel bias sub-module is connected with the pixel resistor and is used to provide a pixel bias voltage for the pixel resistor; the correction sub-module is connected with the correction voltage end and is used to correct the deviation of the readout circuit output caused by the resistance deviation of the pixel resistor; and a readout circuit bias module including a working resistor, a bias voltage providing module and a feedback module connected thereto; wherein one connection end of the bias voltage providing module is connected with the feedback module, and the output end of the bias voltage providing module is connected with one end of the working resistor; the other end of the working resistor is connected with the first node; the voltage of the output end of the bias voltage providing module fluctuates with at least one of the voltage of the correction voltage end and the target temperature of the pixel resistor; and the feedback module is used to generate a feedback current corresponding to the voltage of the first node according to the voltage of the first node, and provide the feedback current to the bias voltage providing module.

[0005] In some embodiments, the uncooled infrared focal plane array readout circuit further comprises a voltage detection module connected between the feedback module and the first node, for detecting the voltage of the first node and providing the detected voltage of the first node to the feedback module.

[0006] In some embodiments, the feedback module has an input end and an output end, the input end of the feedback module is connected with the voltage detection module, and the output end of the feedback module is connected with the connection end of the bias voltage providing module.

[0007] In some embodiments, the feedback current is proportional to the voltage of the first node detected by the voltage detection module.

[0008] In some embodiments, the feedback current is inversely proportional to the voltage of the first node detected by the voltage detection module.

[0009] In some embodiments, the uncooled infrared focal plane array readout circuit further comprises: an integration module connected with the first node, for integrating the voltage of the first node to generate a corresponding analog response signal.

[0010] In some embodiments, the uncooled infrared focal plane array readout circuit further comprises: a driving module connected between the integration module and the first node, capable of increasing the current from the first node to the integration module.

[0011] In some embodiments, the voltage detection module has a detection end; wherein, the detection end is connected between the driving module and the integration module; or the detection end is connected between the driving module and the first node.

[0012] In some embodiments, the uncooled infrared focal plane array readout circuit further comprises: an analog-to-digital converter connected with the integration module, for converting the analog response signal generated by the integration module into a digital signal; an output unit connected with the analog-to-digital converter, for processing the digital signal converted by the analog-to-digital converter to generate processed data, and outputting the processed data.

[0013] In some embodiments, the pixel biasing sub-module comprises a first field effect transistor, a first pole of the first field effect transistor is connected with the first node, a second pole of the first field effect transistor is connected with the pixel resistance, a control pole of the first field effect transistor is connected with a control voltage end, and the pixel biasing sub-module provides the pixel biasing voltage for the pixel resistance under the control voltage provided by the control voltage end.

[0014] In some embodiments, the correction submodule comprises a second field effect transistor and a correction resistor, a first pole of the second field effect transistor is connected with the correction resistor, a second pole of the second field effect transistor is connected with the first node, and a control pole of the second field effect transistor is connected with the correction voltage terminal.

[0015] In some embodiments, the uncooled infrared focal plane array has a plurality of pixel units arranged in an array, each of the pixel units has at least one infrared sensitive pixel, and the pixel resistance is the resistance of the at least one infrared sensitive pixel in each of the pixel units.

[0016] Embodiments of the present application also provide an uncooled infrared focal plane array readout circuit detector, which comprises the uncooled infrared focal plane array readout circuit as described above.

[0017] The uncooled infrared focal plane array readout circuit and the uncooled infrared focal plane array readout circuit detector provided by the embodiments of the present application have the biasing module of the readout circuit arranged to comprise a biasing voltage providing module and a feedback module connected in series; one connection end of the biasing voltage providing module is connected with the feedback module; and the feedback module is used to generate a feedback current corresponding to the voltage of the first node and provide the feedback current to the biasing voltage providing module, so that the output end of the biasing voltage providing module has a stable voltage, the responsivity of the uncooled infrared focal plane array readout circuit can be stabilized, and the readout effect of the readout circuit is improved.

[0018] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related art, the drawings needed to be used in the embodiments or the related art description will be briefly introduced. The drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creating any creative labor on the basis of these drawings.

[0020] FIG. 1 is a partial circuit schematic diagram of an uncooled infrared focal plane array readout circuit in the related art.

[0021] FIG. 2 is a module schematic diagram of an uncooled infrared focal plane array readout circuit and a corresponding uncooled infrared focal plane array provided by an embodiment of the present application.

[0022] FIG. 3 is a partial circuit schematic diagram of an uncooled infrared focal plane array readout circuit provided by an embodiment of the present application.

[0023] Fig. 4 is a partial circuit schematic diagram of a non-cooled infrared focal plane array readout circuit according to another embodiment of the present application.

[0024] Fig. 5 is a partial circuit schematic diagram of a non-cooled infrared focal plane array readout circuit according to yet another embodiment of the present application. DETAILED DESCRIPTION

[0025] The exemplary embodiments will be described in detail herein with reference to the attached drawings. In the following description, unless otherwise indicated, like numbers in the attached drawings refer to the same or similar elements. The following detailed description includes specific details for the purpose of providing a thorough understanding of the exemplary embodiments. However, it will be apparent to those skilled in the art that the exemplary embodiments can be practiced without these specific details. In some instances, well-known structures and components are not described in detail in order to avoid obscuring the understanding of the present description.

[0026] Some terms used herein are explained as follows.

[0027] Transconductance g m : the amount of change in transistor drain current divided by the amount of change in gate-source voltage, which represents the ability of the transistor to convert voltage to current.

[0028] Responsivity: the output signal voltage generated by a pixel per unit of radiant energy, which is commonly referred to as the response of the pixel to different radiant energy of objects.

[0029] As shown in Fig. 1, in the related art, a non-cooled infrared focal plane array readout circuit includes a bias module 30' connected to and providing a bias voltage required for operation of an infrared sensitive pixel 1001', a correction sub-module 11' connected to the infrared sensitive pixel 1001', an integration module 20' connected to the correction sub-module 11', and an analog-to-digital conversion module (not shown) connected to the integration module 20'. For different infrared sensitive pixels 1001' in the non-cooled infrared focal plane array, the corresponding correction sub-module 11' corrects the deviation in the output of the readout circuit caused by the resistance deviation between different pixel resistances. The inventors have found through analysis and research that configuring different correction voltages for different correction sub-modules 11' can directly result in different responsivities of the readout circuit.

[0030] Specifically, as shown in Fig. 1, Rs is the resistance of the infrared sensitive pixel 1001' (referred to as pixel resistance), and the response relationship between the resistance value and the target temperature can be expressed as: Rs = R so exp(TCR*ΔTt), where R so is the initial value of the pixel resistance, TCR is the resistance temperature coefficient, and ΔTt is the change in the target temperature. This relationship Rs = R soexp(TCR*ΔTt) reflects the different resistance of the pixel resistance Rs at different target temperature. The transistor M1 converts the resistance change of Rs into the corresponding response current I1, where I1=Vs / Rs. Since the Rd of the correction sub-module 11' is not sensitive to the target temperature, I2 is a constant current, so the current I4 flowing through R is I1-I2. The function of the biasing module 30' is to provide the bias voltage required for the entire readout circuit to work, which can be adjusted by adjusting the overall voltage of the Vd node to adjust the output voltage Vo of the integration module 20'.

[0031] The integration module 20' converts the voltage Vd into an integral current, and then integrates the integral current to obtain the output voltage Vo, so Vo=K*Vd, K is the coefficient of Vd mapped to Vo.

[0032] The biasing module 30' includes: a current source, which provides a current with a size of I0; and a bias voltage providing module 33', which is connected with an adjusting voltage end VT, the voltage of the adjusting voltage end is Vt, and the current I3 of the transistor inside the bias voltage providing module 33' is I0-I4=I0+I2-I1, so Vd=Vt+Vg s3 -I4R, Vg s3 =I3 / g m3 By combining the above formulas, the response rate formula is obtained as:

[0033] Since , the transconductance of the transistor inside the bias voltage providing module 33' changes with different I3, so Vg s3 changes accordingly, so Vg s3 is different in size at different ranges of target temperature or with different correction voltages Veb, and the response rate obtained is also different, and the slope of the change of the response rate is also different. That is, the response rate is affected by Vg s3 , and also changes nonlinearly with the target temperature and the correction voltage Veb, thereby affecting the imaging and the effect of adjusting the correction voltage Veb on the pixel deviation correction.

[0034] To this end, the application provides a non-cooled infrared focal plane array readout circuit and a detector. The non-cooled infrared focal plane array readout circuit comprises a pixel circuit module and a readout circuit biasing module. The pixel circuit module comprises a pixel resistor, a correction voltage terminal, a first node, a pixel biasing submodule connected to the first node, and a correction submodule, wherein the pixel biasing submodule is connected to the pixel resistor and is configured to provide a pixel biasing voltage for the pixel resistor; and the correction submodule is configured to correct a deviation of an output result of the readout circuit caused by a resistance deviation of the pixel resistor. The readout circuit biasing module comprises a working resistor, a biasing voltage providing module connected to the working resistor, and a feedback module, wherein one connection end of the biasing voltage providing module is connected to the feedback module, an output end of the biasing voltage providing module is connected to one end of the working resistor, the other end of the working resistor is connected to the first node, a voltage of the output end of the biasing voltage providing module fluctuates with at least one of a voltage of the correction voltage terminal and a target temperature of the pixel resistor, and the feedback module is configured to generate a feedback current corresponding to the voltage of the first node according to the voltage of the first node and provide the feedback current to the biasing voltage providing module. In the non-cooled infrared focal plane array readout circuit, the readout circuit biasing module comprises the biasing voltage providing module and the feedback module connected to each other, one connection end of the biasing voltage providing module is connected to the feedback module, and the feedback module is configured to generate a feedback current corresponding to the voltage of the first node according to the voltage of the first node and provide the feedback current to the biasing voltage providing module. Since the voltage stability of the output end of the biasing voltage providing module can affect the response rate of the non-cooled infrared focal plane array readout circuit, the arrangement of the non-cooled infrared focal plane array readout circuit can make the output end of the biasing voltage providing module have stable voltage, stabilize the response rate of the non-cooled infrared focal plane array readout circuit, and improve the readout effect of the readout circuit.

[0035] The non-cooled infrared focal plane array readout circuit and the detector provided by the embodiment of the application will be described in detail below with reference to FIGS. 2-5.

[0036] Referring to FIGS. 2 and 3, the application provides a non-cooled infrared focal plane array readout circuit 200. The non-cooled infrared focal plane array readout circuit 200 can be applied to signal readout of a non-cooled infrared focal plane array 100, the non-cooled infrared focal plane array 100 having a plurality of pixel units 101 arranged in an array, each pixel unit 101 having at least one infrared sensitive pixel 1001. The non-cooled infrared focal plane array readout circuit 200 comprises a pixel circuit module 10 and a readout circuit biasing module 30.

[0037] The pixel circuit module 10 comprises a pixel resistor 13, a correction voltage terminal VEB, a first node N1, a pixel biasing sub-module 12 connected to the first node N1, and a correction sub-module 11.

[0038] It can be understood that the pixel resistor 13 is the resistance of the at least one infrared sensitive pixel 1001 in the pixel unit 101. Each pixel resistor 13 is the resistance of the at least one infrared sensitive pixel 1001 in the corresponding pixel unit 101.

[0039] The uncooled infrared focal plane array readout circuit 200 can comprise one pixel circuit module or a plurality of pixel circuit modules. For the case of comprising one pixel circuit module, the pixel resistors 13 corresponding to the pixel units 101 can be respectively connected to the pixel circuit module 10 through timing control or other designs. For the case of comprising a plurality of pixel circuit modules 10, the plurality of pixel circuit modules 10 can be arranged in the same column or the same row, or in other arrangements. Taking the uncooled infrared focal plane array 100 having M rows and N columns of pixel units 101 as an example, for the case of the uncooled infrared focal plane array readout circuit 200 comprising 1 row and N columns of pixel circuit modules, the pixel resistors 13 corresponding to different pixel units 101 in each column can be respectively connected to the pixel circuit modules 10 in the corresponding column through timing control or other designs. Similarly, for the case of the uncooled infrared focal plane array readout circuit 200 comprising M rows and 1 column of pixel circuit modules, the pixel resistors 13 corresponding to different pixel units 101 in each row can be respectively connected to the pixel circuit modules 10 in the corresponding row through timing control or other designs.

[0040] The pixel biasing sub-module 12 is connected to the at least one pixel resistor 13 and provides a pixel biasing voltage Vs to the at least one pixel resistor 13.

[0041] The correction sub-module 11 is configured to correct the deviation of the readout circuit output caused by the resistance deviation of the pixel resistor 13. The correction sub-modules 11 corresponding to different pixel resistors 13 can be configured with different correction voltages to correct the deviation of the readout circuit output caused by the resistance deviation among different pixel resistors 13.

[0042] The readout circuit biasing module 30 comprises a working resistor R, a bias voltage providing module 33 connected thereto, and a feedback module 32; wherein one connection end of the bias voltage providing module 33 is connected to the feedback module 32, the other connection end of the bias voltage providing module 33 is connected to one end of the working resistor R, and the connection end of the bias voltage providing module 33 connected to the working resistor R is the output end of the bias voltage providing module 33. The other end of the working resistor R is connected to the first node N1, and the voltage of the output end of the bias voltage providing module 33 fluctuates with the voltage Veb (hereinafter referred to as the correction voltage Veb) of the correction voltage end VEB. The feedback module is configured to generate a feedback current corresponding to the voltage Vd of the first node N1 according to the voltage Vd of the first node N1, and provide the feedback current to the bias voltage providing module 33, so that the output end of the bias voltage providing module 33 can output a stable voltage. Since the voltage stability of the output end of the bias voltage providing module 33 can affect the response rate of the non-cooled infrared focal plane array readout circuit, the output of the stable voltage by the output end of the bias voltage providing module 33 can stabilize the response rate of the non-cooled infrared focal plane array readout circuit. Specifically, the output of the stable voltage by the output end of the bias voltage providing module 33 can reduce the influence of the correction voltage Veb of the correction sub-module 11 and the target temperature of the corresponding pixel unit 101 on the response rate of the non-cooled infrared focal plane array readout circuit 200.

[0043] The bias voltage providing module 33 can also be referred to as a source follower module.

[0044] It should be noted that the voltage output by the output end of the bias voltage providing module 33 can also be referred to as a bias voltage, and the voltage after the voltage of the bias voltage is divided by the working resistor R can be provided to the first node N1.

[0045] As shown in FIG. 3, in some embodiments, the bias voltage providing module 33 has a current connection end 331, a voltage connection end 332, and a voltage output end 333 (i.e., the output end 333 of the bias voltage providing module 33), the current connection end 331 is connected to the feedback module 32, the voltage connection end 332 is connected to the adjustment voltage end VT, and the voltage output end 333 is connected to one end of the working resistor R.

[0046] The other end of the working resistor R is connected to the first node N1.

[0047] For example, the one pixel unit 101 comprises one infrared sensitive pixel 1001. In other embodiments, the pixel unit can comprise a plurality of infrared sensitive pixels.

[0048] In some embodiments, the pixel biasing sub-module 12 comprises a field effect transistor M1. The first pole of the field effect transistor M1 is connected with the first node N1, and the second pole of the field effect transistor M1 is connected with the infrared sensitive pixel 1001 (i.e. the pixel resistance 13) of the pixel unit 101. The control pole of the field effect transistor M1 is connected with the control voltage terminal VFID. The pixel biasing sub-module 12 can provide the pixel biasing voltage Vs for the infrared sensitive pixel 1001 (i.e. the pixel resistance 13) of the pixel unit 101 under the control voltage provided by the control voltage terminal VFID.

[0049] In some embodiments, the correction sub-module 11 comprises a field effect transistor M2 and a correction resistance Rd. The first pole of the field effect transistor M2 is connected with the correction resistance Rd, and the second pole of the field effect transistor M2 is connected with the first node N1. The control pole of the field effect transistor M2 is connected with the correction voltage terminal VEB. The correction sub-module 11 is used to correct the deviation of the readout circuit output caused by the resistance deviation among different pixel resistances 13. The correction voltage Veb of the correction sub-module 11 and the size of the target temperature of the corresponding pixel unit 101 affect the response rate of the uncooled infrared focal plane array readout circuit 200.

[0050] As shown in FIG. 3, in some embodiments, the uncooled infrared focal plane array readout circuit 200 further comprises a voltage detection module 31. The voltage detection module 31 is connected between the feedback module 32 and the first node N1, and is used to detect the voltage Vd of the first node N1 and provide the detected voltage Vd of the first node N1 to the feedback module 32.

[0051] The voltage detection module 31 has a detection end 311 and an output end 312.

[0052] The feedback module 32 has an input end 321 and an output end 322. The input end 321 of the feedback module 32 is connected with the voltage detection module 31, and the output end 322 of the feedback module 32 is connected with a connection end of the bias voltage providing module 33, and can generate the feedback current I0 corresponding to the detected voltage Vd according to the detected voltage Vd.

[0053] Specifically, the output end 322 of the feedback module 32 can be connected with the current connection end 331 of the bias voltage providing module 33. The input end 321 of the feedback module 32 can be connected with the output end 312 of the voltage detection module 31.

[0054] In some embodiments, the feedback current I0 is proportional to the voltage Vd detected by the voltage detection module 31.

[0055] In some embodiments, the voltage detection module 31 can directly detect the voltage Vd, or can detect a signal proportional to the voltage Vd, and the feedback current lo is inversely proportional to the voltage Vd detected by the voltage detection module 31, so as to better reduce the influence of the change of the correction voltage Veb and the target temperature of the corresponding pixel unit 101 on the response rate of the non-cooled infrared focal plane array readout circuit 200.

[0056] Of course, in other embodiments, if a processing module is connected between the detection end of the voltage detection module and the first node, and the processing module can form a signal inversely proportional to the voltage of the first node according to the voltage, the feedback current can be proportional to the voltage detected by the voltage detection module.

[0057] As shown in FIG. 2, in some embodiments, the non-cooled infrared focal plane array readout circuit 200 further comprises: an integration module 20 connected to the first node N1, and configured to perform integration processing on the voltage Vd of the first node N1 to generate a corresponding analog response signal.

[0058] In combination with FIGS. 4 and 5, in other embodiments, the non-cooled infrared focal plane array readout circuits 300, 400 further comprise a driving module 60. The driving module 60 is connected between the integration module 20 and the first node N1.

[0059] The driving module 60 can increase the current from the first node N1 to the integration module 20, so as to improve the voltage build-up speed from the first node N1 to the integration module 20.

[0060] For example, the driving module 60 can transmit the value of the voltage Vd of the first node N1 to the integration module 20 at a ratio of 1:1, so as to improve the accuracy of the analog response signal obtained by the integration module 20.

[0061] In some embodiments, the detection end 311 of the voltage detection module 31 is connected between the driving module 60 and the first node N1.

[0062] For example, as shown in FIG. 4, the detection end 311 of the voltage detection module 31 is connected between the driving module 60 and the first node N1.

[0063] In other embodiments, the detection end 311 of the voltage detection module 31 is connected between the driving module 60 and the integration module 20.

[0064] For example, as shown in FIG. 5, the detection end 311 of the voltage detection module 31 is connected between the driving module 60 and the integration module 20.

[0065] In combination with Fig. 2, in some embodiments, the non-cooled infrared focal plane array readout circuit 200 further comprises an analog-to-digital converter 40 and an output unit 50.

[0066] The analog-to-digital converter 40 is connected to the integration module 20, and is configured to convert the analog response signal corresponding to each infrared sensitive pixel 1001 generated by the integration module 20 into a digital signal.

[0067] The output unit 50 is connected to the analog-to-digital converter 40, and is configured to process the digital signal converted by the analog-to-digital converter 40 to generate processed data, and output the processed data.

[0068] From the perspective of a large signal, if the target temperature increases, the resistance of Rs decreases, I1 increases, I4 increases, and I3 decreases without the feedback module 32, the transconductance g m3 of the internal transistor M3 of the bias voltage providing module 33 changes, and the response rate is affected. When the feedback module 32 is introduced, the voltage Vd decreases, I0 increases, and I3 increases. The amount of increase of I3 after the introduction of the feedback module 32 can compensate for the amount of decrease of I3 without the feedback module 32 to a great extent, so that I3 can remain basically unchanged, and g m3 of the internal transistor M3 of the bias voltage providing module 33 basically does not change, and Vg s3 remains basically unchanged. Therefore, after the introduction of the feedback module 32, the response rate can remain basically unchanged under different target temperatures and different VEB configuration voltages, the influence of the nonlinearity of the response rate on imaging and pixel-level correction is greatly reduced, and the correction effect is improved.

[0069] In addition, in order to ensure that the current source can provide sufficient current in a large temperature range, and prevent the pixel biasing sub-module 12 (such as a field effect transistor M1) from entering a linear region due to the inability to extract the required current, affecting the circuit function, in the related technology, the current I0 provided by the constant current source increases by some design redundancy compared with the actual required current to ensure normal operation of the circuit, and the readout circuit biasing module 30 proposed in the present application includes a feedback module, I0 can provide a corresponding current according to the size of the current required for normal operation of the circuit, improve the utilization rate of the current, and reduce power consumption.

[0070] The present application also provides a non-cooled infrared focal plane array readout circuit detector, which comprises the non-cooled infrared focal plane array readout circuit 200 as described above.

[0071] In the present application, the structural embodiments can complement each other without conflict.

[0072] In this application, the terms "first", "second", etc. are used only to describe particular elements, and do not connote or imply any relative importance of the elements. The terms "a number of", "several", etc. mean two or more, unless otherwise expressly specified.

[0073] Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. It is intended that the specification and examples be considered as exemplary only, with the true scope and spirit of the application being indicated by the following claims.

[0074] It is to be understood that the application is not limited to the precise details of construction and the exact arrangements of the components described above and illustrated in the drawings, and that various modifications and changes can be made without departing from the scope thereof. The scope of the application is limited only by the claims that follow.

Claims

1. A readout circuit for a uncooled infrared focal plane array, comprising: a pixel circuit module, including a pixel resistor, a correction voltage terminal, a first node, a pixel biasing sub-module connected to the first node, and a correction sub-module, wherein the pixel biasing sub-module is connected to the pixel resistor and configured to provide a pixel bias voltage to the pixel resistor, and the correction sub-module is connected to the correction voltage terminal and configured to correct a deviation of an output of the readout circuit caused by a resistance deviation of the pixel resistor; and a readout circuit biasing module, including a working resistor, a bias voltage providing module, and a feedback module, wherein one connection end of the bias voltage providing module is connected to the feedback module, an output end of the bias voltage providing module is connected to one end of the working resistor, the other end of the working resistor is connected to the first node, a voltage of the output end of the bias voltage providing module fluctuates with at least one of a voltage of the correction voltage terminal and a target temperature of the pixel resistor, and the feedback module is configured to generate a feedback current corresponding to the voltage of the first node according to the voltage of the first node and provide the feedback current to the bias voltage providing module.

2. The readout circuit for a uncooled infrared focal plane array according to claim 1, further comprising a voltage detecting module connected between the feedback module and the first node, configured to detect the voltage of the first node and provide the detected voltage of the first node to the feedback module.

3. The readout circuit for a uncooled infrared focal plane array according to claim 2, wherein: the feedback module has an input end and an output end, the input end of the feedback module is connected to the voltage detecting module, and the output end of the feedback module is connected to the connection end of the bias voltage providing module.

4. The uncooled infrared focal plane array readout circuit of claim 2 or 3, wherein, the feedback current is proportional to the voltage of the first node detected by the voltage detecting module.

5. The uncooled infrared focal plane array readout circuit of claim 4, wherein the first and second capacitors are each a capacitor formed by a metal layer of the readout circuit and a metal layer of the infrared detector. the feedback current is inversely proportional to the voltage of the first node detected by the voltage detecting module.

6. The readout circuit for a uncooled infrared focal plane array according to any one of claims 2 to 5, further comprising: an integration module connected to the first node and configured to integrate the voltage of the first node to generate a corresponding analog response signal.

7. The readout circuit for a uncooled infrared focal plane array according to claim 6, further comprising: a driving module connected between the integration module and the first node and configured to increase a current from the first node to the integration module.

8. The uncooled infrared focal plane array readout circuit of claim 7, wherein the first and second capacitors are each a capacitor formed by a metal layer of the readout circuit and a metal layer of the infrared detector. the voltage detecting module has a detection end, wherein: the detection end is connected between the driving module and the integration module; or the detection end is connected between the driving module and the first node.

9. The readout circuit for a uncooled infrared focal plane array according to any one of claims 6 to 8, further comprising: an analog-to-digital converter connected to the integration module and configured to convert the analog response signal generated by the integration module into a digital signal. An output unit is connected to the analog-to-digital converter, and is configured to process the digital signal converted by the analog-to-digital converter to generate processed data, and output the processed data.

10. The uncooled infrared focal plane array readout circuit of any of claims 1 to 9, wherein, The pixel biasing submodule comprises a first field effect transistor, a first electrode of the first field effect transistor is connected to the first node, a second electrode of the first field effect transistor is connected to the pixel resistance, a control electrode of the first field effect transistor is connected to a control voltage terminal, and the pixel biasing submodule provides the pixel biasing voltage for the pixel resistance under the control voltage provided by the control voltage terminal.

11. The uncooled infrared focal plane array readout circuit of any one of claims 1 to 10, wherein, The correction submodule comprises a second field effect transistor and a correction resistance, a first electrode of the second field effect transistor is connected to the correction resistance, a second electrode of the second field effect transistor is connected to the first node, and a control electrode of the second field effect transistor is connected to the correction voltage terminal.

12. The uncooled infrared focal plane array readout circuit of any of claims 1 to 11, wherein, The uncooled infrared focal plane array has a plurality of pixel units arranged in an array, each of the pixel units has at least one infrared sensitive pixel, and the pixel resistance is the resistance of the at least one infrared sensitive pixel in each of the pixel units.

13. An uncooled infrared focal plane array readout circuit detector comprising the uncooled infrared focal plane array readout circuit according to any one of claims 1 to 12.

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