Inverter arrangement and method for intermediate circuit balancing

Abstract

The application relates to an inverter arrangement (10) in a supply unit (20) for supplying a load (22), wherein the inverter arrangement (10) has at least one divided intermediate circuit (12) and at least two bridges (14, 14.A, 14.B) connected in parallel with their respective AC outputs (16.A, 16.B) to an AC terminal (18) of the inverter arrangement (10), wherein it is provided to balance the DC voltages (UDClPos, UDClNeg) in the parts of the divided intermediate circuit (12) and, for balancing, to switch at least one bridge (14.A, 14.B) between a two-stage and a three-stage operation and to control a cross current current (IACQ) flowing between the AC outputs (16.A, 16.B) of the bridges (14.A, 14.B). The application further relates to a supply unit (20), and to a method for intermediate circuit balancing.

Description

[0001] 24-131-P-WO - 1 - submitted version

[0002] INVERTER ARRANGEMENT AND METHOD FOR INTERCIRCUIT SYMMETING

[0003] Technical field

[0004] The application concerns an inverter arrangement for supplying an AC island grid and a method for intermediate circuit balancing in such an inverter.

[0005] background

[0006] In DE 20 2012 004 347 Ul, an inverter is described which is configured to balance a split intermediate circuit via a balancing circuit when the mains disconnect switch is open.

[0007] In S. Foti, HH Khan, A. Testa, A. O. Di Tommaso, R. Miceli and C. Nevoloso, "A simple DC-Link Voltage Balancing Strategy for NPC Three-level Inverters", 2023 25th European Conference on Power Electronics and Applications (EPE'23 ECCE Europe), Aalborg, Denmark, 2023, pp. 1-8, a three-phase 3-level drive inverter is described in which fluctuations in the midpoint voltage of a split DC link are avoided by switching from three-stage to two-stage operation.

[0008] J.ZHOU;O. OJO;J. HARUNA;F. TANG, "Circulating Currents Suppression and Neutral-Point Potential Balancing Strategy for Parallel Three-Level T-type DC-AC Converters" in the conference paper from the 2019 IEEE Energy Conversion Congress and Exposition (ECCE) also deals with the balancing of the intermediate circuit.

[0009] Overview

[0010] An inverter arrangement for supplying an AC island grid (AC, alternating current) has at least one shared DC link and at least two bridges connected in parallel with their respective AC outputs to an AC terminal of the inverter arrangement. The AC island grid is supplied via the AC terminal of the inverter arrangement. 24-131-P-WO - 2 - submitted version

[0011] The inverter arrangement is designed to balance the DC voltages (DC, direct current, DC / DC voltage) in the parts of the intermediate circuit and, for balancing, to switch at least one bridge between a two-stage and a three-stage operation and to regulate a cross current flowing between the AC outputs of the bridges.

[0012] In particular, the inverter arrangement can include one or more inverters. An inverter comprises one or more bridges and one or more shared DC links. Each inverter can be housed in its own enclosure, which protects the inverter components from external influences, especially environmental influences, and is accessible, for example, via external connections. An inverter can also include a processing unit for controlling and / or regulating the inverter. The control and / or regulating can, in particular, include controlling semiconductor power switches of the bridges for the purpose of electrical power conversion.

[0013] The parallel connection of bridges makes it possible to design the inverter configuration for higher power outputs. The bridges are preferably connected in parallel with respect to one phase of the AC island grid, with their respective AC outputs.

[0014] Any topology is possible for the bridges that can be switched between two-stage and three-stage operation, e.g. T-Type Neutral-Point-Clamped (TNPC), Active Neutral Point Clamped (ANPC).

[0015] The switching between two-stage and three-stage operation is used to balance the split DC link during the inverter's power-controlling operation. By generating and controlling the cross-current between the parallel-connected bridges, the current in each bridge is increased to achieve higher balancing power in combination with the switching between two-stage and three-stage operation. This reduces uneven voltage distribution in the split DC link sections and compensates for the influence of half-wave unbalanced loads.

[0016] The described inverter arrangement enables cost-effective balancing of the split DC link without the need for a separate balancing unit. This avoids costs that can arise from additional hardware, such as semiconductor switches, drivers, magnetic components, capacitors, current and / or voltage sensors, or increased PCB space requirements (as described in the submitted version 24-131-P-WO - 3). At the same time, if desired, a high power input into a portion of the DC link can be achieved, thereby compensating for larger imbalances or asymmetrical loads.

[0017] The higher the cross-current setting, the greater the potential balancing power. For a given cross-current, the balancing power can be reduced by temporarily using three-stage operation instead of two-stage operation. Preferably, the cross-current is set such that a balancing power is achieved that compensates for the asymmetry caused by a half-wave unbalanced load on the phase. Alternatively, the cross-current can be chosen to be somewhat higher, and the parallel-connected bridges are operated temporarily in three-stage operation instead of two-stage operation to reduce the balancing power to the required value. For the balancing of the DC link halves according to the invention, a flowing cross-current, i.e., a cross-current greater than zero, is required. In other words, the flowing cross-current is regulated by the control system to a setpoint greater than zero.

[0018] In one embodiment, the inverter arrangement is provided for supplying one phase of the AC island grid, wherein the phase is arranged between the AC terminal of the inverter arrangement and a neutral conductor of the AC island grid. The neutral conductor is connected to an intermediate tap of the DC link.

[0019] If the inverter arrangement is used in voltage-regulating operation for an AC island grid, the DC link will be subjected to an unbalanced load, for example, when supplying half-wave unbalanced loads, such as those including half-wave rectification. The present inverter arrangement has the advantage that, under such an unbalanced load, a drift in the voltages of the two DC link halves can be reduced or prevented. This prevents the voltage of one DC link half from becoming too high or the voltage of the other half from becoming too low for continued operation.

[0020] In one embodiment of the inverter arrangement, the cross-current control includes the control of semiconductor power switches in the bridges. This allows, for example, the cross-current (24-131-P-WO - 4 - submitted version) to be generated in the desired strength and shape by switching the semiconductor power switches, in order to reduce or compensate for the asymmetry of the DC link.

[0021] In one embodiment of the inverter arrangement, the cross-current is regulated as direct current, alternating current, or a combination of direct and alternating current. The alternating current can, in particular, have a sinusoidal, trapezoidal, or triangular waveform.

[0022] In one embodiment of the inverter arrangement, the cross-current control includes sensing the respective AC bridge current at the respective AC outputs of the bridges and, optionally, sensing an AC phase current at the AC terminal. The sensed values ​​are used as actual values ​​for cross-current control.

[0023] In one embodiment of the inverter arrangement, the at least one divided intermediate circuit is further divided into two sections. In the event of a power deficit in the upper half of the intermediate circuit, the respective bridge is operated in two-stage mode, at least temporarily, if its respective AC bridge current is negative. For this purpose, the short-term average value (= average value over one switching period) of the respective AC bridge current can be used.

[0024] In one embodiment of the inverter arrangement, the at least one divided intermediate circuit is further divided into two sections. In the event of a power deficit in the lower half of the intermediate circuit, the respective bridge is operated in two-stage mode, at least temporarily, if its respective AC bridge current is positive. For this purpose, the short-term average value of the respective AC bridge current can be used in particular.

[0025] In one embodiment, the inverter arrangement is designed to supply multiple phases of the AC island grid. For each phase, the inverter arrangement has a dedicated AC connection with parallel-connected bridges. The use of a split DC link in combination with a three-stage bridge is particularly advantageous for three-phase inverter arrangements. The described balancing can therefore also be used in multi-phase AC island grids, where at least one phase has, for example, at least two parallel-connected bridges.

[0026] In embodiments of the inverter arrangement, several of the parallel-connected bridges can be connected to a common shared DC link and / or at least one of the parallel-connected bridges can be connected to a respective shared DC link. In particular, all parallel-connected bridges can be connected to a common DC link, or each bridge can be connected to a respective DC link. Hybrid configurations are also conceivable, where several bridges are connected to a common shared DC link and other bridges are connected to their respective assigned shared DC links.

[0027] In this embodiment, in particular, two inverters can be provided, which are, for example, arranged in separate housings and operated on the AC island grid. Each inverter then has, for example, one or more parallel-connected bridges and one or more intermediate circuits. The inverters can then, in turn, be connected in parallel on the AC side. It can then be provided, in particular, that the respective processing units of the inverters communicate with each other to control the cross-current.

[0028] In one embodiment of the inverter arrangement, each shared intermediate circuit is connected to a separate DC source. The DC source can be connected directly to the intermediate circuit or via an additional DC-DC converter. Hybrid configurations are also possible within an inverter arrangement with multiple DC sources.

[0029] In one embodiment of the inverter arrangement, one of the bridges provides the cross-current in the form of a reactive current for balancing the parts of the intermediate circuit of the other bridge. The bridges can be connected in parallel, particularly at the phase of the AC island grid.

[0030] In one embodiment of the inverter arrangement, a further bridge provides an additional cross-current in the form of a reactive current for balancing the intermediate circuit components of the parallel-connected bridges. This further bridge can, in particular, be connected to the same phase of the AC island grid as the parallel-connected bridges. Specifically, the AC output of this further bridge can be connected in parallel with the AC outputs of the parallel-connected bridges.

[0031] The additional bridge can have any topology and, in particular, can be provided at the phase. The additional bridge provides additional reactive current as the additional cross current. This can serve to support the balancing (24-131-P-WO - 6 - submitted version). In one embodiment, the additional cross current, e.g., a reactive current, can be generated by at least one inverter. The additional cross current can then be provided between two or more inverters to increase the balancing power.

[0032] The AC island grid features the described inverter configuration, at least one phase, and a neutral conductor. The load can be connected to at least one phase between the AC terminal and the neutral conductor and supplied with electrical power by the AC island grid.

[0033] The inverter arrangement comprises at least one split DC link and at least two bridges connected in parallel with their respective AC outputs to an AC terminal of the inverter arrangement. A method for DC link balancing of the inverter arrangement comprises:

[0034] • Switching at least one bridge between two-stage and three-stage operation and

[0035] • Control of a cross current flowing between the AC outputs for the intermediate circuit balancing of the bridges.

[0036] Tour list

[0037] The following section provides further explanation and description of exemplary implementations of this application with reference to the figures. They show

[0038] Fig. 1. schematically a first embodiment of an AC island grid with inverter,

[0039] Fig. 2. schematically shows a possible structure of a bridge,

[0040] Fig. 3. Schematic representation of possible current and voltage waveforms for a first embodiment,

[0041] Fig. 4. Schematic representation of possible voltage and power curves for the embodiment of Figure 3.

[0042] Fig. 5. Schematic representation of possible current and voltage waveforms for a second embodiment,

[0043] Fig. 6. Schematic representation of possible voltage and power curves for the embodiment of Figure 5.

[0044] Fig. 7. Schematic representation of power transferable by means of a cross-flow, 24-131-P-WO - 7 - submitted version

[0045] Fig. 8. schematically an embodiment of a control system for intermediate circuit balancing,

[0046] Fig. 9. Schematic illustration of an embodiment of cross-flow control,

[0047] Fig. 10. schematically a second embodiment of an AC island grid with inverter,

[0048] Fig. 11. schematically a third embodiment of an AC island grid with a three-phase inverter,

[0049] Fig. 12. schematically a fourth embodiment of an AC island grid with inverter,

[0050] Fig. 13. schematically shows a fifth embodiment of an AC island grid with two inverters.

[0051] The same reference symbols are used in the figures for identical or similar elements. Representations in the figures may not be to scale.

[0052] Facial description

[0053] Figure 1 schematically shows a first embodiment of an inverter arrangement 10 with a DC source 24 in a power supply unit 20. One phase PH of the power supply unit 20 is shown as an example. The power supply unit 20 can have one or more phases PH, in particular three phases PH. A load 22 is connected to phase PH between an AC terminal 18 of an inverter arrangement 10 and a neutral conductor N. The load 22 is a single-phase AC load that can be supplied with electrical power by the power supply unit 20. The load 22 represents any combination of individual devices or other elements in an AC island grid that has at least one load.

[0054] The inverter arrangement 10 includes an inverter which can supply electrical power, in particular to phase PH of the supply unit 20. The supply unit 20 is designed for so-called island grid operation, in which the electrical power is provided by a DC source 24 and the inverter arrangement 10 is operated in voltage-regulating and grid-forming mode. The DC source 24 can, for example, include a PV generator and / or an energy storage device such as a battery. 24-131-P-WO - 8 - submitted version

[0055] The inverter arrangement 10 converts the DC power or DC voltage supplied by the DC source 24 into grid-forming AC voltage UAC. The power conversion in the inverter arrangement 10 is carried out by means of parallel-connected bridges 14, which have controllable semiconductor power switches. The power conversion can be controlled, for example, by controlling, in particular by clocking, the semiconductor power switches of the parallel-connected bridges 14. The inverter arrangement 10 can be configured, in particular, to convert and transfer electrical power in any of the possible directions. It can therefore also be operated as a rectifier.

[0056] The inverter arrangement 10 shown in Figure 1 includes an inverter for electrical power conversion. The control of the power switches of the parallel-connected bridges 14 of the inverter can be carried out by a processing unit of the inverter.

[0057] The inverter of the inverter arrangement 10 has two parallel-connected bridges 14, comprising a first bridge 14.A and a second bridge 14.B. The first bridge 14.A and the second bridge 14.B are connected in parallel on their AC side via their respective AC outputs 16.A and 16.B. Conventionally, the AC outputs 16.A and 16.B are connected in parallel via at least one inductor to avoid undesirable effects. On their DC side, they are connected to a split DC link 12 with the intermediate tap 12.M. The split DC link 12 is connected to the DC source 24, which provides a DC input voltage. A DC / DC converter can optionally be arranged between the DC source 24 and the DC link 12.

[0058] The split intermediate circuit 12 has an upper half that connects an upper DC line DC+ to the intermediate tap 12.M. The split intermediate circuit 12 has a lower half that connects a lower DC line DC- to the intermediate tap 12.M. The DC voltage is present between the upper DC line DC+ and the lower DC line DC-.

[0059] The parallel-connected bridges 14 are arranged in phase PH, which can be one of several phases PH of the AC island network. With a symmetrical load on the components of the intermediate circuit 12, the arrangement can be controlled such that the AC phase current IAC is evenly distributed between the two bridges 14.A, 14.B (24-131-P-WO - 9 - submitted version). Then IACA = IACB = IAC / 2. Furthermore, with a symmetrical load on the components of the intermediate circuit 12, continuous control in three-stage operation is possible. In three-stage operation, during the positive voltage half-cycle, the AC output 16.A, 16.B is switched back and forth between the positive DC line DC+ and the intermediate tap 12.M. In three-stage operation, during the negative voltage half-wave, the AC output 16. A, 16. B is switched back and forth between the negative DC line DC- and the intermediate tap 12. M.

[0060] In the case of asymmetrical loading, the intermediate circuit 12 can be symmetrical as described below.

[0061] Bridges 14.A and 14.B supply phase PH on their parallel AC side. Bridges 14.A and 14.B provide their respective bridge currents IACA and IACB at their AC outputs 16.A and 16.B. A cross current, IACQ, is the current flowing between bridges 14.A and 14.B. The bridge current IACA is calculated as IACA = IAC / 2 + IACQ, and the bridge current IACB is calculated as IACB = IAC / 2 - IACQ.

[0062] The currents IACA, IACB, and IACQ are influenced by the control of the power semiconductor switches, particularly by their switching frequency. A switching frequency refers to one switching period. Here, the currents IACA, IACB, IAC, and IACQ are considered as average values ​​over the switching period.

[0063] Bridges 14.A and 14.B can be operated in a two-stage mode. In two-stage operation, the bridge branches between the upper DC line DC+ and the lower DC line DC- are switched to generate the AC voltage UAC.

[0064] Bridges 14.A and 14.B can be operated in three-stage mode. In three-stage mode, to generate the positive partial wave of the AC voltage UAC, the bridge branches between the upper DC line DC+ and the intermediate tap 12.M are switched. In three-stage mode, to generate the negative partial wave of the AC voltage UAC, the bridge branches between the lower DC line DC- and the intermediate tap 12.M are switched.

[0065] A sine wave filter 15 is arranged between the AC outputs 16.A, 16.B of the bridges 14.A, 14.B and the AC terminal 18. At the AC terminal 18, the inverter arrangement 10 directly supplies an AC phase current IAC to phase PH (24-131-P-WO - 10 - submitted version).

[0066] This is achieved by providing an AC voltage which, depending on the load, results in a phase current IAC.

[0067] In the case of an asymmetrical load on the split DC link 12, e.g., due to a half-wave asymmetrical load 22, as occurs, for example, with half-wave rectification in the load 22, the bridges 14.A and 14.B are controlled such that the cross-current IACQ is generated. Furthermore, the cross-current IACQ can be generated in such a way that, with suitable inverter bridge switching, it reduces or compensates for the unequal power dissipation from the parts of the DC link 12. Thus, the cross-current IACQ can be generated and controlled by the targeted control of the semiconductor power switches. In particular, the cross-current IACQ can be controlled in the desired shape and magnitude.

[0068] The described control of the bridges and the associated regulation of the cross current IACQ additionally includes switching between the two-stage clocking and the three-stage clocking of bridges 14. A, 14. B.

[0069] For example, switching between two-stage and three-stage clocking of bridges 14.A and 14.B can be performed as follows to reduce or compensate for an unequal power load on the intermediate circuit halves:

[0070] 1.) In the event of a power deficit in the upper half of the intermediate circuit, the corresponding bridge 14.A, 14.B is operated with two-stage switching if its bridge current IACA, IACB is negative. Otherwise, the corresponding bridge is operated with three-stage switching. This ensures that additional power is transferred from the lower to the upper half of the intermediate circuit, thus compensating for the unbalanced power draw.

[0071] 2.) In the event of a power deficit in the lower half of the intermediate circuit, the corresponding bridge 14.A, 14.B is operated with two-stage switching if its bridge current IACA, IACB is positive. Otherwise, the corresponding bridge is operated with three-stage switching. This ensures that additional power is transferred from the upper to the lower half of the intermediate circuit, thus compensating for the unbalanced power draw.

[0072] Various current waveforms are possible for controlling the cross-current IACQ, for example, direct current, alternating currents of different frequencies and phase angles, combined alternating currents (e.g., 1st and 3rd harmonics), or other current waveforms (trapezoidal, delta). A cross-current IACQ with a significant alternating component has the advantage that the two bridges 14.A, 14.B are operated with approximately equal frequency in two-stage switching, thus achieving an approximately symmetrical power loss distribution. If a direct current is selected for the cross-current IACQ, then, for example, in the case of a purely half-wave unbalanced load 22, one of the bridges 14.A, 14.B is operated continuously in two-stage switching, while the other is operated continuously in three-stage switching (see Figs. 3, 4).This can adversely affect the losses in the semiconductor power switches and a filter choke of the bridge 14. A, 14. B, which is operated with two-stage switching.

[0073] Figure 2 shows an example of a bridge 14.A, 14.B with a split intermediate circuit 12, which can be operated in three stages. An example of a TNPC topology is shown on the right side of Figure 2. Other three-stage topologies are also conceivable. For the purposes of this document, the symbol shown on the right side of Figure 2 is used as an abbreviation for a three-stage bridge topology.

[0074] Particularly in three-phase inverter arrangements 10, the use of a split DC link 12 in combination with a three-stage bridge 14.A, 14.B, e.g., T-Type Neutral-Point-Clamped (TN PC), Active Neutral Point Clamped (ANPC), is advantageous. If the inverter arrangement 10 is used in voltage-regulating operation for the AC island grid 20, the DC link 12 is subjected to an unbalanced load when supplying half-wave unbalanced loads 22, which include, for example, half-wave rectification. Under suitable operating conditions, the present inverter arrangement 10 has the advantage that, under such an unbalanced load, a drift in the voltages of the two DC link halves can be reduced or prevented. This prevents the voltage of one DC link half from becoming too high or the voltage of the other half from becoming too low for continued operation.

[0075] Figure 3 shows exemplary current and voltage waveforms for a first embodiment. Time in milliseconds is plotted on the horizontal axis. Currents and voltages are plotted vertically in amps (A) and voltages (V). The waveforms show the embodiment with a rectified load of 5.2 kW at an AC voltage UAC of 230 V RMS and a frequency of 50 Hz with a DC link voltage of 800 V. In this case, a constant DC current of 33 A is used as the cross-current IACQ. The top graph in Figure 3 shows the AC voltage UAC of 230 V RMS. The second graph shows the AC phase current IAC, which represents the load current, and the cross-current IACQ. (24-131-P-WO - 12 - submitted version)

[0076] The cross-current IACQ is shown as an average value over one switching period and, in this example, is a DC current with a constant average amplitude. The third graph shows the bridge currents IACA and IACB, also as average values ​​over one switching period, at the AC outputs 16.A and 16.B of the respective parallel-connected bridges 14.A and 14.B. The fourth graph shows the switching mode of the bridges used at the respective time (three-stage 3L or two-stage 2L). Mode A denotes the switching mode of bridge 14.A. Mode B denotes the switching mode of bridge 14.B. In the first embodiment shown, bridge 14.A is therefore continuously operated in three-stage mode, and bridge 14.B is continuously operated in two-stage mode.

[0077] Figure 4 shows exemplary voltage and power curves for the embodiment of Figure 3. Voltages are plotted vertically in V. Power is plotted vertically in kW. Time is plotted on the horizontal axis in ms. Graphs 1 and 2 show the resulting pulse-width modulated voltages 42.A and 42.B generated by the clocking at the AC outputs 16.A and 16.B of bridges 14.A and 14.B. It is clearly visible that bridge 14.A is continuously clocked in three stages, and bridge 14.B is continuously clocked in two stages. The lower graph shows the total power input to the intermediate circuit 12. Graph 44 shows the power input to the upper half of the intermediate circuit, and graph 46 shows the power input to the lower half of the intermediate circuit.The total power input into the intermediate circuit 12 consists of the power flowing from the DC-side DC source 24 into the intermediate circuit 12, minus the power flowing towards the load 22, and the effect of power balancing through shunt current control and the application of two-stage and three-stage switching. Due to the applied method, the average power input over one period of the AC voltage UAC to the two intermediate circuit halves is zero. The intermediate circuit voltages do not diverge but remain stable.

[0078] Figure 5 shows exemplary current and voltage waveforms for a second embodiment. Currents and voltages are plotted vertically in A and V, respectively. Time is plotted on the horizontal axis in ms. The waveforms illustrate the embodiment with a rectified load of 5.2 kW at an AC voltage UAC of 230 V RMS and a frequency of 50 Hz with a DC link voltage of 800 V. In this case, a sinusoidal shunt current IACQ of 30 A RMS is used, with the same frequency as the applied AC voltage UAC and with a 90° phase shift relative to the applied AC voltage UAC. The top graph in Figure 5 shows the AC voltage UAC of 230 V RMS. The second graph shows the AC phase current IAC, which represents the load current, and the shunt current IACQ. The cross-current is shown as an average value over one switching period. The 3rdThe graph shows the bridge currents IACA and IACB as average values ​​over one switching period at the AC outputs 16.A and 16.B of the respective parallel-connected bridges 14.A and 14.B. The fourth graph shows the switching mode of the bridges used at the respective time (three-stage 3L or two-stage 2L). Mode A denotes the switching mode of bridge 14.A. Mode B denotes the switching mode of bridge 14.B. In the second embodiment shown, both bridges 14.A and 14.B switch between three-stage and two-stage operation.

[0079] Figure 6 shows exemplary voltage and power curves for the embodiment of Figure 5. Time is plotted on the horizontal axis in ms. Voltages are plotted on the vertical axis in V. Power is plotted on the vertical axis in kW. Graphs 1 and 2 show the resulting pulse-width modulated voltages 62.A, 62.B generated by the clocking at the AC outputs 16.A, 16.B of the bridges 14.A, 14.B. The change between two-stage and three-stage clocking is clearly visible here. The lower graph shows the total power input into the intermediate circuit 12. Graph 64 shows the power input into the upper half of the intermediate circuit, and graph 66 shows the power input into the lower half of the intermediate circuit.The total power input into the intermediate circuit 12 consists of the power flowing from the DC-side DC source 24 into the intermediate circuit 12, minus the power flowing towards the load 22, and the influence of power balancing through the control of the cross-current and the switching between two-stage and three-stage switching. Due to the applied method, the average power value over one period of the AC voltage UAC in the two intermediate circuit halves is zero. The intermediate circuit voltages do not diverge but remain stable.

[0080] Figure 7 shows, as an example of a typical filter design of the sine filter 15, the RMS value of the cross current IACQ in A (sine wave, 90° phase shift to the AC voltage UAC, as in the second embodiment of Figures 5 and 6) in the vertical direction. In the horizontal direction, values ​​in kW for a load 22 connected to phase PH as a half-wave rectified load are shown. The version shown is the one submitted in 24-131-P-WO - 14 -.

[0081] Cross-current IACQ, which is at least necessary for balancing the intermediate circuit 12. It can be seen that with three-stage-two-stage switching alone and without using the cross-current (i.e., IACQ = 0 A), only 315 W of half-wave rectified load would be possible.

[0082] Figure 8 schematically shows a possible control of a difference UDClDiff of the DC voltages of the intermediate circuit halves.

[0083] The differential voltage UDClDiff = UDClPos - UDClNeg is determined from the intermediate circuit voltages UDClPos of the upper intermediate circuit half and UDClNeg of the lower intermediate circuit half.

[0084] The deviation eUDCIDiff from a reference value UDClDiff* of the difference UDClDiff of the DC voltages of the intermediate circuit halves is determined as eUDCIDiff = UDClDiff* - UDClDiff.

[0085] A symmetry controller 80 determines the reference value of the necessary cross current IACQ* based on the deviation eUDCIDiff, and depending on the deviation eUDCIDiff and the direction of the current IACA, the operating mode ModeA of bridge 14. A and depending on the deviation eUDCIDiff and the direction of the current IACB, the operating mode ModeB of bridge B.

[0086] A cross-current controller 82 determines the duty cycles for the respective bridges 14. A, 14. B from the reference value IACQ* of the desired setpoint of the cross-current IACQ and from the duty cycle DuCy, which is specified by a higher-level control for regulating the output voltage.

[0087] Figure 9 shows an exemplary embodiment of the control loop 82 for controlling the cross current IACQ for the embodiment of two parallel-connected bridges 14. A, 14. B.

[0088] IACQ = (IACA - IACB) / 2. IACQ* denotes the desired setpoint of the cross current IACQ. The controller 90 determines a difference ADuCy in the duty cycles of the parallel-connected bridges 14 from the difference between the setpoint IACQ* and the actual value IACQ. The controller 90 can be, for example, a PI controller, a resonant controller, a combination of resonant controllers, a repetitive controller, or other suitable controllers or combinations of controllers. 24-131-P-WO - 15 - submitted version

[0089] The duty cycle of the semiconductor power switches of the parallel-connected bridges 14 is determined for bridge 14. A to DuCyA = DuCy + ADuCy / 2 and for bridge 14. B to DuCyB = DuCy - ADuCy / 2.

[0090] Figure 10 shows a second embodiment of the inverter arrangement 10. In contrast to the first embodiment shown in Figure 1, the sine wave filter 15 is designed with two pairs of filter chokes and three capacitors, as shown. The current path of the AC currents IACA and IACB is only combined after the second pair of filter chokes. As in Figure 1, the parallel-connected bridges 14 have two three-stage AC bridges 14.A and 14.B.

[0091] Figure 11 shows a third embodiment of the inverter arrangement 10. This third embodiment comprises a three-phase inverter arrangement 10 with a three-phase inverter. The inverter has three pairs of parallel-connected bridges 14. The three pairs of parallel-connected bridges 14 are connected to a common shared DC link 12 and are connected in parallel phase-wise on their AC side. Each pair of parallel-connected bridges 14 supplies one phase PH. The respective bridges 14.A, 14.B of the parallel-connected bridge pairs 14 are, for example, configured as three-stage AC bridges 14.A, 14.B as shown in Figure 2.

[0092] For higher power ratings of the parallel-connected bridges 14, the parallel-connected bridges can also comprise three or more parallel bridges 14.A, 14.B, etc. The corresponding AC currents IACA, IACB, etc. at the AC output of the bridges 14.A, 14.B, etc., can be selected such that the desired cross-current IACQ results as the sum current.

[0093] For an example case with three bridges with three AC currents IACA, IACB, IACC, it is possible to define two independent currents lAlpha and IBeta, and to derive the currents IACA, IACB, IACC from them as follows:

[0094] IACA = IAC / 3 + lAlpha IACB = IAC / 3 - IAIpha / 2 + sqrt(3) / 2 * IBeta IACC = IAC / 3 - IAIpha / 2 - sqrt(3) / 2 * IBeta

[0095] For lAlpha and IBeta, various current waveforms can be used analogously to IACQ, for example, direct current, alternating currents of different frequencies and phases, combined alternating currents (e.g., 1st and 3rd harmonics), or other waveforms (trapezoidal, triangular). The selection of the waveform is subject to analogous considerations as for the transverse current IACQ. 24-131-P-WO - 16 - submitted version

[0096] Figure 12 shows a fourth embodiment of the inverter arrangement 10. The inverter arrangement 10 comprises two separate single-phase inverters 10.A, 10.B, each connected to a respective DC source 24 and each having a respective intermediate circuit 12.

[0097] More than two inverters 10.A, 10.B are also conceivable. The inverter arrangement 10 can also include two or more multi-phase inverters 10.A, 10.B. In multi-phase inverters 10.A, 10.B, each phase preferably has a cross-current controller 82 for regulating the respective cross-current IACQ.

[0098] For higher power outputs of the parallel-connected bridges 14, the parallel-connected bridges can also comprise three or more parallel bridges 14.A, 14.B, etc. In this case, two or more shunt current controllers 82 can be used.

[0099] Figure 13 schematically shows a fifth embodiment of an AC island grid 20 with two inverters 10. A, 10. B.

[0100] Inverter 10.A has bridge 14.A, which supplies phase PH. Bridge 14.A is connected to the split DC link 12. Another inverter 10.B with bridge 10.B provides reactive current, which flows as cross current IACQ into bridge 14.A and, in combination with the switching between two-stage and three-stage operation, can balance the split DC link 12 of inverter 10.A.

[0101] Alternatively, the inverter 10.A can have two or three parallel-connected bridges 14.A, 14.B, each supplying one phase PH. These bridges 14.A, 14.B, each supplying one phase PH, can be connected to the same shared intermediate circuit 12.

[0102] The additional inverter 10.B with bridge 10.B and another split DC link 12 serves to provide a reactive current, which flows as cross current IACQ into bridge 14.A and can balance the split DC link 12 of inverter 10.A. The additional inverter 10.B can be single-phase or multi-phase, in particular three-phase.

Claims

24-131-P-WO - 17 - submitted version REQUIREMENTS 1. Inverter arrangement (10) in a supply unit (20) for supplying a load (22), wherein the inverter arrangement (10) has at least one split DC link (12) and at least two bridges (14, 14. A, 14. B) connected in parallel with their respective AC outputs (16. A, 16. B) to an AC terminal (18) of the inverter arrangement (10), wherein it is provided to balance the DC voltages (UDClPos, UDClNeg) in the parts of the DC link (12) and, for balancing, to switch at least one bridge (14. A, 14. B) between a two-stage and a three-stage operation and to regulate a cross current (IACQ) flowing between the AC outputs (16. A, 16. B) of the bridges (14. A, 14. B).

2. Inverter arrangement according to claim 1, wherein the inverter arrangement (10) of the supply unit (20) is provided for supplying a phase (PH), wherein the phase (PH) is arranged between the AC terminal (18) and a neutral conductor (N) of the supply unit (20), wherein the neutral conductor (N) is connected to an intermediate tap (12. M) of the intermediate circuit (12).

3. Inverter arrangement according to claim 1 or 2, wherein the control (82) of the cross current (IACQ) comprises a control of semiconductor power switches of the bridges (14. A, 14. B).

4. Inverter arrangement according to one of the preceding claims, wherein the cross current (IACQ) is controlled as direct current, alternating current or a combination of direct and alternating current, wherein the alternating current in particular has a sinusoidal shape, a trapezoidal shape or a triangular shape.

5. Inverter arrangement according to one of the preceding claims, wherein the control (82) of the cross current (IACQ) comprises a detection of a respective AC bridge current (IACA, IACB) at the respective AC outputs (16. A, 16. B) of the bridges (14. A, 14. B) and optionally a detection of an AC phase current (IAC) at the AC terminal (18). 24-131-P-WO - 18 - submitted version 6. Inverter arrangement according to one of the preceding claims, wherein the at least one intermediate circuit (12) is divided into two parts and, in the event of a power deficit in the upper intermediate circuit half, the respective bridge (14. A, 14. B) is operated at least temporarily in two-stage operation when its respective AC bridge current (IACA, IACB) is negative.

7. Inverter arrangement according to one of the preceding claims, wherein the at least one intermediate circuit (12) is divided into two parts and, in the event of a power deficit in the lower intermediate circuit half, the respective bridge (14. A, 14. B) is operated at least temporarily in two-stage operation when its respective AC bridge current (IACA, IACB) is positive.

8. Inverter arrangement according to one of the preceding claims, wherein the inverter arrangement (10) is provided for supplying several phases (PH) of the AC island network (20) and has for each phase a respective AC connection (18) with respective parallel-connected bridges (14, 14. A, 14. B).

9. Inverter arrangement according to one of the preceding claims, wherein several of the parallel-connected bridges (14, 14.A, 14.B) are connected to a common shared intermediate circuit (12) and / or wherein at least one of the parallel-connected bridges (14, 14.A, 14.B) is connected to a respective shared intermediate circuit (12).

10. Inverter arrangement according to one of the preceding claims, wherein each divided intermediate circuit (12) is connected to each DC source (22).

11. Inverter arrangement according to one of the preceding claims, wherein a further bridge provides a further cross current in the form of a reactive current for balancing the parts of the intermediate circuit (12) of the parallel-connected bridges (14).

12. Supply unit (20) comprising the inverter arrangement (10) according to one of the preceding claims, at least one phase (PH) and a neutral conductor (N), wherein a load (22) can be arranged in the at least one phase (PH) between the AC terminal of the inverter arrangement and the neutral conductor (N). 24-131-P-WO submitted version 13. Method for DC link balancing of an inverter arrangement (10), wherein the inverter arrangement (10) has at least one split DC link (12) and at least two bridges (14. A, 14. B) connected in parallel with their respective AC outputs (16. A, 16. B) to an AC terminal (18) of the inverter arrangement (10), wherein the method for DC link balancing comprises: • Switching at least one bridge (14. A, 14. B) between two-stage and three-stage operation and • Control of a cross current (IACQ) flowing between the AC outputs (16. A, 16. B) for the intermediate circuit balancing of the bridges (14. A, 14. B).

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