Chiplet assembly and a method for translating memory access commands in the chiplet assembly

Abstract

The invention relates to a chiplet assembly (1) comprising: - A shared electronic memory (2), - A system management controller (3), the system management controller (3) comprising a memory interface (4) for accessing the shared electronic memory (2), - A System-on-Chip (5), the System-on-Chip (5) being connected to the system management controller (3) via a physical interface (6), the physical interface (6) being designed to enable an access of the System-on-Chip (5) to electronic memories, - A substrate (7) for accommodating the system management controller (3) and the System-on-Chip (5). The invention further relates to a method for translating memory access commands in the chiplet assembly.

Description

[0001] R.415220

[0002] - 1 -

[0003] Description

[0004] Title

[0005] Chiplet assembly and a method for translating memory access commands in the chiplet assembly

[0006] The invention relates to chiplet assembly and a method for translating memory access commands in the chiplet assembly.

[0007] State of the art

[0008] With the trend of automotive system complexity, the dedicated SoCs (System-on- Chip), which are performing either In Vehicle Infotainment (I VI) functions, Advanced driver-assistance systems (ADAS) ones or a merge of both, are reaching huge physical size. Until recent period, the technology race has compensated this complexity by shrinking the chip size to ensure a proper manufacturing yield at a reasonable cost. Unfortunately, as the Moore law is weakening for fine pitch technologies, this paradigm is no longer valid. This is paving the way for the era of chiplet deployment.

[0009] In the context of chiplets, a system is no longer made of a single piece of silicon but is gathering multiple pieces of silicon from heterogeneous technology nodes. Those pieces of silicon are fitted over an organic substrate, or over an interposer made of silicon which is itself fitted over an organic substrate. Those constructions are often referred to as 2D, 2.5D packaging technologies and further complexify into 3D when multiple pieces of silicon are stacked over each other.

[0010] Similarly, to subsystems in a monolithic SoC, the collection of silicon pieces which are referred as chiplets must communicate between each other over Chiplet to Chiplet (C2C) or Die to Die (D2D) interfaces. There are multiple R.415220

[0011] - 2 - possibilities for D2D interfaces, but over time a standard has emerged: UCIe. This standard allows to communicate over a high-speed link ranging from 4 GT / s up to 32 GT / s and using from 16 lines (simplest standard packaging version) up to 1024 lines (most complex advanced packaging version). There are alternate solutions like BoW, PCIe, as well as proprietary solution like Hyper-Transport or Infinity from AMD among other ones.

[0012] In essence, a chiplet is looking as a standard SoC, except that it offers specialized communication channels to its mates via D2D interfaces, such as UCIe interfaces. This practically means that the specialized communication interfaces must be planned from the original inception of the chiplets. This situation at early days of chiplets deployment is a potential bottleneck for chiplets proliferation as those pieces of silicon are yet to be designed. At the same time, the semi-conductor market is full of existing SoCs which cover multiple needs: Mobile phone, Digital TV, Networking, Computing, Automotive, etc. Unfortunately none of these existing devices can be used right away as a chiplet because they do not offer the appropriate communication interfaces to be aggregated in a chiplet assembly.

[0013] Disclosure of the invention

[0014] According to aspects of the invention a chiplet assembly with the features of claim 1 and a method with the features of claim 10 are provided. Further features and details of the invention are disclosed in the respective dependent claims, the description and the drawings. Features and details described in the context to the inventive chiplet assembly also correspond to the inventive method, and vice versa.

[0015] According to an aspect of the invention a chiplet assembly is provided, the chiplet assembly comprising:

[0016] A shared electronic memory,

[0017] A system management controller, the system management controller comprising a memory interface for accessing the shared electronic memory, R.415220

[0018] - 3 -

[0019] A System-on-Chip, the System-on-Chip being connected to the system management controller via a physical interface, the physical interface being designed to enable an access of the System-on-Chip to electronic memories, A substrate for accommodating the system management controller and the System-on-Chip.

[0020] The chiplet assembly may also be designated and understood as a chiplet system. A chiplet is particularly an integrated circuit (IC) that contains a defined subset of functionality. The system management controller may be a specific chiplet of the chiplet assembly. The system management controller may comprise a corresponding physical interface for communicating with the System- on-Chip. The physical interface may be a UCIe interface. The shared electronic memory may comprise a corresponding memory interface for allowing the access of the system management controller. The physical interface and the memory interface may be of a same type of interface, for example a UCIe interface. The shared electronic memory may be provided within the chiplet assembly and may also be accommodated by the substrate. The shared electronic memory may also be provided externally with regard to the chiplet assembly or the substrate. The shared electronic memory may be a (centralized) Dynamic Random Access Memory, particularly Double Data Rate Synchronous Dynamic Random Access Memory. The System-on-Chip may be designed to be housed as a standalone die in a dedicated package and may be an off-the-shelf application specific standard product. Within the substrate, connections between the different interfaces, i.e. the physical and memory interfaces, may be provided.

[0021] The System Management Controller (SMC) may, inter alia, perform the following tasks: A first task may be regulating and monitoring a power usage across different chiplets, optimizing energy efficiency, and controlling power states (e.g., sleep, idle, active). A second task may be monitoring temperature sensors on the chiplets and adjusting cooling mechanisms (e.g., fans or throttling) to prevent overheating. A third task may be balancing workloads across chiplets, managing clock speeds, and optimizing overall system performance. Another task may be coordinating data flow between chiplets, ensuring proper interconnect protocols are followed and minimizing latency. Another task may be detecting hardware R.415220

[0022] - 4 - faults within chiplets and implementing corrective actions, such as resetting certain components or rerouting tasks to prevent system failure.

[0023] By means of the chiplet assembly according to the invention, it may advantageously become possible to integrate existing, i.e. off-the-shelf, System- on-Chips into chiplet assemblies.

[0024] It is possible that the System-on-Chip is a multi-core CPU architecture comprising at least one CPU (Central Processing Unit) core, at least one GPU (Graphics Processing Unit) core, a cache memory and at least one high bandwidth memory module, i.e. the System-on-Chip may be a proprietary chiplet. It is also possible that the System-on-Chip comprises at least one CPU core, at least one GPU core, an image processing unit and an artificial intelligence accelerator, i.e. the System-on-Chip may also be an open standard chiplet. Said components may be connected by interconnect elements. It is also possible that the System-on-Chip is a complex System-on-Chip like the Jetson AGX Orin Series Hardware Architecture by Nvidia.

[0025] It is possible that the system management controller further comprises a sensor interface to provide an access to at least one sensor. The sensor may be a camera, radar, lidar, or ultrasonic sensor. It is also possible that the system management controller further comprises at least one communication interface, for example Ethernet, PCIe, USB, CAN and / or SPI.

[0026] The chiplet assembly may thus be advantageously integrated in a technical system with various sensors and / or communication interfaces like a vehicle.

[0027] It is possible that the system management controller is designed to translate memory access commands of the System-on-Chip into memory mapped transactions suitable to a bus structure and / or bus protocol of the system management controller towards the shared electronic memory. The translation may be implemented by performing an offset addition or subtraction to an original base address of the System-on-Chip which may be submitted in the memory mapped transaction. The bus structure may utilise and / or the bus protocol of the system management controller may be the AXI protocol of the ARM Ltd AMBA R.415220

[0028] - 5 - bus specification. It may be extended to a more complex protocol like the CHI protocol of ARM Ltd AMBA bus specification, to the equivalent OCP open standard specification, or the Intel proprietary CPI bus specification by applying the same principles according to the invention.

[0029] It is further possible that the translation of the memory access commands comprises a remapping of memory addresses. The memory address remapping may be performed by a Memory Management Unit of the system management controller. A Memory Management Unit (MMU) is particularly a hardware component that is responsible for managing the memory access of a computing system. It may translate virtual memory addresses used by a program into physical memory addresses used by the computing system's memory. The Memory Management Unit of the system management controller may also be configured to perform other memory-related tasks, such as memory compression and decompression, to further optimize system performance and resource utilization.

[0030] It is further possible that the translation of the memory access commands comprises defining an addressing scheme of read and / or write transactions from the System-on-Chip to the shared electronic memory. This may have the advantage of reducing the complexity of the memory access commands, thereby improving an overall performance of the chiplet assembly. Additionally, the addressing scheme may be optimized to minimize the latency of the read and / or write transactions, further improving the performance of the shared electronic memory.

[0031] Another aspect of the invention is a method for translating memory access commands in a chiplet assembly according to any one of the preceding claims, the method comprising:

[0032] Translating memory access commands of a System-on-Chip into memory mapped transactions suitable to a bus structure of the system management controller towards a shared electronic memory of the chiplet assembly, the translating particularly comprising a remapping of memory addresses and / or defining an addressing scheme of read and / or write transactions from the System-on-Chip to the shared electronic memory. R.415220

[0033] - 6 -

[0034] Thus the according to the invention method brings about the same advantages as have been described in detail with reference to the chiplet assembly according to the invention.

[0035] In another aspect of the invention, a computer program may be provided, in particular a computer program product, comprising instructions which, when the computer program is executed by a computer, cause the computer to carry out the method according to the invention. Thus, the computer program according to the invention can have the same advantages as have been described in detail with reference to a method according to the invention.

[0036] In another aspect of the invention, an apparatus for data processing may be provided, which is configured to execute the method according to the invention. As the apparatus, for example, a computer or microcomputer or micro controller can be provided which executes the computer program according to the invention. The computer or microcomputer or micro controller may be provided within the system management controller according to the invention and may include at least one processor that can be used to execute the computer program. Also, a non-volatile data memory may be provided in which the computer program may be stored and from which the computer program may be read by the processor for being carried out.

[0037] According to another aspect of the invention a computer-readable storage medium may be provided which comprises the computer program according to the invention and / or instructions which, when executed by a computer or microcomputer or micro controller, cause the computer or microcomputer or micro controller to carry out the steps of the method according to the invention. The storage medium may be formed as a data storage device such as a hard disk and / or a non-volatile memory and / or a memory card and / or a solid state drive. The storage medium may, for example, be integrated into the computer or microcomputer or micro controller.

[0038] Furthermore, the method according to the invention may be implemented as a computer-implemented method. Alternatively or additionally, at least one of the disclosed method steps may be computer-implemented and / or automated. R.415220

[0039] - 7 -

[0040] Further advantages, features and details of the invention will be apparent from the following description, in which embodiments of the invention are described in detail with reference to the drawings. In this context, the features mentioned in the claims and in the description may each be essential to the invention individually or in any combination. Showing:

[0041] Fig. 1 : A chiplet assembly according to embodiments of the invention,

[0042] Fig. 2a: A first alternative for a System-on-Chip according to embodiments of the invention,

[0043] Fig. 2b: A second alternative for a System-on-Chip according to embodiments of the invention,

[0044] Fig. 3: A system management controller according to embodiments of the invention.

[0045] Fig. 1 shows a chiplet assembly 1 according to embodiments of the invention. The chiplet assembly 1 comprises a shared electronic memory 2, a system management controller 3 and a System-on-Chip 5. The system management controller 3 is connected to and communicating with the shared electronic memory 2 via respective memory interfaces 4. The system management controller 3 is connected to and communicating with the System-on-Chip 5 via respective physical interfaces 6. The system management controller 3 further comprises a memory management unit 17. The shared electronic memory 2, the system management controller 3 and the System-on-Chip 5 are accommodated by a substrate 7.

[0046] Fig. 2a shows a first alternative for a System-on-Chip 5 according to embodiments of the invention. This System-on-Chip 5 comprises a physical interface 6, a CPU (Central Processing Unit) core 8, a GPU (Graphics Processing Unit) core 9, a cache memory 10 and a high bandwidth memory module 11. R.415220

[0047] - 8 -

[0048] Fig. 2b shows a second alternative for a System-on-Chip 5 according to embodiments of the invention. This System-on-Chip 5 comprises a physical interface 6, a CPU (Central Processing Unit) core 8, a GPU (Graphics Processing Unit) core 9, an image processing unit 12 and an artificial intelligence accelerator 13.

[0049] Fig. 3 shows a system management controller 3 according to embodiments of the invention. The system management controller 3 comprises a memory interface 4, a physical interface 6, a sensor interface 14, a communication interface 15, a bus structure 16 and a memory management unit 17.

[0050] The invention particularly defines means to enable a standard System-on-Chip 5 (SoC) to be used in the context of a chiplet assembly 1 provided it offers a physical interface 6 for connection to an electronic memory, particularly a Dynamic Random Access Memory (DRAM). This condition may almost always be satisfied as the SoCs are in vast majority equipped with an interface toward a Dynamic Random Access Memory to be able to run software, load, and store data.

[0051] There are multiple candidates for System-on-Chip 5 integration, such as proprietary chiplets like multi-core CPU architectures where basic chiplets may be CPU cores 8, GPU cores 9, Level 3 cache memory 10 and High bandwidth memory (HBM) modules. Further, open standard chiplets may be used where CPU core 8, GPU core 9, interconnect elements an image processing unit 12 and an artificial intelligence (Al) accelerator may be used to build a large SoC. Also, complex SoCs like the Jetson AGX Orin Series Hardware Architecture by Nvidia may be used.

[0052] Large SoCs may have a worse manufacturing yield than smaller ones. This may justify the usage of chiplets. In case of a chiplet-based system, one major hurdle to overcome may however be to amortize the development of the complete set of SoCs in the form of chiplets.

[0053] In an optimized context, it may be beneficial to reuse existing System-on-Chips 5 which have been designed to be housed as a standalone die in a dedicated R.415220

[0054] - 9 - package. The reuse in the context of chiplets may be possible provided these System-on-Chips 5 provide a function close to the expected one. This may be typically the case of an Al (artificial intelligence) accelerator device, a standalone CPU, or a standalone GPU. The benefit may become obvious as those System- on-Chips 5 are already existing and have already a validated business model which amortizes the development and manufacturing costs.

[0055] Considering that a chiplet is a part of a larger SoC assembly / system, the typical exchanges over an SoC interconnect may be memory mapped accesses using bus transactions. The physical medium to carry those transactions for chiplet- based system may for example be defined per UCIe standard. Unfortunately, off- the-shelf application specific standard products (ASSPs) may not provide such kind of interface.

[0056] According to embodiments of the invention, an off-the-shelf ASSP as a System- on-Chip 5 may be used in the chiplet assembly 1 . The off-the-shelf ASSP may comprise a physical interface 6 for connection to an electronic memory, particularly a Dynamic Random Access Memory, particularly a Double Data Rate Synchronous Dynamic Random Access Memory (DDR-RAM). The chiplet assembly 1 according to the invention may comprise a specific chiplet, namely the system management controller 3 (SMC), which may provide access via corresponding interfaces 4 to a shared electronic memory 2, particularly a (centralized) Dynamic Random Access Memory, preferably a DDR memory, to at least one sensor (f.e. a camera, radar, lidar or ultrasonics sensor) as well as to at least one communication interface 15 (f.e. Ethernet, PCIe, USB, CAN, SPI, etc...). The chiplet assembly 1 may be organized around the shared electronic memory 2, i.e. the Dynamic Random Access Memory, particularly DDR memory, under the control of the system management controller 3. The System-on-Chip 5 specifically developed for the chiplet assembly 1 according to the invention may be attached to the system management controller 3 and perform memory mapped transactions by way of the physical interface 6, particularly a UCIe physical interface 6. Off-the-shelf ASSPs, when reused as chiplets, may be attached to the system management controller 3 and access the shared electronic memory 2 through their physical interface 6, i.e. the DDR interface. R.415220

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[0058] The system management controller 3 may be equipped with two kinds of memory interfaces 4. A first memory interface 4 may be the regular one performing access towards external DDR devices. This may be the one used to implement access to / from the shared electronic memory 2 for needs of the system management controller 3 as well as for other chiplets’ needs. A second memory interface 4 may be a dual form, which may normally be found in memory devices, particularly DDR memory devices, to allow the System-on-Chip 5 to perform memory mapped transactions using its regular memory interface 4. In other words, the System-on-Chip 5 may think it is exchanging with a memory device while it is exchanging with the system management controller 3.

[0059] The system management controller 3 may translate memory access commands which are posted by the off-the-shelf ASSP, into memory mapped transactions suitable to a bus structure and / or bus protocol of the system management controller 3 towards the shared electronic memory 2. The translation of the memory access commands to the interconnect bus commands may necessitate some address remapping which may be performed by a Memory Management Unit 17 (MMU), but other means are also possible. This address translation may take place in the system management controller 3.

[0060] The memory interface 4 may use an LPDDR5 / LPDDR5X standard. Particularly, commands of the JEDEC 209-5C standard may be utilized. However, only a subset of these commands may have to be considered by the system management controller 3, as the off-the-shelf ASSP, i.e. the System-on-Chip 5 according to the invention operating in the chiplet assembly 1 is no longer exchanging with a true memory device but with the system management controller 3 in charge of translating those commands into a memory mapped transaction suitable to be carried out over the bus structure 16 of the system management controller 3.

[0061] The commands that should remain are particularly the ones allowing to define an addressing scheme of read and / or write transactions. It may be noticed that DDR memory devices typically operate in burst mode. R.415220

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[0063] Depending on a channel width (x8, x16) of a LPDDR5 / LPDDR5X device that is used, a bank size (8Mb to 512 Mb) and an addressing mode (8B, BG, 16B), it may be possible to form a linear byte address from the Bank group number, the Bank number, the Row number, the Column number, and the burst index.

[0064] Any collection of commands for read and / or write access may be analysed to form such start address of burst access. It seeds the principle that it could be translated into any bus protocol capable of burst accesses.

[0065] As an example, the AXI protocol of the ARM Ltd AMBA bus specification may be used in the bus structure or as the bus protocol of the system management controller 3. It can be extended to a more complex protocol like the CHI protocol of ARM Ltd AMBA bus specification, to the equivalent OCP open standard specification, or the Intel proprietary CPI bus specification by applying the same principles. However, any form of bus protocol offering the capability of memory mapped burst transactions may offer an acceptable translation of original memory access transactions according to the invention.

[0066] According to the invention, the memory access commands may be turned to a memory mapped transaction in the form of burst accesses. The characteristics of the memory mapped transactions may have a lot of common aspects with capabilities of protocols like the AXI bus protocol or the CHI protocol. Some form of translation may thus be possible.

[0067] Beside the memory mapped transaction to bus transaction translation, some form of address translation may be needed. A reason for the addresses translation need may be that the System-on-Chip 5, planned to be reused in the chiplet assembly 1 , has been built without any knowledge of the memory mapping it will face when in the context of the chiplet assembly 1 . The memory mapping of the System-on-Chip 5 may have some flexibility but some elements may remain hardcoded, hence a translation may be required. In case the shared electronic memory 2 managed by the system management controller 3 must be entirely or partly visible to the System-on-Chip 5, its local DDR memory aperture may be entirely or partially remapped in the targeted shared electronic memory 2 of the chiplet assembly 1 . R.415220

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[0069] Part of the memory map of the System-on-Chip 5 may be remapped in a single chunk into the shared electronic memory 2 managed by the system management controller 3. Such address translation may easily be implemented by a simple offset addition / subtraction to the original base address which is submitted in the memory mapped transaction.

[0070] The remapping may also be scattered. In that context a simple hardware for a linear mapping may no longer suffice. Thus, a form of MMU 17 may be used to perform the address translation required by the expected memory remapping.

[0071] The above explanation of the embodiments describes the present invention in the context of examples. Of course, individual features of the embodiments can be freely combined with each other, provided that this is technically reasonable, without leaving the scope of the present invention.

Claims

R.415220- 13 -Claims1 . A chiplet assembly (1), comprising:A shared electronic memory (2),A system management controller (3), the system management controller (3) comprising a memory interface (4) for accessing the shared electronic memory (2),A System-on-Chip (5), the System-on-Chip (5) being connected to the system management controller (3) via a physical interface (6), the physical interface (6) being designed to enable an access of the System-on-Chip (5) to electronic memories,A substrate (7) for accommodating the system management controller (3) and the System-on-Chip (5).

2. The chiplet assembly (1) of claim 1 , characterized in that the System-on- Chip (5) is a multi-core CPU architecture comprising at least one CPU core (8), at least one GPU core (9), a cache memory (10) and at least one high bandwidth memory module (11).

3. The chiplet assembly (1) of claim 1 , characterized in that the System-on- Chip (5) comprises at least one CPU core (8), at least one GPU core (9), an image processing unit (12) and an artificial intelligence accelerator (13).

4. The chiplet assembly (1) of any one of the preceding claims, characterized in that the system management controller (3) further comprises a sensor interface (14) to provide an access to at least one sensor.

5. The chiplet assembly (1) of any one of the preceding claims, characterized in that the system management controller (3) further comprises at least one communication interface (15).R.415220- 14 -6. The chiplet assembly (1) of any one of the preceding claims, characterized in that the system management controller (3) is designed to translate memory access commands of the System-on-Chip (5) into memory mapped transactions suitable to a bus structure (16) of the system management controller (3) towards the shared electronic memory (2).

7. The chiplet assembly (1) of claim 6, characterized in that the translation of the memory access commands comprises a remapping of memory addresses.

8. The chiplet assembly (1) of claim 7, characterized in that the memory address remapping is performed by a Memory Management Unit (17) of the system management controller (3).

9. The chiplet assembly (1) of claims 6 to 8, characterized in that the translation of the memory access commands comprises defining an addressing scheme of read and / or write transactions from the System- on-Chip (5) to the shared electronic memory (2).

10. A method for translating memory access commands in a chiplet assembly (1) according to any one of the preceding claims, comprising:Translating memory access commands of a System-on-Chip (5) into memory mapped transactions suitable to a bus structure (16) of the system management controller (3) towards a shared electronic memory (2) of the chiplet assembly (1), the translating particularly comprising a remapping of memory addresses and / or defining an addressing scheme of read and / or write transactions from the System-on-Chip (5) to the shared electronic memory (2).

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