Semiconductor device

Abstract

The present invention provides a semiconductor device having reduced power consumption. The semiconductor device has a first transistor, a second transistor, a third transistor, a first capacitive element, and a second capacitive element. The first transistor has a first gate and a second gate. The first gate of the first transistor is electrically connected to one among a source and a drain of the second transistor and a first terminal of the first capacitive element. The second gate of the first transistor is electrically connected to one among a source and a drain of the third transistor and a first terminal of the second capacitive element. The first transistor has a function for writing a first potential corresponding to first data to the first terminal of the first capacitive element and writing a second potential corresponding to second data to the first terminal of the second capacitive element, thereby causing a current corresponding to a multiplication result of the first data and the second data to flow between a source and a drain of the first transistor.

Description

Semiconductor equipment

[0001] One aspect of the present invention relates to a semiconductor device.

[0002] Furthermore, one aspect of the present invention is not limited to the above-mentioned technical field. The technical field of the invention disclosed herein relates to objects, methods of operation, or methods of manufacturing. Alternatively, one aspect of the present invention relates to processes, machines, manufactures, or compositions of matter. More specifically, examples of the technical field of one aspect of the present invention disclosed herein include semiconductor devices, display devices (including liquid crystal display devices), light-emitting devices, energy storage devices, imaging devices, memory devices, processing devices, signal processing devices, sensors, computing devices (including processors), electronic devices, systems, methods for driving them, methods for manufacturing them, or methods for testing them.

[0003] Currently, there is a great deal of activity in developing integrated circuits that mimic the structure of the human brain. These integrated circuits incorporate the brain's structure as electronic circuits, and have circuits that mimic the "neurons" and "synapses" of the human brain. For this reason, such integrated circuits are sometimes called, for example, "neuromorphic," "brainmorphic," or "brain-inspired." These integrated circuits have a non-von Neumann architecture and are expected to be able to perform parallel processing with extremely low power consumption compared to the von Neumann architecture, where power consumption increases with increasing processing speed.

[0004] A model of information processing that mimics a neural network having "neurons" and "synapses" is called an artificial neural network (ANN). For example, Non-Patent Documents 1 and 2 disclose a computing device that constructs an artificial neural network using SRAM (Static Random Access Memory).

[0005] Furthermore, as a computing device that constitutes an artificial neural network, Patent Document 1 discloses, for example, a computing device that includes a multiplication cell that performs multiplication using the current in the subthreshold region of a transistor. Patent Document 1 also discloses, for example, a method for adjusting weight coefficients in order to correct for variations in the calculation results.

[0006] Japanese Patent Publication No. 2024-65044

[0007] M. Kang et al., "IEEE Journal of Solid-State Circuits", 2018, Volume 53, No. 2, pp. 642-655. J. Zhang et al., "IEEE Journal of Solid-State Circuits", 2017, Volume 52, No. 4, pp. 915-924. Takashi Koida, "High-Mobility Transparent Conductive Film", National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Presentation Meeting 2019, Internet <URL: https: / / unit.aist.go.jp / jp / rpd-envene / PV / ja / results / 2019 / oral / T13. html>

[0008] An example of a computing device that constitutes an artificial neural network is a computing device that performs a sum-of-products operation by adding up analog currents corresponding to the product of weight coefficients and input data, such as the computing device described in Patent Document 1. Because this computing device uses analog current for calculations, it can reduce the circuit size and circuit area compared to a computing device composed of digital circuits. Furthermore, by designing this computing device to handle small analog currents in calculations, the power consumption of the computing device can be reduced.

[0009] One example of the above-mentioned arithmetic device is a configuration having a cell array in which arithmetic cells are arranged in a matrix, each holding a weight coefficient in an arithmetic cell, multiplying the held weight coefficient by the input data input to the arithmetic cell, and outputting the result of the multiplication as an analog current. By configuring the system in such a way that the analog currents output from each arithmetic cell arranged in a row are added together, the sum of the analog currents can be treated as the result of a sum-of-products operation between the weight coefficient and the input data.

[0010] The calculation cell in the above-mentioned arithmetic unit has the function of holding weight coefficients, and by providing input data to the calculation cell, it is possible to multiply the weight coefficients by the input data. However, since the calculation cell cannot hold the input data, when multiplication is performed in the calculation cell, the input data must be input to the calculation cell from the drive circuit each time. At this time, the drive circuit performs a process of converting the input data into analog current each time, which may result in high power consumption.

[0011] One aspect of the present invention aims to provide a semiconductor device with reduced power consumption. Alternatively, one aspect of the present invention aims to provide a semiconductor device capable of holding a multiplier and a multiplicand. Alternatively, one aspect of the present invention aims to provide a semiconductor device with a wide range of arithmetic operations. Alternatively, one aspect of the present invention aims to provide a novel semiconductor device.

[0012] It should be noted that the problems addressed by one aspect of the present invention are not limited to the above-mentioned problems. The above-mentioned problems do not preclude the existence of other problems. These other problems are those not mentioned in this section, which are described below. Those skilled in the art can deduce these other problems from the description in the specification or drawings, and can be appropriately extracted from these descriptions. It should be noted that one aspect of the present invention solves at least one of the above-mentioned problems and other problems, but it is not necessary to solve all of them.

[0013] Consider a configuration of a calculation cell that uses weight coefficients as multipliers and input data as the multiplicand, and includes at least two capacitive elements to hold the multipliers and multiplicands. Furthermore, this configuration will use an amplifying transistor that can output the multiplication result as a subthreshold current.

[0014] The following describes an example of the configuration of a computing cell, which is a semiconductor device according to one aspect of the present invention.

[0015] (1) One aspect of the present invention is a semiconductor device having a first transistor, a second transistor, a third transistor, a first capacitance element, and a second capacitance element. The first transistor also has a first gate and a second gate.

[0016] The first gate of the first transistor is electrically connected to either the source or drain of the second transistor and to the first terminal of the first capacitance element, and the second gate of the first transistor is electrically connected to either the source or drain of the third transistor and to the first terminal of the second capacitance element. Furthermore, the first transistor has the function of flowing a current between its source and drain corresponding to the multiplication result of the first data and the second data by writing a first potential corresponding to the first data to the first terminal of the first capacitance element and writing a second potential corresponding to the second data to the first terminal of the second capacitance element.

[0017] (2) Alternatively, in one aspect of the present invention, in (1) above, the second terminal of the second transistor and the second terminal of the third transistor may each be electrically connected to the first wiring.

[0018] (3) Alternatively, in one aspect of the present invention, in (1) above, the gate of the second transistor and the gate of the third transistor may each be electrically connected to the first wiring.

[0019] (4) Alternatively, in one aspect of the present invention, in (1) above, the second terminal of the first capacitance element and the second terminal of the second capacitance element may each be electrically connected to the first wiring.

[0020] (5) Alternatively, one aspect of the present invention is a semiconductor device having a plurality of first cells and a second cell. The first cell has a first transistor, a second transistor and a first capacitance element, and the second cell has a third transistor and a second capacitance element. The first transistor has a first gate and a second gate.

[0021] The first gate of the first transistor is electrically connected to either the source or drain of the second transistor and to the first terminal of the first capacitance element. Furthermore, the gates of each of the second transistors contained in multiple first cells are electrically connected to the first wiring. Additionally, the second gates of each of the first transistors contained in multiple first cells are electrically connected to either the source or drain of the third transistor and to the first terminal of the second capacitance element.

[0022] Each of the first transistors contained in the multiple first cells has the function of passing a current between the source and drain of the first transistor, corresponding to the product of the first data and the second data, by writing a first potential corresponding to the first data to the first terminal of the first capacitance element and a second potential corresponding to the second data to the first terminal of the second capacitance element.

[0023] (6) Alternatively, in one aspect of the present invention, in (5) above, the gate of the third transistor may be electrically connected to the first wiring.

[0024] (7) Alternatively, in one aspect of the present invention, in (5) above, the second terminal of each of the first capacitance elements contained in a plurality of first cells and the second terminal of the second capacitance element contained in a second cell may be electrically connected to the second wiring.

[0025] (8) Alternatively, in any one of (1) to (7) above, each of the first to third transistors may have an oxide containing indium in the channel forming region. In particular, each of the first to third transistors has an on current ratio to off current of 1.0 × 10 １７ It is preferable that the above conditions are met.

[0026] By using the semiconductor device configurations described in (1) to (8) above as a calculation cell, a multiplier can be held at the first terminal of the first capacitance element, and a multiplicand can be held at the first terminal of the second capacitance element. Furthermore, since a potential corresponding to the multiplier is applied to the gate of the first transistor, and a potential corresponding to the multiplicand is applied to the back gate of the first transistor, the first transistor can supply a current proportional to the product of the multiplier and the multiplicand as a source-drain current. In addition, by including an indium-containing oxide in the channel formation region of the first transistor, the ranges of multipliers and multiplicands that can be handled can be widened.

[0027] According to one aspect of the present invention, a semiconductor device with reduced power consumption can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device capable of storing multipliers and multiplicands can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with a wide range of arithmetic operations can be provided. Alternatively, according to one aspect of the present invention, a novel semiconductor device can be provided.

[0028] Furthermore, the effects of one aspect of the present invention are not limited to the effects described above. The effects described above do not preclude the existence of other effects. Other effects are those described below that are not mentioned in this section. Effects not mentioned in this section can be derived by those skilled in the art from the description in the specification or drawings, etc., and can be appropriately extracted from these descriptions. Furthermore, one aspect of the present invention has at least one of the effects described above and other effects. Accordingly, one aspect of the present invention may, in some cases, not have the effects listed above.

[0029] Figures 1A, 1B, 1C, and 1D are circuit diagrams showing an example of an arithmetic circuit. Figure 2 is a circuit diagram showing an example of the configuration of an arithmetic unit. Figures 3A, 3B, 3C, and 3D are circuit diagrams showing an example of the configuration of a circuit included in an arithmetic unit. Figure 4 is a timing chart showing an example of the operation of an arithmetic unit. Figure 5 is a circuit diagram showing an example of the configuration of an arithmetic unit. Figure 6 is a schematic plan view showing an example of the configuration of an arithmetic circuit. Figure 7 is a schematic cross-sectional view showing an example of the configuration of an arithmetic unit. Figure 8 is a schematic cross-sectional view showing an example of the configuration of a transistor included in an arithmetic unit. Figures 9A and 9B are schematic cross-sectional views showing an example of the configuration of a transistor included in an arithmetic unit. Figure 10A is a schematic plan view showing an example of the configuration of a transistor included in an arithmetic unit, and Figures 10B and 10C are schematic cross-sectional views showing an example of the configuration of a transistor included in an arithmetic unit. Figure 11 is a schematic perspective view showing an example of the configuration of a transistor included in an arithmetic unit. Figures 12A and 12B are diagrams illustrating the carrier concentration dependence of Hall mobility. Figure 12C is a cross-sectional view illustrating an indium oxide film. Figures 13A, 13B, 13C, and 13D are diagrams illustrating examples of electronic components. Figure 14 is a diagram illustrating an example of an information processing system. Figure 15 is a diagram illustrating an example of space equipment. Figure 16 is a diagram illustrating an example of a storage system applicable to a data center. Figures 17A1, 17A2, 17A3, 17A4, 17A5, 17A6, 17A7, and 17B1, 17B2, 17B3, 17B4, 17B5, and 17B6 are circuit diagrams illustrating electrical connections.

[0030] (Notes relating to this specification) In this specification, a semiconductor device is a device that utilizes semiconductor properties, and refers to a circuit containing semiconductor elements (e.g., transistors, diodes, and photodiodes), or a device having such a circuit. Furthermore, a semiconductor device refers to any device that can function by utilizing semiconductor properties. An example of a semiconductor device is an integrated circuit. Another example of a semiconductor device is a chip equipped with an integrated circuit. Another example of a semiconductor device is an electronic component in which a chip is housed in a package. Furthermore, for example, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices may be semiconductor devices themselves or may have semiconductor devices.

[0031] In this specification, "connection" includes, for example, "electrical connection."

[0032] Furthermore, when describing the connection relationships of circuit elements as physical objects, the term "electrical connection" includes, for example, "direct connection" and "indirect connection." "A and B are directly connected" means, for example, that A and B are connected without the use of circuit elements (e.g., transistors or switches; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means, for example, that A and B are connected through one or more circuit elements. A, B, and C (described later) refer to objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0033] Here, when we define "A and B are indirectly connected," it refers to the following type of connection, as an example: That is, assuming the circuit is operating, if there are times during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then such a circuit can be defined as having "A and B indirectly connected" as a physical object. Even if there are times when no electrical signals are exchanged or potential interactions occur between A and B, if there are times during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined as having "A and B indirectly connected." Note that "A and B are indirectly connected" is a definition of the connection relationship between circuit elements as a physical object. Therefore, for example, even if no power supply voltage is supplied to the circuit and the circuit is not operating, the circuit can still be defined as having "A and B indirectly connected" as a physical object (however, as an example, this is limited to cases where, when power supply voltage is supplied to the circuit and the circuit is operating, electrical signals are exchanged or potential interactions occur between A and B during the circuit's operation).

[0034] The following are specific examples of "indirect connections". First, an example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors, as shown in Figures 17A1 and 17A2. Another example of a case where "A and B are indirectly connected" is when A and B are connected via one or more switches. When "A and B are indirectly connected", assuming the circuit is operating, one transistor between A and B will be in an ON state, conducting state, or a state in which current can flow at least once. Note that when "A and B are indirectly connected", this includes cases where one transistor between A and B is in an OFF state or a non-conducting state. When "A and B are indirectly connected" and multiple transistors are connected between A and B, assuming the circuit is operating, each of the multiple transistors between A and B will be in an ON state, conducting state, or a state in which current can flow at least once. In other words, when "A and B are indirectly connected," it is not necessary for all of the transistors to be in an ON state, a conducting state, or a state in which current can flow simultaneously. Therefore, when "A and B are indirectly connected," it includes cases where the transistors between A and B are in an OFF state or a non-conducting state at the same time or at different times. As another example, as shown in Figure 17A3, when A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, it can be defined as "A and C are indirectly connected," "B and C are indirectly connected," or "A and B are indirectly connected." However, as will be discussed later, if a constant potential V is supplied to C from a power supply or GND, it can be said that "A and C are indirectly connected," or "B and C are indirectly connected," but it cannot be said that "A and B are indirectly connected."

[0035] Having shown examples of cases where a connection can be considered "indirect" and cases where it cannot, let's look at another example of a case where a connection cannot be considered "indirect." Even if electrical signals are exchanged or potential interactions occur between A and B during the operation of the circuit, there are exceptional cases where it cannot be said that "A and B are indirectly connected." An example of such an exceptional case is when A and B are connected via an insulator. In other words, when A and B are connected via an insulator, it cannot be said that "A and B are indirectly connected." A specific example of when A and B are connected via an insulator is when a capacitive element is connected between A and B, as shown in Figure 17A4. Another example of when A and B are connected via an insulator is when a transistor gate insulating film is interposed between A and B, as shown in Figure 17A5. In this case, it cannot be said that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected."

[0036] Another example of a situation where it cannot be said that "A and B are indirectly connected" is when there is no timing for the exchange of electrical signals or potential interaction between A and B. For example, as shown in Figures 17A6 and 17A7, multiple transistors are connected via sources and drains in the path from A to B, and a constant potential V is supplied to the nodes between the transistors from a power source or GND. In this case, it cannot be said that "A and B are indirectly connected," but it can be said that "A and V are indirectly connected," or "B and V are indirectly connected." In Figure 17A3, if A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, and a constant potential V is supplied to C from a power supply or GND, then the connection relationship is the same as in Figures 17A6 and 17A7, so it cannot be said that "A and B are indirectly connected," but it can be said that "A and C are indirectly connected" or "B and C are indirectly connected."

[0037] As shown above, we have provided an example of "indirect connection." As an example, the provisions for "indirect connection" are included in the provisions for "electrical connection," so if "A and B are indirectly connected," then "A and B are electrically connected."

[0038] Next, we will show specific examples of "direct connection." An example of "A and B being directly connected" is when A and B are connected without any circuit elements in between, as shown in Figures 17B1, 17B2, and 17B3. Furthermore, as shown in Figures 17B4 and 17B5, when A and B are connected to a power source that supplies a constant potential V, or to GND, without any circuit elements in between, we can say that "A and B are directly connected," "A and V are directly connected," or "B and V are directly connected." Furthermore, as shown in Figure 17B6, even when A (or B) is connected to a constant potential V via the source and drain of a transistor, we can say that "A and B are directly connected." Furthermore, since A and V, or B and V, are connected via the source and drain of a transistor, they cannot be said to be directly connected, and we can say that "A and V are indirectly connected," or "B and V are indirectly connected."

[0039] As shown above, an example of "direct connection" has been given, but as an example, since the provisions for "direct connection" are included in the provisions for "electrical connection," if "A and B are directly connected," then "A and B are electrically connected."

[0040] Even if independent components are shown connected in a circuit diagram, one component may possess the functions of multiple components. For example, if part of a "wire" also functions as an "electrode," then one conductive film possesses the functions of both a "wire" and an "electrode." Similarly, if part of a "wire" also functions as a "terminal," then one conductive film possesses the functions of both a "wire" and a "terminal." Therefore, it can be said that two or more components selected from "electrodes," "wires," and "terminals" are formed as a single unit. Furthermore, the terms "electrode," "wire," or "terminal" may be replaced with the term "region" depending on the context. Accordingly, in this specification, connection includes cases where a single conductive film possesses the functions of multiple components.

[0041] The switches described herein are described as having the function of being in an ON state or an OFF state and controlling whether or not to allow current to flow, or having the function of selecting and switching the path through which current flows.

[0042] Furthermore, in this specification, "conductive state" means a state in which current can flow between two input / output terminals, and "non-conductive state" means a state in which the two input / output terminals can be considered electrically disconnected. Also, in this specification, the ON state of a switch falls under the category of "conductive state," and the OFF state of a switch falls under the category of "non-conductive state." For this reason, in this specification, "conductive state" and "ON state" are interchangeable with each other, and "non-conductive state" and "OFF state" are interchangeable with each other.

[0043] Furthermore, in this specification, the terms "conductive" or "conductive state" used when conductive layers are in direct contact with each other refer, for example, to a state in which an electric current can flow between the conductive layers.

[0044] Furthermore, a switch may have two or more terminals for conducting current, in addition to its control terminals. Examples include electrical switches and mechanical switches. In other words, a switch is not limited to a specific type, as long as it has the function of controlling current.

[0045] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, and diode-connected transistors), or logic circuits combining these. An example of a mechanical switch is a switch using MEMS (Micro-Electro-Mechanical Systems) technology. This switch has mechanically movable electrodes, and the movement of these electrodes controls the on and off states.

[0046] In this specification, a transistor has three terminals called the gate, source, and drain. The gate is a control terminal that controls the switching between the conductive and non-conductive states of the transistor. The two terminals that function as either the source or the drain are the input and output terminals of the transistor. Depending on the conductivity type of the transistor (n-channel or p-channel) and the potential applied to the three terminals of the transistor, one of the two input and output terminals becomes the source and the other becomes the drain. For this reason, in this specification, the terms source and drain may be interchangeable. In this specification, when describing the connection relationships of a transistor, the notations "one of the source and drain" and "the other of the source and drain" are used. In this specification, one of the source and drain may be referred to as the "first electrode of the transistor" or "first terminal of the transistor," and the other of the source and drain may be referred to as the "second electrode of the transistor" or "second terminal of the transistor." Depending on the structure of the transistor, in addition to the three terminals described above, there may be a back gate. In this specification, one of the gate or back gate of a transistor may be referred to as the first gate, and the other of the gate or back gate of a transistor may be referred to as the second gate. Furthermore, in the same transistor, the terms "gate" and "back gate" may be interchangeable. Also, if a transistor has three or more gates, each gate may be referred to as the first gate, second gate, third gate, and so on.

[0047] For example, one example of a transistor described herein may include a multi-gate transistor with two or more gate electrodes. In a multi-gate structure, the channel formation regions are connected in series, resulting in a structure where multiple transistors are connected in series. Therefore, a multi-gate structure can reduce off-current and improve the transistor's breakdown voltage (improve reliability). Alternatively, a multi-gate structure can be used to obtain an Id-Vds characteristic where, when operating in the saturation region of the Id (source-drain current)-Vds (drain-source voltage) characteristic, the current between the drain and source does not change much even when the voltage between the drain and source changes, resulting in a flat slope. By utilizing an Id-Vds characteristic with a flat slope, an ideal current source circuit or an active load with a very high resistance can be realized. As a result, a differential circuit or current mirror circuit with good characteristics can be realized.

[0048] Generally, the threshold voltage of a transistor is the voltage located between the subthreshold region (weak inversion region) and the strong inversion region, and can also be described as the voltage at which the switching between the subthreshold region and the strong inversion region occurs. One example of a method for measuring the threshold voltage is to use the Id (source-drain current) - Vgs (gate-source voltage) characteristic as a basis for measuring the Id １／２ - Plot the Vgs characteristics and Id １／２ -Id on the tangent line where the slope of the Vgs characteristic is maximum １／２ One method is to use the Vgs value where = 0 as the threshold voltage. Another example is an Id-Vgs characteristic with a drain potential of 1.2V, where Id = 1.0 × 10 −１２ One method is to use Vgs, which is A, as the threshold voltage.

[0049] Furthermore, in this specification, operation in the subthreshold region of a transistor includes the case where the gate-source voltage of the transistor is lower than the threshold voltage, and more preferably, the case where the drain current of the transistor increases exponentially with respect to the gate-source voltage. In this case, the gate potential, source potential, and drain potential supplied to the transistor are also included in the case where they are appropriately supplied as potentials for the transistor to operate in the subthreshold region.

[0050] Furthermore, in this specification, the subthreshold region refers to the region in the graph showing the Id-Vgs characteristic of a transistor where Vgs is lower than the threshold voltage. Alternatively, the subthreshold region refers to the region where current flows due to carrier diffusion, deviating from the gradient dual-channel approximation (a model that only considers drift current). Alternatively, the subthreshold region refers to the region where Id increases exponentially with increasing Vgs. Alternatively, the subthreshold region includes regions that can be considered as the regions described in each of the above explanations.

[0051] Furthermore, in this specification, the source-drain current when a transistor operates in the subthreshold region is referred to as the subthreshold current. The subthreshold current increases exponentially with respect to the gate-source voltage, regardless of the drain potential.

[0052] Furthermore, generally speaking, the off-current in a transistor sometimes refers to the source-drain current that flows when the gate-source voltage Vgs is lower than the threshold voltage. For this reason, the off-current may include the subthreshold current. In this specification, since we are dealing with circuits driven by the subthreshold current, unless otherwise specified, the off-current will be described as a current smaller than the subthreshold current.

[0053] Furthermore, in this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of constituent elements. Therefore, they do not limit the number of constituent elements. Nor do they limit the order of constituent elements, such as process order or layering order. In addition, even if a term in this specification does not have an ordinal number, an ordinal number may be added in the claims to avoid confusion of constituent elements. Also, even if a term in this specification has an ordinal number, a different ordinal number may be added in the claims. Furthermore, even if a term in this specification has an ordinal number, the classifier may be omitted in the claims. For example, a constituent element that is labeled with the ordinal number "first" in one embodiment of this specification may be labeled with a different ordinal number such as "second," "third," etc., in other embodiments or claims. Also, for example, a constituent element that is labeled with the ordinal number "first" in one embodiment of this specification may be omitted in other embodiments or claims.

[0054] Furthermore, this specification may use timing charts to explain the operation of semiconductor devices. The timing charts used in this specification represent ideal operating examples, and the periods, magnitudes of signals (e.g., potential or current) and timings shown in the timing charts are not limited unless otherwise specified. Depending on the situation, the magnitudes and timings of the signals (e.g., potential or current) input to each wiring (including nodes) in the timing charts described herein may be modified. For example, even if two periods are shown at equal intervals in a timing chart, the lengths of the two periods may differ. Also, for example, even if one period is shown as longer and the other as shorter, the lengths of the two periods may be equal, or one period may be shorter and the other longer. Furthermore, in order to clearly illustrate the timing chart, for example, two or more overlapping signals may be intentionally offset in the illustration.

[0055] The embodiments described herein are explained with reference to the drawings. However, it will be readily apparent to those skilled in the art that the embodiments can be implemented in many different ways, and their form and details can be modified in various ways without departing from the spirit and scope thereof. Therefore, the present invention is not to be interpreted as being limited to the contents described in the embodiments. In the configuration of the invention in the embodiments, the same reference numerals are used in common across different drawings for the same parts or parts having similar functions, and repeated explanations may be omitted. Also, in perspective views and the like, some components may be omitted in order to ensure clarity of the drawings.

[0056] In this specification, when the same reference numeral is used for multiple elements, and especially when it is necessary to distinguish them, the reference numeral may be accompanied by an identifying numeral such as "_1", "[n]", or "[m,n]". In addition, in drawings, etc., when an identifying numeral such as "_1", "[n]", or "[m,n]" is accompanied by a reference numeral, the identifying numeral may be omitted in this specification if it is not necessary to distinguish them.

[0057] Furthermore, in the drawings of this specification, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown in the drawings. For example, they may include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences.

[0058] (Embodiment 1) This embodiment describes a semiconductor device according to one aspect of the present invention.

[0059] <Example of arithmetic circuit configuration 1> Figure 1A shows a two-input, one-output arithmetic circuit MP. Specifically, the arithmetic circuit MP has, for example, terminal ITW, which is one of the two input terminals, terminal ITX, which is the other of the two input terminals, and terminal OT, which is the output terminal. The arithmetic circuit MP also has a transistor M1. In addition to the gate, transistor M1 also has a back gate.

[0060] The calculation circuit MP inputs an analog potential corresponding to the multiplier to terminal ITW and an analog potential corresponding to the multiplicand to terminal ITX, thereby converting the product of the multiplier and the multiplicand into a current and flowing that amount of current through terminal OT. Specifically, for example, if the multiplier is w and the multiplicand is x, the calculation circuit MP can flow a current of w × x through terminal OT.

[0061] In this specification, the multiplier is referred to as the first data, and each of the multiple multiplicands is referred to as the second data. Furthermore, the terms multiplier and multiplicand are interchangeable by the commutative property of multiplication. For example, the multiplier can be referred to as the second data, and each of the multiple multiplicands can be referred to as the first data.

[0062] In the arithmetic circuit MP, the gate of transistor M1 is connected to terminal ITW, the back gate of transistor M1 is connected to terminal ITX, and the first terminal of transistor M1 is connected to wiring VEL. The second terminal of transistor M1 is connected to terminal OT.

[0063] In this specification, transistor M1 is described as operating in the subthreshold region. Therefore, the operation of transistor M1 in this specification includes the case where the gate, back gate, source, and drain of transistor M1 are each appropriately supplied with a potential for transistor M1 to operate in the subthreshold region.

[0064] In Figure 1A, transistor M1 is an n-channel transistor. Preferably, transistor M1 is an OS transistor (also called an OS transistor) that includes an oxide semiconductor in its channel formation region. OS transistors have the characteristic of having an extremely low off-current. In particular, it is even more preferable to use an OS transistor that includes indium oxide in its channel formation region (an I / O transistor). Among OS transistors, I / O transistors have a large on-current. Therefore, the ratio of the on-current to the off-current of an I / O transistor is 1.0 × 10⁻⁶. １７As described above, it has large characteristics, and the range of current flowing when the IO transistor is operated in the subthreshold region (subthreshold current) is larger than that of a transistor that includes silicon in the channel formation region (also called a Si transistor). By applying an IO transistor to transistor M1 and increasing the range of subthreshold current in transistor M1, the output range of the calculation result output from terminal OT of the arithmetic circuit MP can be widened.

[0065] In this context, the on-current of a transistor can be defined as the current that flows between the source and drain of the transistor when the gate-source voltage is higher than the threshold voltage. Specifically, the on-current can be defined as the source-drain current that saturates as Vgs increases in the Id-Vgs characteristic graph. Furthermore, the off-current of a transistor can be defined as the minimum source-drain current at which the transistor operates in the subthreshold region. In addition, the off-current may be defined as the source-drain current that saturates as Vgs decreases in the region where the gate-source voltage is lower than the subthreshold voltage, as represented by the Id-Vgs characteristic graph.

[0066] Furthermore, indium oxide will be described in detail in Embodiment 2.

[0067] Wiring VEL functions, for example, as wiring that provides a fixed potential. This fixed potential can be the ground potential, a negative potential, or, depending on the circumstances, a positive potential.

[0068] Furthermore, since transistor M1 is an n-channel transistor, if the wiring VEL is set to a fixed potential that provides ground potential or a negative potential, the current output by the arithmetic circuit MP to terminal OT will be a sink current.

[0069] Furthermore, in the arithmetic circuit MP, the analog potential input to terminal ITW is the potential at which transistor M1 is driven in the subthreshold region. Therefore, for example, the analog potential corresponding to the multiplier w is V ｗ When this is the case, w and Vｗ The relationship shall satisfy the following formula (1.1). That is, V ｗ shall be proportional to log[w].

[0070]

[0071] In addition, when w is 0, in this specification, the arithmetic circuit MP is described as not outputting current to the terminal OT. In this specification, the description of "not flowing current" may be described by rephrasing it as a current of amount 0 flowing.

[0072] Similarly, in the arithmetic circuit MP, the analog potential input to the terminal ITX is the potential at which the transistor M1 is driven in the subthreshold region. Therefore, for example, when the analog potential corresponding to the multiplicand x is V ｘ when x and V ｘ The relationship shall satisfy the following formula (1.2). That is, V ｘ shall be proportional to log[x].

[0073]

[0074] In addition, when x is 0, in this specification, the arithmetic circuit MP is described as flowing a current of amount 0 to the terminal OT.

[0075] Next, consider the amount of current I flowing between the source and drain of the transistor M1. When the transistor M1 is driven in the subthreshold region, I, which is the amount of subthreshold current, can be expressed as in the following formula (1.3).

[0076]

[0077] Note that V Ｇ is the effective gate potential in the transistor M1, V Ｓ is the source potential, V ｔｈ is the threshold voltage of the transistor M1. Also, I ａ is the source-drain current when V Ｇ −V Ｓ is V ｔｈ . Also, J is a correction coefficient determined by the temperature, device structure, etc. of the transistor M1.

[0078] Furthermore, the effective gate potential V in transistor M1 in this specification Ｇ This takes into account the potentials of the gate and back gate of transistor M1. ｗ A voltage is provided, and the back gate of transistor M1 is connected to terminal ITX. ｘ Given V Ｇ This can be expressed as shown in equation (1.4) below. Furthermore, by using equation (1.4), equation (1.3) can be rewritten as shown in equation (1.5) below.

[0079]

[0080] Furthermore, the first data w can be described as shown in equation (1.6) below, derived from equation (1.1). Similarly, the second data x can be described as shown in equation (1.7) below, derived from equation (1.2). Also, I ０ It is defined as shown in equation (1.8) below.

[0081]

[0082] By using equations (1.6) through (1.8), equation (1.5) can be rewritten as equation (1.9) below.

[0083]

[0084] As shown in equation (1.9), the amount of subthreshold current I flowing between the source and drain of transistor M1 is proportional to the product of the first data w and the second data x. Therefore, by performing analog current-to-digital potential conversion on the amount of current I flowing through terminal OT of the arithmetic circuit MP, the product of the first data w and the second data x can be obtained as digital data.

[0085] <Example of arithmetic circuit configuration 2> Next, we will explain an example of modifying the arithmetic circuit MP.

[0086] The arithmetic circuit IM1 shown in Figure 1B is a modified example of the arithmetic circuit MP in Figure 1A, and in addition to the function of multiplying the first data w and the second data x, it also has the function of an analog potential V corresponding to the first data w. ｗ And V, which is the analog potential corresponding to the second data x. ｘ The configuration has the function of holding each of these elements using different capacitive elements.

[0087] The arithmetic circuit IM1 includes, as an example, transistors M1 to M3, a capacitive element C1, and a capacitive element C2.

[0088] The gate of transistor M1 is connected to the first terminal of transistor M2 and the first terminal of capacitive element C1, and the back gate of transistor M1 is connected to the first terminal of transistor M3 and the first terminal of capacitive element C2. Furthermore, the first terminal of transistor M1 is connected to wiring VEL, and the second terminal of transistor M1 is connected to wiring ZL via terminal OT. The gate of transistor M2 is connected to wiring WSL, and the second terminal of transistor M2 is connected to wiring WCL via terminal ITW. The gate of transistor M3 is connected to wiring XSL, and the second terminal of transistor M3 is connected to wiring XCL via terminal ITX.

[0089] In Figure 1B, the connection points between the gate of transistor M1, the first terminal of transistor M2, and the first terminal of capacitive element C1 are shown as node N1. Furthermore, the connection points between the back gate of transistor M1, the first terminal of transistor M3, and the first terminal of capacitive element C2 are shown as node N2.

[0090] Transistor M2 functions as a switching transistor to maintain the potential of node N1. Similarly, transistor M3 functions as a switching transistor to maintain the potential of node N2.

[0091] Transistors M2 and M3 can each be transistors applicable to transistor M1. In particular, it is preferable to use OS transistors for each of transistors M2 and M3. Because OS transistors have the characteristic of having an extremely small off-current, by using OS transistors for transistors M2 and M3, which function as switching transistors, the fluctuation of the potentials of nodes N1 and N2 due to the off-current can be reduced. As a result, the potentials of nodes N1 and N2 can be maintained for a long period of time in the arithmetic circuit IM1. Furthermore, it is even more preferable to use I / O transistors among OS transistors for each of transistors M2 and M3. Because I / O transistors have a large on-current among OS transistors, by using I / O transistors for each of transistors M2 and M3, the amount of current flowing between the source and drain when transistors M2 and M3 are in the ON state can be increased. As a result, the writing speed of the potentials to nodes N1 and N2 can be increased in the arithmetic circuit IM1.

[0092] For example, the wiring WSL functions as a selection signal line for transmitting a selection signal to turn on the writing transistor included in the arithmetic circuit IM1 when selecting the arithmetic circuit IM1 as the destination for writing the first data w. This writing transistor can be transistor M2. Furthermore, for example, the wiring WSL also functions as a wiring for transmitting a non-selection signal to turn off the writing transistor in the arithmetic circuit IM1 where the first data w is not written.

[0093] Wiring XSL, for example, functions as a wire for transmitting a selection signal to turn on the writing transistor included in the arithmetic circuit IM1 when selecting the arithmetic circuit IM1 as the writing destination for the second data x. This writing transistor can be transistor M3. Wiring XSL also functions as a wire for transmitting a non-selection signal to turn off the writing transistor in the arithmetic circuit IM1 where the second data x is not written, for example.

[0094] In Figure 1B, since transistors M2 and M3 are both n-channel transistors, it is preferable that the selection signal transmitted to wiring WSL and wiring XSL be at a high level potential, and the deselection signal transmitted to wiring WSL and wiring XSL be at a low level potential.

[0095] Wiring WCL, for example, functions as wiring for writing a potential corresponding to the first data w to node N1.

[0096] Wiring XCL, for example, functions as wiring for writing a potential corresponding to the second data x to node N2.

[0097] For example, in the arithmetic circuit IM1, wiring ZL functions as wiring for passing the result of multiplication between the first data w written to node N1 and the second data x written to node N2 as current.

[0098] Wiring VCL1 functions, for example, as wiring for providing a fixed potential. This fixed potential can be a positive potential, ground potential, negative potential, etc. By providing this fixed potential to wiring VCL1, the voltage between the first and second terminals of the capacitive element C1 can be maintained, preventing unintended fluctuations in the potential of node N1. Similarly, wiring VCL2 also functions, for example, as wiring for providing a fixed potential. This fixed potential can be a positive potential, ground potential, negative potential, etc. By providing this fixed potential to wiring VCL2, the voltage between the first and second terminals of the capacitive element C2 can be maintained, preventing unintended fluctuations in the potential of node N2. If the fixed potentials provided by wiring VCL1 and wiring VCL2 are equal, wiring VCL1 and wiring VCL2 can be considered the same wiring.

[0099] In the circuit configuration of the calculation circuit MP shown in Figure 1A, in order to output the result of the multiplication of the first data w and the second data x as a current from terminal OT, a potential V corresponding to the first data w is set at each of terminals ITW and ITX. ｗ and the potential V corresponding to the second data x ｘ You need to keep inputting this. In other words, the potential V ｗ A drive circuit that generates and applies to terminal ITW, and potential V ｘ The drive circuit that generates and supplies it to terminal ITX, and each of these must be kept in an active state at all times.

[0100] On the other hand, the arithmetic circuit IM1 in Figure 1B can hold the first data w by the capacitive element C1 and the second data x by the capacitive element C2. Therefore, the drive circuit is at potential V ｗ The following is generated and written once to the first terminal of the capacitive element C1, and the drive circuit is at potential V ｘ After generating the data and writing it once to the first terminal of the capacitive element C2, each drive circuit can be stopped. In other words, unlike the case of the arithmetic circuit MP in Figure 1A, by using the arithmetic circuit IM1 in Figure 1B, the power consumption required to drive the drive circuit can be reduced.

[0101] Furthermore, the semiconductor device according to one aspect of the present invention is not limited to the circuit configuration of the arithmetic circuit IM1 shown in Figure 1B. The semiconductor device according to one aspect of the present invention can be provided by appropriately modifying the circuit configuration of the arithmetic circuit IM1.

[0102] The calculation circuit IM2 in Figure 1C is a modified example of the calculation circuit IM1, in which the wiring WCL and wiring XCL in Figure 1B are replaced by a single wiring, wiring WXCL. Therefore, the wiring WXCL shown in Figure 1C is assumed to have the same roles as the wiring WCL and wiring XCL in Figure 1B. In other words, wiring WXCL controls the potential V corresponding to the first data w. ｗ , or the potential V corresponding to the second data x ｘ It functions as wiring to provide [something].

[0103] In the calculation circuit IM2 of Figure 1C, a potential V corresponding to the first data w is applied to the first terminal of the capacitive element C1. ｗ When writing, a selection signal is sent to wiring WSL to turn on transistor M2, and a deselection signal is sent to wiring XSL to turn off transistor M3, and then a potential V corresponding to the first data w is sent to wiring WXCL. ｗ You just need to provide this. Also, apply a potential V corresponding to the second data x to the first terminal of the capacitive element C2. ｘ When writing, a non-selection signal is sent to wiring WSL to turn off transistor M2, and a selection signal is sent to wiring XSL to turn on transistor M3, and then a potential V corresponding to the second data x is sent to wiring WXCL. ｘ You should give it to them.

[0104] The arithmetic circuit IM2 in Figure 1C has one fewer wire than the arithmetic circuit IM1 in Figure 1B. Therefore, by using the arithmetic circuit IM2 in Figure 1C, the circuit area can be reduced compared to the arithmetic circuit IM1 in Figure 1B.

[0105] Furthermore, the arithmetic circuit IM3 in Figure 1D is a modified example of the arithmetic circuit IM1, different from the arithmetic circuit IM2 in Figure 1C, and is configured in which the wiring WSL and wiring XSL in Figure 1B are replaced by a single wiring, wiring WXSL. Therefore, the wiring WXSL shown in Figure 1D is assumed to have the respective roles of wiring WSL and wiring XSL in Figure 1B. In other words, wiring WXSL functions as wiring to provide a selection signal or a deselection signal to each of the writing transistors, transistors M2 and M3.

[0106] In the arithmetic circuit IM3 shown in Figure 1D, the wirings WSL and XSL in Figure 1B are combined into a single wiring WXSL, allowing the first data w and the second data x to be written to the arithmetic circuit IM3 simultaneously. For example, by sending a selection signal to wiring WXSL, transistors M2 and M3 are both turned on simultaneously, and at this time, wiring WCL reaches a potential V corresponding to the first data w. ｗ The wiring XCL gives a potential V corresponding to the second data x. ｘ By providing this, V is supplied to the first terminals of the respective capacitive elements C1 and C2. ｗ and V ｘ It can write to them simultaneously.

[0107] The arithmetic circuit IM3 in Figure 1D has one fewer wire configuration compared to the arithmetic circuit IM1 in Figure 1B. Therefore, by using the arithmetic circuit IM3 in Figure 1D, the circuit area can be reduced compared to the arithmetic circuit IM1 in Figure 1B. In addition, since the arithmetic circuit IM3 in Figure 1D can write the first data and the second data simultaneously, it can operate faster than the arithmetic circuit IM2 in Figure 1C, where the wires WCL and XCL are combined into a single wire WXCL.

[0108] <Example of arithmetic unit configuration> Next, we will describe an example of an arithmetic unit configuration in which the arithmetic circuits described above are arranged as arithmetic cells in a cell array.

[0109] Figure 2 shows an example configuration of an arithmetic unit capable of performing sum-of-products operations and calculating a function using the result of the sum-of-products operation as input. The arithmetic unit CDVA1, as an example, includes a cell array CA, a storage cell area CX, a drive circuit WXCD, a drive circuit WSD, a drive circuit XSD, and a drive circuit ITS.

[0110] The cell array CA has arithmetic circuits, which are arithmetic cells WM[1,1] to WM[m,n] (where m and n are integers of 1 or more), and each of the arithmetic cells WM[1,1] to WM[m,n] is arranged in an m x n matrix within the cell array CA.

[0111] The memory cell region CX has memory circuits, namely memory cells XM[1] to XM[m], and each of the memory cells XM[1] to XM[m] is arranged along the column direction in the cell array CA.

[0112] Figure 2 shows a selection of calculation cells WM[1,1], WM[1,n], WM[m,1], and WM[m,n] from the calculation cells WM[1,1] to WM[m,n], and a selection of memory cells XM[1] and XM[m] from the memory cells XM[1] to XM[m].

[0113] Furthermore, the cell array CA has wirings WCL[1] to WCL[n] and wirings ZL[1] to ZL[n], each extending along the column direction. Also, the cell array CA has wirings WSL[1] to WSL[m], each extending along the row direction. Furthermore, the storage cell area CX has wiring XCL, which extends along the column direction. Also, each of the wirings XSL[1] to XSL[m] extends to be connected to the drive circuit XSD.

[0114] Figure 2 shows excerpts of wiring WCL[1] to WCL[n], specifically wiring WCL[1] and wiring WCL[n]; excerpts of wiring ZL[1] to ZL[n], specifically wiring ZL[1] and wiring ZL[n]; and excerpts of wiring WSL[1] to WSL[m], specifically wiring WSL[1] and wiring WSL[m]. Furthermore, Figure 2 shows excerpts of wiring XSL[1] to XSL[m], specifically wiring XSL[1] and wiring XSL[m].

[0115] Each of the calculation cells WM[1,1] to WM[m,n] has a transistor M1, a transistor M2, and a capacitive element C1. Each of the memory cells XM[1] to XM[m] has a transistor M3 and a capacitive element C2.

[0116] In each of the calculation cells WM[1,1] to WM[m,n], the gate of transistor M1 is connected to the first terminal of transistor M2 and the first terminal of capacitive element C1. The second terminal of capacitive element C1 is connected to wiring VCL1, and the first terminal of transistor M1 is connected to wiring VEL.

[0117] We focus on the calculation cell WM[i,j] located in the i-th row and j-th column of the cell array CA (where i is an integer between 1 and m, and j is an integer between 1 and n), and the storage cell XM[i] located in the i-th row of the storage cell area CX. The back gate of transistor M1 in the calculation cell WM[i,j] is connected to the first terminal of transistor M3 and the first terminal of capacitive element C2 in storage cell XM[i]. The second terminal of capacitive element C2 is connected to wiring VCL2.

[0118] Furthermore, in memory cell XM[i], the first terminal of transistor M3 and the first terminal of capacitive element C2 are connected to the back gate of transistor M1 contained in each of the calculation cells WM[i,1] to WM[i,n], respectively. Therefore, the potential V corresponding to the second data x held by memory cell XM[i] ｘThis is applied to the back gate of each transistor M1 in the calculation cells WM[i,1] to WM[i,n]. Therefore, the calculation unit CDVA1 is configured such that the second data x held by the storage cell XM[i] is shared by each of the calculation cells WM[i,1] to WM[i,n] in the same row.

[0119] In the calculation cell WM[i,j], the second terminal of transistor M1 is connected to wiring ZL[j]. Also, the second terminal of transistor M2 is connected to wiring WCL[j]. Furthermore, the gate of transistor M2 is connected to wiring WSL[i].

[0120] The second terminal of transistor M3 contained in each of the memory cells XM[1] through XM[m] is connected to wiring XCL. In memory cell XM[i], the gate of transistor M3 is connected to wiring XSL[i].

[0121] Note that wiring WSL[i] corresponds to wiring WSL shown in Figure 1B, wiring WCL[j] corresponds to wiring WCL shown in Figure 1B, and wiring ZL[j] corresponds to wiring ZL shown in Figure 1B. Also, wiring XSL[i] corresponds to wiring XSL shown in Figure 1B, and wiring XCL in Figure 2 corresponds to wiring XCL shown in Figure 1B.

[0122] Furthermore, the wiring VCL1, VCL2, and VEL shown in Figure 2 function as wiring that provides a fixed potential, similar to the wiring VCL1, VCL2, and VEL shown in Figure 1B.

[0123] As described above, the circuit elements contained in the calculation cell WM[i,j] and the memory cell XM[i] shown in Figure 2 constitute the connection configuration of the calculation circuit IM1 in Figure 1B. Therefore, for the circuit configuration of the calculation cell WM[i,j] and the memory cell XM[i], as well as the multiplication operation of the first data w and the second data x, refer to the explanation of the calculation circuit IM1 in Figure 1B.

[0124] The drive circuit WXCD has the function of a drive circuit for writing first data to each of the calculation cells WM[1,1] to WM[m,n], and the function of a drive circuit for writing second data to each of the memory cells XM[1] to XM[m]. Specifically, for example, when the drive circuit WXCD writes first data w to the calculation cell WM[i,j], it has the function of acquiring first data w, which is digital data, from an external source via wiring IWL[i], converting first data w to an analog potential, and outputting it to wiring WCL[j]. Also, for example, when the drive circuit WXCD writes second data x to memory cell XM[i], it has the function of acquiring second data x, which is digital data, from an external source via wiring IXL, converting second data x to an analog potential, and outputting it to wiring XCL.

[0125] As an example, the drive circuit WXCD has circuits WCDa[1] to WCDa[n] and circuit XCDa, as shown in Figure 2. The drive circuit WXCD is also connected to wiring IWL[1] to IWL[n] and wiring IXL for transmitting digital data from an external source. Note that in Figure 2, circuits WCDa[1] and WCDa[n] are shown as an excerpt from circuits WCDa[1] to WCDa[n], and wiring IWL[1] and IWL[n] are shown as an excerpt from wiring IWL[1] to IWL[n].

[0126] Specifically, the input terminal of circuit WCDa[j] located in column j is connected to wiring IWL[j], and the output terminal of circuit WCDa[j] is connected to wiring WCL[j]. In addition, the input terminal of circuit XCDa is connected to wiring IXL, and the output terminal of circuit XCDa is connected to wiring XCL.

[0127] Each of circuits WCDa[1] to WCDa[n] has, for example, the function of generating an analog potential corresponding to a first data w. Specifically, for example, circuit WCDa[j] located in column j acquires the first data w, which is digital data, from an external source via wiring IWL[j] and generates an analog potential corresponding to the first data w. Circuit WCDa[j] also outputs the analog potential corresponding to the first data w to wiring WCL[j]. For this reason, it is preferable that each of circuits WCDa[1] to WCDa[n] has a digital-to-analog conversion circuit.

[0128] In particular, the analog potential output by the digital-to-analog conversion circuit is set to the potential at which transistor M1 is driven in the subthreshold region. Therefore, in the digital-to-analog conversion circuit included in the circuit WCDa[j] located in column j, the first data w, which is digital data input to its input terminal, and the analog potential V, which is output from its output terminal, are used. ｗ The relationship between and satisfies equations (1.1) and (1.6) above.

[0129] Furthermore, when the first data w is 0, it is preferable that each of circuits WCDa[1] to WCDa[n] outputs a potential equal to the fixed potential supplied by the wiring VEL from its output terminal.

[0130] Furthermore, circuit XCDa has, for example, the function of generating an analog potential corresponding to the second data x. Specifically, for example, circuit XCDa acquires the second data x, which is digital data, from an external source via wiring IXL and generates an analog potential corresponding to the second data x. Circuit XCDa also outputs the analog potential corresponding to the second data x to wiring XCL. For this reason, it is preferable that circuit XCDa has a digital-to-analog conversion circuit.

[0131] In particular, the analog potential output by the digital-to-analog conversion circuit is set to the potential at which transistor M1 is driven in the subthreshold region. Therefore, in the digital-to-analog conversion circuit included in circuit XCDa, the second data x, which is digital data input to its input terminal, and the analog potential V, which is output from its output terminal, are used.ｘ The relationship between and satisfies equations (1.2) and (1.7) above.

[0132] Furthermore, if the second data x is 0, it is preferable that circuit XCDa outputs a potential from its output terminal that is equal to or lower than the fixed potential supplied by wiring VEL.

[0133] As an example, the drive circuit WSD has the function of sending a selection signal to the wiring WSL[i] to turn on the transistor M2 contained in each of the calculation cells WM[i,1] to WM[i,n] located in row i, which will be the destination for writing the first data w.

[0134] Furthermore, the drive circuit WSD also has a function to send a non-selection signal to turn off the transistor M2 contained in each of the calculation cells WM[i,1] to WM[i,n] located in the i-th row, for example, when the first data w is not written to them.

[0135] For example, the drive circuit XSD has the function of sending a selection signal to the wiring XSL[i] to turn on the transistor M3 contained in the memory cell XM[i] when selecting the memory cell XM[i] to be the destination for writing the second data x.

[0136] Furthermore, the drive circuit XSD also has a function to send a non-selection signal to turn off the transistor M2 contained in the memory cell XM[i], which is located in the i-th row and does not write the second data x, as an example.

[0137] The drive circuit ITS, as an example, is the sum of the currents corresponding to the multiplication of the first data w and the second data x output by each of the calculation cells WM[1,j] to WM[m,j] located in the j-th column of the cell array CA, which flow through wiring ZL[j]. ＳＵＭ Get [j] and I ＳＵＭ The function F is used as input value [j], and the result of this operation is output as F(IＳＵＭ It has the function of outputting [j]).

[0138] The functions described above can be linear or nonlinear. Examples of nonlinear functions include the sigmoid function, tanh function, softmax function, ReLU (Rectified Linear Unit) function, or threshold function. In particular, the nonlinear functions used in the calculations of artificial neural network models are sometimes called activation functions. An example configuration of the ITS drive circuit for calculating the ReLU function will be described later.

[0139] Furthermore, if it is not necessary for the drive circuit ITS to perform the activation function calculation in the arithmetic unit CDVA1, the drive circuit ITS calculates the sum of currents I corresponding to the sum-of-products calculation of the first data w and the second data x. ＳＵＭ Get [j] and its I ＳＵＭ The output should be [j]. Alternatively, if it is not necessary to perform the activation function calculation by the drive circuit ITS, the CDVA1 may be configured without the drive circuit ITS.

[0140] The drive circuit ITS, as an example, has circuits ITSa[1] to ITSa[n] as shown in Figure 2. Furthermore, wiring OL[1] to OL[n] for outputting the results calculated by the arithmetic unit CDVA1 to the outside is connected to the drive circuit ITS. Specifically, wiring ZL[j] is connected to the input terminal of circuit ITSa[j] located in column j, and wiring OL[j] is connected to the output terminal of circuit ITSa[j].

[0141] In Figure 2, circuits ITSa[1] and ITSa[n] are shown as excerpts from circuits ITSa[1] to ITSa[n], and wiring OL[1] and wiring OL[n] are shown as excerpts from wiring OL[1] to wiring OL[n].

[0142] Next, we will describe an example of the configuration of circuits ITSa[1] to ITSa[n] provided in the drive circuit ITS shown in Figure 2.

[0143] The circuit ITSa shown in Figure 3A is an example of a circuit configuration that can be applied to circuits ITSa[1] to ITSa[n] shown in Figure 2. Circuit ITSa, as an example, includes circuit FC, conversion circuit CVT, and switch SW2.

[0144] Wiring ZL corresponds to one of the wirings ZL[1] to ZL[n] shown in Figure 2. Also, wiring OL corresponds to one of the wirings OL[1] to OL[n] shown in Figure 2.

[0145] The first terminal of switch SW2 is connected to the input terminal of circuit ITSa, and the second terminal of switch SW2 is connected to the input terminal of circuit FC. The output terminal of circuit FC is connected to the input terminal of conversion circuit CVT, and the output terminal of conversion circuit CVT is connected to the output terminal of circuit ITSa.

[0146] The switch SW2 shown in Figure 3A has the function of selecting whether or not to acquire the current flowing through wiring ZL in circuit ITSa. For example, by turning switch SW2 ON, the current flowing through wiring ZL can be acquired in circuit ITSa, and by turning switch SW2 OFF, the inflow of current from wiring ZL to circuit ITSa can be prevented. In particular, since circuit ITSa can be stopped by turning switch SW2 OFF, providing switch SW2 leads to a reduction in power consumption related to circuit ITSa.

[0147] The circuit FC shown in Figure 3A is a circuit that has the function of performing the calculation of the function described above. Specifically, as an example, circuit FC has the function of acquiring the amount of current flowing through wiring ZL and using a value corresponding to the amount of current as an input value to perform the calculation of the function. Furthermore, as an example, circuit FC has the function of outputting the result of the calculation as a current to the output terminal of circuit FC.

[0148] Furthermore, the conversion circuit CVT shown in Figure 3A, as an example, has the function of acquiring the current output from circuit FC flowing through the input terminal of the conversion circuit CVT and generating a digital value or analog potential according to the amount of said current. In other words, the conversion circuit CVT has the function of converting the result calculated by circuit FC into data in the form of a digital value or analog potential. The conversion circuit CVT also has the function of outputting said data to the output terminal of circuit ITSa. For this reason, the conversion circuit CVT can be, for example, a current-voltage conversion circuit.

[0149] As described above, circuit ITSa can perform a function calculation using the result of a multiplication operation performed by one calculation cell WM in the cell array CA, or the result of a sum-of-products operation performed by multiple calculation cells WM arranged in the same column, and output the result to wiring OL.

[0150] Next, we will describe a specific example of the configuration of circuit FC included in circuit ITSa in Figure 3A.

[0151] Figure 3D is a circuit diagram showing, as an example, the specific configuration of circuit FC included in circuit ITSa in Figure 3A. Circuit FC in Figure 3D has the function of performing calculations of the ReLU function.

[0152] The circuit FC shown in Figure 3D includes, as an example, p-channel transistors MP1i, MP1o, MP2i, MP2o, MP3i, MP3o, MP4i, and MP4o, n-channel transistors MN1i, MN1o, MN2i, and MN2o, and a constant current source CNI.

[0153] Furthermore, for each of the transistors listed above, for example, a Si transistor can be used. By using Si transistors as the transistors included in the circuit FC, a CMOS (Complementary MOS) circuit can be easily constructed.

[0154] In the circuit FC shown in Figure 3D, a first current mirror circuit is formed by transistors MP1i, MP2i, MP1o, and MP2o. A second current mirror circuit is formed by transistors MN1i, MN2i, MN1o, and MN2o. A third current mirror circuit is formed by transistors MP3i, MP4i, MP3o, and MP4o.

[0155] The drain of transistor MP1i is connected to the second terminal of switch SW2, and the drain of transistor MP1o is connected to the input terminal of constant current source CNI and the drain of transistor MN2i. The drain of transistor MN2o is connected to the drain of transistor MP3i. Transistor MP3o is connected to the output terminal of circuit FC. The output terminal of constant current source CNI is connected to wiring VGE.

[0156] The VGE wiring, for example, functions as wiring that provides a fixed potential. This fixed potential can be, for instance, a negative potential or ground potential. Depending on the circumstances, the fixed potential provided by the VGE wiring can be a positive potential, etc.

[0157] The first current mirror circuit ideally has the function of flowing the same amount of current between the source and drain of transistor MP2o as the source and drain current corresponding to the gate-source potential of transistor MP2i. Similarly, the second current mirror circuit ideally has the function of flowing the same amount of current between the source and drain of transistor MN1o as the source and drain current corresponding to the gate-source potential of transistor MN1i. Similarly, the third current mirror circuit ideally has the function of flowing the same amount of current between the source and drain of transistor NP4o as the source and drain current corresponding to the gate-source potential of transistor MP4i.

[0158] In the first current mirror circuit, transistor MP1i functions as a clamp transistor to prevent a decrease in the threshold voltage of transistor MP2i due to drain-induced barrier lowering (DIBL). Similarly, transistor MP1o also functions as a clamp transistor to prevent a decrease in the threshold voltage of transistor MP2o due to DIBL. Therefore, wiring RSWL1, which provides a desired bias potential, is connected to the gates of transistors MP1i and MP1o, respectively.

[0159] In the second and third current mirror circuits, each of the transistors MN2i, MN2o, MP3i, and MP3o also functions as a clamp transistor to prevent a drop in the threshold voltage of the transistors connected in series by DIBL. In this case, each of the wirings RSWL2 and RSWL3 functions as a wiring that provides a desired bias potential.

[0160] Furthermore, the bias potentials provided by each of the wirings RSWL1 to RSWL3 can be made equal to each other. Therefore, wirings RSWL1 to RSWL3 can be the same wiring.

[0161] Furthermore, transistors MP1i and MP1o can each function as switching transistors. In this case, it is preferable that the wiring RSWL1 functions as wiring for controlling the switching between the on and off states of transistors MP1i and MP1o, respectively. Also, by turning off transistors MP1i and MP1o, the first current mirror circuit can be stopped, thereby reducing the power consumption in circuit FC.

[0162] Similarly, by having transistors MN2i and MN2o each function as switching transistors, the second current mirror circuit can be stopped at a desired timing. In this case, it is preferable that wiring RSWL2 functions as wiring to control the switching between the on and off states of transistors MN2i and MN2o, respectively. Similarly, by having transistors MP3i and MP3o each function as switching transistors, the third current mirror circuit can be stopped at a desired timing. In this case, it is preferable that wiring RSWL3 functions as wiring to control the switching between the on and off states of transistors MP3i and MP3o, respectively.

[0163] Furthermore, transistors MP1i and MP1o, and transistors MP3i and MP3o, can each be simultaneously on or off. Therefore, wiring RSWL1 and wiring RSWL3 can be the same wiring.

[0164] In the first current mirror circuit, the source of transistor MP2i and the source of transistor MP2o are connected to wiring VDE. Since the first current mirror circuit is composed of p-channel transistors, it also functions as a current source circuit. Therefore, wiring VDE functions as wiring that provides a positive potential, which is the high power supply potential supplied to the first current mirror circuit. Similarly, the third current mirror also functions as a current source circuit, and therefore the positive potential supplied by wiring VDE also functions as the high power supply potential supplied to the third current mirror circuit.

[0165] In the second current mirror circuit, the source of transistor M1i and the source of transistor MN1o are connected to the wiring VSE. Since the second current mirror circuit is composed of n-channel transistors, it also functions as a current sink circuit. Therefore, the wiring VSE functions as a wiring that provides ground potential or a negative potential as the low power supply potential of the second current mirror circuit.

[0166] A constant current source CNI is, for example, a quantity I ＩＢ It has the function of supplying current from the drains of transistor MP1o and transistor MN2i to the wiring VGE.

[0167] When a high-level potential is applied to wiring SWL2, the control terminal of switch SW2 is also supplied with the same high-level potential, and switch SW2 turns ON. At this time, wiring IL is supplied with a quantity I corresponding to the value multiplied by one or more calculation cells WM arranged in the same row. ＩＬ Assume that a current of 1 is flowing. Therefore, a quantity of 1 is drawn from wiring VDE to wiring IL. ＩＬ A current flows. Therefore, the amount of source-drain current of transistor MP2o is also I due to the first current mirror circuit. ＩＬ This is the result.

[0168] Furthermore, when the constant current source CNI is operating, according to Kirchhoff's current law, I ＩＬ = I ＩＢ +I ＯＬ This holds true. ＯＬ This is the amount of current flowing between the source and drain of transistor MN1i. Therefore, the amount of source-drain current of transistor MN1o is also I due to the second current mirror circuit. ＯＬ This is the result.

[0169] Also, the amount of source-drain current of transistor MN1o is I ＯＬ Therefore, the amount of source-drain current in transistor MP4i is also I ＯＬ Therefore, the amount of source-drain current of transistor MP4o is also I due to the third current mirror circuit. ＯＬ As a result, the input terminal of the conversion circuit CVT receives quantity I ＯＬ An electric current flows.

[0170] Circuit FC is I ＩＬ I Ｂ If it is greater than, the difference is quantity I ＯＬ The current is passed to the input terminal of the conversion circuit CVT. Also, I ＩＬ I ＢIn the following cases, the current flowing between the input and output terminals of the constant current source CNI is I ＩＬ And also, I ＯＬ = 0. In this case, no current flows from circuit FC to the input terminal of the conversion circuit CVT. In other words, the ReLU function can be calculated using circuit FC shown in Figure 3D.

[0171] In addition, in the circuit ITSa shown in Figure 3A, the data output to wiring OL may be an analog current instead of a digital value or analog potential. In this case, it is preferable to use a configuration without a conversion circuit CVT, as shown in the circuit ITSa shown in Figure 3B, rather than the circuit ITSa shown in Figure 3A. Since the circuit ITSa shown in Figure 3B does not have a conversion circuit CVT, the circuit area of ​​the drive circuit ITS can be reduced by using the circuit ITSa shown in Figure 3B. Furthermore, the power consumption required to drive the conversion circuit CVT can be reduced.

[0172] Furthermore, circuit ITSa may not be configured to perform a function calculation using the amount of current flowing through wiring IL as the input value, as shown in Figure 3A, and then convert the calculation result into a digital value or analog potential. Instead, it may convert the amount of current flowing through wiring IL into a digital value or analog potential, and then perform the function calculation using the converted digital value or analog potential as the input value. Specifically, circuit ITSa in Figure 3A can be changed to the configuration of circuit ITSa in Figure 3C.

[0173] The circuit ITSa shown in Figure 3C has the following configuration: the input terminal of the conversion circuit CVT is connected to the input terminal of circuit ITSa, the output terminal of the conversion circuit CVT is connected to the input terminal of circuit FC, and the output terminal of circuit FC is connected to the output terminal of circuit ITSa.

[0174] <<Example of Operation Method of the Arithmetic Unit>> Next, an example of the operation method of the arithmetic unit CDVA1 shown in Figure 2 will be explained.

[0175] Figure 4 is a timing chart illustrating an example of how the arithmetic unit CDVA1 in Figure 2 operates. The timing chart in Figure 4 shows an example of operation in which first data w[1,1] to w[m,j] is written to each of the arithmetic cells WM[1,j] to WM[m,j] in the j-th column of the cell array CA, and second data x[1] to x[m] is written to each of the storage cells XM[1] to XM[m] in the storage cell area CX, and current is obtained from the wiring ZL[j] according to the result of the sum-of-products operation between the first data w[1,1] to w[m,j] and the second data x[1] to x[m].

[0176] The timing chart in Figure 4 shows the potential fluctuations of wiring WSL[1], wiring WSL[2], wiring WSL[m], wiring XSL[1], wiring XSL[2], and wiring XSL[m] during periods T01 to T05 or nearby thereto. Note that the timing chart shows values ​​corresponding to the potentials supplied to wiring WCL[j] and wiring XCL, instead of the actual potentials themselves. The timing chart also shows the fluctuations in the amount of current flowing through wiring ZL[j].

[0177] Furthermore, in the timing chart in Figure 4, the types of wiring and nodes are listed on the left, and the potential height or current amount is listed on the right. Specifically, "High" in the timing chart indicates a high-level potential in that wiring, and "Low" indicates a low-level potential in that wiring.

[0178] In this example, the potential supplied by wiring VEL is assumed to be the ground potential. Furthermore, it is assumed that wiring ZL[j] is supplied with the ground potential before period T01.

[0179] [Period T01] During period T01, the following operations are performed: the analog potential corresponding to the first data w[1,j] is written to the calculation cell WM[1,j], and the analog potential corresponding to the second data x[1] is written to the storage cell XM[1].

[0180] First, the first data, w[1,j], which is digital data, is supplied to the input terminal of circuit WCDa[j] from outside the arithmetic unit CDVA1 via wiring IWL[j]. As a result, circuit WCDa[j] converts the first data w[1,j] into an analog potential and outputs the analog potential to wiring WCL[j].

[0181] During period T01, the drive circuit WSD transmits a selection signal (high-level potential) to wiring WSL[1]. This turns on transistor M2 in the calculation cell WM[1,j] located in the first row of cell array CA. Also during period T01, the drive circuit WSD transmits a deselection signal to wiring WSL[2] through WSL[m]. This turns off transistor M2 in each of the calculation cells WM located in the second through m rows of cell array CA.

[0182] At this time, in the j-th column of the cell array CA, an analog potential corresponding to the first data w[1,j] provided to the wiring WCL[j] is written to the first terminal (node ​​N1) of the capacitive element C1 of the calculation cell WM[1,j]. Subsequently, the drive circuit WSD switches the selection signal provided to the wiring WSL[1] to a deselection signal, thereby turning off the transistor M2 included in the calculation cell WM[1,j] located in the first row of the cell array CA, and thus the analog potential can be held at the first terminal of the capacitive element C1 of the calculation cell WM[1,j].

[0183] Furthermore, during period T01, a second data x[1], which is digital data, is supplied to the input terminal of circuit XCDa from outside the arithmetic unit CDVA1 via wiring IXL. As a result, circuit XCDa converts the second data x[1] into an analog potential and outputs the analog potential to wiring XCL.

[0184] Furthermore, during period T01, the drive circuit XSD transmits a selection signal to wiring XSL[1]. This turns on transistor M3 in memory cell XM[1] located in the first row of memory cell area CX. Also during period T01, the drive circuit WSD transmits a deselection signal to wiring XSL[2] through wiring XSL[m]. This turns off transistor M3 in each of the memory cells XM[2] through memory cells XM[m] located in the second through m rows of memory cell area CX.

[0185] At this time, in the first row of the memory cell area CX, an analog potential corresponding to the second data x[1] provided to the wiring XCL is written to the first terminal (node ​​N2) of the capacitive element C2 of the memory cell XM[1]. Subsequently, the drive circuit XSD switches the selection signal provided to the wiring XSL[1] to a deselection signal, thereby turning off the transistor M3 included in the memory cell XM[1] located in the first row of the memory cell area, and thus can hold the analog potential at the first terminal of the capacitive element C2 of the memory cell XM[1].

[0186] Furthermore, as described above, in the calculation cell WM[1,j], the gate of transistor M1 is held at an analog potential corresponding to the first data w[1,j] by the capacitive element C1, and the back gate of transistor M1 is held at an analog potential corresponding to the second data x[1] by the capacitive element C2 of the memory cell XM[1]. Therefore, the amount of current I[1,j] flowing between the source and drain of transistor M1 is, from equation (1.9) above, I[1,j] = w[1,j]x[1]I ０ This results in the following relationship between the calculation cell WM[1,j] and the wiring ZL[j]: I[1,j] = w[1,j] x [1]I ０ A current of that amount flows.

[0187] [Period T02] In period T02, similar to period T01, the operation is performed in which the analog potential corresponding to the first data w[2,j] is written to the calculation cell WM[2,j] and the analog potential corresponding to the second data x[2] is written to the storage cell XM[2]. For this reason, the operation of writing the analog potential corresponding to the first data w[2,j] to the calculation cell WM[2,j] and the operation of writing the analog potential corresponding to the second data x[2] to the storage cell XM[2] can be explained by referring to the operation example in period T01.

[0188] As a result, in the calculation cell WM[2,j], the gate of transistor M1 is held at an analog potential corresponding to the first data w[2,j] by the capacitive element C1, and the back gate of transistor M1 is held at an analog potential corresponding to the second data x[2] by the capacitive element C2 of the memory cell XM[2]. Therefore, the amount of current I[2,j] flowing between the source and drain of transistor M1 is, from equation (1.9) above, I[2,j] = w[2,j]x[2]I ０ Therefore, between the calculation cell WM[2,j] and the wiring ZL[j], I[2,j] = w[2,j] x [2]I ０ A current of this amount flows. Also, during period T02, a current of amount I[1,j] flows through wiring ZL[j] from calculation cell WM[1,j], so the amount of current flowing through wiring ZL[j] is the sum of the currents output from calculation cell WM[1,j] and calculation cell WM[2,j] I. ＳＵＭ As, I ＳＵＭ This can be expressed as = I[1, j] + I[2, j].

[0189] [Period T03] In period T03, as in periods T01 and T02, analog potentials corresponding to the first data w[3,j] to w[m-1,j] are sequentially written to each of the calculation cells WM[3,j] to WM[m-1,1]. Also, as in periods T01 and T02, analog potentials corresponding to the second data x[3,j] to x[m-1,j] are sequentially written to each of the storage cells XM[3] to XM[m-1].

[0190] As a result, the amount of current flowing between the source and drain of each transistor M1 in the calculation cell WM[3,j] to the calculation cell WM[m-1,j] is I[3,j] = w[3,j] x [3]I ０ 〜I[m-1,j]=w[m-1,j]x[m-1]I ０ This is the result. Also, when the first data w[m-1,j] is written to the calculation cell WM[m-1,j] and the second data x[m-1] is written to the memory cell XM[m-1], the total sum of currents I flowing through the wiring ZL[j] is... ＳＵＭ This is the sum of the currents output from each of the calculation cells WM[1,j] to WM[m-1,j].

[0191] [Period T04] In period T04, similar to periods T01 to T03, the operation is performed in which an analog potential corresponding to the first data w[m,j] is written to the calculation cell WM[m,j] and an analog potential corresponding to the second data x[m] is written to the storage cell XM[m]. For this reason, the operation of writing the analog potential corresponding to the first data w[m,j] to the calculation cell WM[m,j] and the operation of writing the analog potential corresponding to the second data x[m] to the storage cell XM[m] can be explained by referring to the operation example in period T01.

[0192] As a result, in the calculation cell WM[m,j], the gate of transistor M1 is held at an analog potential corresponding to the first data w[m,j] by the capacitive element C1, and the back gate of transistor M1 is held at an analog potential corresponding to the second data x[m] by the capacitive element C2 of the memory cell XM[m]. Therefore, the amount of current I[m,j] flowing between the source and drain of transistor M1 is, from equation (1.9) above, I[m,j] = w[m,j]x[m]I ０ Therefore, between the calculation cell WM[m,j] and the wiring ZL[j], I[m,j] = w[m,j] x [m]I ０A current of this magnitude flows. Also, during period T05, current flows through wiring ZL[j] from each of the calculation cells WM[1,j] to WM[m-1,j], so the amount of current flowing through wiring ZL[j] is the sum of the currents output from each of the calculation cells WM[1,j] to WM[m,j] I. ＳＵＭ [j] can be expressed as shown in equation (1.10) below.

[0193]

[0194] Therefore, the total sum of currents I flowing through wiring ZL[j] ＳＵＭ As [j] flows into circuit ITSa[j], circuit FC becomes I ＳＵＭ The value of the function F(I) corresponding to [j] ＳＵＭ [j]) is calculated, F(I ＳＵＭ [j]) is output to wiring OL[j]. Note that F(I) output to wiring OL[j] ＳＵＭ [j]) can be expressed as digital data or as an analog potential, depending on the configuration of the circuit ITSa.

[0195] The above describes the summation of the multiplication results of the first data w and the second data x output from each of the calculation cells WM[1,j] to WM[m,j] located in the j column of the cell array CA. However, by performing the above operation simultaneously on the first to n columns of the cell array CA, the matrix operation shown in equation (1.11) below can be performed.

[0196]

[0197] In this way, by arranging the calculation cells WM in an m x n matrix, it is possible to simultaneously perform sum-of-products operations on the first data w[1,j] to w[m,j] written in the calculation cells WM of each column of the cell array CA and the second data x[1] to x[m] written in the storage cells XM. Furthermore, by inputting the results of each output sum-of-products operation into circuits ITSa[1] to ITSa[n] of the drive circuit ITS, it is possible to simultaneously perform function operations using the results in each column as input values.

[0198] <Examples of Modifications to the Arithmetic Processing Unit> Furthermore, the semiconductor device according to one aspect of the present invention is not limited to the configuration of the arithmetic processing unit CDVA1 described above. The semiconductor device according to one aspect of the present invention can be a device in which the circuit configuration of the arithmetic processing unit CDVA1 is appropriately modified.

[0199] The arithmetic unit CDVA2 shown in Figure 5 is a modified version of the arithmetic unit CDVA1 shown in Figure 2. Specifically, the arithmetic unit CDVA2 differs from the arithmetic unit CDVA1 in that the wiring WSL[1] to WSL[m] shown in Figure 2 are replaced with wiring WXSL[1] to WXSL[m], the gate of transistor M3 is connected to wiring WXSL instead of wiring XSL, the drive circuit XSD is not provided, and wiring XSL[1] to XSL[m] is not provided.

[0200] In the arithmetic unit CDVA2, the gate of transistor M2 contained in the arithmetic cell WM[i,j] and the gate of transistor M3 contained in the memory cell XM[i] are each connected to the wiring WXSL[i]. Note that wiring WXSL[i] corresponds to the wiring WXSL shown in Figure 1D. In other words, in the arithmetic unit CDVA2 of Figure 5, the circuit elements contained in the arithmetic cell WM[i,j] and the memory cell XM[i] respectively form the connection configuration of the arithmetic circuit IM3 in Figure 1D. Therefore, for the circuit configuration of the arithmetic cell WM[i,j] and the memory cell XM[i], as well as the multiplication operation of the first data w and the second data x, refer to the explanation of the arithmetic circuit IM3 in Figure 1D.

[0201] As described in Figure 1D, the arithmetic circuit IM3 can be supplied with the same selection or deselection signal to the gates of multiple transistors M2 and transistor M3 in the memory cell XM[i] and arithmetic cells WM[i,1] to WM[i,n] located in the same row. Therefore, the multiple transistors M2 in the arithmetic cells WM[i,1] to WM[i,n] located in the same row, and the transistor M3 in the memory cell XM[i] can be simultaneously turned on or off. As a result, the arithmetic unit CDVA2 can write and hold first data in each of the arithmetic cells WM[i,1] to WM[i,n] located in the same row, and simultaneously hold second data in the memory cell XM[i].

[0202] Unlike the CDVA1 in Figure 2, the CDVA2 arithmetic unit in Figure 5 does not require the XSD drive circuit. Therefore, the circuit area of ​​the CDVA2 arithmetic unit can be smaller than that of the CDVA1 arithmetic unit. Furthermore, because there are fewer drive circuits, the power consumption of the CDVA2 arithmetic unit can be lower than that of the CDVA1 arithmetic unit.

[0203] This embodiment can be appropriately combined with the same or other embodiments shown in this specification. For example, the configurations, structures, and methods shown in this embodiment can be appropriately combined with other configurations, structures, and methods shown in this embodiment. Also, for example, the configurations, structures, and methods shown in this embodiment can be appropriately combined with configurations, structures, and methods shown in other embodiments.

[0204] (Embodiment 2) In this embodiment, an example of a schematic plan view of the semiconductor device described in the above embodiment and an example of a cross-sectional configuration will be described.

[0205] <Example of Semiconductor Device Circuit Layout> Figure 6 is a schematic plan view showing an example of the circuit configuration of the arithmetic circuit IM1 shown in Figure 1B, which is a semiconductor device described in the above embodiment.

[0206] Figure 6 shows an example of a circuit layer including the arithmetic circuit IM1 in a plan view. This circuit layer includes a conductive layer 231, a conductive layer 232, a conductive layer 233, a conductive layer 234, a conductive layer 235, a conductive layer 236, a conductive layer 237, a conductive layer 238, and a semiconductor layer 251. For clarity, the insulating layer included in this circuit layer is not shown in the schematic plan view of Figure 6.

[0207] In Figure 6, each of transistors M1 to M3 has an island-shaped insulating layer, a semiconductor layer 251 formed on the insulating layer, a conductive layer 232 formed on the semiconductor layer 251, a gate insulating film formed on the semiconductor layer 251, and a conductive layer 233 formed on the gate insulating film. Furthermore, each of transistors M1 to M3 can have a GL (Gate Last) structure (also called a TGSA (Trench Gate Self Align or Top Gate Self Align) structure), which will be described later. In addition, transistor M1 has a conductive layer 231 below the island-shaped insulating layer of transistor M1, which has a region that overlaps with the conductive layer 233.

[0208] Furthermore, in Figure 6, each of the capacitive element C1 and the capacitive element C2 has a conductive layer 237 that functions as one of a pair of electrodes, a conductive layer 238 that functions as the other of a pair of electrodes, and an insulating layer that functions as a dielectric sandwiched between the pair of electrodes.

[0209] For example, the conductive layer 231 is located below the semiconductor layer 251. For example, the semiconductor layer 251 is located below the conductive layers 232 and 233. For example, the conductive layer 234 is located above the conductive layers 232 and 233. For example, the conductive layer 235 is located above the conductive layer 234. For example, the conductive layer 236 is located above the conductive layers 233 and 235. For example, the conductive layer 237 is located above the conductive layer 236. For example, the conductive layer 238 is located above the conductive layer 237. The formation order can be, for example, conductive layer 231 first, semiconductor layer 251 second, conductive layer 232 third, conductive layer 233 fourth, conductive layer 234 fifth, conductive layer 235 sixth, conductive layer 236 seventh, conductive layer 237 eighth, and conductive layer 238 ninth.

[0210] In the schematic plan view of Figure 6, a portion of the conductive layer 231 functions, for example, as the back gate of transistor M1. A portion of the conductive layer 232 functions, for example, as the source or drain of transistors M1 to M3. A portion of the conductive layer 233 functions, for example, as the gate of transistors M1 to M3. Furthermore, the conductive layer 234 functions, for example, as wiring for conductivity between conductive layers 231 and 235, between conductive layers 232 and 235, and between conductive layers 233 and 235. For this reason, the conductive layer 234 is sometimes referred to as a contact plug.

[0211] Furthermore, in the schematic plan view of Figure 6, a portion of the conductive layer 237 functions, for example, as one of a pair of electrodes of the capacitive element C1 and as one of a pair of electrodes of the capacitive element C2. Also, the conductive layer 238 functions, for example, as the other of a pair of electrodes of the capacitive element C1 and as the other of a pair of electrodes of the capacitive element C2.

[0212] Furthermore, in the schematic plan view of Figure 6, a portion of each of the conductive layer 233 and conductive layer 235 functions as wiring. For example, a portion of the conductive layer 233 is provided as wiring WSL, wiring XSL, wiring VCL1, and wiring VCL2, extending in the left-right direction of the drawing. Also, for example, a portion of the conductive layer 235 is provided as wiring WCL, wiring XCL, wiring VEL, and wiring ZL, extending in the up-down direction of the drawing. For this reason, it is preferable to use a highly conductive material for each of the conductive layer 233 and conductive layer 235. In addition, since a portion of each of the conductive layer 231 and conductive layer 238 also functions as wiring, it is preferable to use a highly conductive material for each of the conductive layer 231 and conductive layer 238 as well.

[0213] Furthermore, each of the conductive layers described above can be formed, for example, using lithography. Specifically, for example, when forming the conductive layer 231, the conductive material that will become the conductive layer 231 can be formed using one or more methods selected from sputtering, CVD (Chemical Vapor Deposition), PLD (Pulsed Laser Deposition), and ALD (Atomic Layer Deposition), and then the desired pattern can be formed by lithography. In addition, conductive layers other than the conductive layer 231, semiconductor layers, and insulating layers can also be formed by the same methods as described above.

[0214] In this specification, lithography includes, for example, photolithography, ion beam lithography, X-ray lithography, electron beam lithography, multiphoton lithography, interference lithography, and nanoimprinting.

[0215] Each of the capacitive elements C1 and C2 has a parallel plate structure, as shown in Figure 6. Also, in the plan view of Figure 6, a portion of the edge (also called the margin) of the upper conductive layer 238 is located inward from the edge of the lower conductive layer 237. Specifically, for example, in Figure 6, the width d1 of the conductive layer 238 that covers the other region of the pair of electrodes of the capacitive element C1 is shorter than the width d2 of the conductive layer 237 that covers one region of the pair of electrodes of the capacitive element C1. When an insulating layer having dielectric function is formed on the conductive layer 237, a formation defect of the insulating layer may occur at the edge of the conductive layer 237 or in the surrounding region. As a formation defect, the film-holding ability of the insulating layer formed at the edge of the conductive layer 233 or in the surrounding region may be low, and if the width d1 of the conductive layer 238 becomes longer than the width d2 of the conductive layer 237, the edge of the conductive layer 237 or the surrounding region and the overlapping region of the conductive layer 238 may come into contact with each other and short-circuit. Therefore, it is preferable that the width d1 of the conductive layer 238 is shorter than the width d2 of the conductive layer 237.

[0216] Conversely, if the coating properties of the insulating layer formed on the edge or surrounding region of the conductive layer 238 can be increased, it is preferable to make the width d1 longer than the width d2. Specifically, since the capacitance value of a capacitive element is proportional to the area of ​​the region where one electrode of the pair and the dielectric overlap with the other electrode of the pair, it is preferable to increase the area of ​​this region if the capacitance value is to be increased. Therefore, by making the width d1 longer than the width d2, the width of this region can be increased from d1 to d2. As a result, the conductive layer 238 is formed above the edge of the conductive layer 237, so the area of ​​the other electrode of the pair of electrodes of the capacitive element C1 increases, and the capacitance value of the capacitive element C1 can be increased.

[0217] Note that the schematic plan view of a semiconductor device according to one embodiment of the present invention is not limited to Figure 6. The schematic plan view of an arithmetic circuit according to one embodiment of the present invention can be Figure 6, which has been appropriately modified depending on the circumstances.

[0218] Furthermore, although the schematic plan view in Figure 6 shows that the sizes of transistors M1 to M3 (including channel length and channel width) are equal, the sizes of transistors M1 to M3 may be different.

[0219] For example, it is preferable that the channel width of the switching transistor be shorter than the channel width of the amplifying transistor. Specifically, in Figure 6, it is preferable that the channel widths d3 of transistors M2 and M3 are shorter than the channel width d5 ​​of transistor M1. By shortening the channel widths d3 of transistors M2 and M3, which function as switching transistors, the off-currents of transistors M2 and M3 can be reduced, thereby allowing the gate and back gate potentials of transistor M1 to be maintained for a long period of time.

[0220] Furthermore, for example, it is preferable that the channel length of the switching transistor be longer than the channel length of the amplifying transistor. Specifically, in Figure 6, it is preferable that the channel lengths d4 of transistors M2 and M3 are longer than the channel length d6 of transistor M1. By increasing the channel lengths d4 of transistors M2 and M3, which function as switching transistors, the off-currents of transistors M2 and M3 can be reduced.

[0221] Furthermore, for example, it is preferable that the channel width of an amplifying transistor be longer than the channel width of a switching transistor. Specifically, it is preferable that the channel width d5 ​​of transistor M1 be longer than the channel widths d3 of transistors M2 and M3, respectively. By increasing the channel width d5 ​​of transistor M1, which functions as an amplifying transistor, the on-current of transistor M1 can be increased.

[0222] Furthermore, for example, it is preferable that the channel length of an amplifying transistor be shorter than the channel length of a switching transistor. Specifically, it is preferable that the channel length d6 of transistor M1 be shorter than the channel lengths d4 of transistors M2 and M3, respectively. By shortening the channel length d6 of transistor M1, which functions as an amplifying transistor, the on-current of transistor M1 can also be increased.

[0223] <Example of Cross-Sectional Device Configuration> Figure 7 is a schematic cross-sectional diagram showing an example of the configuration of the arithmetic unit CDVA1 and arithmetic unit CDVA2 (sometimes collectively referred to as arithmetic unit CDVA) described in the above embodiment. The arithmetic unit CDVA shown in Figure 7, as an example, has a configuration that includes circuit layer PHRL and circuit layer OMAL located above circuit layer PHRL. In the schematic cross-sectional diagram of Figure 7, the arithmetic unit CDVA has a configuration in which transistors M1 to M3, capacitive element C1, and capacitive element C2 are each included in circuit layer OMAL.

[0224] Note that the schematic cross-sectional view in Figure 7 shows transistors M1 to M3, capacitive element C1, and capacitive element C2, respectively, and therefore the arrangement of circuit elements differs from that in the schematic plan view shown in Figure 6.

[0225] The circuit layer PHRL can be constructed, for example, by providing circuit elements such as transistors and capacitive elements on a substrate. A semiconductor substrate (for example, a single-crystal substrate made of silicon or germanium) can be used as the substrate. Other substrates that can be used include, for example, SOI (Silicon On Insulator) substrates, glass substrates, quartz substrates, plastic substrates, sapphire glass substrates, metal substrates, stainless steel substrates, substrates with stainless steel foil, tungsten substrates, substrates with tungsten foil, flexible substrates, laminated films, paper containing fibrous materials, or base films. In this embodiment, the substrate included in the circuit layer PHRL will be described as a semiconductor substrate containing silicon.

[0226] By using a silicon semiconductor substrate as the substrate included in the circuit layer PHRL, the transistors included in the drive circuits WXCD, XSD, WSD, and ITS shown in Figure 2 can be formed on the semiconductor substrate. Similarly, the transistors included in the drive circuits WXCD, WXSD, and ITS shown in Figure 5 can be formed on the semiconductor substrate. In this case, the transistors will be Si transistors. Since Si transistors have high field-effect mobility, they can carry large on-currents. This makes it possible to increase the driving speed of each of the drive circuits listed above, widen the signal range, and so on.

[0227] In Figure 7, transistor 100, which is part of the circuit layer PHRL, is shown as an example of a Si transistor. By using a Si transistor for transistor 100, a CMOS circuit can be configured in the circuit layer PHRL that includes both a p-channel transistor and an n-channel transistor. In particular, the drive circuit WXCD described in the above embodiment includes, for example, a digital-to-analog conversion circuit, and this digital-to-analog conversion circuit can be a CMOS circuit that includes both a p-channel transistor and an n-channel transistor. It is preferable that the drive circuit WXCD, etc., is provided in the circuit layer PHRL as a CMOS circuit.

[0228] Furthermore, the laminated structure of circuit layer PHRL and circuit layer OMAL can be fabricated by directly forming circuit layer OMAL on top of circuit layer PHRL. Alternatively, circuit layer OMAL can be fabricated by mounting the substrate on top of circuit layer PHRL, with circuit elements such as transistors and capacitive elements provided on the substrate. When circuit layer OMAL is directly formed on top of circuit layer PHRL, it is preferable that circuit layer OMAL includes an OS transistor. An I / O transistor can be used as the OS transistor. Since the OS transistor can be formed on a substrate such as a semiconductor substrate, an insulating substrate, or a conductive substrate, or on a film such as a conductive film, an insulating film, or a semiconductor film, it can be easily provided on a semiconductor substrate (on circuit layer PHRL) on which a Si transistor is formed.

[0229] Alternatively, p-channel transistors may be provided as Si transistors in the PHRL circuit layer, and n-channel transistors may be provided as OS transistors in the OMAL circuit layer. Specifically, for example, transistors M1 to M3 included in the arithmetic circuit IM1 shown in Figure 1B may be provided in the OMAL circuit layer.

[0230] Furthermore, when forming circuit elements such as transistors and capacitive elements on a substrate as the circuit layer OMAL, and mounting the substrate on the circuit layer PHRL, a flip-chip bonding method or a wire bonding method can be used. Alternatively, the circuit layer OMAL may be mounted on the circuit layer PHRL by providing a first bonding layer on the circuit layer PHRL side, providing a second bonding layer on the circuit layer OMAL substrate, and bonding the first bonding layer and the second bonding layer using either or both of the surface activation bonding method and the hydrophilic bonding method. In particular, when copper (Cu) is used as the conductor in both the first and second bonding layers, and the copper of the first bonding layer and the copper of the second bonding layer are directly bonded, this is called Cu-Cu (copper-copper) direct bonding.

[0231] The transistor 100 is provided on a substrate 101 and includes a conductive layer 131 that functions as a gate, an insulating layer 161 and an insulating layer 111 that functions as a gate insulating film, a semiconductor region 171 that includes a part of the substrate 101, and a low-resistance region 172a and a low-resistance region 172b that include a part of the substrate and function as a source region or drain region.

[0232] Furthermore, the semiconductor region 171, the low-resistance region 172a, and the low-resistance region 172b, each included in the transistor 100 shown in Figure 7, are formed by providing an element isolation layer 102 on the substrate 101. It can also be said that the element isolation layer 102 is provided to separate the multiple transistors formed on the substrate 101. The element isolation layer 102 can be formed, for example, using the LOCOS (Local Oxidation of Silicon) method, the STI (Shallow Trench Isolation) method, or the mesa isolation method.

[0233] Furthermore, the transistor 100 shown in Figure 7 may, as an example, have a convex shape in the semiconductor region 171 (part of the substrate 101) where the channel is formed, as shown in the schematic cross-sectional view of Figure 8. Figure 8 is a schematic cross-sectional view of the transistor 100 in the channel width direction. The side and top surfaces of the semiconductor region 171 are covered by a conductive layer 131 via an insulating layer 161. The conductive layer 131 may be made of a material that adjusts the work function. Such a transistor 100 is also called a fin-type transistor because it utilizes the convex portion of the semiconductor substrate. It may also have an insulating layer that is in contact with the upper part of the convex portion and functions as a mask for forming the convex portion. In addition, although the case of forming the convex portion by processing a part of the semiconductor substrate is shown here, a semiconductor film having a convex shape may be formed by processing an SOI substrate.

[0234] Furthermore, in Figure 8, a conductive layer 136 is provided so as to be in contact with the conductive layer 131 and to fill the opening formed in the insulating layer 112. The conductive layer 136 functions as a contact plug or wiring, which will be described later.

[0235] Note that the transistor 100 shown in Figures 7 and 8 is just one example, and its structure is not limited to that; any appropriate transistor can be used depending on the circuit configuration or driving method.

[0236] The CDVA computing unit may be provided with a wiring layer having an interlayer film, wiring, and a plug. Furthermore, multiple wiring layers may be provided depending on the design. Also, in this specification, the wiring and the plug connecting to the wiring may be a single integrated unit. That is, there may be cases where a part of the conductive layer functions as wiring, and cases where a part of the conductive layer functions as a plug.

[0237] For example, on the transistor 100, insulating layers 112, 181, and 113 are sequentially stacked as interlayer films. A conductive layer 132 is embedded in the insulating layer 112. A conductive layer 133 is embedded in the insulating layer 181 and the insulating layer 113. The conductive layers 132 and 133 function as contact plugs or wiring.

[0238] Furthermore, the insulating layer, which functions as an interlayer film, may also function as a planarizing film that covers the uneven shape beneath it. For example, the upper surface of the insulating layer 112 may be planarized by a planarizing treatment using chemical mechanical polishing (CMP) to improve its flatness.

[0239] Wiring layers may be provided on the insulating layer 113 and the conductive layer 133. For example, in Figure 7, insulating layers 182, 114, 115, and 116 are sequentially laminated on the insulating layer 113 and the conductive layer 133. Furthermore, conductive layers 134 are formed on insulating layers 182, 114, and 115. The conductive layer 134 functions as a contact plug or wiring.

[0240] An insulating layer 281 is provided on the insulating layer 116. Preferably, contact plugs or wiring for connecting to an upper circuit (for example, a circuit element included in a circuit included in the circuit layer OMAL) are embedded in the insulating layer 116 and the insulating layer 281.

[0241] For conductive layers 132, 133, 134, and 136, for example, materials applicable to conductive layers 231, 232, 233, or 234 described later can be used.

[0242] Next, we will describe an example of the configuration of the arithmetic cells included in the circuit layer OMAL shown in Figure 7.

[0243] In the circuit layer OMAL shown in Figure 7, each of the transistors M1 to M3 is formed on the insulating layer 281. Furthermore, each of the capacitive elements C1 and C2 is formed on the insulating layer 287. The insulating layer 287 is located above the insulating layer 281. Therefore, it can be said that the capacitive elements C1 and C2 are located above the transistors M1 to M3.

[0244] Furthermore, it is preferable that each of the insulating layers 181, 182, 281, and 287 shown in Figure 7 functions as a barrier insulating film that suppresses the permeation of impurities such as water and hydrogen. Therefore, insulating layers 181, 182, 281, and 287 are designed to suppress the permeation of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (for example, N ２ O, NO, or NO ２ It is preferable to use an insulating material that has the function of suppressing the diffusion of impurities such as ) and copper atoms (i.e., the above impurities do not easily permeate). Alternatively, it is preferable to use an insulating material that has the function of suppressing the diffusion of oxygen (for example, oxygen atoms and oxygen molecules, or both) (i.e., the above oxygen does not easily permeate). For materials that can be applied to insulating layer 181, insulating layer 182, insulating layer 281 and insulating layer 287, refer to the description of the insulating layer of the transistor constituent materials.

[0245] Furthermore, a conductive layer 235, which functions as wiring XCL, is connected to either the source or drain electrode of transistor M3 via a conductive layer 234, which functions as a contact plug. Additionally, a conductive layer 237, which functions as one of a pair of electrodes of capacitive element C2, is connected to the other source or drain electrode of transistor M3 via conductive layers 234 to 236, which also function as contact plugs. A portion of the conductive layer 233 also functions as the gate electrode of transistor M3.

[0246] Furthermore, a conductive layer 235, which functions as a wiring WCL, is connected to either the source or drain electrode of transistor M2 via a conductive layer 234, which functions as a contact plug. Additionally, a conductive layer 237, which functions as one of a pair of electrodes of capacitive element C1, is connected to the other source or drain electrode of transistor M2 via conductive layers 234 to 236, which also function as contact plugs. A portion of the conductive layer 233 also functions as the gate electrode of transistor M2.

[0247] Furthermore, a conductive layer 235, which functions as wiring ZL, is connected to either the source electrode or the drain electrode of transistor M1 via a conductive layer 234, which functions as a contact plug. Also, a conductive layer 235, which functions as wiring VEL, is connected to the other source electrode or drain electrode of transistor M1 via the same conductive layer 234. Additionally, a portion of the conductive layer 233 functions as the gate electrode of transistor M1. Furthermore, a portion of the conductive layer 231 functions as the back gate electrode of transistor M1.

[0248] Furthermore, the gate electrodes of transistors M1 to M3 are, for example, represented as conductive layers 233, extending along the front-to-depth direction in Figure 7.

[0249] The conductive layer 234 is provided so as to be embedded in the openings formed in the insulating layers 213, 283, 214, and 284, which will be described later. In addition, the insulating layer 215 and the conductive layer 235 are provided on the conductive layer 234 and on the insulating layer 284, respectively. In particular, the conductive layer 235 is provided so as to be embedded in the openings formed in the insulating layer 215. In addition, the insulating layer 286 is provided on the insulating layer 215 and on the conductive layer 235, and the insulating layer 287 is provided on the insulating layer 286. Furthermore, the conductive layer 236 is provided so as to be embedded in the openings formed in the insulating layer 286 and the insulating layer 287.

[0250] Furthermore, the insulating layer 215 can be made of a material applicable to the insulating layers 213 and 214, which will be described later. The insulating layers 284 and 286 can be made of a material applicable to the insulating layers 281 and 287, for example. The conductive layers 235, 236, and 237 can be made of a material applicable to the conductive layers 231 to 233 or 234 included in the transistor 200, for example.

[0251] The conductive layer 237, which functions as one of the pair of electrodes of the capacitive elements C1 and C2, is in contact with the insulating layer 287 and the conductive layer 236, and is provided so as to be embedded in an opening formed in the insulating layer 219 on the insulating layer 287. Furthermore, an insulating layer 441, which functions as the dielectric for each of the conductive layers that form one of the pair of electrodes of the capacitive elements C1 and C2, is provided above the insulating layer 441. Furthermore, a conductive layer 238, which functions as the other of the pair of electrodes of the capacitive elements C1 and C2, is provided above the insulating layer 441.

[0252] Furthermore, the conductive layer 238 can be made of a material that is applicable to conductive layers 231 to 233 or conductive layer 234 included in the transistor 200, for example.

[0253] By embedding the conductive layer 237, which functions as one of the pair of electrodes of the capacitive element C1, into the insulating layer 219, the conductive layer and the insulating layer 219 can be made flush and flat. As a result, the insulating layer 441, which functions as a dielectric, and the conductive layer 238, which functions as the other of the pair of electrodes of the capacitive element C1, can be formed with good flatness on the upper surfaces of the conductive layer 237 and the insulating layer 219, which have good flatness. By improving the flatness of both of the pair of electrodes of the capacitive element C1 and the insulating layer 441, which functions as a dielectric, localized electric field concentration can be suppressed, and as a result, leakage current between the pair of electrodes of the capacitive element C1 can be prevented. Furthermore, one of the pair of electrodes of the capacitive element C1 (here, the lower electrode) is provided in a smaller area than the other of the pair of electrodes of the capacitive element C1 (here, the upper electrode). This configuration makes it possible to suppress localized electric field concentration that can be applied to the dielectric film (insulating film sandwiched between a pair of electrodes) of the capacitive element C1, thereby enabling the realization of a highly reliable semiconductor device.

[0254] For example, in the arithmetic circuit IM1 shown in Figure 1B, by configuring the capacitive element C1 as described above, leakage current between the pair of electrodes of the capacitive element C1 that occurs between the gate of transistor M1 and the wiring VCL1 can be prevented. Therefore, in the arithmetic circuit IM1, fluctuations in the potential of the gate of transistor M1 due to this leakage current can be prevented, and the potential can be maintained for a long period of time. In addition, localized electric field concentration can be suppressed with respect to the dielectric of the capacitive element C1, thereby increasing the reliability of the arithmetic circuit IM1. Similarly, with respect to the capacitive element C2, leakage current between the pair of electrodes of the capacitive element C2 that occurs between the back gate of transistor M1 and the wiring VCL2 can be prevented.

[0255] In Figure 7, a conductive layer 231 functioning as a back gate is provided only on transistor M1, but back gates may also be provided on one or both of transistors M2 and M3. By providing a back gate on each transistor and changing the potential of the back gate, the threshold voltage of that transistor can be changed. For example, by providing back gates on both transistors M2 and M3, the influence of external electric fields is reduced, and the off state can be stably maintained. Therefore, the data written to capacitive elements C1 and C2 can be stably retained. In this way, by providing back gates, the operation of the arithmetic circuit IM1 is stabilized, and the reliability of the circuit layer OMAL including the arithmetic circuit IM1 can be improved.

[0256] Furthermore, when a back gate is provided in a transistor, it is preferable not to provide a conductive layer near the back gate in order to avoid the formation of parasitic capacitance with the back gate.

[0257] Preferably, each of transistors M1 to M3 is an OS transistor in which an oxide semiconductor, a type of metal oxide, is used in the semiconductor layer where the channel is formed. Since oxide semiconductors have a band gap of 2 eV or more, the off-current is significantly low. Therefore, the power consumption of the arithmetic circuit can be reduced. Therefore, the power consumption of the arithmetic unit CDVA, which includes the arithmetic circuit IM1, can be reduced.

[0258] Furthermore, OS transistors operate stably even in high-temperature environments and exhibit minimal characteristic fluctuations. For example, the off-current hardly increases even in high-temperature environments. Specifically, the off-current hardly increases even in environments between room temperature (e.g., 25°C) and 200°C. Also, the on-current does not easily decrease even in high-temperature environments. In addition, the arithmetic cell shown in Figure 7 can hold the first data, thus also functioning as a memory device. For this reason, the arithmetic cell operates stably even in high-temperature environments, resulting in high reliability.

[0259] In particular, by using indium oxide for the oxide semiconductor mentioned above, that is, by making each of transistors M1 to M3 an I / O transistor, it is possible to create transistors with low off-current and high on-current. This can sometimes lead to the realization of a computing device that combines high reliability with high operating speed.

[0260] <<Transistor Configuration Example 1>> Next, we will explain a specific configuration example of a transistor called a GL structure that can be applied to transistors M1 to M3 shown in Figure 7. Transistor 200 shown in Figures 9A and 9B is an example of a GL structure transistor that can be applied to transistors M1p, M3p and M4p in Figure 7.

[0261] In particular, Figure 9A shows a schematic cross-sectional view of transistor 200 in the channel length direction, and Figure 9B shows a schematic cross-sectional view of transistor 200 in the channel width direction.

[0262] As shown in Figures 9A and 9B, the transistor 200 includes, for example, a semiconductor layer 251a, a semiconductor layer 251b, a conductive layer 231, a conductive layer 232a, a conductive layer 232b, a conductive layer 233, an insulating layer 212, insulating layers 261 to 264, insulating layers 281 to 283, and insulating layers 212 to 214. However, the transistor 200 may not have all of the above-mentioned components. For example, although the conductive layer 231 functions as a back gate electrode in the transistor 200, the transistor 200 can also be configured without the conductive layer 231.

[0263] The conductive layer 231 (conductive layer 231a and conductive layer 231b) and the insulating layer 212 are arranged on top of the substrate (not shown). In particular, it is preferable that the conductive layer 231 is embedded in the insulating layer 212. Specifically, it is preferable that the conductive layer 231a is provided in contact with the bottom surface and side wall of an opening provided in the insulating layer 212. It is also preferable that the conductive layer 231b is provided so as to be embedded in a recess formed in the conductive layer 231a. In the transistor 200 shown in Figures 9A and 9B, the height of the upper surface of the conductive layer 231b is approximately the same as the height of the upper surface of the conductive layer 231a and the height of the upper surface of the insulating layer 212.

[0264] The insulating layer 212, for example, functions as a planarizing film that flattens steps caused by plugs and the like, similar to the insulating layer 112. Therefore, the insulating layer 212 can be made of a material that functions as a planarizing film, similar to the insulating layer 112.

[0265] Furthermore, by using a material with a low dielectric constant for the insulating layer 212, parasitic capacitance between wirings can be reduced. For example, silicon oxide, silicon oxynitride, silicon oxide nitride, or silicon nitride can be used for the insulating layer 212. Alternatively, for example, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, or porous silicon oxide can be used for the insulating layer 212. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, or porous silicon oxide are particularly preferred because they can easily form regions containing oxygen that is desorbed by heating. Alternatively, for example, resin can be used for the insulating layer 212. The material used for the insulating layer 212 may also be an appropriate combination of the insulating materials described above.

[0266] In this specification, "oxide-nitride" refers to a material in which the oxygen content is greater than the nitrogen content, and "nitride oxide" refers to a material in which the nitrogen content is greater than the oxygen content. For example, when "silicon oxynitride" is written, it refers to a material in which the oxygen content is greater than the nitrogen content, and when "silicon nitride oxide" is written, it refers to a material in which the nitrogen content is greater than the oxygen content.

[0267] Furthermore, the semiconductor layer 251 and the conductive layer 233 are arranged in a region that overlaps with the conductive layer 231. The semiconductor layer 251b is arranged on top of the semiconductor layer 251a. The conductive layers 232a and 232b are arranged on top of the semiconductor layer 251b, spaced apart from each other. The insulating layer 213 is arranged on top of the conductive layers 232a and 232b. In particular, the insulating layer 213 has an opening formed in the region between the conductive layers 232a and 232b. The conductive layer 233 is arranged within this opening. The insulating layer 264 is arranged between the semiconductor layer 251b, the conductive layer 232a, the conductive layer 232b, and the insulating layer 213, and the conductive layer 233. Here, as shown in Figures 9A and 9B, it is preferable that the upper surface of the conductive layer 233 substantially coincides with the upper surface of the insulating layer 264 and the insulating layer 213. In the following, conductive layers 231a and 231b may be collectively referred to as conductive layer 231. Also, semiconductor layers 251a and 251b may be collectively referred to as semiconductor layer 251. Furthermore, conductive layers 232a and 232b may be collectively referred to as conductive layer 232.

[0268] Furthermore, as shown in Figure 9A, a low-resistance region 271a may be formed at and near the interface of the semiconductor layer 251b with the conductive layer 232a. Similarly, a low-resistance region 271b may be formed at and near the interface of the semiconductor layer 251b with the conductive layer 232b. In this case, region 271a functions as either a source region or a drain region, and region 271b functions as either a source region or a drain region. In addition, a channel-forming region is formed in the region sandwiched between region 271a and region 271b.

[0269] For the semiconductor layer 251, it is preferable to use a metal oxide that functions as an oxide semiconductor and includes a channel formation region. In particular, indium oxide, as described in Embodiment 3, is preferred as the metal oxide. In addition to indium oxide, various other metal oxides that form the channel formation region of the transistor 200 will also be described below.

[0270] As the metal oxide that forms the channel formation region of the transistor 200, it is preferable to use one with a band gap of 2 eV or more, preferably 2.5 eV or more. Specifically, for example, in the case of the transistor 200 shown in Figures 9A and 9B, it is preferable to use a metal oxide that functions as an oxide semiconductor for the semiconductor layer 251.

[0271] Metal oxide structures can be classified into single-crystal structures and other structures (non-single-crystal structures). Examples of non-single-crystal structures include CAAC (c-axis aligned crystalline) structures, polycrystalline structures, nanocrystalline structures, a-like (amorphous-like) structures, and amorphous structures. The structure of the metal oxide in one aspect of the present invention is not particularly limited, and any of the above structures may be used. However, using crystalline metal oxides such as CAAC structures and nc structures is preferable because it allows for the creation of highly reliable semiconductor devices.

[0272] Furthermore, it is preferable that the above metal oxide contains at least indium. It may also contain indium and zinc. In addition to these, it may also contain element M. Element M can be one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony. In particular, element M can be one or more selected from aluminum, gallium, yttrium, or tin. It is even more preferable that element M contains either or both gallium and tin.

[0273] As the above metal oxides, indium oxide (also called indium oxide, IO), gallium oxide (also called gallium oxide), zinc oxide (also called zinc oxide), indium zinc oxide (In-Zn oxide), indium tin oxide, indium titanium oxide, indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide, indium gallium tin oxide, gallium zinc oxide, aluminum zinc oxide, indium aluminum zinc oxide, indium tin zinc oxide, indium titanium zinc oxide, indium gallium zinc oxide (also called In-Ga-Zn oxide, IGZO), indium gallium tin zinc oxide, indium gallium aluminum zinc oxide, etc. can be used. Alternatively, indium tin oxide, gallium tin oxide, aluminum tin oxide, etc. containing silicon can be used.

[0274] As stated above, the metal oxide preferably contains indium. Specifically, it is preferable to use indium oxide as the metal oxide. Crystalline indium oxide is particularly preferable.

[0275] Metal oxides can be suitably formed using sputtering or ALD (Advanced Laser Deposition). When metal oxides are formed by sputtering, films with high crystallinity or high film density can be formed. When metal oxides are formed using ALD, atoms can be deposited layer by layer, resulting in film formation with fewer defects such as pinholes, excellent coverage, and the ability to form films at low temperatures. Furthermore, it is preferable to perform an impurity removal treatment after the formation of the metal oxide to remove impurities (typically water, hydrogen, carbon, nitrogen, etc.) from the metal oxide film. Examples of impurity removal treatments include plasma treatment and heat treatment. Microwave plasma treatment is an example of plasma treatment.

[0276] In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less. Microwave plasma processing refers to processing using a device that has a power supply that generates high-density plasma using microwaves, for example. Microwave plasma processing can also be called microwave-excited high-density plasma processing.

[0277] In the transistor 200, a configuration is shown in which two semiconductor layers, semiconductor layer 251a and semiconductor layer 251b, are stacked in the region where the channel is formed (hereinafter also referred to as the channel formation region) and in its vicinity. However, the present invention is not limited to this. For example, a single-layer structure of semiconductor layer 251b or a stacked structure of three or more layers may be provided. Furthermore, each of semiconductor layer 251a and semiconductor layer 251b may have a stacked structure of two or more layers.

[0278] The conductive layer 233 functions as the first gate electrode of the transistor (sometimes referred to as the top gate electrode or front gate electrode), and as described above, the conductive layers 232a and 232b function as the source electrode or drain electrode, respectively. As described above, the conductive layer 233 is formed to be embedded in the opening of the insulating layer 213 and in the region sandwiched between the conductive layers 232a and 232b. Here, the conductive layer 233, conductive layer 232a, and conductive layer 232b are formed in a self-aligned manner with respect to the opening of the insulating layer 213. In other words, in the transistor 200, the first gate electrode can be positioned in a self-aligned manner between the source electrode and the drain electrode. Therefore, since the conductive layer 233 can be formed without providing a positional margin, the occupied area of ​​the transistor 200 can be reduced. This makes it possible to increase the density of arithmetic cells in the arithmetic unit.

[0279] The transistor 200 can be formed by first forming an island-shaped laminate on an insulating layer 262 (described later), including an insulating layer 263 (described later), a semiconductor layer 251, and conductive layers that will become conductive layers 232a and 232b; then stacking insulating layers 282 and 213 (collectively referred to here as the interlayer film) above the island-shaped laminate and above the insulating layer 262 in that order; and then forming an opening in the region of the interlayer film that overlaps the island-shaped laminate, and providing an insulating layer 264 and a conductive layer 233 in that order in the opening. In particular, it is preferable to form the conductive layers 232a and 232b simultaneously by forming the opening in the interlayer film. In this specification, a transistor structure in which, after the formation of the island-shaped laminate and the interlayer film, an opening reaching the island-shaped laminate is provided in the interlayer film, and a conductive layer that will become the first gate electrode of the transistor is provided to fill the opening is referred to as the GL structure. This type of structure is sometimes also called a TGSA structure.

[0280] In Figures 9A and 9B, the conductive layer 233 is shown as a two-layer structure. Here, it is preferable that the conductive layer 233 has a conductive layer 233a and a conductive layer 233b disposed on top of the conductive layer 233a. For example, it is preferable that the conductive layer 233a is arranged to enclose the bottom and sides of the conductive layer 233b. In this case, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion as the conductive layer 233a.

[0281] It is preferable to use a conductive material for the conductive layer 233a that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, one or both of oxygen atoms and oxygen molecules). Furthermore, by having the function of suppressing the diffusion of oxygen in the conductive layer 233a, it is possible to suppress the oxidation of the conductive layer 233b by oxygen contained in the insulating layer 213, etc., and the decrease in the conductivity of the conductive layer 233b. As a conductive material that has the function of suppressing the diffusion of oxygen, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc.

[0282] Furthermore, it is preferable to use a conductive layer with high conductivity for the conductive layer 233b. For example, the conductive layer 233b can be made of a conductive material mainly composed of tungsten, copper, or aluminum. The conductive layer 233b may also be in a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.

[0283] Although Figures 9A and 9B show the conductive layer 233 as a two-layer laminated structure, the present invention is not limited to this. For example, the conductive layer 233 may be a single layer or a laminated structure of three or more layers.

[0284] For the conductive layer 232a and the conductive layer 232b, it is preferable to use, for example, a conductive material that is difficult to be oxidized or a conductive material having a function of suppressing the diffusion of oxygen. Examples of the conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. Thereby, it is possible to suppress a decrease in the conductivity of the conductive layer 232a and the conductive layer 232b. When using a conductive material containing metal and nitrogen as the conductive layer 232a and the conductive layer 232b, the conductive layer 232a and the conductive layer 232b become a conductive layer having at least metal and nitrogen. For example, as the material applied to the conductive layer 232a and the conductive layer 232b, a conductive material that is difficult to be oxidized or a conductive material having a function of suppressing the diffusion of oxygen can be selected from the materials applicable to each of the above-described conductive layer 233a and the conductive layer 233b.

[0285] For the conductive layer 234a and the conductive layer 234b, a conductive material mainly composed of tungsten, copper, or aluminum can be used. Further, the conductive layer 234a and the conductive layer 234b can have a laminated structure having a plurality of layers. In particular, it is preferable that the laminated structure is a structure in which a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen and a material having high conductivity are laminated with each other.

[0286] In addition, the conductive layer 231 may function as a second gate electrode (sometimes referred to as a bottom gate electrode or a back gate electrode). In this case, by independently changing the potential applied to the conductive layer 231 separately from the potential applied to the conductive layer 233, the threshold voltage V ｔｈ of the transistor 200 can be controlled. In particular, by applying a negative potential to the conductive layer 231, it is possible to make V ｔｈ of the transistor 200 larger and reduce the off-current. Therefore, applying a negative potential to the conductive layer 231 can make the drain current smaller when the potential applied to the conductive layer 233 is 0V than when no potential is applied.

[0287] The conductive layer 231 should be larger than the channel formation region in the semiconductor layer 251. In particular, as shown in Figure 9B, it is preferable that the conductive layer 231 extends as wiring even in the region outside the edge that intersects with the channel width direction of the semiconductor layer 251. That is, it is preferable that the conductive layer 231 and the conductive layer 233 are superimposed on the outside of the side surface in the channel width direction of the semiconductor layer 251, with an insulating layer in between.

[0288] For the conductive layer 231, for example, a material applicable to the conductive layer 233a and conductive layer 233b described above can be selected and used.

[0289] As shown in Figures 9A and 9B, the transistor 200 preferably has an insulating layer 211 disposed on a substrate (not shown), an insulating layer 281 disposed on the insulating layer 211, an insulating layer 212 disposed on the insulating layer 281, a conductive layer 231 disposed so as to be embedded in the insulating layer 212, an insulating layer 261 disposed on the insulating layer 212 and the conductive layer 231, an insulating layer 262 disposed on the insulating layer 261, and an insulating layer 263 disposed on the insulating layer 262. It is preferable that a semiconductor layer 251a is disposed on the insulating layer 263.

[0290] Furthermore, as shown in Figures 9A and 9B, it is preferable that an insulating layer 282 is placed between the insulating layer 262, insulating layer 263, semiconductor layer 251a, semiconductor layer 251b, conductive layer 232a, conductive layer 232b, and insulating layer 213. Here, it is preferable that the insulating layer 282 is in contact with the side surface of the insulating layer 264, the top and side surface of the conductive layer 232a, the top and side surface of the conductive layer 232b, the semiconductor layer 251a, semiconductor layer 251b, the side and top surface of the insulating layer 263, and the top surface of the insulating layer 262, as shown in Figures 9A and 9B.

[0291] Furthermore, insulating layer 264 functions as a first gate insulating film in transistor 200. In addition, insulating layers 261 to 263 function as second gate insulating films. For these gate insulating films, for example, silicon oxide, silicon oxide nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, or silicon oxide with vacancies can be used. In addition, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO) can be used. ３ ) or (Ba, Sr)TiO ３ An insulating layer containing a so-called high-k material such as (BST) can be used in a single layer or a multilayer configuration. Furthermore, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the above insulating layer material. Alternatively, these insulating layers may be subjected to nitriding treatment.

[0292] Preferably, insulating layers 283 and 214, which function as interlayer films, are arranged on the transistor 200. Here, it is preferable that the insulating layer 283 is arranged in contact with the upper surfaces of the conductive layer 233, the insulating layer 264, and the insulating layer 213. In this case, it is preferable that the upper surface of the insulating layer 213 is flattened.

[0293] It is preferable that a conductive layer 234 (conductive layer 234a and conductive layer 234b) is provided, which connects to the transistor 200 and functions as a plug. For this reason, the conductive layer 234 is provided in contact with the inner wall of the opening of the insulating layer 282, insulating layer 213, insulating layer 283, and insulating layer 214. In particular, a first conductive layer of the conductive layer 234 may be provided in contact with the inner wall, and a second conductive layer of the conductive layer 234 may be provided on the side surface of the first conductive layer. Here, the height of the upper surface of the conductive layer 234 and the height of the upper surface of the insulating layer 214 can be made to be approximately the same.

[0294] Specifically, for example, a first conductive layer of conductive layer 234a is provided in contact with one inner wall of two openings in insulating layer 214, insulating layer 283, insulating layer 213 and insulating layer 282, and a second conductive layer of conductive layer 234a is formed in contact with its side surface. A conductive layer 232a is located in a part of the bottom of the opening, and conductive layer 234a is in contact with conductive layer 232a. Similarly, for example, a first conductive layer of conductive layer 234b is provided in contact with the other inner wall of two openings in insulating layer 214, insulating layer 283, insulating layer 213 and insulating layer 282, and a second conductive layer of conductive layer 234b is formed in contact with its side surface. A conductive layer 232b is located in a part of the bottom of the opening, and conductive layer 234b is in contact with conductive layer 232b.

[0295] Although the transistor 200 shows a configuration in which a first conductive layer and a second conductive layer of the conductive layer 234 are stacked, the present invention is not limited thereto. For example, the conductive layer 234 may be provided as a single layer or as a stacked structure of three or more layers. When a structure has a stacked structure, an ordinal number may be assigned to distinguish it according to the order of formation.

[0296] As shown in Figure 9B, in the region of the semiconductor layer 251b that does not overlap with the conductive layer 232, in other words, in the channel formation region of the semiconductor layer 251, the side surface of the semiconductor layer 251 is covered by the conductive layer 233. This makes it easier to apply the electric field of the conductive layer 233, which functions as the first gate electrode, to the side surface of the semiconductor layer 251, and as a result, the channel formation region of the semiconductor layer 251 can be electrically surrounded by the electric field of the conductive layer 233. Therefore, the on-current of the transistor 200 can be increased and the frequency characteristics can be improved.

[0297] For example, the insulating layer 213 preferably has a lower dielectric constant than the insulating layer 262. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance between wirings can be reduced. Therefore, as a material with a low dielectric constant, the insulating layer 213 can be made from a material that can be used for the insulating layer 212.

[0298] <<Transistor Configuration Example 2>> In the schematic cross-sectional view of Figure 7, which shows an example of the configuration of a computing device, a semiconductor device according to one aspect of the present invention, each of transistors M1 to M3 is described as having a GL structure. However, the structures of each of transistors M1 to M3 according to one aspect of the present invention are not limited to this. Each of transistors M1 to M3 according to one aspect of the present invention can be, for example, a vertical channel type transistor structure as described below, as an alternative to the GL structure.

[0299] Figures 10A to 10C show examples of the configuration of a vertical channel transistor. In a vertical channel transistor, the source electrode and drain electrode are located at different heights, and the current flowing through the semiconductor layer flows in the height direction. In other words, the channel length direction can be said to have a component in the height direction (vertical direction).

[0300] The transistors shown in Figures 10A to 10C may also be called VFETs (Vertical Field Effect Transistors), vertical transistors, or vertical channel transistors, in addition to being vertical channel transistors. Furthermore, in this specification, in vertical channel transistors, one of the source electrode or drain electrode located at the bottom may be referred to as the bottom electrode. Also, the other of the source electrode or drain electrode located at the top may be referred to as the top electrode.

[0301] In particular, Figure 10A shows a schematic plan view of an example of a vertical channel type transistor 300, and Figures 10B and 10C show schematic cross-sectional views of the transistor 300. Figure 10B is a schematic cross-sectional view along the dashed line A1-A2 shown in Figure 10A, and Figure 10C is a schematic cross-sectional view along the dashed line A3-A4 shown in Figure 10A. Figure 10B shows a selection of transistors included in the circuit layer OMAL. Figure 11 shows a schematic perspective view of the transistor 300 and its surrounding wiring as shown in Figures 10A to 10C.

[0302] The transistor 300 shown in Figures 10A to 10C and Figure 11 includes, as an example, a conductive layer 331 that functions as wiring or an electrode, a conductive layer 332 that functions as wiring or an electrode, a semiconductor layer 351 that includes a channel formation region of the transistor 300, an insulating layer 361 that functions as a gate insulating film of the transistor 300, a conductive layer 333 that functions as the gate of the transistor 300, and a conductive layer 334 that functions as wiring.

[0303] The conductive layer 331 is provided above the insulating layer 311, which functions as an interlayer film. Furthermore, since the conductive layer 331 functions as wiring, it extends along the dashed line A3-A4 in the schematic plan view of Figure 10A.

[0304] For example, the conductive layer 331 can be a conductive layer applicable to transistors M1 to M3 as described above. The same applies to conductive layers 332 to 334, which will be described later.

[0305] An insulating layer 312 and a conductive layer 332, which function as an interlayer film, are formed in this order on the insulating layer 311 and the conductive layer 331. In Figure 10(B), the insulating layer 312 has a three-layer structure consisting of two barrier insulating films that suppress the diffusion of impurities and an interlayer film sandwiched between these barrier insulating films. Preferably, these barrier insulating films have the function of suppressing the diffusion of oxygen to prevent oxidation of the conductive layer 331 or the conductive layer 332. Furthermore, since the conductive layer 332 functions as wiring, it extends along the direction of the dashed line A1-A2 in the schematic plan view of Figure 10A.

[0306] Furthermore, the insulating layer 312 and the conductive layer 332 have openings that reach the conductive layer 331 in the region overlapping with the conductive layer 331. Semiconductor layers 351 are formed on the sides and bottom of these openings. In other words, the semiconductor layer 351 is formed on the upper surface of the conductive layer 331, the side surface of the insulating layer 312, and the side surface of the conductive layer 332. The semiconductor layer 351 is also formed on a part of the upper surface of the conductive layer 332. The insulating layer 361 is provided so as to be in contact with the conductive layer 332, the semiconductor layer 351, and the insulating layer 312 both inside and outside the openings. Furthermore, conductive layers 333 are formed on the upper and side surfaces of the insulating layer 361 so as to fill the openings.

[0307] Furthermore, an insulating layer 313, which functions as an interlayer film, is formed on the upper surface of the insulating layer 361 and the upper surface of the conductive layer 333. In addition, an opening that reaches the conductive layer 333 is formed in the region of the insulating layer 313 that overlaps with the conductive layer 333. Conductive layers 334 are embedded in the sides and bottom of the opening. A portion of the conductive layer 334 may be formed on the upper surface of the insulating layer 313. Furthermore, an insulating layer 314, which functions as an interlayer film, is formed on both the insulating layer 313 and the conductive layer 334.

[0308] Furthermore, since the conductive layer 334 functions as wiring, it extends along the dashed line A3-A4 in the schematic plan view of Figure 10A.

[0309] For insulating layers 311 to 314, it is preferable to use an insulating material with a low relative permittivity. By using an insulating material with a low relative permittivity as the interlayer film, parasitic capacitance occurring between wiring can be reduced. For this reason, each of the insulating layers 311 to 314 can be made from a material applicable to the insulating layer 212 or insulating layer 213 described above.

[0310] Furthermore, since the insulating layer 361 functions as a gate insulating film, the insulating layer 361 can be made of a material that can be used for the insulating layer 264, for example.

[0311] A portion of the conductive layer 331 functions as either the source electrode or the drain electrode in the transistor 300. A portion of the conductive layer 332 functions as the other source electrode or drain electrode in the transistor 300. Furthermore, a portion or all of the conductive layer 333 functions as the gate electrode in the transistor 300.

[0312] As described above, by forming an insulating layer, a conductive layer, and a semiconductor layer, a vertical channel transistor can be formed in which the channel length has a component in the height direction (vertical direction). Furthermore, the channel length of transistor 300 depends on the thickness of the insulating layer 312; the thinner the insulating layer 312, the shorter the channel length, and thus the on-current of transistor 300 can be increased. On the other hand, the thicker the insulating layer 312, the longer the channel length, and thus the off-current of transistor 300 can be decreased.

[0313] Furthermore, the wiring connecting the source, drain, or gate of the vertical channel transistor is not formed by the same process, but by different processes. As a result, the wiring connecting the source, drain, or gate of the vertical channel transistor has overlapping regions in a plan view. Since the wiring connecting the source, drain, or gate of the vertical channel transistor is provided at different heights, the parasitic capacitance occurring in each wiring can be reduced. This allows the drive frequency of the transistor 300 to be increased, and the drive speed of the arithmetic unit CDVA and other components to be increased.

[0314] This embodiment can be appropriately combined with the same or other embodiments shown in this specification. For example, the configurations, structures, and methods shown in this embodiment can be appropriately combined with other configurations, structures, and methods shown in this embodiment. Also, for example, the configurations, structures, and methods shown in this embodiment can be appropriately combined with configurations, structures, and methods shown in other embodiments.

[0315] (Embodiment 3) This embodiment describes an indium oxide film that can be used as a metal oxide for the channel formation region of an I / O transistor according to one aspect of the present invention described in the above embodiment.

[0316] In this specification, indium oxide having at least a crystalline portion or crystalline region in the film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystal IO or crystalline IO include single-crystal indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0317] Indium oxide is a semiconductor material with completely different physical properties from oxide semiconductors such as In-Ga-Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0318] The carrier concentration dependence of the hole (Hall) mobility of indium oxide, silicon, and IGZO is described. Figure 12A shows silicon (Si) and indium oxide (InO Ｘ Figure 12B is a schematic diagram of the carrier concentration dependence of hole mobility with respect to IGZO.

[0319] First, as indicated by the arrows in Figure 12B, IGZO tends to exhibit higher hole mobility as the carrier concentration increases. On the other hand, as indicated by the arrows in Figure 12A, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases (see Non-Patent Literature 3). This trend is similar to that of silicon, where the lower the concentration of dopants (impurities) in the material, the less impurity scattering occurs and the higher the hole mobility. In other words, the higher the purity and intrinsic nature of indium oxide, the higher its hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to silicon. Note that the properties of indium oxide shown in Figure 12A are assumed to be those of a single crystal. Therefore, when indium oxide is not a single crystal (for example, polycrystalline), the properties may differ from those shown in Figure 12A.

[0320] In FIG. 12A, since the range R1 with a low carrier concentration has an extremely high hole mobility, it can be said that it is a range of carrier concentration suitable for, for example, the channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range including a carrier concentration value of 1×10 １５ cm −３ and, for example, is a range of 1×10 １４ cm −３ or more and 1×10 １８ cm −３ or less. By sufficiently reducing the carrier concentration, it can be expected that the value of the hole mobility can be increased to about 270 cm ２ / (V·s).

[0321] In indium oxide, the region where the carrier concentration is in the range R1 can contain an element that lowers the carrier concentration. Examples of the element that lowers the carrier concentration include magnesium, calcium, zinc, cadmium, copper, etc. By substituting these elements for indium, the carrier concentration can be lowered. Also, examples of the element that lowers the carrier concentration include nitrogen, phosphorus, arsenic, antimony, etc. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0322] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and it can be said that it is a range of carrier concentration suitable for, for example, the source region and drain region of a transistor, or a resistor, or a transparent conductive film. The range R2 is a range including a carrier concentration value of 1×10 ２０ cm −３ and, for example, is a range of 1×10 １９ cm −３ or more and 1×10 ２２ cm −３ or less. By sufficiently increasing the carrier concentration, it can be expected that the resistivity can be reduced to 1×10 −４ Ω·cm or less.

[0323] Furthermore, in the indium oxide, the region where the carrier concentration is in the range R2 may contain elements that increase the carrier concentration. For example, it is preferable to include elements common to the source electrode and drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use elements whose oxides are conductive or semiconducting. In addition to the elements mentioned above, other examples include elements contained in the conductive layer that can be used for the source electrode or drain electrode of the transistor, as described in Embodiment 2.

[0324] In this way, indium oxide uses regions with low carrier concentrations for the transistor's channel formation region and regions with high carrier concentrations for the transistor's source and drain regions. In other words, indium oxide can be considered an oxide in which valence electron control is possible. Note that in IGZO, strain may be formed in the source and drain regions due to stress on the electrodes in contact with IGZO, and an n-type region may be formed. On the other hand, unlike IGZO, indium oxide allows for valence electron control, so it does not require strain to be formed in the film as in IGZO. Less strain in the film is expected to improve reliability. For example, by creating regions with carrier concentrations in the range R1 and range R2 shown in Figure 12A within the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in silicon transistors is generally known. On the other hand, valence electron control in indium oxide transistors is a novel technological concept that would not normally be conceived.

[0325] By applying the above technical concept, the indium oxide transistor described herein has two or more, preferably three or more, more preferably four or more, and most preferably five of the following features (1) to (5): (1) High on-current (in other words, high mobility). (2) Low off-current. (3) Normally off is possible. (4) High reliability. (5) High cutoff frequency (fT). For example, the indium oxide transistor described herein has high mobility, low off-current, and is normally off. This transistor is different from a transistor that is high mobility and normally on.

[0326] Next, we will describe indium oxide films applied to transistors. Indium oxide films are preferably crystalline (i.e., they have crystal grains). Examples of films with crystal grains include single-crystal films, polycrystalline films, or amorphous films containing crystal grains (also called microcrystalline films). In particular, polycrystalline films are preferred for indium oxide films, and single-crystal films are more preferred. Single-crystal films do not have crystal grain boundaries. Impurities that inhibit carrier flow (typically insulating impurities, insulating oxides, etc.) tend to segregate at crystal grain boundaries. By using single-crystal films, carrier scattering at crystal grain boundaries can be suppressed, enabling the realization of transistors exhibiting high field-effect mobility. Furthermore, it has the excellent effect of suppressing variations in transistor characteristics caused by these crystal grain boundaries.

[0327] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using polycrystalline films, it is preferable to use films with the largest possible grain size and few grain boundaries. In a transistor to which a polycrystalline indium oxide film is applied, if there are no grain boundaries in the channel formation region, or if no grain boundaries are observed, the channel formation region is located within the single-crystal region contained in the polycrystalline film, and therefore it can be considered a transistor to which single-crystal indium oxide is applied.

[0328] The crystallinity of indium oxide can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0329] Furthermore, in this specification, a semiconductor layer in which no grain boundaries are observed in the channel-forming region, a semiconductor layer in which the channel-forming region is contained within a single crystal grain, or a semiconductor layer in which the direction of the crystal axes is the same in at least two regions within the channel-forming region can be called a single crystal film. In addition, a semiconductor layer in which, within a single crystal grain in the channel-forming region, the direction of other crystal axes changes continuously with respect to a certain crystal axis or crystal orientation as the axis of rotation can be called a single crystal film.

[0330] The channel formation region refers to the area within the semiconductor layer that overlaps with (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, grain boundaries, crystal axes, and crystal orientation in the channel formation region can be confirmed by cross-sectional observation including the semiconductor layer, source electrode, and drain electrode.

[0331] The indium oxide film in the channel-forming region is preferable to have a low impurity concentration. Impurities in the indium oxide film in the channel-forming region can act as a scattering source for carriers, and thus can cause a decrease in field-effect mobility. Furthermore, these impurities can also inhibit crystal growth in the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The concentration of these impurities in the indium oxide film is preferably 0.1% or less, and more preferably 0.01% (100 ppm) or less. Note that elements such as carbon and hydrogen may be present in the deposition gas or precursor during film formation, and may remain in the indium oxide film in higher concentrations than the impurities mentioned above.

[0332] Furthermore, the indium oxide film in the channel-forming region may contain elements that can become trivalent cations like indium, as long as their crystals maintain a cubic crystal structure (Bixbite type). Examples include Group 13 elements of the periodic table such as gallium and aluminum, and Group 3 elements of the periodic table. Since these elements mainly exist as trivalent cations in the oxide, the carrier concentration of indium oxide can be kept low.

[0333] By using such an indium oxide film in a transistor, the field-effect mobility of the transistor can be increased to 50 cm². ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ It can be set to (V・s) or more.

[0334] One of the characteristics of indium oxide films is that they have higher oxygen permeability (diffusivity) compared to IGZO films. As shown in Figure 12C, indium oxide films (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and oxygen molecules (O) ２ It is released as water molecules (H) by reacting with hydrogen contained in the membrane. ２ It may also be released as O. Furthermore, oxygen deficiencies (V) can form in the membrane. Ｏ If oxygen atoms are present, diffusing oxygen atoms will fill the oxygen deficiency. Indium oxide films allow oxygen to diffuse easily, so they can be said to fill oxygen deficiencies more easily than IGZO films.

[0335] Thus, because indium oxide films are more likely to reduce oxygen vacancies in the film compared to IGZO films, applying such indium oxide films to transistors makes it possible to realize transistors with extremely high reliability.

[0336] Furthermore, as shown in Figure 12C, the indium oxide film diffuses hydrogen. Hydrogen diffusing into the indium oxide film from the outside permeates the film and forms hydrogen molecules (H ２It is released as ) or, by reacting with oxygen contained in the membrane, it is released as water molecules.

[0337] Transistors using indium oxide films are storage-type transistors that use electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, in a transistor, the on-current or field-effect mobility of the transistor can be increased.

[0338] The table below shows single crystal indium oxide (here, In ２ O ３ The table below shows the effective masses of indium oxide and single-crystal silicon (Si). As shown in the table below, indium oxide is characterized by a small effective electron mass and a large effective hole mass. Furthermore, the effective electron mass of indium oxide is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in transistors, transistors with high field-effect mobility and high frequency characteristics (also called f-characteristics) can be realized. In addition, because the effective hole mass is large, transistors with extremely low off-currents can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width is 1 fA (1 × 10⁻¹⁶) in an environment of 125°C. −１５ A) Less than or equal to, or 1aA (1 × 10 −１８ A) is less than or equal to 1aA (1 × 10) under room temperature (25°C) conditions. −１８ A) Less than or equal to, or 1zA (1 × 10⁻¹⁰ −２１ A) The following is possible. Furthermore, as shown in the table below, indium oxide has a smaller effective electron mass and a larger effective hole mass than silicon, so it may be possible to realize a transistor with higher field-effect mobility and lower off-current than a Si transistor.

[0339]

[0340] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. It is preferable to use a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with the indium oxide for the seed layer. This improves the crystallinity of the indium oxide film. A substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0341] One method for evaluating the degree of lattice mismatch is to use the following lattice mismatch value. The lattice mismatch Δa [%] of the crystals in the formed film (in this case, the indium oxide film) relative to the crystals in the seed layer is given by Δa = ((L １ -L ２ ) / L ２ It is calculated as ) × 100. Here L １ L is the length of the unit cell vector of the crystals in the formed film, or the lattice constant. ２ is the length of the unit cell vector of the crystal in the seed layer, or the lattice constant.

[0342] The lattice mismatch Δa between the seed layer and the indium oxide film is preferably small in absolute value, and most preferably zero. For example, Δa can be -5% or more and 5% or less, preferably -4% or more and 4% or less, more preferably -3% or more and 3% or less, and even more preferably -2% or more and 2% or less.

[0343] Here, the indium oxide crystal has a cubic structure (bixbite type). For example, yttria-stabilized zirconia (YSZ) crystals can have a cubic structure (fluorite type). The lattice mismatch of the indium oxide crystal with respect to the cubic YSZ crystal is in the range of -2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on a YSZ substrate.

[0344] Furthermore, the crystal structure of the seed layer and the crystal structure of the indium oxide film do not necessarily have to be the same in terms of crystal system or crystal orientation. For example, a film with a hexagonal or trigonal crystal structure can be used beneath an indium oxide film with a cubic crystal structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to crystal orientation necessary for epitaxial growth can be met. Examples of hexagonal or trigonal crystals include wurtzite-type structures and YbFe. ２ O ４ Type structure, Yb ２ Fe ３ O ７ These include type structures and their modified type structures. YbFe ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a type structure is IGZO.

[0345] This embodiment can be appropriately combined with the same or other embodiments shown in this specification. For example, the configurations, structures, and methods shown in this embodiment can be appropriately combined with other configurations, structures, and methods shown in this embodiment. Also, for example, the configurations, structures, and methods shown in this embodiment can be appropriately combined with configurations, structures, and methods shown in other embodiments.

[0346] (Embodiment 4) This embodiment describes an electronic component that can use the semiconductor device described in the above embodiment. An electronic component using a semiconductor device according to one aspect of the present invention is effective in improving performance, such as reducing power consumption.

[0347] [Electronic Components] A perspective view of the electronic component 1700 is shown in Figure 13A. The electronic component 1700 shown in Figure 13A comprises a substrate 1701, a semiconductor device 1710 on the substrate 1701, and a mold 1711. In particular, the semiconductor device 1710 is sealed by the mold 1711. Note that in Figure 13A, some details have been omitted in order to show the inside of the electronic component 1700.

[0348] For example, the substrate 1701 can be a ceramic substrate, a plastic substrate, or a glass epoxy substrate.

[0349] The electronic component 1700 is provided with, for example, a lead frame 1712. A portion of the lead frame 1712 located on the substrate 1701 is covered by a mold 1711, while another portion of the lead frame 1712 is exposed to the outside of the mold 1711. In particular, the lead frame 1712 exposed to the outside of the mold 1711 functions, for example, as a terminal for mounting the electronic component 1700 onto a printed circuit board.

[0350] Within the mold 1711, electrode pads 1713 are provided on the lead frame 1712, and the electrode pads 1713 are connected to the semiconductor device 1710 via wires 1714. The electronic component 1700 is mounted on the printed circuit board, for example, by bringing the lead frame 1712 into contact with the wiring on the printed circuit board side. In this way, multiple electronic components are combined and connected on the printed circuit board to complete the mounted circuit board.

[0351] Next, the semiconductor device 1710 will be described. For example, as shown in Figure 13B, the semiconductor device 1710 has a drive circuit layer 1715 and a storage layer 1716. The storage layer 1716 can be configured by stacking multiple cell arrays. The cell array can include the arithmetic cells, drive cells, and storage cells described in the above embodiment. The configuration in which the drive circuit layer 1715 and the storage layer 1716 are stacked can be a monolithic stack configuration. In a monolithic stack configuration, the layers can be connected without using through-electrode technology (for example, TSV (Through Silicon Via)) and bonding technology such as Cu-Cu direct bonding. By configuring the drive circuit layer 1715 and the storage layer 1716 in a monolithic stack configuration, for example, a so-called on-chip memory configuration can be achieved in which memory is directly formed on the processor. By using an on-chip memory configuration, it is possible to speed up the operation of the interface portion between the processor and the memory. For example, by using the arithmetic unit described in the above embodiment as the processor, the transmission speed of the first data (e.g., weight coefficients) from memory to the arithmetic unit can be increased.

[0352] Furthermore, by using an on-chip memory configuration, it is possible to reduce the size of connection wiring and other components compared to technologies that use through-hole electrodes such as TSVs, thus increasing the number of connection pins. Increasing the number of connection pins enables parallel operation, which in turn improves the memory bandwidth (also called memory bandwidth).

[0353] Furthermore, it is preferable to form the multiple memory cell arrays of the memory layer 1716 using I / O transistors and to stack these multiple memory cell arrays monolithically. By configuring the multiple memory cell arrays in a monolithic stack, it is possible to improve either or both of the memory bandwidth and / or the memory access latency. Bandwidth is the amount of data transferred per unit time, and access latency is the time from access to the start of data exchange. In the case of a configuration using Si transistors in the memory layer 1716, it is difficult to create a monolithic stack configuration compared to I / O transistors. Therefore, in a monolithic stack configuration, I / O transistors can be said to have a superior structure compared to Si transistors.

[0354] Furthermore, the semiconductor device 1710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained in the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disc-shaped substrate (also called a wafer) and cutting it into cubes. Examples of semiconductor materials that can be used for dies include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) is sometimes called a silicon die.

[0355] Next, Figure 13C shows an example of a modification of the electronic component 1700. Unlike the electronic component 1700, the electronic component 1700A shown in Figure 13C does not use a lead frame 1712, and instead has electrodes 1733 provided at the bottom of the substrate 1701. The electrodes 1733 function as connection terminals for mounting the electronic component 1700A onto the printed circuit board.

[0356] Figure 13C shows an example in which the electrode 1733 is formed with solder balls. By arranging solder balls in a matrix at the bottom of the substrate 1701, BGA (Ball Grid Array) mounting can be realized. For this purpose, the substrate 1701 is provided with through-hole vias, and a conductive layer 1732 that functions as wiring is provided on these vias. On the substrate 1701, the electrode pad 1713 is provided in contact with the conductive layer 1732 above, and on the substrate 1701, the electrode 1733 is provided in contact with the conductive layer 1732 below.

[0357] Alternatively, the electrodes 1733 may be formed with conductive pins instead of solder balls. By arranging conductive pins in a matrix at the bottom of the substrate 1701, PGA (Pin Grid Array) mounting can be realized.

[0358] Furthermore, the electronic component 1700A can be mounted on other boards using various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0359] Furthermore, an electronic component according to one aspect of the present invention may take the form of a SiP (System in Package) or an MCM (Multi-Chip Module). For example, the electronic component 1700C shown in Figure 13D has an interposer 1731 provided on a package substrate 1734 (printed circuit board), and a semiconductor device 1735 and a plurality of semiconductor devices 1710 are provided on the interposer 1731.

[0360] In Figure 13D, the electronic component 1700C is shown as an example in which the semiconductor device 1710 is used as a high-bandwidth memory (HBM). For example, the semiconductor device 1735 can be used as an arithmetic circuit in an integrated circuit such as a CPU, GPU, or FPGA (Field Programmable Gate Array).

[0361] The package substrate 1734, like the substrate 1701, can be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 1731 can be, for example, a silicon interposer or a resin interposer.

[0362] The interposer 1731 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 1731 also has the function of connecting integrated circuits provided on the interposer 1731 to electrodes provided on the package substrate 1734. For these reasons, the interposer is sometimes called a "redistribution substrate" or "intermediate substrate". In addition, through electrodes may be provided on the interposer 1731, and these through electrodes may be used to connect the integrated circuits and the package substrate 1734. Furthermore, in silicon interposers, TSVs can also be used as through electrodes.

[0363] In HBMs, many connections are necessary to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted requires fine and high-density wiring. For this reason, it is preferable to use a silicon interposer for mounting the HBM.

[0364] Furthermore, in SiP and MCM using silicon interposers, reliability degradation due to differences in expansion coefficients between the integrated circuit and the interposer is less likely to occur. In addition, because silicon interposers have high surface flatness, connection failures between the integrated circuit placed on the silicon interposer and the silicon interposer are less likely to occur. In particular, in 2.5D packages (2.5-dimensional packaging) where multiple integrated circuits are arranged side by side on the interposer, it is preferable to use a silicon interposer.

[0365] On the other hand, when connecting multiple integrated circuits with different terminal pitches using silicon interposers and TSVs, space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 1700C, the width of the terminal pitch becomes a problem, and it may become difficult to provide the many wires necessary to achieve a wide memory bandwidth. For this reason, as described above, a monolithic stacked configuration using I / O transistors is preferable. Furthermore, for example, a memory cell array stacked using TSVs and a monolithic stacked memory cell array can be combined. A structure that combines a memory cell array stacked using TSVs and a monolithic stacked memory cell array is sometimes called a composite structure.

[0366] Furthermore, if the temperature of the electronic component 1700C rises due to heat generated during operation, the characteristics of the circuit elements (such as transistors) provided in the electronic component 1700C may deteriorate. Therefore, it is preferable to provide a heat sink (heat dissipation plate) on top of the electronic component 1700C. When a heat sink is provided, it is preferable to align the heights of the integrated circuits provided on the interposer 1731. For example, in the electronic component 1700C shown in this embodiment, it is preferable to align the heights of the semiconductor device 1710 and the semiconductor device 1735.

[0367] This embodiment can be appropriately combined with the same or other embodiments shown in this specification. For example, the configurations, structures, and methods shown in this embodiment can be appropriately combined with other configurations, structures, and methods shown in this embodiment. Also, for example, the configurations, structures, and methods shown in this embodiment can be appropriately combined with configurations, structures, and methods shown in other embodiments.

[0368] (Embodiment 5) This embodiment describes an electronic device using the electronic components described in the above embodiment, and an information processing system using the electronic device.

[0369] Figure 14 shows an example of the configuration of an information processing system. The information processing system 8000 shown in Figure 14 includes an example of various electronic devices and a server located within the network.

[0370] Figure 14 shows, as examples of such electronic devices, a portable information terminal 8200, a wearable information terminal 8300, a notebook personal computer 8400, an automobile 8500, an industrial robot 8600, and a camera 8700. Figure 14 also shows a network 8100 and a large computer 8110 located within the network 8100.

[0371] The term "large-scale computer 8110" can sometimes refer to multiple computers installed in a server room or similar location. For example, a rack-mount type large-scale computer 8110 is one in which multiple computers are housed in a rack. The large-scale computer 8110 is sometimes referred to as a supercomputer. Furthermore, in the information processing system 8000, the large-scale computer 8110 may also be referred to as a server or cloud server.

[0372] Each of the plurality of computers provided in the mainframe computer 8110 has a motherboard, and the motherboard is provided with a plurality of slots, a plurality of connection terminals, and the like. For example, one or more PC cards can be inserted into the slots. The PC card is an example of a processing board provided with a processing device such as a CPU and a GPU. For example, as the processing device, for example, the electronic component 1700 can be used.

[0373] The mainframe computer 8110 can also function as a parallel computer. By using the mainframe computer 8110 as a parallel computer, for example, large-scale calculations required for artificial intelligence learning and inference can be performed.

[0374] When performing wired communication as the network 8100, specifications standardized by IEEE such as Ethernet (registered trademark) can be used. Examples of the type of communication include electrical communication using electric wires such as twisted pair cables, and optical communication using optical fibers.

[0375] On the other hand, when performing wireless communication as the network 8100, as the communication protocol or communication technology, communication standards such as the 4th generation mobile communication system (4G), the 5th generation mobile communication system (5G), and the 6th generation mobile communication system (6G), or specifications standardized by IEEE such as Wi-Fi (registered trademark) and Bluetooth (registered trademark) can be used.

[0376] As the network 8100, for example, PAN (Personal Area Network), LAN (Local Area Network), CAN (Campus Area Network), MAN (Metropolitan Area Network), WAN (Wide Area Network), GAN (Global Area Network), etc. can be used. For example, by using GAN for the network 8100, the Internet, which is the foundation of the World Wide Web (WWW), can be used.

[0377] In addition, when the information processing system 8000 is constructed as a LAN as the network 8100, the possibility of, for example, confidential information leakage can be reduced compared to the case of using the Internet.

[0378] In addition, an enterprise or individual that manages the mainframe computer 8110 can provide services using the information processing system 8000 to users of each electronic device via, for example, the network 8100. As an example of such a service, there is a usage form called cloud computing. By means of such cloud computing, users of the above-described electronic devices can utilize functions such as a function for storing a large amount of data, a function for performing large-scale computations, and other applications provided in the mainframe computer 8110.

[0379] In particular, the semiconductor device according to one aspect of the present invention can execute large-scale computations such as a model of an artificial neural network by being provided in each of the above-described electronic devices and the mainframe computer 8110. As a result, the information processing system 8000 can provide services to users in a usage form called cloud AI or edge AI.

[0380] Generally, cloud AI is a usage form of a service in which the mainframe computer 8110 performs learning and inference of an artificial neural network. The mainframe computer 8110 has been pre-trained using collected data. Each electronic device transmits input data for the artificial neural network to the mainframe computer 8110, and in the mainframe computer 8110, inference on the input data is performed. The mainframe computer 8110 then transmits the result of the inference to each electronic device, and each electronic device can utilize the result of the inference. Since learning and inference are performed by the mainframe computer 8110 in cloud AI, it is suitable for performing computations on a large amount of data and processing including complex computations.

[0381] On the other hand, edge AI generally refers to a service where each electronic device performs the learning and inference of an artificial neural network. In this case, the mainframe computer 8110 provides each electronic device with the artificial neural network model, weight coefficients (sometimes called weight data, connection coefficients, etc.), etc. The results of the learning and inference performed on each electronic device are also transmitted to the mainframe computer 8110. Furthermore, a usage model in which the mainframe computer 8110 learns the artificial neural network and each electronic device performs inference using the learned neural network is also sometimes referred to as edge AI.

[0382] Edge AI performs artificial neural network inference on each individual electronic device, thus reducing the communication time required compared to cloud AI. In other words, edge AI is well-suited for real-time analysis of input data. Furthermore, the amount of data transmitted between each electronic device and the mainframe computer 8110 is reduced, lowering data communication costs and power consumption. The reduced data transmission also minimizes security risks such as information leaks. For these reasons, edge AI is suitable for building small-scale systems, for example.

[0383] Furthermore, since the semiconductor device according to one aspect of the present invention consumes extremely little power in standby mode, it can be suitably used for edge AI. A specific example of an edge AI system is described below.

[0384] [Personal Information Terminal] The personal information terminal 8200 shown in Figure 14 is an electronic device that integrates a display device and a touch panel. The personal information terminal 8200 can also be equipped with electronic component 8201 as the electronic component 1700 mentioned above, thereby enabling large-scale calculations such as artificial neural networks in the personal information terminal 8200. The personal information terminal 8200 can also be equipped with a camera.

[0385] By equipping the personal digital assistant (PDA) 8200 with a camera, image recognition using edge AI can be performed on images captured by the PDA 8200. The objects that can be recognized include humans, animals, plants, characters, and pictograms. In particular, by performing image recognition on images of human faces, fingerprints, palm prints, irises, and veins, it can be used for biometric authentication.

[0386] [Wearable Information Terminal] The wearable information terminal 8300 shown in Figure 14 is an electronic device that can be worn on a person's head. The wearable information terminal 8300 in Figure 14 has an eye cover, a display device, temples (arms) that hook onto the ears, and earphones, but other examples include HMDs (head-mounted displays) and glasses-type XR devices. The wearable information terminal 8300 can also be equipped with a camera, similar to the portable information terminal 8200.

[0387] Furthermore, the wearable information terminal 8300 can be equipped with the electronic component 8301 as the aforementioned electronic component 1700, thereby enabling large-scale computations such as artificial neural networks to be performed in the wearable information terminal 8300.

[0388] By equipping the wearable information terminal 8300 with a camera, images captured by the wearable information terminal 8300 can be displayed on a display device in real time. Furthermore, by performing image recognition using edge AI, information about objects included in the image displayed on the display device can be added to the display device. In addition, by performing image recognition on moving objects such as pedestrians, bicycles, cars, and trains displayed on the display device, it is possible to perform risk prediction to determine whether or not there is a risk of collision.

[0389] [Notebook Personal Computer] The notebook personal computer 8400 shown in Figure 14 is an electronic device primarily used on a desktop. The notebook personal computer 8400 can also be equipped with electronic component 8401 as the electronic component 1700 mentioned above, thereby enabling the notebook personal computer 8400 to perform large-scale calculations such as artificial neural networks.

[0390] The 8400 notebook personal computer can, for example, use edge AI as part of its computational processing when using applications. Examples of its applications include upconversion, which increases the screen resolution of images (including still images and videos) displayed on a display device in real time; translation, which converts text into another language; and editing tasks for text or images.

[0391] [Automobile] The automobile 8500 shown in Figure 14 is an example of a mobile device. The automobile 8500 can also be equipped with the electronic component 8501 as the electronic component 1700 described above, thereby enabling the automobile 8500 to be used as an electronic device for edge AI.

[0392] Edge AI in the Automobile 8500 can be used for applications such as autonomous driving, hazard prediction in autonomous driving, and in-car air conditioning management.

[0393] In this specification, automobiles are used as an example of a mobile device, but other examples of mobile devices include trains, monorails, ships, and aircraft (e.g., helicopters, unmanned aerial vehicles (drones), airplanes, and rockets). The aforementioned mobile devices can also be used as electronic devices for edge AI.

[0394] [Industrial Robot] The industrial robot 8600 shown in Figure 14 can be deployed, for example, in a production plant. The industrial robot 8600 preferably has multiple drive axes to finely control the drive range. The industrial robot 8600 may also have one or more functions such as grasping, cutting, welding, coating, and attaching objects. In addition, the industrial robot 8600 is preferably equipped with sensors such as an image detection module or a camera to detect the object. Furthermore, the industrial robot 8600 is preferably equipped with a sensor that detects minute currents to determine whether or not it has grasped an object.

[0395] Furthermore, the industrial robot 8600 can be equipped with the electronic component 8601 as the aforementioned electronic component 1700, thereby enabling the industrial robot 8600 to be used as an electronic device for edge AI. The edge AI in the industrial robot 8600 can be used for applications such as image recognition of objects to classify them by type, by size, and inspection to determine whether they are good or defective.

[0396] [Camera] The camera 8700 shown in Figure 14 can be used, for example, as a surveillance camera, security camera, or pet camera. Furthermore, the housing of the camera 8700 is not limited to the ceiling-mounted type shown in Figure 14, but various types exist, such as tabletop type and wall-mounted type.

[0397] It should be noted that "surveillance camera," "security camera," and "pet camera" are common terms and do not necessarily limit their use to those purposes. For example, a pet camera may be used as a surveillance camera or security camera, and vice versa. Also, the Camera 8700 is sometimes referred to as a video camera.

[0398] Furthermore, the camera 8700 can be equipped with the electronic component 8701 as the electronic component 1700 mentioned above, thereby enabling the camera 8700 to be used as an edge AI electronic device. The edge AI in the camera 8700 can be used, for example, for security purposes, to detect motion in objects displayed in images (still images and videos) captured by the camera 8700. It can also be used for disaster prevention purposes, such as detecting river flooding and tsunamis.

[0399] This embodiment can be appropriately combined with the same or other embodiments shown in this specification. For example, the configurations, structures, and methods shown in this embodiment can be appropriately combined with other configurations, structures, and methods shown in this embodiment. Also, for example, the configurations, structures, and methods shown in this embodiment can be appropriately combined with configurations, structures, and methods shown in other embodiments.

[0400] (Embodiment 6) This embodiment describes space equipment and a data center (also referred to as a Data Center: DC) that can use the semiconductor device described in the above embodiment. Space equipment and data centers are effective in achieving high performance, such as low power consumption.

[0401] [Space Equipment] A semiconductor device according to one aspect of the present invention can be suitably used in space equipment (for example, equipment having the function of processing and storing information).

[0402] A semiconductor device according to one aspect of the present invention may include an I / O transistor. This I / O transistor exhibits small fluctuations in electrical properties due to radiation exposure. In other words, it has high resistance to radiation and can therefore be suitably used in environments where radiation may be incident. For example, an I / O transistor can be suitably used in outer space.

[0403] Figure 15 shows an example of space equipment, specifically a satellite 6800. The satellite 6800 comprises a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. In Figure 15, a planet 6804 is shown as an example in outer space. Outer space refers to, for example, an altitude of 100 km or more, but as described herein, outer space includes the thermosphere, mesosphere, and stratosphere.

[0404] Furthermore, although not shown in Figure 15, a battery management system (also known as a BMS) or a battery control circuit may be provided with the secondary battery 6805. Using an I / O transistor in the above-mentioned battery management system or battery control circuit is preferable because it consumes little power and has high reliability even in outer space.

[0405] Furthermore, outer space is an environment with radiation levels more than 100 times higher than those on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0406] When sunlight shines on the solar panel 6802, the power necessary for the satellite 6800 to operate is generated. However, if, for example, the solar panel is not exposed to sunlight, or if the amount of sunlight hitting the solar panel is low, the amount of power generated will decrease. Therefore, there is a possibility that the power necessary for the satellite 6800 to operate may not be generated. To operate the satellite 6800 even under conditions of low power generation, it is advisable to equip the satellite 6800 with a secondary battery 6805. Note that solar panels are sometimes called solar cell modules.

[0407] The artificial satellite 6800 can generate signals. These signals are transmitted via the antenna 6803, and for example, a receiver installed on the ground or another artificial satellite can receive these signals. By receiving the signals transmitted by the artificial satellite 6800, the position of the receiver that has received the signals can be measured. From the above, the artificial satellite 6800 can constitute a satellite positioning system.

[0408] Moreover, the control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured by using, for example, one or more selected from a CPU, a GPU, and a memory circuit. It is preferable to use the semiconductor device which is one aspect of the present invention for the control device 6807. Compared with Si transistors, IO transistors have less variation in electrical characteristics due to radiation irradiation. That is, they have high reliability even in an environment where radiation can enter, and can be preferably used.

[0409] Also, the artificial satellite 6800 can be configured to have sensors. For example, by being configured to have a visible light sensor, the artificial satellite 6800 can have a function of detecting sunlight reflected by an object provided on the ground. Or, by being configured to have a thermal infrared sensor, the artificial satellite 6800 can have a function of detecting thermal infrared rays emitted from the earth's surface. From the above, the artificial satellite 6800 can, for example, have a function as an earth observation satellite.

[0410] In the present embodiment, an artificial satellite has been exemplified as an example of space equipment, but the present invention is not limited to this. For example, it is preferable that the semiconductor device according to one aspect of the present invention can also be used for space equipment such as spacecrafts, space capsules, and space probes.

[0411] As described above, compared with Si transistors, IO transistors have excellent effects such as the ability to achieve a wide memory bandwidth and high radiation resistance.

[0412] [Data Center] One embodiment of the present invention is suitably used in storage systems applied to data centers, for example. Data centers are required to manage data over the long term, such as ensuring the immutability of data. Managing data over the long term requires the installation of storage and servers to store vast amounts of data, securing a stable power supply to hold the data, and securing cooling equipment required for data storage, which necessitates the construction of a large building. Furthermore, it is preferable for data centers to have a function to perform calculations on data, and it is even more preferable that the speed of such calculations is fast.

[0413] By using a semiconductor device according to one aspect of the present invention in a storage system applied to a data center, it is possible to reduce the power required for calculations and improve the speed of calculations.

[0414] Furthermore, because the semiconductor device according to one aspect of the present invention has low power consumption, heat generation from the circuit can be reduced. Therefore, adverse effects on the circuit itself, peripheral circuits, and modules due to such heat generation can be reduced. In addition, by using the semiconductor device according to one aspect of the present invention, a data center that operates stably even in high-temperature environments can be realized. Therefore, the reliability of the data center can be improved.

[0415] Figure 16 shows a storage system applicable to a data center. The storage system 7000 shown in Figure 16 has multiple servers 7001sb as hosts 7001 (indicated as Host computer) and multiple storage devices 7003md as storage 7003 (indicated as Storage). The host 7001 and storage 7003 are connected via a storage area network 7004 (SAN: Storage Area Network) and a storage control circuit 7002 (indicated as Storage Controller).

[0416] Host 7001 can be a computer that accesses data stored in storage 7003. The hosts 7001 may also be connected to each other via a network.

[0417] Although storage 7003 uses flash memory to shorten data access speed, that is, the time required for data storage and output, this time is significantly longer than the time required by DRAM (Dynamic Random Access Memory), which can be used as cache memory within the storage. In storage systems, cache memory is usually provided within the storage to shorten the time required for data storage and output in order to solve the problem of the long access speed of storage 7003.

[0418] The aforementioned cache memory is used within the storage control circuit 7002 and storage 7003. Data exchanged between the host 7001 and storage 7003 is stored in the cache memory within the storage control circuit 7002 and storage 7003, and then output to the host 7001 or storage 7003.

[0419] By using I / O transistors to store the data in the aforementioned cache memory and maintaining a potential corresponding to the data, the frequency of refreshes can be reduced, thereby lowering power consumption. Furthermore, miniaturization is possible by stacking memory cell arrays.

[0420] Furthermore, by applying a semiconductor device according to one aspect of the present invention to one or more selected from the electronic components, electronic devices, large computers, space equipment, and data centers described in the above embodiments, it is expected that power consumption will be reduced. Therefore, given the expected increase in energy demand due to the increased performance or high integration of the above-mentioned components, equipment, and data centers, it is expected that using a semiconductor device according to one aspect of the present invention will reduce carbon dioxide (CO2). ２ It is also possible to reduce greenhouse gas emissions, such as those represented by [specific examples of emissions]. Furthermore, because the semiconductor device according to one aspect of the present invention consumes little power, it is also effective as a measure against global warming.

[0421] This embodiment can be appropriately combined with the same or other embodiments shown in this specification. For example, the configurations, structures, and methods shown in this embodiment can be appropriately combined with other configurations, structures, and methods shown in this embodiment. Also, for example, the configurations, structures, and methods shown in this embodiment can be appropriately combined with configurations, structures, and methods shown in other embodiments.

[0422] M1: Transistor, M2: Transistor, M3: Transistor, MP1i: Transistor, MP1o: Transistor, MP2i: Transistor, MP2o: Transistor, MP3i: Transistor, MP3o: Transistor, MP4i: Transistor, MP4o: Transistor, MN1i: Transistor, MN1o: Transistor, MN2i: Transistor, MN2o: Transistor, C1: Capacitor, C2: Capacitor, N1: Node, N2: Node, SW2: Switch, CA: Cell Array, CDVA: Arithmetic Unit, CDVA1: Arithmetic Unit, CDVA2 : arithmetic unit, CNI: constant current source, CVT: conversion circuit, CX: memory cell area, FC: circuit, IL: wiring, IM: arithmetic circuit, ITS: drive circuit, ITSa: circuit, ITW: terminal, ITX: terminal, IXL: wiring, MP: arithmetic circuit, OL: wiring, OMAL: circuit layer, OT: terminal, PHRL: circuit layer, RSWL1: wiring, RSWL2: wiring, RSWL3: wiring, TrP: transistor, TrQ: transistor, VDE: wiring, VEL: wiring, VGE: wiring, VSE: wiring, VCL1: wiring, VCL2: wiring, WCDe: circuit, WCL: wiring, WM: arithmetic cell, WSD : Drive circuit, WSL: Wiring, WXCD: Drive circuit, WXCL: Wiring, WXSD: Drive circuit, WXSL: Wiring, XCDa: Circuit, XCL: Wiring, XM: Memory cell, XSD: Drive circuit, XSL: Wiring, ZL: Wiring, 100: Transistor, 101: Substrate, 102: Element isolation layer, 111: Insulating layer, 112: Insulating layer, 113: Insulating layer, 114: Insulating layer, 115: Insulating layer, 116: Insulating layer, 131: Conductive layer, 132: Conductive layer, 133: Conductive layer, 134: Conductive layer, 136: Conductive layer, 161: Insulating layer, 171: Semiconductor region, 172a: Low resistance region, 172b: Low resistance region ,181: insulating layer, 182: insulating layer, 200: transistor, 211: insulating layer, 212: insulating layer, 213: insulating layer, 214: insulating layer, 215: insulating layer, 219: insulating layer, 231: conductive layer, 231a: conductive layer, 231b: conductive layer, 232: conductive layer, 232a: conductive layer, 232b: conductive layer, 233: conductive layer, 233a: conductive layer, 233b: conductive layer, 234: conductive layer, 234a: conductive layer, 234b: conductive layer, 235: conductive layer, 236: conductive layer, 237: conductive layer, 238: conductive layer, 251: semiconductor layer, 251a: semiconductor layer, 251b: semiconductor layer, 261: insulating layer,262: insulating layer, 263: insulating layer, 264: insulating layer, 271a: region, 271b: region, 281: insulating layer, 282: insulating layer, 283: insulating layer, 284: insulating layer, 286: insulating layer, 287: insulating layer, 300: transistor, 311: insulating layer, 312: insulating layer, 313: insulating layer, 314: insulating layer, 331: conductive layer, 332: conductive layer, 333: conductive layer, 334: conductive layer, 351: semiconductor Body layer, 361: insulating layer, 441: insulating layer, 1700: electronic component, 1700A: electronic component, 1700C: electronic component, 1701: substrate, 1710: semiconductor device, 1711: mold, 1712: lead frame, 1713: electrode pad, 1714: wire, 1715: drive circuit layer, 1716: memory layer, 1731: interposer, 1732: conductive layer, 1733: electrode, 1734: pad Cage substrate, 1735: Semiconductor equipment, 6800: Artificial satellite, 6801: Aircraft body, 6802: Solar panel, 6803: Antenna, 6804: Planet, 6805: Secondary battery, 6807: Control device, 7000: Storage system, 7001: Host, 7001sb: Server, 7002: Storage control circuit, 7003: Storage, 7003md: Memory device, 8000: Information processing system, 8100: Network, 8110: Large-scale computer, 8200: Portable information terminal, 8201: Electronic component, 8300: Wearable information terminal, 8301: Electronic component, 8400: Notebook personal computer, 8401: Electronic component, 8500: Automobile, 8501: Electronic component, 8600: Industrial robot, 8601: Electronic component, 8700: Camera, 8701: Electronic component,

Claims

It comprises a first transistor, a second transistor, a third transistor, a first capacitance element, and a second capacitance element. The first transistor has a first gate and a second gate. The first gate of the first transistor is electrically connected to either the source or the drain of the second transistor and to the first terminal of the first capacitive element. The second gate of the first transistor is electrically connected to either the source or the drain of the third transistor and to the first terminal of the second capacitance element. The first transistor has the function of flowing a current between its source and drain corresponding to the multiplication result of the first data and the second data, by writing a first potential corresponding to the first data to the first terminal of the first capacitance element and a second potential corresponding to the second data to the first terminal of the second capacitance element. Semiconductor equipment. 　 In claim 1, The second terminal of the second transistor and the second terminal of the third transistor are each electrically connected to the first wiring. Semiconductor equipment. 　 In claim 1, The gates of the second transistor and the gates of the third transistor are each electrically connected to the first wiring. Semiconductor equipment. 　 In claim 1, The second terminal of the first capacitance element and the second terminal of the second capacitance element are each electrically connected to the first wiring. Semiconductor equipment. 　 It has multiple first cells and second cells, The first cell comprises a first transistor, a second transistor, and a first capacitance element. The second cell comprises a third transistor and a second capacitance element. The first transistor has a first gate and a second gate. The first gate of the first transistor is electrically connected to either the source or the drain of the second transistor and to the first terminal of the first capacitive element. Each gate of the second transistor contained in the plurality of first cells is electrically connected to the first wiring, The second gate of each of the first transistors contained in the plurality of first cells is electrically connected to either the source or drain of the third transistor and to the first terminal of the second capacitive element. Each of the first transistors contained in the plurality of first cells has the function of flowing a current between the source and drain of the first transistor, corresponding to the multiplication result of the first data and the second data, by writing a first potential corresponding to the first data to the first terminal of the first capacitance element and a second potential corresponding to the second data to the first terminal of the second capacitance element. Semiconductor equipment. 　 In claim 5, The gate of the third transistor is electrically connected to the first wiring. Semiconductor equipment. 　 In claim 5, Each of the second terminals of the first capacitance elements contained in the plurality of first cells, and each of the second terminals of the second capacitance elements contained in the second cell, are electrically connected to the second wiring. Semiconductor equipment. 　 In any one of claims 1 to 7, Each of the first to third transistors has an indium-containing oxide in its channel-forming region. Each of the first to third transistors has an on-current ratio of 1.0 × 10⁻¹⁰ １７ That's all. Semiconductor equipment.

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