Semiconductor device and method for manufacturing semiconductor device

Abstract

Provided is a semiconductor device (1) with which it is possible to achieve high bonding strength at a low bonding temperature. In the semiconductor device (1), the glass transition temperature of an organic insulating material is 140-180°C, a metal material includes solder, and the formation area of the organic insulating material in contact with the metal material is the same as the outer shape of a semiconductor chip that is the smaller of stacked semiconductor chips (5) or is more to the inside than the outer shape.

Description

Semiconductor device and method for manufacturing a semiconductor device

[0001] The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device.

[0002] Embedded microbump bonding is known in which a thermosetting organic material is used for an insulating material, a metal is used for an electrode material, and the insulating material and the electrode material are connected together. For example, Patent Document 1 discloses a technique for embedded microbump bonding that uses a polyimide precursor having an ester moiety as the material of an insulating film for the purpose of reducing the bonding temperature while maintaining the heat resistance of the insulating film.

[0003] Japanese Patent Application Laid-Open No. 2023-151489

[0004] However, in the prior art, in order to increase the bonding strength between organic insulating materials, it is necessary to set the bonding temperature to a temperature exceeding, for example, 200°C. When the bonding temperature is high, the bonding process requires time and cost, and the performance of the semiconductor device may deteriorate.

[0005] Therefore, an object of the present invention is to provide a semiconductor device and a method for manufacturing a semiconductor device that can achieve strong bonding strength at a low bonding temperature.

[0006] The semiconductor device of the present invention is a semiconductor device in which two or more semiconductor chips are laminated and bonded with a metal material for electrodes and a thermosetting organic insulating material, wherein the glass transition temperature of the organic insulating material is 140°C or higher and 180°C or lower, the metal material contains solder, includes a resin bonding portion formed of the organic insulating material in contact with the metal material, and the formation area of the resin bonding portion is the same as or inside the outer shape of the semiconductor chip having the smaller size among the laminated semiconductor chips.

[0007] Furthermore, the semiconductor device of the present invention is a semiconductor device in which a semiconductor chip and an interposer are laminated and bonded with a metal material for electrodes and a thermosetting organic insulating material, wherein the glass transition temperature of the organic insulating material is 140°C or more and 180°C or less, the metal material includes solder and includes a resin joint portion that is in contact with the metal material and formed of the organic insulating material, and the formation area of ​​the resin joint portion is the same as or inside the outer shape of the smaller of the laminated semiconductor chip and the interposer.

[0008] Furthermore, the present invention relates to a method for manufacturing a semiconductor device, comprising laminating and bonding two semiconductor chips with a metal material for electrodes and a thermosetting organic insulating material, and including: a resin-bonded portion forming step of forming resin-bonded portions made of the organic insulating material at predetermined intervals on the main surface of each semiconductor chip; a metal-bonded portion forming step of forming metal-bonded portions made of the metal material between adjacent resin-bonded portions; an alignment step of aligning the two semiconductor chips so that at least one of the positions of the corresponding resin-bonded portions of each semiconductor chip and the corresponding metal-bonded portions of each semiconductor chip coincides; a temporary bonding step of bonding at least the corresponding resin-bonded portions of each semiconductor chip; and a final bonding step of bonding at least the corresponding metal-bonded portions of each semiconductor chip.

[0009] According to the present invention, it is possible to provide a semiconductor device and a method for manufacturing a semiconductor device that can achieve high bonding strength at a low bonding temperature.

[0010] Figure 1A is a cross-sectional view of a semiconductor device according to an embodiment of the present invention. Figure 1B is a cross-sectional view of a semiconductor device with a different configuration according to an embodiment of the present invention. Figure 2 is a cross-sectional view of a semiconductor chip according to this embodiment. Figure 3A is a cross-sectional view of a semiconductor chip body, etc., for illustrating the manufacturing method of the semiconductor device according to this embodiment. Figure 3B is a cross-sectional view of a semiconductor chip body, etc., for illustrating the manufacturing method of the semiconductor device according to this embodiment. Figure 3C is a cross-sectional view of a semiconductor chip body, etc., for illustrating the manufacturing method of the semiconductor device according to this embodiment. Figure 3D is a cross-sectional view of a semiconductor chip body, etc., for illustrating the manufacturing method of the semiconductor device according to this embodiment. Figure 3E is a cross-sectional view of a semiconductor chip body, etc., for illustrating the manufacturing method of the semiconductor device according to this embodiment. Figure 3F is a cross-sectional view of a semiconductor chip body, etc., for illustrating the manufacturing method of the semiconductor device according to this embodiment. Figure 3G is a cross-sectional view of a semiconductor chip body, etc., for illustrating the manufacturing method of the semiconductor device according to this embodiment. Figure 3H is a cross-sectional view of a semiconductor chip body, etc., for illustrating the manufacturing method of the semiconductor device according to this embodiment. Figure 3I is a cross-sectional view of a semiconductor chip body, etc., for illustrating the manufacturing method of the semiconductor device according to this embodiment. Figure 3J is a cross-sectional view of a semiconductor chip body, etc., for illustrating the manufacturing method of the semiconductor device according to this embodiment. Figure 4A is a cross-sectional view of a semiconductor chip body, etc., for illustrating the alignment process in the manufacturing method of the semiconductor device according to this embodiment. Figure 4B is a cross-sectional view of a semiconductor chip body, etc., for illustrating the temporary crimping process in the manufacturing method of the semiconductor device according to this embodiment. Figure 4C is a cross-sectional view of a semiconductor chip body, etc., for illustrating the crimping process in the semiconductor device manufacturing method of this embodiment. Figure 5 is a flowchart of the semiconductor device manufacturing method of this embodiment. Figure 6 is a table showing the conditions and characteristics evaluation results of the samples of the examples and comparative examples. Figure 7A is a diagram showing a modified example of the semiconductor device manufacturing method of this embodiment. Figure 7B is a diagram showing a modified example of the semiconductor device manufacturing method of this embodiment.

[0011] (Overview of Semiconductor Device) A semiconductor device 1 according to an embodiment of the present invention will be described with reference to the drawings. Figure 1A is a cross-sectional view of the semiconductor device 1 according to an embodiment of the present invention. As shown in Figure 1A, the semiconductor device 1 has a configuration in which two semiconductor chips 5 are stacked and bonded together. One of the semiconductor chips 5 is called the first semiconductor chip 5A. The other semiconductor chip 5 is called the second semiconductor chip 5B. The semiconductor chips 5 are formed on a substrate such as a silicon wafer.

[0012] (Semiconductor Chip) The semiconductor chip 5 will be described with reference to Figure 2. Figure 2 is a cross-sectional view of the semiconductor chip 5.

[0013] (Semiconductor Chip Body) The semiconductor chip 5 includes the semiconductor chip body 10 and the bonding layer 30. The semiconductor chip body 10 is the portion on a silicon substrate or the like where semiconductor elements are formed. The bonding layer 30 is the portion that joins the semiconductor chips 5 to each other when laminating and bonding two silicon substrates.

[0014] (Crimping Layer) The crimping layer 30 is formed on one main surface 12 of the semiconductor chip 5. The crimping layer 30 includes a metal crimping portion 34 and a resin crimping portion 36. The metal crimping portion 34 is a portion formed of a metal material. The metal material can be a material that constitutes an electrode. The resin crimping portion 36 is a portion formed of an organic insulating material. The organic insulating material can be a thermosetting type organic insulating material. The metal crimping portion 34 and the resin crimping portion 36 are formed continuously on the main surface 12 at predetermined intervals in a cross-sectional view on a plane perpendicular to the main surface 12 shown in Figure 2.

[0015] The following mainly describes the laminated layer 30. In the description, each part is denoted as follows. The first semiconductor chip 5A and the second semiconductor chip 5B shown in Figure 1A have similar configurations. Therefore, for each part related to the semiconductor chip 5, the name of the first semiconductor chip 5A is given the prefix "first" and the denotation "A". Similarly, the name of the second semiconductor chip 5B is given the prefix "second" and the denotation "B".

[0016] (Joint) As shown in Figure 1A, the stack bonding of the first semiconductor chip 5A and the second semiconductor chip 5B is performed by bonding the first semiconductor chip body 10A and the second semiconductor chip body 10B via a joint 20.

[0017] The joint 20 is formed by the pressing of the first layer to be pressed 30A and the second layer to be pressed 30B together.

[0018] The joint portion 20 includes a metal joint portion 21 and a resin joint portion 22. The metal joint portion 21 is formed by the crimping of a first metal crimped portion 34A and a second metal crimped portion 34B. The resin joint portion 22 is formed by the crimping of a first resin crimped portion 36A and a second resin crimped portion 36B.

[0019] (Other Configurations of the Semiconductor Device) Referring to Figure 1B, other configurations of the semiconductor device 1 according to an embodiment of the present invention will be described. Figure 1B is a diagram showing a cross-section of the semiconductor device 1 according to another configuration of an embodiment of the present invention. Figure 1A shows an example of the configuration of the semiconductor device 1 in which a first semiconductor chip 5A and a second semiconductor chip 5B are stacked and bonded. Various modifications of the configuration of the semiconductor device 1 are possible. For example, as shown in Figure 1B, one of the two semiconductor chips 5 can be an interposer 15. In the example shown in Figure 1B, the first semiconductor chip 5A is replaced with an interposer 15 in the semiconductor device 1 shown in Figure 1A. In other words, the semiconductor device 1 shown in Figure 1B is configured by stacking and bonding an interposer 15 and a second semiconductor chip 5B.

[0020] The interposer 15 includes an interposer body 16 and a first crimpable layer 30A. The interposer body 16 is a portion of a silicon substrate or the like on which vias such as through-silicon vias (TSVs), electrodes, and wiring layers are formed. These are not shown in Figure 1B. The first crimpable layer 30A included in the interposer 15 can be the same as the first crimpable layer 30A included in the first semiconductor chip 5A. In the semiconductor device 1 shown in Figure 1B, the first semiconductor chip body 10A is replaced by the interposer body 16. When the first semiconductor chip body 10A is replaced by the interposer body 16, the joint portion 20 may be provided on a part of the main surface 161 of the interposer body 16. This is because, as shown in Figure 1B, the size of the interposer 15 may be larger than that of the second semiconductor chip 5B.

[0021] (Method of Manufacturing a Semiconductor Device) The method of manufacturing the semiconductor device 1 will be described below in order. As mentioned above, the semiconductor device 1 has a configuration in which a first semiconductor chip 5A and a second semiconductor chip 5B are stacked and bonded together. The first semiconductor chip 5A and the second semiconductor chip 5B are processed into a wafer with microbumps attached, that is, a microbump-formed wafer (also called an embedded microbump wafer), before being stacked and bonded together. The microbump-formed wafer has a configuration in which a bonding layer 30 is formed on the semiconductor chip body 10. The microbump-formed wafer is shown in Figure 3J. The microbump-formed wafer is also called an embedded microbump wafer.

[0022] First, the method for forming the bonding layer 30 on the semiconductor chip body 10 will be explained. After that, the method for bonding semiconductor chips together will be explained.

[0023] Before stacking and bonding, the microbump-forming wafer of the first semiconductor chip 5A and the microbump-forming wafer of the second semiconductor chip 5B have the same configuration. Hereinafter, the method for manufacturing the semiconductor device 1 will be described without distinguishing between the first semiconductor chip 5A and the second semiconductor chip 5B.

[0024] Figures 3A to 3J are cross-sectional views of the semiconductor chip body 10 and other components used to illustrate the manufacturing method of the semiconductor device 1. Figures 3A to 3J are arranged in order of the manufacturing process.

[0025] Figure 5 is a flowchart showing the manufacturing method of the semiconductor device 1 according to this embodiment. In Figure 5 and the following description, S1 indicates step 1. The same applies to S2 and subsequent steps.

[0026] (Process for forming the resin-bonded portion) The resin-bonded portion formation process S1 will be explained based on Figures 3A to 3E. S1 is the process of forming the resin-bonded portion 36 on the semiconductor chip body 10.

[0027] (Organic insulating layer) As shown in Figure 3A, a polyimide layer 40 is formed on one main surface 12 of the semiconductor chip body 10. The organic insulating layer 40 is made of polyimide or polybenzoxazole. Polyimide is an example of a thermosetting organic insulating material. As the organic insulating material, a thermosetting type that does not have photosensitive function can be preferably used. To impart photosensitive function, it is necessary to include a photosensitive agent, and the photosensitive agent may cause a decrease in electrical and bonding reliability. An example of the thickness of the cured polyimide layer 40 is 8 μm.

[0028] The thermosetting organic insulating material used has a glass transition temperature of 140°C to 180°C. This allows for a lower temperature for the temporary crimping process, which will be explained later. It also helps to suppress a decrease in the reliability of the semiconductor device 1.

[0029] The glass transition temperature of the organic insulating material is more preferably 160°C or lower. This allows for a lower temperature during the initial crimping process.

[0030] (Upward direction) The direction perpendicular to one main surface 12 of the semiconductor chip 5 is defined as the upward direction 500. In the following description, up and down are based on the upward direction 500.

[0031] (Photoresist layer) Next, as shown in Figure 3B, a photoresist layer 50 is formed on the organic insulating material layer 40.

[0032] (Pores in the photoresist layer) Next, as shown in Figure 3C, photoresist layer pores 52 are formed in the photoresist layer 50. The photoresist layer pores 52 are holes that penetrate the photoresist layer 50. The photoresist layer pores 52 can be formed, for example, using photolithography techniques involving exposure and development. An example of the shape of the photoresist layer pores 52 is cylindrical.

[0033] (Dry Etching) Next, as shown in Figure 3D, dry etching is performed using the photoresist layer 50 as a mask. An example of an etching gas used during dry etching is an oxygen-containing gas. By dry etching the organic insulating material layer 40, organic insulating material layer pores 42 are formed in the organic insulating material layer 40. The organic insulating material layer pores 42 are holes that penetrate the organic insulating material layer 40. An example of the shape of the organic insulating material layer pores 42 is a cylindrical shape.

[0034] (Resist Removal) Next, as shown in Figure 3E, the photoresist layer 50 remaining on the organic insulating material layer 40 is removed. The photoresist layer 50 can be removed, for example, by cleaning with acetone. As a result, a resin-bonded portion 36 with the organic insulating material layer 40 processed is formed on the semiconductor chip body 10.

[0035] (Metal-bonded portion formation process) The metal-bonded portion formation process S2 will be explained based on Figures 3F to 3I. S2 is the process of forming a metal-bonded portion 34 on the semiconductor chip body 10.

[0036] (Seed layer) As shown in Figure 3F, a seed layer 60 is formed on the surface of the organic insulating material layer 40. The seed layer 60 can consist of two layers, for example, a titanium seed layer and a copper seed layer, starting from the organic insulating material layer 40. The titanium seed layer and the copper seed layer can be formed, for example, by sputtering. An example of the thickness of the titanium seed layer is 50 nm. An example of the thickness of the copper seed layer is 150 nm.

[0037] (Copper layer) Next, as shown in Figure 3G, a copper layer 70 is formed in the pores 42 of the organic insulating material layer. The copper layer 70 is also called a copper post. The copper layer 70 can be formed by electrolytic copper plating. During electrolytic copper plating, the seed layer 60 is used as the electrode for electrolytic plating. An example of the thickness D70 of the copper layer 70 is 3 μm.

[0038] (Solder layer) Next, as shown in Figure 3H, a solder layer 80 is formed on the copper layer 70. The material of the solder layer 80 is not particularly limited, and alloys of tin and bismuth can be used, but it is preferable that the main component is tin and that the layer contains silver. A silver content of about 2 to 3% is preferable from the viewpoint of reliability and metallic bonding. The solder layer 80 can be formed by electroplating. An example of the thickness D80 of the solder layer 80 is 3 μm. A layer containing nickel or cobalt may be formed between the copper layer and the solder layer to suppress the mutual diffusion of copper and solder material.

[0039] In this way, a copper layer 70 as a copper post and a solder layer 80 as a solder layer are formed in order within the holes 42 of the organic insulating material layer. The metal layer formed within the holes 42 of the organic insulating material layer is called the metal layer 92. In the example shown in Figure 3H, the metal layer 92 includes the seed layer 60, the copper layer 70, and the solder layer 80. The metal layer 92 is formed not only within the holes 42 of the organic insulating material layer but also on the surface of the organic insulating material layer 40.

[0040] (Removal of copper and solder layers) Next, as shown in Figure 3I, the metal layer 92 formed on the organic insulating material layer 40, i.e., the seed layer 60, the copper layer 70, and the solder layer 80, are removed by grinding. This grinding can be done, for example, using a fry cutter. As a result, a metal crimped portion 34 with the copper layer 70 and solder layer 80 processed is formed on the semiconductor chip body 10.

[0041] (Surface polishing process) The surface polishing process S3 will be explained based on Figure 3J. S3 is a process of polishing the surfaces of the organic insulating material layer 40 and the metal layer 92.

[0042] (Chemical Mechanical Polishing) As shown in FIG. 3J, the organic insulating material layer 40 and the metal layer 92 are polished by the CMP (Chemical Mechanical Polishing) method. In the example shown in FIG. 3J, for the metal layer 92, particularly the solder layer 80 is polished. Let the thickness of the organic insulating material layer 40 after polishing be thickness D40. Let the sum of the thickness of the copper layer 70 and the thickness of the solder layer 80 after polishing be the thickness D92 of the metal layer 92. By polishing, the thickness D40 of the organic insulating material layer 40 and the thickness D92 of the metal layer 92 can be made the same.

[0043] (Microbump Forming Wafer) In the hole of the organic insulating material layer hole 42, the portion where the solder layer 80 is formed on the surface of the copper layer 70 is called the bump 90. The bump 90 is the metal joint 21 formed in the hole of the organic insulating material layer hole 42.

[0044] By the processing up to this point, a microbump forming wafer 3 in which the bump 90 is embedded in the hole of the organic insulating material layer hole 42 with the surface of the organic insulating material layer 40 exposed can be obtained. The microbump forming wafer 3 is also called an embedded microbump wafer.

[0045] (Semiconductor Chip) The microbump forming wafer 3 is diced to obtain the semiconductor chip 5. Dicing can be performed, for example. Examples of the size of the semiconductor chip 5 are 7 mm × 7 mm and 10 mm × 10 mm, etc. However, this size is an example. The size of the semiconductor chip 5 is not limited to these.

[0046] (Laminating and Bonding by Pressure Bonding) Referring to FIGS. 4A to 4C, the lamination bonding of the semiconductor chips 5 will be described. Two semiconductor chips 5 are laminated and bonded by being pressure bonded. That is, two semiconductor chips 5 are bonded by pressure bonding.

[0047] The sizes of the two semiconductor chips 5 to be laminated and bonded may be the same or different. For example, a 7 mm × 7 mm semiconductor chip 5 and a 10 mm × 10 mm semiconductor chip 5 may be laminated and bonded. Or, two 7 mm × 7 mm semiconductor chips 5, or two 10 mm × 10 mm semiconductor chips 5 may be laminated and bonded.

[0048] Referring to FIGS. 4A to 4C, a method of bonding semiconductor chips 5 will be described. The bonding process includes, in order, an alignment step S4, a temporary bonding step S5, and a main bonding step S6.

[0049] (Alignment Step) First, the alignment step S4 will be described with reference to FIG. 4A. FIG. 4A is a cross-sectional view of a semiconductor chip body 10 or the like for explaining the alignment step.

[0050] (Plane Direction and Bonding Direction) As shown in FIG. 4A, the direction parallel to the main surface 12 is called the plane direction 510. The direction perpendicular to the plane direction 510 is called the bonding direction 520.

[0051] In the alignment step S4, the first semiconductor chip 5A and the second semiconductor chip 5B are aligned in the plane direction 510. First, the first semiconductor chip body 10A and the second semiconductor chip body 10B are arranged such that their main surfaces 12 face each other.

[0052] Next, the relative positions of the first semiconductor chip body 10A and the second semiconductor chip body 10B are adjusted so that at least one of the positions of the corresponding first metal bonding portion 34A and the second metal bonding portion 34B in the plane direction 510 and the positions of the corresponding first resin bonding portion 36A and the second resin bonding portion 36B coincide.

[0053] As shown in FIG. 4A, in the alignment step S4, the first semiconductor chip 5A and the second semiconductor chip 5B are not in contact in the bonding direction 520.

[0054] (Temporary Bonding Step) After the alignment step, the process proceeds to the temporary bonding step S5. The temporary bonding step S5 will be described with reference to FIG. 4B. In the temporary bonding step S5, the first resin bonding portion 36A and the second resin bonding portion 36B are thermally bonded.

[0055] As shown in Figure 4B, the first semiconductor chip 5A and the second semiconductor chip 5B are placed on the thermal compression bonder 300 after alignment and are pressed together in the bonding direction 520 by the thermal compression bonder 300. An example of the pressure applied during the initial bonding is 300 N. An example of the temperature during the initial bonding is 140 °C. In the initial bonding process S5, the first resin-bonded portion 36A and the second resin-bonded portion 36B are heat-bonded. This forms the resin joint portion 22 in the joint portion 20.

[0056] In the temporary crimping process, the first metal crimping portion 34A and the second metal crimping portion 34B are not crimped together. Therefore, the metal joint portion 21 is not formed in the temporary crimping process.

[0057] Furthermore, the temporary crimping temperature mentioned above is an example. The temporary crimping temperature can be, for example, between 100°C and 210°C.

[0058] (Main Crimping Process) After the preliminary crimping process S5, the process proceeds to the main crimping process S6. The main crimping process S6 will be explained with reference to Figure 4C. In the main crimping process S6, the first metal crimping portion 34A and the second metal crimping portion 34B are heat-pressed together.

[0059] As shown in Figure 4C, the first semiconductor chip 5A and the second semiconductor chip 5B, having completed temporary bonding, are placed on the thermal compression bonder 310 and bonded in the bonding direction 520 by the thermal compression bonder 310. The thermal compression bonder used in this bonding step S6 may be the same as or different from the thermal compression bonder used in the temporary bonding step S5.

[0060] As described above, the resin joint 22 is formed in the temporary bonding process S5. Therefore, the first semiconductor chip 5A and the second semiconductor chip 5B are, so to speak, temporarily fixed together. For this reason, even if a different thermal compression bonder is used in the main bonding process S6 than the one used in the temporary bonding process S5, the first semiconductor chip 5A and the second semiconductor chip 5B can be moved to the different thermal compression bonder without causing problems such as misalignment.

[0061] The temperature for this crimping can be different from the temperature for the initial crimping, specifically higher than the initial crimping temperature. For example, the temperature for this crimping can be above 210°C, specifically 250°C. An example of the pressure applied during this crimping is 300 N.

[0062] In this crimping process, the first metal crimping portion 34A and the second metal crimping portion 34B are crimped together. As a result, a metal joint portion 21 is formed. This forms a joint portion 20 including the metal joint portion 21 and the resin joint portion 22.

[0063] With the above steps completed, the semiconductor device 1 is formed, and the flowchart for the manufacturing method of the semiconductor device 1 in this embodiment is complete.

[0064] (Examples and Comparative Examples) Examples and comparative examples will be described with reference to Figure 6. Figure 6 is a table showing the conditions and evaluation results of the samples of the examples and comparative examples.

[0065] The following describes the common aspects of the samples evaluated in the examples and comparative examples. (Samples) The semiconductor chip obtained by cutting the microbump-formed wafer 3, mentioned in the description of the manufacturing method above, into 7 mm x 7 mm pieces is called semiconductor chip B. Also, the semiconductor chip obtained by cutting the microbump-formed wafer 3 into 10 mm x 10 mm pieces is called semiconductor chip C.

[0066] Semiconductor chips B and C were bonded together using a thermal compression bonder, with their respective bumps facing each other.

[0067] The initial pressure applied to semiconductor chip B and semiconductor chip C was 300 N, and the temperature was as shown in Figure 6. The final pressure applied to semiconductor chip B and semiconductor chip C was 300 N, and the temperature was 250°C.

[0068] The evaluation method for the samples will be explained. (Tg of the organic insulating layer) The Tg (glass transition temperature) of the organic insulating layer was determined by the following method. The elastic modulus was measured by vibration using a nanoindenter while changing the temperature of the vertical cross-section of the central part of the crimped semiconductor chip B and semiconductor chip C. A temperature dependence curve of the measured elastic modulus was created, and the differential curve of the temperature dependence curve was calculated. The peak value was determined as the glass transition temperature. The vertical cross-sections of the central part of semiconductor chip B and semiconductor chip C were prepared by the cross-sectional polishing method.

[0069] (Ra after CMP) After polishing by CMP, the Ra (arithmetic mean surface roughness) of the organic insulating material layer was measured. Ra was measured using an AFM (atomic force microscope).

[0070] (Semiconductor chip adhesion strength after temporary bonding) The semiconductor chip adhesion strength after temporary bonding was evaluated by die shear test after temporary bonding of semiconductor chip B and semiconductor chip C.

[0071] (Solder overflow) Solder overflow was evaluated by observing the cross-section of the semiconductor chip joined after the final crimping using a scanning electron microscope. This cross-sectional observation allowed us to check whether or not solder had overflowed at the bonding interface between the organic insulating material layers. If solder overflowed, it was judged as insufficient temporary crimping. This is because solder overflow is caused by insufficient temporary crimping.

[0072] (Bonding reliability of organic insulating layer) The bonding reliability of the organic insulating layer was evaluated as follows. A polyimide layer was formed on a silicon wafer as a cured organic insulating layer with a thickness of 8 μm. It was diced into pieces of 7 mm × 7 mm and 10 mm × 10 mm. The semiconductor chips diced into 7 mm × 7 mm pieces are called semiconductor chip G. The semiconductor chips diced into 10 mm × 10 mm pieces are called semiconductor chip H.

[0073] Semiconductor chips G and H were bonded together by stacking them so that their polyimide layers faced each other, and performing preliminary and final bonding using a thermal compression bonder. During bonding, the relative positions of semiconductor chips G and H were adjusted so that the entire surface of the polyimide layer 40 on semiconductor chip G was in close contact with the polyimide layer 40 on semiconductor chip H.

[0074] The conditions for bonding semiconductor chip G and semiconductor chip H were the same as those for bonding semiconductor chip B and semiconductor chip C, as described earlier. Specifically, the pressure applied for the preliminary bonding of semiconductor chip G and semiconductor chip H was 300 N, and the temperature was as shown in Figure 6. Furthermore, the pressure applied for the final bonding of semiconductor chip G and semiconductor chip H was 300 N, and the temperature was 250°C.

[0075] A die-shear test was performed on the bonded semiconductor chip at a temperature of 125°C. Samples that delaminated at a pressure of 20N or less were deemed unacceptable. On the other hand, samples that did not delaminate even at pressures exceeding 20N were deemed acceptable.

[0076] (Condition of metal bonding) The condition of the metal bonding was evaluated in the same way as the solder overflow described above, as follows: The metal bonding interface between the bumps of semiconductor chip B and semiconductor chip C was observed by cross-sectional observation using a scanning electron microscope.

[0077] Samples in which areas where metal bonding was not achieved, even partially, were observed at the metal bonding interface were classified as having a "NG" (not good) metal bonding state. Samples in which metal bonding was achieved across the entire metal bonding interface were classified as having an "OK" (good) metal bonding state.

[0078] ((111)-oriented nanotwin) The sample of Example 10 differs from the sample of Example 1 in the thickness of the polyimide layer 40 and the structure of the copper layer 70. The thickness of the cured polyimide layer 40 is 8 μm in the other samples, while in Example 10 it is 5 μm.

[0079] Furthermore, in the sample of Example 10, (111)-oriented nanotwin structures were formed within the copper layer 70 during electroplating. In addition, in the sample of Example 10, a solder layer 80, which is a tin layer containing silver, was not formed. The sample of Example 10 was the same as that of Example 1, except for the above.

[0080] (Comparative Examples 1 and 2) In Comparative Examples 1 and 2, the bonding reliability of the polyimide was poor. This is because the Tg of the polyimide film was low, at 120°C and 130°C. In Comparative Examples 1 and 2, the bonding reliability decreased not only due to heating during manufacturing but also during actual use.

[0081] (Comparative Examples 3 and 4) In Comparative Examples 3 and 4, the metal bonding was unsatisfactory. This was because the Tg of the polyimide film was high, at 190°C and 200°C, making it difficult for stress relaxation to occur at the resin bonding site, resulting in unsatisfactory metal bonding.

[0082] (Comparative Examples 5 and 6) In Comparative Examples 5 and 6, solder overflow was observed. This is thought to be because, despite the high Tg of the polyimide layers (190°C and 200°C), the pre-bonding temperature was low (150°C), resulting in poor adhesion between the polyimide films. This created gaps at the interface between the polyimide films, and solder overflowed into these gaps during final bonding. Similarly, the poor bonding reliability of the polyimide is also thought to be due to the low adhesion between the polyimide films.

[0083] In all of the examples, no defects were found in terms of solder overflow, polyimide bonding reliability, or metal bonding condition.

[0084] The semiconductor device and method for manufacturing the semiconductor device described above are examples of the present invention. A more detailed explanation of the semiconductor device and method for manufacturing the semiconductor device, as well as examples of modifications, will be provided below. The following explanation will use the case of joining semiconductor chips together as an example. However, the following explanation also applies to cases where a semiconductor chip is joined to an interposer or other substrate.

[0085] (Preliminary crimping and final crimping) As mentioned above, preliminary crimping and final crimping may be performed consecutively in a single device, or in separate devices. In the semiconductor device and method for manufacturing the semiconductor device according to the embodiment of the present invention, the semiconductor chip after preliminary crimping is less prone to misalignment. Therefore, it is easy to move the semiconductor chip to another device after preliminary crimping.

[0086] Preliminary and final crimping are relatively time-consuming processes. Performing these processes using different equipment can improve the productivity of semiconductor equipment.

[0087] Furthermore, if temporary and final crimping are performed using different devices, multiple semiconductor chips may be temporarily crimped onto a single semiconductor chip, and then the entire set of semiconductor chips may be crimped together using a separate device. This can further improve the productivity of semiconductor devices.

[0088] (Alignment) The alignment process before temporary bonding is explained below. Alignment can be performed while the two semiconductor chips are held in the bonding head of the thermal compression bonder. Alignment is performed by recognizing the alignment marks that have been pre-applied to both semiconductor chips. Through alignment, the bumps on the electronic semiconductor chips to be bonded are aligned.

[0089] (Temporary Crimping) After alignment, the semiconductor chips are temporarily crimped together. When performing temporary crimping, the temperature T1 of the crimping area should be below the melting point of the metal material contained in the bump.

[0090] (Crimping section) The crimping section refers to the part where the corresponding resin bonding sections of each semiconductor chip are pressed together. Specifically, the crimping section refers to the part where the first resin-bonded section 36A and the second resin-bonded section 36B are pressed together.

[0091] The smaller the difference between the temperature T1 and room temperature, the easier it is to achieve high positional accuracy during temporary crimping. In other words, it is possible to reduce positional deviations that occur during temporary crimping.

[0092] (When temporary and permanent bonding are performed consecutively in a single device) When temporary and permanent bonding are performed consecutively in a single device, after temporary bonding, the head temperature of the thermal compression bonder is increased while the semiconductor chip is still held in place. Then, metal bonding is performed by setting the temperature T2 of the contact area between the bumps on both semiconductor chips to the temperature at which atomic diffusion occurs between the metals of the two bumps. Temperature T2 can be, for example, the temperature at which the metal material contained in the bumps melts.

[0093] (Contact area) Here, the contact area refers to the part where the corresponding metal bonding areas of each semiconductor chip are pressed together. Specifically, the contact area refers to the part where the first metal crimped portion 34A and the second metal crimped portion 34B are pressed together.

[0094] (When temporary bonding and final bonding are performed in separate devices) When temporary bonding and final bonding are performed in separate devices, the temporarily bonded semiconductor chip is heated and pressurized by a bonding head in a final bonding device separate from the temporary bonding device to perform final bonding. Even when final bonding is performed in a separate device from temporary bonding, the temperature T2 at the contact area of ​​the bumps on both semiconductor chips must be such that atomic diffusion between the metals of both bumps occurs.

[0095] (In the case of solder) When solder material is used at the tip of the bump, a metal joint can be formed in a short time by setting the temperature T2 to be above the melting point of the solder material. In the microbump-formed wafer 3 illustrated in Figure 3J, the bump 90 in the pore 42 of the polyimide layer contains two layers: a copper layer 70 and a solder layer 80. The solder layer 80, which is the solder material, is located on the front side of the bump 90, that is, at the tip of the bump 90.

[0096] In this configuration, by setting the temperature T2 to be above the melting point of the solder layer 80, an efficient and reliable connection with the mating bump can be achieved.

[0097] The material of the bumps 90 within the polyimide layer pores 42 is not limited to the example shown in Figure 3J. For example, materials other than tin and silver can be used as soldering material. Also, the bumps 90 can be formed using only one type of metal material, such as copper only or soldering material only.

[0098] For example, when forming the bump 90 using only copper, electroplating can be performed so that (111) oriented nanotwin forms when the copper is formed in the pores 42 of the polyimide layer.

[0099] Alternatively, when forming the bump 90 using only solder material, it is preferable to form a barrier layer against the solder material on the inner wall of the polyimide layer pore 42. By forming a barrier layer, it is possible to suppress the diffusion of the solder material into the interior of the semiconductor chip body 10. An example of a barrier layer is a nickel layer.

[0100] In Figure 4C, length D25 indicates the length of the metal joint 21 in the planar direction 510 in the cross-section of the semiconductor device 1. In Figure 4C, length D26 indicates the length of the metal joint 21 in the crimping direction 520 in the cross-section of the semiconductor device 1.

[0101] As bumps become smaller, their length D25 tends to decrease. On the other hand, in order to ensure a reliable connection with the mating bump, it is preferable that the volume of metal material contained in the bump 90 be above a certain value.

[0102] Therefore, in the semiconductor device 1 of this embodiment, even if the length D25 is reduced, by keeping D26 at 3 μm or more, it becomes easier to ensure a reliable connection with the mating bump while miniaturizing the bump 90.

[0103] In Figure 4C, length D27 indicates the distance between the centers of adjacent metal joints 21. In the semiconductor device 1 of this embodiment, length D27 can be 20 micrometers or less. Preferably, length D27 can be 10 micrometers or less, and more preferably, length D27 can be 5 micrometers or less. This is because the semiconductor device 1 of this embodiment can suppress the solder overflow described earlier. By setting length D27 within the above range, it becomes possible to increase the density of connections.

[0104] (Substrate, etc.) The semiconductor chips and interposers used in the semiconductor device 1 only need to have embedded microbumps formed in predetermined positions, and these may be formed on silicon or on a different material. Furthermore, the size of the semiconductor chips and interposers, as well as the motherboard before they are cut out, is not particularly limited.

[0105] (Through-silicon vias) When semiconductor chips and interposers are formed on a silicon substrate, using a silicon substrate with through-silicon vias (TSVs) formed on it enables three-dimensional stacking of semiconductor chips. As a result, it becomes easier to achieve high-speed and high-density connectivity.

[0106] (Number of Layers) The above describes an example of stacking and bonding two semiconductor chips. However, the number of semiconductor chips stacked in the semiconductor device of this embodiment is not limited to two. For example, three semiconductor chips may be stacked and bonded in order to form three layers. Also, for example, two semiconductor chips may be stacked and bonded at different positions on a single interposer.

[0107] (Organic insulating material) The organic insulating material is not limited to the polyimide mentioned above. The organic insulating material can also be, for example, polybenzoxazole.

[0108] (Surface polishing process and temporary crimping process) As explained with reference to Figure 3J, the manufacturing method of the semiconductor device 1 of this embodiment includes a surface polishing process. In the surface polishing process, the organic insulating material layer 40 and the metal layer 92 are polished by chemical mechanical polishing (CMP) or the like. For example, after chemical mechanical polishing, the position 500 upward on the surface of the organic insulating material layer 40 and the position 500 upward on the surface of the metal layer 92 do not need to coincide. In other words, the surface of the crimped layer 30 does not need to be flat.

[0109] The organic insulating material forming the resin joint 22, such as the organic insulating layer 40, and the metal material forming the metal joint 21, such as the metal layer 92, have different coefficients of linear expansion. Generally, organic insulating materials have a higher coefficient of linear expansion than metal materials. Therefore, heating during the temporary crimping process causes the resin joint 22 to expand more than the metal joint 21.

[0110] Therefore, as shown in Figure 3J, for example, even if the surface of the microbump-forming wafer 3 is smooth, that is, the height of the resin bonding portion 22 (first resin-bonded portion 36A, second resin-bonded portion 36B) and the metal bonding portion 21 (first metal-bonded portion 34A, second metal-bonded portion 34B) is the same, as shown in Figure 4B, the first resin-bonded portion 36A and the second resin-bonded portion 36B can be bonded in the temporary bonding process without bonding the first metal-bonded portion 34A and the second metal-bonded portion 34B.

[0111] This prevents the metal material forming the metal-bonded portion 34 from protruding into the resin-bonded portion 36. This is because, in the preliminary bonding process, the joining of the first resin-bonded portion 36A and the second resin-bonded portion 36B is completed. Therefore, when the metal material melts in the main bonding process, no gap is formed between the first resin-bonded portion 36A and the second resin-bonded portion 36B.

[0112] As described above, the surface of the crimped layer 30 after the surface polishing process does not have to be flat. Also, if the surface of the crimped layer 30 is not flat, the resin joint portion 22 (first resin crimped portion 36A, second resin crimped portion 36B) may be higher than the metal joint portion 21 (first metal crimped portion 34A, second metal crimped portion 34B). In other words, the thickness D40 of the organic insulating material layer 40 may be thicker than the thickness D92 of the metal layer 92. Even in this case, the first resin crimped portion 36A and the second resin crimped portion 36B can be joined in the temporary crimping process without joining the first metal crimped portion 34A and the second metal crimped portion 34B.

[0113] Furthermore, if the surface of the crimped layer 30 after the surface polishing process is not flat, the metal joint portion 21 (first metal crimped portion 34A, second metal crimped portion 34B) may be higher than the resin joint portion 22 (first resin crimped portion 36A, second resin crimped portion 36B). In other words, the thickness D92 of the metal layer 92 may be thicker than the thickness D40 of the organic insulating material layer 40. Even in this case, the first resin crimped portion 36A and the second resin crimped portion 36B can be joined without joining the first metal crimped portion 34A and the second metal crimped portion 34B in the temporary crimping process. This will be explained with reference to Figures 7A and 7B. The surface shape of the crimped layer 30 can be adjusted, for example, by appropriately changing the slurry in CMP. Specifically, by adjusting, for example, the material and particle size distribution of the abrasive particles contained in the slurry, the relative sizes of the thickness D92 of the metal layer 92 (height of the metal-bonded portion 34) and the thickness D40 of the organic insulating material layer 40 (height of the resin-bonded portion 36) shown in Figure 3J can be adjusted.

[0114] Figures 7A and 7B show modified examples of the manufacturing method of the semiconductor device 1 according to this embodiment. Figure 7A corresponds to Figure 3J described earlier. Figure 7B corresponds to Figure 4A described earlier.

[0115] In the example shown in Figure 3J, the thickness D40 of the organic insulating material layer 40 and the thickness D92 of the metal layer 92 were equal. In contrast, in the example shown in Figure 7A, the thickness D92 of the metal layer 92 is greater than the thickness D40 of the organic insulating material layer 40. The thickness D100 shown in Figure 7A represents the difference between the thickness D92 and the thickness D40.

[0116] As shown in Figure 7B, when the microbump-formed wafers 3 shown in Figure 7A are placed facing each other for alignment, the distance D36 between the first resin-bonded portion 36A and the second resin-bonded portion 36B is longer than the distance D34 between the first metal-bonded portion 34A and the second metal-bonded portion 34B. This is because there is a difference of thickness D100 between the thickness D92 and the thickness D40.

[0117] However, if temporary crimping is performed after alignment, the first resin crimping portion 36A and the second resin crimping portion 36B can be joined without joining the first metal crimping portion 34A and the second metal crimping portion 34B, as shown in Figure 4B. This is because the resin joint portion 22 expands more than the metal joint portion 21 due to heating during the temporary crimping process.

[0118] As described above, in the semiconductor device 1 of this embodiment, it is not necessary to flatten the surface of the bonded layer 30 after the surface polishing process. Therefore, it is not necessary to strictly control the polishing conditions in the surface polishing process.

[0119] Furthermore, the thickness D100 must satisfy the following equation: D100 < Expansion amount when the organic insulating material is heated from the time of D100 measurement in the 520 direction to the temporary crimping temperature - Expansion amount when the metal material is heated from the time of D100 measurement in the 520 direction to the temporary crimping temperature

[0120] The embodiments of the present invention have been described above. The present invention is not limited to the embodiments described above, and various modifications, variations, and combinations are possible.

[0121] Thermosetting organic insulating materials exhibit a decrease in elastic modulus above their glass transition temperature. Therefore, bonding of organic insulating materials becomes easy and strong. Furthermore, reliability decreases below 130°C, so the glass transition temperature of organic insulating materials must be 130°C or higher.

[0122] When using copper pillars (copper posts) with solder formed on their tips as metal electrode materials, it is necessary to prevent short circuits between adjacent metal electrodes due to the flow of molten solder during metal joint formation. Therefore, it is important to complete the bonding of the organic insulating material before the solder melts, thereby completely sealing the metal electrodes with the organic insulating material.

[0123] To achieve a strong bond between organic insulating materials, bonding must be performed at a temperature above the glass transition temperature. However, at temperatures above 180°C, diffusion between solder and copper becomes more likely. When mutual diffusion between solder and copper occurs, the melting point of that area rises significantly or melting stops altogether, making it difficult to form a metal bond at normal soldering temperatures, or resulting in a smaller bond area and a weaker bond.

[0124] Against this background, the semiconductor device 1 and the method for manufacturing the semiconductor device 1 of this embodiment can achieve desired characteristics at a low bonding temperature by setting the glass transition temperature of the organic insulating material to an appropriate range and performing the crimping in stages of preliminary crimping and final crimping.

[0125] Furthermore, the glass transition temperature of organic insulating materials can be adjusted as needed, for example, in the case of polyimide, by changing the structure of the parts that form the backbone of the molecular structure, such as aromatic rings, the length of the side chains, and the type of modifying groups.

[0126] <1> A semiconductor device in which two or more semiconductor chips are laminated and bonded with a metal material for electrodes and a thermosetting organic insulating material, wherein the glass transition temperature of the organic insulating material is 140°C or more and 180°C or less, the metal material includes solder, and includes a resin joint formed of the organic insulating material in contact with the metal material, and the area where the resin joint is formed is the same as or inside the outer shape of the smaller of the laminated semiconductor chips. <2> The semiconductor device according to <1>, wherein the organic insulating material does not have a photosensitive function. <3> The semiconductor device according to <1> or <2>, wherein the surface of the metal material for electrodes in contact with the organic insulating material contains titanium. <4> A semiconductor device in which a semiconductor chip and an interposer are laminated and bonded with a metal material for electrodes and a thermosetting organic insulating material, wherein the glass transition temperature of the organic insulating material is 140°C or more and 180°C or less, the metal material includes solder, and includes a resin joint formed of the organic insulating material in contact with the metal material, and the area of ​​the resin joint is the same as or inside the outer shape of the semiconductor chip. <5> The semiconductor device according to <4>, wherein the organic insulating material does not have a photosensitive function. <6> The semiconductor device according to <4> or <5>, wherein the surface of the metal material for electrodes in contact with the organic insulating material contains titanium. <7> The semiconductor device according to any one of <1> to <6>, wherein the organic insulating material is polyimide or polybenzoxazole. <8> The semiconductor device according to any one of <1> to <7>, wherein the metal material contains copper. <9> A semiconductor device according to any one of <1> to <8>, comprising a structure in which a metal joint is formed of the metal material, and the distance between the centers of adjacent metal joints is 20 micrometers or less.<10> A method for manufacturing a semiconductor device comprising laminating and bonding two semiconductor chips with a metal material for electrodes and a thermosetting organic insulating material, the method comprising: a resin-bonded portion forming step of forming resin-bonded portions made of the organic insulating material on the main surface of each semiconductor chip at predetermined intervals in cross-sectional view; a metal-bonded portion forming step of forming metal-bonded portions made of the metal material between adjacent resin-bonded portions; an alignment step of aligning the two semiconductor chips so that at least one of the positions of the corresponding resin-bonded portions of each semiconductor chip and the corresponding metal-bonded portions of each semiconductor chip coincides; a temporary bonding step of bonding at least the corresponding resin-bonded portions of each semiconductor chip; and a final bonding step of bonding at least the corresponding metal-bonded portions of each semiconductor chip. <11> The method for manufacturing a semiconductor device according to <10>, wherein the glass transition temperature of the organic insulating material is 140°C or more and 180°C or less, the metal material includes solder, and when the portion where the corresponding resin-bonded portions of each semiconductor chip are bonded to each other is called a bonded portion, in the preliminary bonding step, the semiconductor chip is heated so that the temperature of the bonded portion is 100°C or more and 210°C or less, and in the main bonding step, the semiconductor chip is heated so that the temperature of the bonded portion exceeds 210°C. <12> The method for manufacturing a semiconductor device according to <10> or <11>, wherein after the metal-bonded portion forming step and before the alignment step, a surface polishing step is included in which the surface of at least one of the resin-bonded portion and the metal-bonded portion is polished, and when the direction away from the main surface of the semiconductor chip is the height direction, in the surface polishing step, the polishing is performed so that the height of the metal-bonded portion is higher than the height of the resin-bonded portion. <13> The method for manufacturing a semiconductor device according to <10> or <11>, wherein the temporary crimping step and the main crimping step are performed using different devices, in the temporary crimping step a plurality of semiconductor chips are temporarily crimped onto the semiconductor chip, and in the main crimping step the plurality of semiconductor chips temporarily crimped onto the semiconductor chip are all crimped together.

[0127] 1 Semiconductor device 3 Microbump-formed wafer 5 Semiconductor chip 5A First semiconductor chip 5B Second semiconductor chip 10 Semiconductor chip body 10 Example 10A First semiconductor chip body 10B Second semiconductor chip body 12 Main surface 15 Interposer 16 Interposer body 20 Bonding part 21 Metal bonding part 22 Resin bonding part 30 Layer to be bonded 30A First layer to be bonded 30B Second layer to be bonded 34 Metal bonding part 34A First metal bonding part 34B Second metal bonding part 36 Resin bonding part 36A First resin bonding part 36B Second resin bonding part 40 Polyimide layer 42 Polyimide layer pores 50 Photoresist layer 52 Photoresist layer pores 60 Seed layer 70 Copper layer 80 Solder layer 90 Bump 92 Metal layer 300 Thermal compression bonder 310 Thermal compression bonder 500 Upward direction 510 Surface direction 520 Crimping direction

Claims

1. A semiconductor device in which two or more semiconductor chips are laminated and bonded with a metal material for electrodes and a thermosetting organic insulating material, wherein the glass transition temperature of the organic insulating material is 140°C or more and 180°C or less, the metal material includes solder, and includes a resin joint formed of the organic insulating material in contact with the metal material, and the area where the resin joint is formed is the same as or inside the outer shape of the smaller of the laminated semiconductor chips.

2. The semiconductor device according to claim 1, wherein the organic insulating material does not have a photosensitive function.

3. The semiconductor device according to claim 1, wherein the surface of the metal material for the electrode that is in contact with the organic insulating material contains titanium.

4. A semiconductor device in which a semiconductor chip and an interposer are laminated and bonded with a metal material for electrodes and a thermosetting organic insulating material, wherein the glass transition temperature of the organic insulating material is 140°C or more and 180°C or less, the metal material includes solder, and includes a resin joint formed of the organic insulating material in contact with the metal material, and the formation area of ​​the resin joint is the same as or inside the outer shape of the semiconductor chip.

5. The semiconductor device according to claim 4, wherein the organic insulating material does not have a photosensitive function.

6. The semiconductor device according to claim 4, wherein the surface of the metal material for the electrode that is in contact with the organic insulating material contains titanium.

7. The semiconductor device according to claim 1 or 4, wherein the organic insulating material is polyimide or polybenzoxazole.

8. The semiconductor device according to claim 1 or 4, wherein the metal material comprises copper.

9. The semiconductor device according to claim 1 or 4, comprising a structure including a metal joint formed of the metal material, wherein the distance between the centers of adjacent metal joints is 20 micrometers or less.

10. A method for manufacturing a semiconductor device, comprising laminating and bonding two semiconductor chips with a metal material for electrodes and a thermosetting organic insulating material, the method comprising: a resin-bonded portion forming step of forming resin-bonded portions made of the organic insulating material at predetermined intervals in cross-sectional view on the main surface of each semiconductor chip; a metal-bonded portion forming step of forming metal-bonded portions made of the metal material between adjacent resin-bonded portions; an alignment step of aligning the two semiconductor chips so that at least one of the positions of the corresponding resin-bonded portions of each semiconductor chip and the corresponding metal-bonded portions of each semiconductor chip coincides; a preliminary bonding step of bonding at least the corresponding resin-bonded portions of each semiconductor chip; and a final bonding step of bonding at least the corresponding metal-bonded portions of each semiconductor chip.

11. The method for manufacturing a semiconductor device according to claim 10, wherein the glass transition temperature of the organic insulating material is 140°C or more and 180°C or less, the metal material includes solder, and when the portion where the corresponding resin-bonded portions of each semiconductor chip are pressed together is called the bonded portion, in the preliminary bonding step, the semiconductor chip is heated so that the temperature of the bonded portion is 100°C or more and 210°C or less, and in the main bonding step, the semiconductor chip is heated so that the temperature of the bonded portion exceeds 210°C.

12. A method for manufacturing a semiconductor device according to claim 10 or 11, comprising a surface polishing step of polishing at least one of the resin-bonded portion and the metal-bonded portion after the metal-bonded portion forming step and before the alignment step, wherein, when the direction away from the main surface of the semiconductor chip is defined as the height direction, the polishing in the surface polishing step is performed such that the height of the metal-bonded portion is greater than the height of the resin-bonded portion.

13. The method for manufacturing a semiconductor device according to claim 10 or 11, wherein the temporary crimping step and the main crimping step are performed using different devices, in the temporary crimping step a plurality of semiconductor chips are temporarily crimped onto the semiconductor chip, and in the main crimping step the plurality of semiconductor chips temporarily crimped onto the semiconductor chip are all crimped together.

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