Semiconductor device design system, method for designing semiconductor device, and program

Abstract

Provided is a semiconductor device design system capable of designing a semiconductor device at high accuracy with consideration to the actual manufacturing process. A semiconductor device design system (1) according to one embodiment of the present disclosure comprises: a design information storage unit (11) in which semiconductor device design information is stored; a process characteristic information storage unit (12) in which information relating to process characteristics for manufacturing a semiconductor device is stored; and a design information optimization unit (13) that, by using the information relating to the process characteristics stored in the process characteristic information storage unit (12), optimizes the semiconductor device design information stored in the design information storage unit (11). The design information optimization unit (13) optimizes the semiconductor device design information so as to reduce the difference between the of the semiconductor device dimensions based on the semiconductor device design information and the semiconductor device dimensions after a process for manufacturing the semiconductor device has been executed.

Description

Semiconductor device design system, semiconductor device design method, and program

[0001] The present disclosure relates to a semiconductor device design system, a semiconductor device design method, and a program.

[0002] In recent years, with the high integration and high functionality of semiconductor devices, the development of microfabrication technology for miniaturization and high density of semiconductor elements has been promoted. In the design of semiconductor devices, it is carried out in consideration of DFM (Design For Manufacturing). That is, the layout design is carried out so as to satisfy the design (DFM) considering the manufacturing process of the semiconductor device.

[0003] Patent Document 1 discloses a technology related to a design device for a semiconductor integrated circuit.

[0004] Japanese Patent Application Laid-Open No. 2013-196186

[0005] As described above, in the design of semiconductor devices, the design is carried out in consideration of the manufacturing process of the semiconductor device (DFM). However, even when the circuit design is carried out in consideration of DFM, the dimensions of the semiconductor device when the semiconductor device is actually manufactured may differ from the design values. For this reason, there is a need for a semiconductor device design system that can accurately design a semiconductor device in consideration of the actual manufacturing process.

[0006] In view of the above problems, an object of the present disclosure is to provide a semiconductor device design system, a semiconductor device design method, and a program that can accurately design a semiconductor device in consideration of the actual manufacturing process.

[0007] The semiconductor device design system, the semiconductor device design method, and the program according to one aspect of the present disclosure are as follows.

[0008] [1] A semiconductor device design system comprising: a design information storage unit that stores design information for a semiconductor device; a process characteristics information storage unit that stores information regarding process characteristics for manufacturing the semiconductor device; and a design information optimization unit that optimizes the design information for the semiconductor device stored in the design information storage unit using the information regarding process characteristics stored in the process characteristics information storage unit, wherein the design information optimization unit optimizes the design information for the semiconductor device so as to reduce the difference between the dimensions of the semiconductor device based on the design information for the semiconductor device and the dimensions of the semiconductor device after the manufacturing process for the semiconductor device has been carried out.

[0009] [2] The semiconductor device design system according to [1], wherein the design information of the semiconductor device stored in the design information storage unit includes information on manufacturing conditions when manufacturing the semiconductor device, and the design information optimization unit optimizes the information on manufacturing conditions when manufacturing the semiconductor device using the information on process characteristics stored in the process characteristics information storage unit.

[0010] [3] The semiconductor device design system according to [1] or [2], wherein the design information of the semiconductor device stored in the design information storage unit includes information regarding the layout of the semiconductor device, and the design information optimization unit optimizes the information regarding the layout of the semiconductor device using the information regarding the process characteristics stored in the process characteristics information storage unit.

[0011] [4] The semiconductor device design system according to any one of [1] to [3], wherein the process characteristic information storage unit stores information on at least one process characteristic among photolithography, cleaning, CMP, film deposition, etching, ion implantation, lamination, and dicing as information on process characteristics for manufacturing the semiconductor device.

[0012] [5] The semiconductor device design system according to any one of [1] to [3], wherein the process characteristics information storage unit stores information about CMP as information about process characteristics for manufacturing the semiconductor device, and the design information optimization unit optimizes the design information of the semiconductor device stored in the design information storage unit using the information about CMP stored in the process characteristics information storage unit.

[0013] [6] The semiconductor device design system according to [5], wherein the process characteristic information storage unit stores at least one of the following as information relating to the CMP: the basic characteristics of the polishing apparatus used, the relationship between the structure of the film to be polished and the polishing speed, the relationship between the slurry used and the polishing speed, the relationship between the wiring width of the layout and the polishing speed, the relationship between the structure of the film to be polished and the amount of dishing, the relationship between the slurry used and the amount of dishing, and the relationship between the wiring width of the layout and the amount of dishing.

[0014] [7] The semiconductor device design system according to [5] or [6], wherein the design information optimization unit optimizes the design information of the semiconductor device by arranging a dummy pattern at a predetermined position, changing the wiring width of the layout, changing the type of slurry used in CMP, or changing the configuration of the film to be polished.

[0015] [8] The semiconductor device design system according to any one of [1] to [7], wherein the design information optimization unit is equipped with an optimization model generation unit that uses the design information of the semiconductor device stored in the design information storage unit, the process characteristics information stored in the process characteristics storage unit, and the information used when optimizing the design information of the semiconductor device as training data to generate an optimization model for optimizing the design information of the semiconductor device.

[0016] [9] The semiconductor device design system according to [8], further comprising an optimization unit which optimizes the design information of the semiconductor device by inputting the design information of the semiconductor device stored in the design information storage unit into an optimization model generated by the optimization model generation unit.

[0017]

[10] A semiconductor device design method comprising: a step of acquiring design information for a semiconductor device; a step of acquiring information regarding process characteristics for manufacturing the semiconductor device; and a step of optimizing the design information for the semiconductor device using the acquired information regarding process characteristics, wherein the design information for the semiconductor device is optimized so as to reduce the difference between the dimensions of the semiconductor device based on the design information for the semiconductor device and the dimensions of the semiconductor device after carrying out the process for manufacturing the semiconductor device.

[0018]

[11] A program that causes a computer to perform the following: a process of acquiring design information for a semiconductor device; a process of acquiring information regarding process characteristics for manufacturing the semiconductor device; and a process of optimizing the design information for the semiconductor device using the acquired information regarding process characteristics, wherein in the optimization process, the design information for the semiconductor device is optimized so as to reduce the difference between the dimensions of the semiconductor device based on the design information for the semiconductor device and the dimensions of the semiconductor device after the process for manufacturing the semiconductor device has been carried out.

[0019] This disclosure provides a semiconductor device design system, a semiconductor device design method, and a program that enable the design of semiconductor devices with high accuracy while taking into account the actual manufacturing process.

[0020] This is a block diagram illustrating a semiconductor device design system according to Embodiment 1. This is a diagram showing an example of information regarding the process characteristics of a CMP. This is a diagram showing an example of information regarding the process characteristics of a CMP. This is a diagram showing an example of information regarding the process characteristics of a CMP. This is a cross-sectional view illustrating an example of the operation of the design information optimization unit. This is a cross-sectional view illustrating an example of the operation of the design information optimization unit. This is a cross-sectional view illustrating an example of the operation of the design information optimization unit. This is a cross-sectional view illustrating an example of the operation of the design information optimization unit. This is a cross-sectional view illustrating an example of the operation of the design information optimization unit. This is a block diagram illustrating a semiconductor device design system according to Embodiment 2. This is a block diagram illustrating an example of the hardware configuration of a semiconductor device design system according to Embodiments 1 and 2.

[0021] <Embodiment 1> Hereinafter, embodiments will be described with reference to the drawings. Figure 1 is a block diagram illustrating the semiconductor device design system according to Embodiment 1. As shown in Figure 1, the semiconductor device design system 1 according to this embodiment includes a design information storage unit 11, a process characteristic information storage unit 12, a design information optimization unit 13, and an optimization information storage unit 14.

[0022] The design information storage unit 11 stores design information for semiconductor devices. Specifically, the design information storage unit 11 stores information regarding the layout of the semiconductor device and information regarding the manufacturing conditions for manufacturing the semiconductor device. In this embodiment, the semiconductor device refers to semiconductor integrated circuits such as SoC (System on a Chip) and system LSI (Large-Scale Integration).

[0023] Information regarding the layout of semiconductor devices refers to information about the layout of semiconductor devices created using design tools such as TCAD (Technology Computer Aided Design). Specifically, this information includes details about the wiring, power supply, and placement of various components (transistors, capacitors, etc.) of the semiconductor device.

[0024] Information regarding the manufacturing conditions for semiconductor devices refers to the process conditions of the semiconductor manufacturing equipment used in the manufacturing of semiconductor devices. When manufacturing semiconductor devices, processes such as photolithography, cleaning, CMP (Chemical Mechanical Polishing), film deposition, etching, ion implantation, lamination, and dicing are performed.

[0025] For example, information regarding the process conditions for photolithography includes the type of exposure equipment, equipment parameters, type of resist, type of light source, etc. Information regarding the process conditions for cleaning includes the equipment used for cleaning, cleaning time, type of cleaning, chemicals used, etc. Information regarding the process conditions for CMP includes the type of polishing equipment used, type of slurry, type of polishing pad, head pressure, head rotation speed, polishing speed, etc. Information regarding the process conditions for film deposition includes the type of film deposition equipment used, film deposition time, type of raw material used for film deposition, etc. Information regarding the process conditions for etching includes the type of etching equipment used, etching time, type of raw material used for etching, etc. Information regarding the process conditions for ion implantation includes the type of ion implantation equipment used, ion implantation time, type of raw material used for ion implantation, etc. Information regarding the process conditions for lamination includes the type of laminating equipment used, lamination time, number of layers to be laminated, temperature during lamination, pressure, etc. Information regarding the process conditions for dicing includes the type of dicing equipment used, dicing time, dicing speed, etc.

[0026] The process characteristics information storage unit 12 stores information regarding process characteristics for manufacturing semiconductor devices. Specifically, the process characteristics information storage unit 12 stores information regarding at least one process characteristic from among photolithography, cleaning, CMP, film deposition, etching, ion implantation, lamination, and dicing as information regarding process characteristics for manufacturing semiconductor devices.

[0027] For example, information regarding the process characteristics of photolithography includes information on how exposure characteristics change when parameters such as the type of exposure equipment, equipment parameters, type of resist, and type of light source are changed. Information regarding the process characteristics of cleaning includes information on how cleaning characteristics change when parameters such as the equipment used for cleaning, cleaning time, type of cleaning, and chemicals used are changed. Information regarding the process characteristics of CMP includes information on how polishing characteristics change when parameters such as the type of polishing equipment used, type of slurry, type of polishing pad, head pressure, head rotation speed, and polishing speed are changed. Information regarding the process characteristics of film deposition includes information on how film deposition characteristics change when parameters such as the type of film deposition equipment used, film deposition time, and type of raw material used for film deposition are changed. Information regarding the process characteristics of etching includes information on how etching characteristics change when parameters such as the type of etching equipment used, etching time, and type of raw material used for etching are changed. Information regarding the process characteristics of ion implantation includes information on how ion implantation characteristics change when parameters such as the type of ion implantation equipment used, ion implantation time, and type of raw material used for ion implantation are changed. Information regarding the lamination process characteristics includes how the lamination characteristics change when parameters such as the type of laminating equipment used, lamination time, number of layers to be laminated, and lamination temperature and pressure are varied. Information regarding the dicing process characteristics includes how the dicing characteristics change when parameters such as the type of dicing equipment used, dicing time, and dicing speed are varied.

[0028] In other words, the process characteristics information storage unit 12 stores information regarding the results of determining the basic conditions of the equipment used for photolithography, cleaning, CMP, film deposition, etching, ion implantation, lamination, and dicing, as information regarding the process characteristics for manufacturing semiconductor devices. Information regarding the process characteristics for manufacturing semiconductor devices can be obtained in advance by conducting experiments using each piece of equipment.

[0029] The design information optimization unit 13 optimizes the semiconductor device design information stored in the design information storage unit 11 using process characteristic information stored in the process characteristic information storage unit 12. At this time, the design information optimization unit 13 optimizes the semiconductor device design information so as to reduce the difference between the dimensions of the semiconductor device based on the semiconductor device design information and the dimensions of the semiconductor device after the manufacturing process has been carried out.

[0030] The design information of the semiconductor device stored in the design information storage unit 11 includes information regarding the manufacturing conditions for manufacturing the semiconductor device. The design information optimization unit 13 optimizes the information regarding the manufacturing conditions for manufacturing the semiconductor device using the process characteristics information stored in the process characteristics information storage unit 12. In other words, the design information optimization unit 13 optimizes the information regarding the manufacturing conditions for manufacturing the semiconductor device (i.e., information regarding the manufacturing conditions for photolithography, cleaning, CMP, film deposition, etching, ion implantation, lamination, and dicing) from the design information of the semiconductor device stored in the design information storage unit 11.

[0031] Furthermore, the design information of the semiconductor device stored in the design information storage unit 11 includes information regarding the layout of the semiconductor device. The design information optimization unit 13 optimizes the information regarding the layout of the semiconductor device using the process characteristics information stored in the process characteristics information storage unit 12. In other words, the design information optimization unit 13 optimizes the layout information of the semiconductor device (such as the wiring, power supply, and arrangement of each element (transistors, capacitors, etc.)) from the design information of the semiconductor device stored in the design information storage unit 11.

[0032] The optimization information storage unit 14 stores the design information of the semiconductor device that has been optimized by the design information optimization unit 13. Note that the optimization information storage unit 14 may be omitted.

[0033] Next, the operation of the semiconductor device design system 1 according to this embodiment will be specifically described using Figures 2 to 5. In the following, as an example, we will describe the case where the information regarding the manufacturing conditions when manufacturing a semiconductor device is information regarding CMP.

[0034] The process characteristics information storage unit 12 stores information regarding the process characteristics of the CMP as information regarding the process characteristics for manufacturing semiconductor devices. The information regarding the process characteristics of the CMP includes information on how polishing characteristics change when parameters such as the type of polishing equipment used, the type of slurry, the type of polishing pad, the head pressing load, the head rotation speed, and the polishing speed are changed.

[0035] Furthermore, in this embodiment, the process characteristic information storage unit 12 may store at least one of the following as information related to CMP: the basic characteristics of the polishing apparatus used, the relationship between the structure of the film to be polished and the polishing speed, the relationship between the slurry used and the polishing speed, the relationship between the wiring width of the layout and the polishing speed, the relationship between the structure of the film to be polished and the dishing amount, the relationship between the slurry used and the dishing amount, and the relationship between the wiring width of the layout and the dishing amount.

[0036] Figures 2A and 2C show an example of information regarding the process characteristics of CMP. Figure 2A shows the relationship between the wiring width and the amount of dishing in the layout. As shown in Figure 2A, in the CMP process, the amount of dishing decreases as the wiring width becomes narrower. The process characteristics information storage unit 12 stores the relationship between the wiring width and the amount of dishing in the layout, as shown in Figure 2A, as information regarding the process characteristics of CMP.

[0037] Figure 2B shows the relationship between the slurry used and the amount of dishing. As shown in Figure 2B, in the CMP process, the amount of dishing changes depending on the slurry used. In other words, when slurry B is used, the amount of dishing is reduced compared to when slurry A is used. The process characteristic information storage unit 12 stores the relationship between the slurry used and the amount of dishing, as shown in Figure 2B, as information regarding the process characteristics of the CMP.

[0038] Figure 2C shows the relationship between the composition of the film to be polished and the amount of dishing. As shown in Figure 2C, in the CMP process, the amount of dishing changes depending on the composition of the film to be polished. In other words, when stopper film B is used, the amount of dishing is reduced compared to when polishing film A is used. The process characteristic information storage unit 12 stores the relationship between the composition of the film to be polished and the amount of dishing, as shown in Figure 2C, as information regarding the process characteristics of CMP. Here, the composition of the film to be polished refers to the layer structure and type of film of the film to be polished.

[0039] The information regarding the process characteristics of the CMP shown in Figures 2A to 2C is just an example, and the process characteristics information storage unit 12 may store other information as information regarding the process characteristics of the CMP. For example, the dishing amount can be controlled by changing conditions such as the type of polishing pad, the head pressing load, and the head rotation speed. The process characteristics information storage unit 12 may store this information as information regarding the process characteristics of the CMP.

[0040] The design information optimization unit 13 (see Figure 1) optimizes the semiconductor device design information stored in the design information storage unit 11 using the CMP information stored in the process characteristics information storage unit 12. The operation of the design information optimization unit 13 will be described in detail below.

[0041] First, the design information optimization unit 13 performs an initial simulation using the semiconductor device design information stored in the design information storage unit 11. Specifically, as shown in the left figure of Figure 3A, it simulates the state after forming an insulating film 22 on a silicon substrate 21 on which a wiring pattern has been formed, and then polishing it using CMP. As shown in the right figure of Figure 3A, the silicon substrate 21 has a region 31 with a wiring width W1 and a region 32 with a wiring width W2. The results of the initial simulation show that in the silicon substrate 21 (semiconductor device) after polishing with CMP, the amount of polishing of the insulating film 22 is greater in the region 31 with a wider wiring width, and less in the region 32 with a narrower wiring width. In other words, the region 31 with a wider wiring width has a greater amount of dishing of the insulating film 22 than the region 32 with a narrower wiring width.

[0042] On the other hand, the dimensions (design values) of the semiconductor device based on the design information of the semiconductor device stored in the design information storage unit 11 show that, as shown in Figure 3B, the amount of polishing of the insulating film 22 in the region with a wide wiring width 31 is approximately the same as the amount of polishing of the insulating film 22 in the region with a narrow wiring width 32.

[0043] Therefore, in the initial simulation state (right figure in Figure 3A), the difference in polishing amount between region 31 and region 32 is large. As a result, the design information optimization unit 13 optimizes the semiconductor device design information so that the difference between the dimensions of the semiconductor device based on the semiconductor device design information (Figure 3B) and the dimensions of the semiconductor device after the manufacturing process for the semiconductor device has been carried out (right figure in Figure 3A) is reduced. Specifically, the design information optimization unit 13 optimizes the CMP conditions when manufacturing the semiconductor device using the information on the process characteristics of CMP stored in the process characteristics information storage unit 12. For example, the design information optimization unit 13 optimizes the semiconductor device design information by (1) placing a dummy pattern in a predetermined position, (2) changing the wiring width of the layout, (3) changing the type of slurry used in CMP, or (4) changing the configuration of the film to be polished. By optimizing the semiconductor device design information in this way, the amount of dishing of the insulating film can be reduced. As a result, deviations in the depth of focus in the next process of patterning can be suppressed, and disconnections of the wiring layer can be suppressed. The following describes in detail the case where the semiconductor device design information is optimized using (1) to (4) above.

[0044] (1) When placing a dummy pattern at a specified position In the process characteristic information storage unit 12, as information regarding the process characteristics of CMP, the relationship between the wiring width and the amount of dishing in the layout as shown in FIG. 2A is stored. That is, when the wiring widths in the layout are about the same, the amounts of dishing are about the same. As shown in FIG. 4A, the design information optimization unit 13 may optimize the design information of the semiconductor device by placing the dummy pattern 24 in the region 31 of the silicon substrate 21 using the relationship between the wiring width and the amount of dishing in the layout stored in the process characteristic information storage unit 12. By placing the dummy pattern 24 in this way, the wiring widths of the region 31 and the region 32 can be made about the same. Therefore, the difference between the polishing amount of the insulating film 22 in the region 31 of the silicon substrate 21 and the polishing amount of the insulating film 22 in the region 32 can be reduced.

[0045] (2) When changing the wiring width of the layout In the example of (1) above, the dummy pattern 24 was placed in the region 31, but the wiring width of the region 31 may be changed. That is, the design information optimization unit 13 may optimize the design information of the semiconductor device by changing the wiring width of the region 31 of the silicon substrate 21 using the relationship between the wiring width and the amount of dishing stored in the process characteristic information storage unit 12. That is, by changing the layout so that the wiring width of the region 31 becomes about the same as the wiring width of the region 32, the difference between the polishing amount of the insulating film 22 in the region 31 of the silicon substrate 21 and the polishing amount of the insulating film 22 in the region 32 can be reduced.

[0046] (3) When changing the type of slurry used in CMP, the process characteristic information storage unit 12 stores, as information regarding the process characteristics of CMP, the relationship between the slurry to be used and the dishing amount as shown in FIG. 2B. That is, even when the wiring widths of the layout are different, it may be possible to make the polishing amounts of the insulating film 22 approximately the same by changing the type of slurry to be used. As shown in FIG. 4B, the design information optimization unit 13 may optimize the design information of the semiconductor device by changing the slurry to be used using the relationship between the slurry to be used and the dishing amount stored in the process characteristic information storage unit 12. By changing the slurry to be used in this way, the difference between the polishing amount of the insulating film 22 in the region 31 of the silicon substrate 21 and the polishing amount of the insulating film 22 in the region 32 can be reduced.

[0047] (4) When changing the structure of the film to be polished, the process characteristic information storage unit 12 stores, as information regarding the process characteristics of CMP, the relationship between the structure of the film to be polished and the dishing amount as shown in FIG. 2C. That is, even when the wiring widths of the layout are different, it may be possible to make the polishing amounts of the insulating film 22 approximately the same by changing the structure of the film to be polished. As shown in FIG. 4C, the design information optimization unit 13 may optimize the design information of the semiconductor device by changing the structure of the film to be polished using the relationship between the structure of the film to be polished and the dishing amount stored in the process characteristic information storage unit 12. That is, a film (stopper film) 25 that is difficult to polish is provided on the silicon substrate 21. By changing the structure of the film to be polished in this way, the difference between the polishing amount of the insulating film 22 in the region 31 of the silicon substrate 21 and the polishing amount of the insulating film 22 in the region 32 can be reduced.

[0048] The design information optimization unit 13 may determine the above (1) to (4) as candidates, and optimize the design information of the semiconductor device using the most suitable one among them. Although the operation of the design information optimization unit 13 has been described above, the above operation is an example, and in the present embodiment, the design information optimization unit 13 may optimize the design information of the semiconductor device using other methods.

[0049] As described above, in this embodiment, the design information optimization unit 13 optimizes the semiconductor device design information stored in the design information storage unit 11 using process characteristic information stored in the process characteristic information storage unit 12. At this time, the design information optimization unit 13 optimizes the semiconductor device design information so as to reduce the difference between the dimensions of the semiconductor device based on the semiconductor device design information and the dimensions of the semiconductor device after the manufacturing process has been carried out. Therefore, a semiconductor device design system that can accurately design semiconductor devices while taking the actual manufacturing process into consideration can be provided.

[0050] <Embodiment 2> Next, Embodiment 2 will be described. Figure 5 is a block diagram illustrating the semiconductor device design system according to Embodiment 2. The semiconductor device design system 2 according to Embodiment 2 differs from the semiconductor device design system 1 according to Embodiment 1 in the configuration of the design information optimization unit 13a. Other than this, it is the same as the semiconductor device design system 1 according to Embodiment 1, so the same reference numerals are used for the same components and redundant explanations are omitted.

[0051] As shown in Figure 5, in the semiconductor device design system 2 according to this embodiment, the design information optimization unit 13a comprises an optimization model generation unit 17 and an optimization unit 18. The optimization model generation unit 17 uses the design information of the semiconductor device stored in the design information storage unit 11, the process characteristics information stored in the process characteristics information storage unit 12, and the information used when optimizing the design information of the semiconductor device as training data to perform machine learning and generate an optimization model for optimizing the design information of the semiconductor device.

[0052] For example, the optimization model generation unit 17 uses the method described in Embodiment 1 to create candidates (candidates (1) to (4)) for optimizing the design information of a semiconductor device, and determines the optimal candidate from among these candidates for optimizing the design information of a semiconductor device. The optimization model generation unit 17 uses the design information of the semiconductor device stored in the design information storage unit 11, the process characteristics information stored in the process characteristics information storage unit 12, and the information used when optimizing the design information of the semiconductor device (for example, any of the candidates (1) to (4)) as training data for machine learning. By performing such machine learning, an optimization model for optimizing the design information of a semiconductor device is generated.

[0053] For example, the optimization model generation unit 17 can generate an optimization model by using a known machine learning algorithm such as a convolutional neural network (CNN) and training the semiconductor device design information stored in the design information storage unit 11, the process characteristics information stored in the process characteristics information storage unit 12, and the information used when optimizing the semiconductor device design information. Known machine learning algorithms that can be used include VGG19, Inception V3, and ResNet.

[0054] The optimization unit 18 optimizes the semiconductor device design information by inputting the semiconductor device design information stored in the design information storage unit 11 into the optimization model generated by the optimization model generation unit 17.

[0055] In this embodiment as well, the design information optimization unit 13a optimizes the semiconductor device design information stored in the design information storage unit 11 using process characteristic information stored in the process characteristic information storage unit 12. Therefore, a semiconductor device design system is provided that can accurately design semiconductor devices while taking the actual manufacturing process into consideration.

[0056] <Other Embodiments> The semiconductor device design method according to this embodiment will be described below. The semiconductor device design method according to this embodiment comprises the steps of acquiring semiconductor device design information, acquiring process characteristics for manufacturing the semiconductor device, and optimizing the semiconductor device design information using the acquired process characteristics. In this embodiment, the semiconductor device design information is optimized so as to reduce the difference between the dimensions of the semiconductor device based on the semiconductor device design information and the dimensions of the semiconductor device after the manufacturing process has been carried out.

[0057] Next, using Figure 6, an example of the hardware configuration of semiconductor device design systems 1 and 2 according to this embodiment will be described. The semiconductor device design systems 1 and 2 include a processor 101 and a memory 102. The processor 101 may be, for example, a microprocessor, an MPU (Micro Processing Unit), or a CPU (Central Processing Unit). The processor 101 may include multiple processors. The memory 102 is composed of a combination of volatile memory and non-volatile memory. The memory 102 may include storage located away from the processor 101. In this case, the processor 101 may access the memory 102 via an input / output interface (not shown).

[0058] Furthermore, each device in the above-described embodiment may be composed of hardware, software, or both, and may consist of one piece of hardware or software, or multiple pieces of hardware or software. The functions (processing) of each device in the above-described embodiment may be implemented by a computer. For example, a program for performing the operations in the embodiment may be stored in memory 102, and each function may be implemented by executing the program stored in memory 102 on the processor 101.

[0059] The program according to this embodiment is a program that causes a computer to perform the following processes: acquiring design information for a semiconductor device; acquiring information regarding process characteristics for manufacturing a semiconductor device; and optimizing the design information for the semiconductor device using the acquired information regarding process characteristics. In the optimization process, the program optimizes the design information for the semiconductor device so that the difference between the dimensions of the semiconductor device based on the design information and the dimensions of the semiconductor device after the manufacturing process has been carried out is reduced.

[0060] The program, when loaded into a computer, includes a set of instructions (or software code) for causing the computer to perform one or more of the functions described in the embodiments. The program may be stored on a non-temporary computer-readable medium or a physical storage medium. Examples, but not limited to, include random-access memory (RAM), read-only memory (ROM), flash memory, solid-state drive (SSD) or other memory technologies, CD-ROM, digital versatile disk (DVD), Blu-ray® disc or other optical disc storage, magnetic cassette, magnetic tape, magnetic disk storage or other magnetic storage devices. The program may be transmitted over a temporary computer-readable medium or a communication medium. Examples, but not limited to, include temporary computer-readable medium or a communication medium that includes electrical, optical, acoustic or other forms of propagating signals.

[0061] Although the present invention has been described above in accordance with the above embodiments, the present invention is not limited to the configuration of the above embodiments, and of course includes various modifications, alterations, and combinations that can be made by a person skilled in the art within the scope of the claims of the present patent application.

[0062] This application claims priority based on Japanese Patent Application No. 2024-166541, filed on 25 September 2024, and incorporates all of its disclosures herein.

[0063] 1, 2 Semiconductor device design system 11 Design information storage unit 12 Process characteristic information storage unit 13, 13a Design information optimization unit 14 Optimization information storage unit 17 Optimization model generation unit 18 Optimization unit 21 Silicon substrate 22 Insulating film 24 Dummy pattern 25 Film 31, 32 Region 101 Processor 102 Memory

Claims

1. A semiconductor device design system comprising: a design information storage unit that stores design information for a semiconductor device; a process characteristics information storage unit that stores information regarding process characteristics for manufacturing the semiconductor device; and a design information optimization unit that optimizes the design information for the semiconductor device stored in the design information storage unit using the information regarding process characteristics stored in the process characteristics information storage unit, wherein the design information optimization unit optimizes the design information for the semiconductor device so as to reduce the difference between the dimensions of the semiconductor device based on the design information for the semiconductor device and the dimensions of the semiconductor device after the manufacturing process for the semiconductor device has been carried out.

2. The semiconductor device design system according to claim 1, wherein the design information of the semiconductor device stored in the design information storage unit includes information regarding manufacturing conditions for manufacturing the semiconductor device, and the design information optimization unit optimizes the information regarding manufacturing conditions for manufacturing the semiconductor device using the information regarding process characteristics stored in the process characteristics information storage unit.

3. The semiconductor device design system according to claim 1 or 2, wherein the design information of the semiconductor device stored in the design information storage unit includes information regarding the layout of the semiconductor device, and the design information optimization unit optimizes the information regarding the layout of the semiconductor device using the information regarding the process characteristics stored in the process characteristics information storage unit.

4. The semiconductor device design system according to claim 1 or 2, wherein the process characteristic information storage unit stores information regarding at least one process characteristic among photolithography, cleaning, CMP, film deposition, etching, ion implantation, lamination, and dicing as information regarding process characteristics for manufacturing the semiconductor device.

5. The semiconductor device design system according to claim 1, wherein the process characteristics information storage unit stores information regarding CMP as information regarding process characteristics for manufacturing the semiconductor device, and the design information optimization unit optimizes the design information of the semiconductor device stored in the design information storage unit using the information regarding CMP stored in the process characteristics information storage unit.

6. The semiconductor device design system according to claim 5, wherein the process characteristic information storage unit stores at least one of the following as information relating to the CMP: the basic characteristics of the polishing apparatus used, the relationship between the configuration of the film to be polished and the polishing speed, the relationship between the slurry used and the polishing speed, the relationship between the wiring width of the layout and the polishing speed, the relationship between the configuration of the film to be polished and the amount of dishing, the relationship between the slurry used and the amount of dishing, and the relationship between the wiring width of the layout and the amount of dishing.

7. The semiconductor device design system according to claim 5 or 6, wherein the design information optimization unit optimizes the design information of the semiconductor device by arranging a dummy pattern at a predetermined position, changing the wiring width of the layout, changing the type of slurry used in CMP, or changing the configuration of the film to be polished.

8. The semiconductor device design system according to claim 1 or 2, wherein the design information optimization unit includes an optimization model generation unit that uses the design information of the semiconductor device stored in the design information storage unit, the process characteristics information stored in the process characteristics information storage unit, and the information used when optimizing the design information of the semiconductor device as training data to generate an optimization model for optimizing the design information of the semiconductor device.

9. The semiconductor device design system according to claim 8, further comprising an optimization unit that optimizes the design information of the semiconductor device by inputting the design information of the semiconductor device stored in the design information storage unit into an optimization model generated by the optimization model generation unit.

10. A semiconductor device design method comprising: a step of acquiring design information for a semiconductor device; a step of acquiring information regarding process characteristics for manufacturing the semiconductor device; and a step of optimizing the design information for the semiconductor device using the acquired information regarding process characteristics, wherein the design information for the semiconductor device is optimized so as to reduce the difference between the dimensions of the semiconductor device based on the design information for the semiconductor device and the dimensions of the semiconductor device after carrying out the process for manufacturing the semiconductor device.

11. A program that causes a computer to perform the following steps: a process to acquire design information for a semiconductor device; a process to acquire information regarding process characteristics for manufacturing the semiconductor device; and a process to optimize the design information for the semiconductor device using the acquired information regarding process characteristics, wherein the optimization process optimizes the design information for the semiconductor device so that the difference between the dimensions of the semiconductor device based on the design information and the dimensions of the semiconductor device after the manufacturing process for the semiconductor device has been carried out is reduced.

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