Cascode amplifier circuit

Abstract

According to the present invention, a high-frequency signal is input to a first transistor. At least one second transistor is cascode-connected to the first transistor. A bias circuit supplies a bias to the second transistor. Power supply wiring applies a voltage-variable power supply voltage to a cascode connection circuit including the first transistor and the second transistor. The bias circuit includes a voltage regulator and a first resistor voltage divider circuit. The first resistor voltage divider circuit supplies a bias voltage, divided on the basis of the output voltage of a voltage control node of which the voltage is being controlled by the voltage regulator and the power supply voltage of the power supply wiring, to the second transistor.

Description

Cascode amplifier circuit

[0001] This invention relates to a cascode amplifier circuit.

[0002] An envelope tracking amplifier is known that modulates the power supply voltage of a cascode amplifier circuit based on an input signal (Patent Document 1). In the cascode amplifier circuit disclosed in Patent Document 1, the power supply voltage modulated based on the input signal is divided by a resistor voltage divider circuit to generate a bias voltage. This bias voltage is supplied to the cascode transistor.

[0003] Special table 2016-530845 publication

[0004] When the power supply voltage is reduced, the bias voltage generated based on the reduced power supply voltage also decreases. If the bias voltage of the cascode transistor drops excessively, the cascode transistor may turn off, and the gain may decrease. The object of the present invention is to provide a cascode amplifier circuit in which the decrease in gain is suppressed even when the power supply voltage is reduced.

[0005] According to one aspect of the present invention, a cascode amplifier circuit is provided comprising: a first transistor to which a high-frequency signal is input; at least one second transistor cascode-connected to the first transistor; a bias circuit that supplies a bias to the second transistor; and a power supply wiring that applies a variable power supply voltage to the cascode connection circuit including the first transistor and the second transistor, wherein the bias circuit includes a voltage regulator and a first resistor voltage divider circuit, and the first resistor voltage divider circuit supplies a bias voltage divided based on the output voltage of a voltage control node whose voltage is controlled by the voltage regulator and the power supply voltage of the power supply wiring to the second transistor.

[0006] Since the bias voltage divided based on the output voltage of the voltage regulator and the power supply voltage is supplied to the second transistor, the decrease in the bias voltage is suppressed even when the power supply voltage decreases, compared with the case where the bias voltage divided based on the reference potential and the power supply voltage is supplied to the second transistor. Thereby, the decrease in the gain in the state where the power supply voltage has decreased is suppressed.

[0007] FIG. 1 is an equivalent circuit diagram of a cascode amplifier circuit according to the first embodiment. FIG. 2 is a graph showing an example of the relationship between the power supply voltage Vdd １ and the bias voltage Vg. FIG. 3 is an equivalent circuit diagram of a cascode amplifier circuit according to the first comparative example. FIG. 4 is a graph showing the relationship between the power supply voltage Vdd １ and the bias voltage Vg of the cascode amplifier circuit according to the first comparative example. FIG. 5 is an equivalent circuit diagram of a cascode amplifier circuit according to the second comparative example. FIG. 6 is a graph showing the relationship between the power supply voltage Vdd １ and the bias voltage Vg of the cascode amplifier circuit according to the second comparative example. FIG. 7 is an equivalent circuit diagram of the voltage regulator 30 used in the cascode amplifier circuit according to a modification of the first embodiment. FIG. 8 is an equivalent circuit diagram of a cascode amplifier circuit according to the second embodiment. FIG. 9 is an equivalent circuit diagram of a cascode amplifier circuit according to the third embodiment. FIG. 10 is an equivalent circuit diagram of a cascode amplifier circuit according to the fourth embodiment.

[0008] [First Embodiment] A cascode amplifier circuit according to the first embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is an equivalent circuit diagram of a cascode amplifier circuit according to the first embodiment. The high-frequency signal Pin is input to the gate of the first transistor Q １ via the impedance matching circuit 71. A bias voltage Vg １ is supplied to the gate of the first transistor Q １ from the bias circuit 70 via the resistor element R １ .

[0009] Four second transistors Q ２ connected in series are cascode-connected to the first transistor Q １ . Note that the second transistor Q ２It is not limited to four, but at least one. For example, the second transistor Q ２ There may be one, two, three, or five or more of them.

[0010] First transistor Q １ and the second transistor Q ２ An NMOSFET is used as the first transistor Q. １ The source is connected to the reference potential (grounded), and the first transistor Q １ Multiple second transistors Q are connected to the drain of the ２ A series circuit consisting of the following is connected. First transistor Q １ and four second transistors Q ２ Then, sequentially numbering is assigned from the reference potential side, for the first transistor Q. １ and four second transistors Q ２ We will distinguish between them. First transistor Q １ This is the first stage transistor, and there are four second-stage transistors Q ２ They are assigned sequential numbers from 2 to 5. Multiple second transistors Q ２ The gates are connected to capacitor C. ２ It is grounded via AC through this.

[0011] The bias circuit 20 has multiple second transistors Q ２ A resistor R is placed at each gate. ２ The bias voltage is supplied via this. Second transistor Q from the second to fifth stages ２ The bias voltage supplied to each gate is Vg ２ , Vg ３ , Vg ４ , Vg ５ This is how it is written.

[0012] The power supply wiring 50 is connected to the variable power supply circuit 51. The variable power supply circuit 51 modulates the voltage of the power supply voltage Vdd according to the high-frequency signal Pin using technologies such as envelope tracking (ET) and average power tracking (APT). １ Apply the following to the power supply wiring 50: Power supply voltage Vdd １It is variable within the set operating range.

[0013] The power supply wiring 50 is connected to the first transistor Q １ and four second transistors Q ２ A cascode connection circuit including the above has the power supply voltage Vdd connected via a choke coil L. １ Apply the following: In other words, the second transistor Q of the fifth stage ２ The drain of the first transistor Q is connected to the power supply wiring 50 via a choke coil L. The amplified high-frequency signal Put is connected to the first transistor Q １ and four second transistors Q ２ The output is generated from the connection point between the cascode connection circuit and the choke coil L, via the impedance matching circuit 75.

[0014] Next, the configuration of the bias circuit 20 will be described. The bias circuit 20 includes a voltage regulator 30 and a first resistor voltage divider circuit 38. The first resistor voltage divider circuit 38 is connected between the power supply wiring 50 and the output node of the voltage regulator 30 (a voltage control node where the voltage is controlled). The first resistor voltage divider circuit 38 divides the voltage of the output node (hereinafter referred to as the output voltage Vreg) of the power supply wiring 50 and the power supply voltage Vdd by the voltage regulator 30. １ Multiple bias voltages Vg divided based on ２ , Vg ３ , Vg ４ , Vg ５ This generates the second transistor Q of the second to fifth stages, respectively. ２ It supplies to the gate.

[0015] For example, the first resistor voltage divider circuit 38 includes four resistors connected in series. The four resistors are numbered sequentially from 1, starting from the output node end of the voltage regulator 30 to the power supply wiring 50 end. The (i+1)th stage second transistor Q ２ The gate of the resistive element R ２ It is connected to the output node end of the i-th resistor element via a , where i is an integer between 1 and 4. In this configuration, the second stage second transistor Q ２ The bias voltage Vg supplied to it ２This becomes equal to the output voltage Vreg of the voltage regulator 30.

[0016] The voltage regulator 30 consists of a driver transistor 31, an operational amplifier 32, a resistor 33, a feedback circuit 35, and a capacitor C. ３ This includes the following: As the driver transistor 31, for example, an NMOSFET is used and is connected between the output node of the voltage regulator 30 and the reference potential (ground). The resistor 33 is connected between the output node and the power supply voltage Vdd for the regulator. ２ It is connected between the two. A second resistor voltage divider circuit containing two resistor elements is used as resistor 33.

[0017] The operational amplifier 32 applies a control voltage to the gate of the driver transistor 31. The resistance between the drain and source of the driver transistor 31 is controlled by the control voltage. The feedback circuit 35 controls the output voltage Vreg of the voltage regulator 30 and the power supply voltage Vdd for the regulator. ２ A feedback voltage Vfb based on this is applied to the non-inverting input node of the operational amplifier 32. More specifically, the voltage divided by the resistor 33 is applied to the non-inverting input node of the operational amplifier 32 as the feedback voltage Vfb. A reference voltage Vref is applied to the inverting input node of the operational amplifier 32 from the reference voltage generation circuit 41 of the control circuit 40.

[0018] The power supply voltage Vdd for the regulator of resistor 33, which constitutes the resistive voltage divider circuit. ２ The resistance value of the resistor element on the side is R １ The resistance value of the resistor element on the output node side is R ２ This is how it is denoted. In this case, the feedback voltage Vfb is expressed by the following equation: Vfb = (R ２ / (R １ +R ２ ))Vdd ２ + (R １ / (R １ +R ２))Vreg...(1) Because the driver transistor 31 and the operational amplifier 32 control the feedback voltage Vfb to match the reference voltage Vref, the output voltage Vreg of the voltage regulator 30 is expressed by the following formula: Vreg = ((R １ +R ２ ) / R １ ) Vref-(R ２ / R １ ) Vdd ２ ... (2)

[0019] Power supply voltage VDD １ When the power supply voltage Vdd is above a predetermined voltage value, the output voltage Vreg is maintained at a constant value expressed by equation (2). １ When the voltage falls below a predetermined value, the feedback voltage Vfb decreases, the driver transistor 31 turns off, and a state occurs where the output voltage Vreg can no longer be controlled to a constant value. The output voltage Vreg at this time is called the control lower limit value Vreg_min. In the range where the output voltage Vreg is below the control lower limit value Vreg_min, the regulator power supply voltage Vdd ２ From resistor 33 and first resistor voltage divider circuit 38, the power supply voltage Vdd １ An electric current flows through it.

[0020] The resistance value of resistor 33 is set to a value sufficiently higher than the sum of the resistance values ​​of the multiple resistor elements in the first resistor voltage divider circuit 38. Therefore, when the output voltage Vreg is within the range of the control lower limit Vreg_min, the output voltage Vreg is equal to the power supply voltage Vdd １ It becomes approximately equal to this.

[0021] The control circuit 40 includes a reference voltage generation circuit 41, a digital circuit 45, and an electronic fuse 46. The reference voltage generation circuit 41 has a temperature sensor and has the function of changing the reference voltage Vref according to the ambient temperature detected by the temperature sensor. For example, the first transistor Q １ , second transistor Q ２ The bias circuit 20 and the control circuit 40 are formed on a common semiconductor substrate, such as a silicon substrate or an SOI substrate, and "ambient temperature" refers to the temperature of the semiconductor substrate on which the control circuit 40 and the like are formed.

[0022] Further, the reference voltage generation circuit 41 has a function of changing the reference voltage Vref in accordance with a command from the digital circuit 45. The digital circuit 45 gives a command to change the reference voltage Vref to the reference voltage generation circuit 41 according to the conduction state of the electronic fuse 46. The function of changing the reference voltage Vref can be used, for example, for correcting variations in the appropriate reference voltage Vref due to variations in the manufacturing process. Also, when the cascode amplifier circuit has a function of operating in a plurality of frequency bands, the reference voltage Vref can be adjusted to an appropriate value according to the operating frequency band.

[0023] FIG. 2 １ is a graph showing an example of the relationship between the power supply voltage Vdd １ and the bias voltage Vg. The horizontal axis represents the normalized value of the power supply voltage Vdd １ , and the vertical axis represents the normalized value of the bias voltage Vg. The normalized value is normalized with the upper limit value of the operating range of the power supply voltage Vdd ２ as 1. In FIG. 2, a plurality of thick solid lines respectively represent the bias voltages Vg ３ , Vg ４ , Vg ５ , and the broken line represents the bias voltage Vg equal to the power supply voltage Vdd １ .

[0024] When the power supply voltage Vdd １ is in a range of not less than the control lower limit value Vreg_min of the output voltage Vreg, the bias voltage Vg ２ is equal to the control lower limit value Vreg_min, and the other bias voltages Vg ３ , Vg ４ , Vg ５ increase as the power supply voltage Vdd １ increases. When the power supply voltage Vdd １ is in a range of less than the control lower limit value Vreg_min, the bias voltages Vg ２ , Vg ３ , Vg ４ , Vg ５ become substantially equal to the power supply voltage Vdd １ .

[0025] Next, the excellent effects of the first embodiment will be described while comparing with the first comparative example shown in FIGS. 3 and 4. FIG. 3 is an equivalent circuit diagram of a cascode amplifier circuit according to the first comparative example. In the first comparative example, the first resistor voltage dividing circuit 38 is connected between the power supply wiring 50 and the reference potential.

[0026] FIG. 4 is a graph showing the relationship between the power supply voltage Vdd １ and the bias voltage Vg of the cascode amplifier circuit according to the first comparative example. The horizontal axis of the graph in FIG. 4 represents the normalized value of the power supply voltage Vdd １ , and the vertical axis represents the normalized value of the bias voltage Vg. In the first comparative example shown in FIG. 3, since one end of the first resistor voltage dividing circuit 38 is connected to the reference potential, when the power supply voltage Vdd １ is 0 V, the bias voltage Vg ２ , Vg ３ , Vg ４ , Vg ５ also becomes 0 V. The bias voltages Vg ２ , Vg ３ , Vg ４ , Vg ５ increase in proportion to the power supply voltage Vdd １ . Also, throughout the operating range of the power supply voltage Vdd １ , the bias voltages Vg ２ , Vg ３ , Vg ４ , Vg ５ are lower than the power supply voltage Vdd １ .

[0027] In this configuration, the gain deviation in the vicinity of the lower limit value when the gain at the upper limit value (normalized value is 1) of the operating range of the power supply voltage Vdd １ is used as a reference is large. Specifically, when the power supply voltage Vdd １ is in the vicinity of the lower limit value of the operating range (for example, the normalized value is about 0.1), the bias voltages Vg ２ , Vg ３ , Vg ４ , Vg ５ are too low, resulting in a large decrease in gain.

[0028] In contrast, in the first embodiment, as shown in FIG. 2, the power supply voltage Vdd １When the bias voltage Vg is near the lower limit of the operating range (for example, a normalized value of approximately 0.1), ２ , Vg ３ , Vg ４ , Vg ５ is the power supply voltage Vdd １ It becomes approximately equal to the power supply voltage Vdd. １ Even when the value is reduced to near the lower limit of the operating range, the decrease in gain can be suppressed.

[0029] Next, the superior effects of the first embodiment will be explained in comparison with the second comparative example shown in Figures 5 and 6.

[0030] Figure 5 is an equivalent circuit diagram of the cascode amplifier circuit according to the second comparative example. In the second comparative example, the first resistor voltage divider circuit 38 is connected between the fixed voltage Vsup and the reference potential. The bias voltage Vg divided by the first resistor voltage divider circuit 38 ２ , Vg ３ , Vg ４ , Vg ５ However, each has four second transistors Q ２ It is supplied to.

[0031] Figure 6 shows the power supply voltage Vdd of the cascode amplifier circuit according to the second comparative example. １ This graph shows the relationship between the power supply voltage Vg and the bias voltage Vd. The horizontal axis of the graph in Figure 6 is the power supply voltage Vdd. １ This graph shows the normalized value of the voltage, and the vertical axis represents the normalized value of the bias voltage Vg. Since a fixed voltage Vsup is applied to the first resistor voltage divider circuit 38, the power supply voltage Vdd １ Even if the bias voltage Vg changes ２ , Vg ３ , Vg ４ , Vg ５ It is constant.

[0032] Power supply voltage VDD １ When the bias voltage Vg has decreased to near the lower limit of the operating range (for example, a normalized value of approximately 0.1), ３ , Vg ４ , Vg ５ is the power supply voltage Vdd １ This becomes considerably higher. Therefore, the Q of the second transistor in the fifth stage in particular... ２In this case, the voltage between the gate and drain exceeds the withstand voltage. This reduces the reliability of the cascode amplifier circuit.

[0033] In contrast, in the first embodiment, as shown in Figure 2, the power supply voltage Vdd １ When the bias voltage Vg drops to near the lower limit of the operating range, ２ , Vg ３ , Vg ４ , Vg ５ is the power supply voltage Vdd １ This becomes approximately equal to the second transistor Q. ２ The voltage between each gate and drain becomes less likely to exceed the withstand voltage. This suppresses the decrease in reliability of the cascode amplifier circuit.

[0034] Furthermore, the bias voltage Vg is generated by the digital arithmetic circuit as shown in Figure 2. ２ , Vg ３ , Vg ４ , Vg ５ It is also possible to change the power supply voltage Vdd. １ A / D conversion using an A / D converter to detect the voltage, digital calculations, and D / A conversion using a D / A converter to generate the bias voltage are required. Therefore, the power supply voltage Vdd １ The bias voltage Vg in response to changes in this voltage. ２ , Vg ３ , Vg ４ , Vg ５ The tracking speed will become slower.

[0035] It is also possible to use an analog arithmetic circuit using an operational amplifier instead of a digital arithmetic circuit. In this configuration as well, the power supply voltage Vdd １ The bias voltage Vg in response to changes in this voltage. ２ , Vg ３ , Vg ４ , Vg ５ The tracking speed is limited by the operating speed of the operational amplifier.

[0036] In contrast, in the first embodiment, the power supply voltage Vdd １ The bias voltage Vg is provided by the first resistor voltage divider circuit 38 (Figure 1) connected to it. ２ , Vg ３, Vg ４ , Vg ５ Because it generates the power supply voltage Vdd １ The bias voltage Vg in response to changes in this voltage. ２ , Vg ３ , Vg ４ , Vg ５ There is almost no delay in the changes.

[0037] As described above, in the first embodiment, the power supply voltage Vdd １ It suppresses gain deviation when the power supply voltage Vdd changes, maintaining high reliability, and １ The bias voltage Vg in response to changes in this voltage. ２ , Vg ３ , Vg ４ , Vg ５ This enables a sufficiently fast tracking speed.

[0038] Next, other excellent effects of the first embodiment will be described. In the first embodiment, the reference voltage generation circuit 41 (Figure 1) can change the output voltage Vreg of the voltage regulator 30 by changing the reference voltage Vref. When the output voltage Vreg changes, the second transistor Q ２ Bias voltage Vg ２ , Vg ３ , Vg ４ , Vg ５ This changes. Therefore, it is possible to increase the degree of freedom in setting the bias voltage.

[0039] Furthermore, the reference voltage generation circuit 41 changes the reference voltage Vref according to the ambient temperature, thereby changing the bias voltage Vg ２ , Vg ３ , Vg ４ , Vg ５ This allows the bias voltage Vg to be changed according to the ambient temperature. ２ , Vg ３ , Vg ４ , Vg ５ The second transistor Q ２ It can be given.

[0040] Next, a modified example of the first embodiment will be described with reference to Figure 7. Figure 7 is an equivalent circuit diagram of the voltage regulator 30 used in the cascode amplifier circuit according to the modified example of the first embodiment. In the cascode amplifier circuit according to the first embodiment (Figure 1), an NMOSFET is used for the driver transistor 31 of the voltage regulator 30. In contrast, in the modified example shown in Figure 7, a PMOSFET is used for the driver transistor 31.

[0041] For example, the source of the driver transistor 31 is the power supply voltage Vdd for the regulator. ２ The driver transistor 31 is connected to the reference potential via resistor 33, and its drain is connected to the reference potential. The drain of the driver transistor 31 becomes the output node (voltage control node), and the output voltage Vreg is output. The feedback voltage Vfb generated by voltage division by resistor 33 is supplied to the non-inverting input node of the operational amplifier 32 by the feedback circuit 35. The reference voltage Vref is supplied to the inverting input node of the operational amplifier 32.

[0042] As shown in Figure 7, a PMOSFET may be used for the voltage regulator 30. In the first embodiment (Figure 1), the current flowing from the power supply wiring 50 to the first resistor voltage divider circuit 38 flows to the reference potential via the driver transistor 31. In contrast, in the modified example shown in Figure 7, the current flowing from the power supply wiring 50 to the first resistor voltage divider circuit 38 flows to the reference potential via the resistor 33. Comparing the first embodiment with the modified example shown in Figure 7, the first embodiment offers the excellent effect of lowering the resistance of the current path flowing from the power supply wiring 50 to the reference potential via the first resistor voltage divider circuit 38.

[0043] Next, other modifications of the first embodiment will be described. In the first embodiment (Figure 1), the resistor 33 of the voltage regulator 30 is configured as a resistive voltage divider circuit, but the feedback circuit 35 may be configured to supply the output voltage Vreg of the voltage regulator 30 as a feedback voltage Vfb to the non-inverting input node of the operational amplifier 32. In this configuration, the resistance value R of the resistor element on the driver transistor 31 side of the resistor 33 (Figure 1) ２This is equivalent to setting it to zero. In this case, as can be seen from equation (2), the output voltage Vreg becomes equal to the reference voltage Vref.

[0044] In the first embodiment, the first resistor voltage divider circuit 38 and the output node of the voltage regulator 30 are directly connected. Therefore, as shown in Figure 2, the power supply voltage Vdd １ The bias voltage Vg is within the range of the lower control limit value Vreg_min of the output voltage Vreg. ２ This is approximately constant. A resistor may be inserted between the first resistor voltage divider circuit 38 and the output node of the voltage regulator 30. In this configuration, the bias voltage Vg shown in Figure 2 ２ However, the power supply voltage Vdd １ It rises in line with the rise of [something].

[0045] First transistor Q of the cascode amplifier circuit according to the first embodiment １ and the second transistor Q ２ An NMOSFET is used, but a bipolar transistor may also be used. First transistor Q １ and the second transistor Q ２ When using a bipolar transistor, in the above explanation, the first transistor Q １ and the second transistor Q ２ Simply replace the source, drain, and gate with emitter, collector, and base, respectively.

[0046] [Second Embodiment] Next, a cascode amplifier circuit according to the second embodiment will be described with reference to Figure 8. Hereinafter, the configuration common to the cascode amplifier circuit according to the first embodiment, described with reference to Figures 1 and 2, will be omitted from the explanation.

[0047] Figure 8 is an equivalent circuit diagram of a cascode amplifier circuit according to the second embodiment. In the cascode amplifier circuit according to the first embodiment (Figure 1), the voltage division ratio by the second resistor voltage divider circuit used in the resistor 33 of the voltage regulator 30 is fixed. In contrast, in the cascode amplifier circuit according to the second embodiment, the voltage division ratio by the resistor 33 is variable. The voltage division ratio is changed by control from the voltage division ratio adjustment circuit 42 of the control circuit 40. For example, the resistance value of at least one of the two resistive elements constituting the resistor 33 is variable. A resistive element with a variable resistance value can be realized, for example, by connecting multiple unit circuits in parallel, each of which a resistive element with a fixed resistance value and a switch element are connected in series. By controlling the on / off state of the switch element, the voltage division ratio of the resistor 33 can be changed.

[0048] As can be seen from equation (2), when the voltage division ratio by resistor 33 changes, the relationship between the output voltage Vreg and the reference voltage Vref changes.

[0049] Next, the excellent effects of the second embodiment will be described. In the second embodiment, as in the first embodiment, the power supply voltage Vdd １ This can suppress gain fluctuations when the voltage decreases. In addition, the reference voltage generation circuit 41 changes the reference voltage Vref according to the ambient temperature, thereby reducing the second transistor Q ２ Bias voltage Vg ２ , Vg ３ , Vg ４ , Vg ５ It is possible to introduce a temperature dependence to it.

[0050] Due to variations in the manufacturing process and the operating frequency range of the cascode amplifier circuit, the second transistor Q ２ The appropriate bias voltage may change. In the second embodiment, by changing the voltage division ratio by resistor 33, the second transistor Q ２ Bias voltage Vg ２ , Vg ３ , Vg ４ , Vg ５ It is possible to set it to an appropriate value.

[0051] [Third Embodiment] Next, a cascode amplifier circuit according to the third embodiment will be described with reference to Figure 9. Hereinafter, the configuration common to the cascode amplifier circuit according to the first embodiment, described with reference to Figures 1 and 2, will be omitted from the explanation.

[0052] Figure 9 is an equivalent circuit diagram of a cascode amplifier circuit according to the third embodiment. In the cascode amplifier circuit according to the first embodiment (Figure 1), the feedback circuit 35 directly connects the voltage divider point of the resistor 33 to the non-inverting input node of the operational amplifier 32. In contrast, in the third embodiment, the feedback circuit 35 generates a feedback voltage Vfb based on the voltage at the voltage divider point of the resistor 33 and a reference potential. For example, the feedback circuit 35 includes two resistor elements 35A and 35B connected in series. One resistor element 35A is connected between the non-inverting input node to which the feedback voltage Vfb of the operational amplifier 32 is applied and the voltage divider point of the resistor 33, while the other resistor element 35B is connected between the non-inverting input node of the operational amplifier 32 and the reference potential.

[0053] In the first embodiment, the feedback voltage Vfb is greater than or equal to the output voltage Vreg of the voltage regulator 30. Since the output voltage Vreg is controlled so that the feedback voltage Vfb is equal to the reference voltage Vref, the reference voltage Vref must be set to be greater than or equal to the output voltage Vreg. In contrast, in the third embodiment, the feedback voltage Vfb can be made less than the output voltage Vreg by adjusting the resistance values ​​of the resistor 33 and the feedback circuit 35, a total of four resistor elements. Thus, the feedback circuit 35 of the cascode amplifier circuit according to the third embodiment has a configuration that generates a voltage lower than the output voltage Vreg as the feedback voltage Vfb. Therefore, it becomes possible to set the reference voltage Vref to a value less than the output voltage Vreg.

[0054] Next, the excellent effects of the third embodiment will be described. In the third embodiment, as in the first embodiment, the power supply voltage Vdd １This makes it possible to suppress gain fluctuations when the voltage decreases. Furthermore, in the third embodiment, it becomes possible to set the reference voltage Vref to a value less than the output voltage Vreg, thus increasing the flexibility in setting the reference voltage Vref. For example, when using the silicon bandgap voltage (approximately 1.2V) as the reference voltage Vref, in the first embodiment, it is not possible to control the output voltage Vreg to a constant value greater than or equal to the silicon bandgap voltage. In contrast, in the third embodiment, it is possible to control the output voltage Vreg to a constant value greater than or equal to the silicon bandgap voltage.

[0055] [Fourth Embodiment] Next, a cascode amplifier circuit according to the fourth embodiment will be described with reference to Figure 10. The following description will omit details of components common to the cascode amplifier circuit according to the third embodiment, which was described with reference to Figure 9.

[0056] Figure 10 is an equivalent circuit diagram of a cascode amplifier circuit according to the fourth embodiment. In the cascode amplifier circuit according to the third embodiment (Figure 9), the feedback circuit 35 includes a resistor 35A inserted between the voltage divider point of the resistor 33 and the non-inverting input node of the operational amplifier 32. In contrast, in the cascode amplifier circuit according to the fourth embodiment, the voltage divider point of the resistor 33 and the non-inverting input node of the operational amplifier 32 are directly connected. The non-inverting input node of the operational amplifier 32 is connected to a reference potential via a resistor 35B, similar to the third embodiment.

[0057] Power supply voltage Vdd for the regulator of resistor 33 ２ The resistance value of the resistor element on the side is R １ The resistance value of the resistor element on the driver transistor 31 side is R ２ The resistance value of the resistor element 35B of the feedback circuit 35 is R ３ When denoted as such, the feedback voltage Vfb is expressed by the following equation: Vfb = (R ２ R ３ / R ０ ) Vdd ２ + (R １ R ３ / R ０ ) Vreg... (3) Here, R ０ It was defined as follows: R ０= R １ R ２ +R ２ R ３ +R ３ R １ ... (4)

[0058] Resistance value R ３ Resistance value R １ , R ２ If the value is made sufficiently small compared to the output voltage Vreg, the feedback voltage Vfb will become lower than the output voltage Vreg.

[0059] Next, the excellent effects of the fourth embodiment will be described. In the fourth embodiment, as in the third embodiment, the feedback voltage Vfb can be made lower than the output voltage Vreg. Therefore, as in the third embodiment, the excellent effect of increased flexibility in setting the reference voltage Vref can be obtained.

[0060] The embodiments described above are illustrative, and it goes without saying that partial substitution or combination of the configurations shown in different embodiments is possible. Similar effects and benefits from similar configurations in multiple embodiments will not be mentioned sequentially for each embodiment. Furthermore, the present invention is not limited to the embodiments described above. For example, it will be obvious to those skilled in the art that various modifications, improvements, and combinations are possible.

[0061] 20 Bias circuit 30 Voltage regulator 31 Driver transistor 32 Operational amplifier 33 Resistor 35 Feedback circuit 35A, 35B Resistor element 38 First resistor voltage divider circuit 40 Control circuit 41 Reference voltage generation circuit 42 Voltage divider ratio adjustment circuit 45 Digital circuit 46 Electronic fuse 50 Power supply wiring 51 Variable power supply circuit 70 Bias circuit 71, 75 Impedance control circuit Q １ First transistor Q ２ Second transistor

Claims

1. A cascode amplifier comprising: a first transistor to which a high-frequency signal is input; at least one second transistor cascode-connected to the first transistor; a bias circuit that supplies a bias to the second transistor; and a power supply wiring that applies a variable power supply voltage to the cascode connection circuit including the first transistor and the second transistor, wherein the bias circuit includes a voltage regulator and a first resistor voltage divider circuit, and the first resistor voltage divider circuit supplies a bias voltage divided based on the output voltage of a voltage control node whose voltage is controlled by the voltage regulator and the power supply voltage of the power supply wiring to the second transistor.

2. The cascode amplifier circuit according to claim 1, wherein at least one of the second transistors comprises a plurality of second transistors, and the first resistor voltage divider circuit generates a plurality of bias voltages divided based on the output voltage and the power supply voltage, and supplies each of the plurality of bias voltages to the plurality of second transistors.

3. The cascode amplifier circuit according to claim 1 or 2, wherein the voltage regulator comprises a driver transistor connected between the voltage control node and a reference potential, a resistor connected between the voltage control node and the power supply voltage for the regulator, an operational amplifier that supplies a control voltage to the driver transistor, a feedback circuit that supplies a feedback voltage based on the output voltage and the power supply voltage for the regulator to one input node of the operational amplifier, and a control circuit that supplies a reference voltage to the other input node of the operational amplifier.

4. The cascode amplifier circuit according to claim 3, wherein the control circuit changes the reference voltage according to the ambient temperature.

5. The cascode amplifier circuit according to claim 3 or 4, wherein the resistor includes a second resistor voltage divider circuit connected between the voltage control node and the power supply voltage for the regulator, and the feedback circuit generates the feedback voltage based on the voltage divided by the second resistor voltage divider circuit.

6. The cascode amplifier circuit according to claim 5, wherein the voltage division ratio of the second resistor voltage divider circuit is variable, and the voltage division ratio of the second resistor voltage divider circuit is changed by control from the control circuit.

7. The cascode amplifier circuit according to claim 6, wherein the control circuit includes an electronic fuse and controls the voltage division ratio of the second resistor voltage divider circuit based on the conduction state of the electronic fuse.

8. The cascode amplifier circuit according to any one of claims 3 to 7, wherein the feedback circuit is configured to generate a voltage lower than the voltage of the voltage control node as the feedback voltage.

9. The cascode amplifier circuit according to claim 8, wherein the feedback circuit includes a resistive element connected between the input node to which the feedback voltage of the operational amplifier is applied and a reference potential.

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