Semiconductor device and method for manufacturing semiconductor device

Abstract

The present invention achieves a semiconductor device which has high resistance to the entrapment of particles between electrodes, achieves electrical connection between the semiconductor device and a semiconductor device or a substrate, and is less prone to peeling of an insulating layer. A semiconductor device (1) in which a first semiconductor device (10) and a connected body (40), which is a second semiconductor device or a wiring device, are electrically connected by a plurality of columnar metal electrodes (54), wherein the columnar metal electrodes (54) have at least a layer containing tin as a main component and a layer containing copper as a main component, and an organic insulating material (80) is disposed around the columnar metal electrodes (54).

Description

Semiconductor Device and Method of Manufacturing the Same

[0001] The present invention relates to a semiconductor device and a method of manufacturing the same.

[0002] In the conventional hybrid bonding technology using a resin insulating material, the bonding of metal electrodes was performed by copper-to-copper bonding.

[0003] Japanese Patent Application Laid-Open No. 2023-151489

[0004] In the hybrid bonding technology using a resin insulating material, since the bonding of metal electrodes was performed by bonding a layer mainly composed of copper and a layer mainly composed of copper, when particles were bitten into the electrode portion during bonding, not only the bonding between the layer mainly composed of copper and the layer mainly composed of copper was not achieved, but also the bonding of the surrounding insulating material was not achieved, and there was a problem that the electrical connection between semiconductor elements and between a semiconductor element and a substrate was not made, and peeling occurred between insulating layers to be connected.

[0005] Therefore, an object of the present invention is to realize a semiconductor device that has high resistance to particle biting between electrodes, achieves electrical connection between a semiconductor device and a connected body such as another semiconductor device or a substrate, and hardly causes peeling of an insulating layer.

[0006] The semiconductor device of the present invention is a semiconductor device in which a first semiconductor device and a connected body that is a second semiconductor device or a wiring device are electrically connected by a plurality of columnar metal electrodes, the columnar metal electrodes have at least a layer mainly composed of tin and a layer mainly composed of copper, and an organic insulating material is disposed around the columnar metal electrodes.

[0007] The present invention provides a method for manufacturing a semiconductor device, comprising the steps of: forming an organic insulating film on one main surface of a semiconductor device; forming holes in the organic insulating film on the electrodes at locations corresponding to the positions of the electrodes on the semiconductor device; filling the holes with a metal mainly composed of copper and a metal mainly composed of tin to form columnar metal electrodes (formed so that the metal mainly composed of tin is at the position furthest from one main surface of the semiconductor device); and aligning the semiconductor device with a connected object which is another semiconductor device or wiring device, and connecting them by flip-chip (thermocompression bonding).

[0008] The present invention provides a method for manufacturing a semiconductor device, comprising the steps of: forming a resist film on one main surface of a semiconductor device; forming holes in the resist film at locations corresponding to the positions of electrodes on the semiconductor device by exposure and development; filling the holes with a metal mainly composed of copper and a metal mainly composed of tin to form columnar metal electrodes (formed so that the metal mainly composed of tin is at the position furthest from the main surface of the semiconductor device); removing the resist film; arranging an organic insulating film so as to cover the periphery of the columnar metal electrodes; performing a process to improve the flatness of the surfaces of the organic insulating film and the columnar metal electrodes; and aligning the semiconductor device with a connected object which is another semiconductor device or wiring device and connecting them by flip-chip (thermocompression bonding).

[0009] The present invention provides a method for manufacturing a semiconductor device, comprising the steps of: forming a first resist film on one main surface of a semiconductor device; forming holes in the first resist film at locations corresponding to the positions of electrodes on the semiconductor device by exposure and development; filling the holes with a metal mainly composed of copper to form a first portion of a columnar metal electrode; removing the first resist film; arranging an organic insulating film so as to cover the periphery of the first portion of the columnar metal electrode; forming a second resist film on the organic insulating film; forming holes in the second resist film at locations corresponding to the positions of the first portion of the columnar metal electrode by exposure and development; forming holes in the organic insulating film at locations corresponding to the positions of the first portion of the columnar metal electrode by dry etching; removing the second resist film; filling the holes with a metal mainly composed of tin to form a second portion of a columnar metal electrode; performing a process to improve the flatness of the surfaces of the organic insulating film and the first portion of the columnar metal electrode; and aligning the semiconductor device with a connected object, which is another semiconductor device or wiring device, and connecting them by flip-chip (thermocompression bonding).

[0010] The semiconductor device of the present invention has high resistance to particle jamming between electrodes, achieves high-density electrical connection between the semiconductor device and the connected object such as a semiconductor device or substrate, and is less prone to peeling of the insulating layer. Furthermore, the present invention provides a method for manufacturing a semiconductor device in which a first semiconductor device and a connected object, which is a second semiconductor device or wiring device, are electrically connected by a plurality of columnar metal electrodes, wherein the columnar metal electrodes have at least a layer mainly composed of tin and a layer mainly composed of copper, and an organic insulating material is arranged around the columnar metal electrodes.

[0011] Figure 1 is a cross-sectional view of a semiconductor device according to the first embodiment of the present invention. Figure 2 is a cross-sectional view of a semiconductor device according to the second embodiment of the present invention. Figure 3A is a diagram showing a cross-section of a semiconductor device. Figure 3B is a diagram showing a state in which an organic insulating material has been formed on the semiconductor device. Figure 3C is a diagram showing a state in which a resist film has been formed on the organic insulating material. Figure 3D is a diagram showing the state after the resist film has been lithographed. Figure 3E is a diagram showing the state after the resist film and organic insulating material have been dry etched. Figure 3F is a diagram showing the state after the resist film has been removed. Figure 3G is a diagram showing a state in which a seed layer has been formed on the surface of the organic insulating material, the first main surface, and the inner surface of the third recess. Figure 3H is a diagram showing a state in which an electrode layer has been formed in the third recess, etc. Figure 3I is a diagram showing a state in which the surface of the organic insulating material has been flattened. Figure 3J is a diagram showing a state in which the semiconductor device has been joined to a wiring device. Figure 4A is a diagram showing a cross-section of a semiconductor device according to the third embodiment of the present invention. Figure 4B is a diagram showing a cross-section of a semiconductor device according to the fourth embodiment of the present invention. Figure 5 is a diagram showing a cross-section of a semiconductor chip according to the third embodiment. Figure 6A is a cross-sectional view of the semiconductor chip body, etc., for explaining the manufacturing method of the semiconductor device according to the third embodiment. Figure 6B is a cross-sectional view of a semiconductor chip body and the like for illustrating a method for manufacturing a semiconductor device according to the third embodiment. Figure 6C is a cross-sectional view of a semiconductor chip body and the like for illustrating a method for manufacturing a semiconductor device according to the third embodiment. Figure 6D is a cross-sectional view of a semiconductor chip body and the like for illustrating a method for manufacturing a semiconductor device according to the third embodiment. Figure 6E is a cross-sectional view of a semiconductor chip body and the like for illustrating a method for manufacturing a semiconductor device according to the third embodiment. Figure 6F is a cross-sectional view of a semiconductor chip body and the like for illustrating a method for manufacturing a semiconductor device according to the third embodiment. Figure 6G is a cross-sectional view of a semiconductor chip body and the like for illustrating a method for manufacturing a semiconductor device according to the third embodiment. Figure 6H is a cross-sectional view of a semiconductor chip body and the like for illustrating a method for manufacturing a semiconductor device according to the third embodiment. Figure 6I is a cross-sectional view of a semiconductor chip body and the like for illustrating a method for manufacturing a semiconductor device according to the third embodiment. Figure 6J is a cross-sectional view of a semiconductor chip body and the like for illustrating a method for manufacturing a semiconductor device according to the third embodiment.Figure 7A is a cross-sectional view of a semiconductor chip body, etc., for illustrating the alignment process in the manufacturing method of a semiconductor device according to the third embodiment. Figure 7B is a cross-sectional view of a semiconductor chip body, etc., for illustrating the temporary crimping process in the manufacturing method of a semiconductor device according to the third embodiment. Figure 7C is a cross-sectional view of a semiconductor chip body, etc., for illustrating the final crimping process in the manufacturing method of a semiconductor device according to the third embodiment. Figure 8 is a flowchart showing the flow of the manufacturing method of a semiconductor device according to the third embodiment. Figure 9A is a diagram showing a modified example of the manufacturing method of a semiconductor device according to the third embodiment. Figure 9B is a diagram showing a modified example of the manufacturing method of a semiconductor device according to the third embodiment. Figure 10A is a cross-sectional view of a semiconductor device according to the fifth embodiment of the present invention. Figure 10B is a cross-sectional view of a semiconductor device for comparison. Figure 10C is a cross-sectional view of a semiconductor device according to the sixth embodiment of the present invention. Figure 11A is a cross-sectional view of a semiconductor device according to the seventh embodiment of the present invention. Figure 11B is a cross-sectional view of a semiconductor device according to another example of the seventh embodiment of the present invention. Figure 11C is a cross-sectional view of a semiconductor device according to another example of the seventh embodiment of the present invention. Figure 11D is a cross-sectional view of a semiconductor device according to the eighth embodiment of the present invention. Figure 12 is a cross-sectional view of a semiconductor device according to the ninth embodiment of the present invention. Figure 13A is a cross-sectional view of a semiconductor device according to the tenth embodiment of the present invention. Figure 13B is a cross-sectional view of a semiconductor device according to the eleventh embodiment of the present invention. Figure 13C is a cross-sectional view of a semiconductor device according to the twelfth embodiment of the present invention. Figure 14 is a cross-sectional view of a semiconductor device according to the thirteenth embodiment of the present invention. Figure 15A is a cross-sectional view of a semiconductor device according to the fourteenth embodiment of the present invention. Figure 15B is a cross-sectional view of a semiconductor device according to the fifteenth embodiment of the present invention. Figure 15C is a cross-sectional view of a semiconductor device according to the sixteenth embodiment of the present invention. Figure 16A is a cross-sectional view of a semiconductor device according to the seventeenth embodiment of the present invention. Figure 16B is a cross-sectional view of a semiconductor device according to the eighteenth embodiment of the present invention. Figure 17A is a cross-sectional view of a semiconductor device according to the nineteenth embodiment of the present invention. Figure 17B is a cross-sectional view of a semiconductor device according to the twentyth embodiment of the present invention. Figure 18A is a cross-sectional view of a modified semiconductor device according to the tenth embodiment of the present invention. Figure 18B is a cross-sectional view of a modified semiconductor device according to the fourteenth embodiment of the present invention. Figure 19A is a cross-sectional view of a modified semiconductor device according to the seventeenth embodiment of the present invention. Figure 19B is a cross-sectional view of a modified semiconductor device according to the nineteenth embodiment of the present invention.Figure 20A is a cross-sectional view showing the manufacturing process of the first manufacturing method according to an embodiment of the present invention. Figure 20B is a cross-sectional view showing the manufacturing process following Figure 20A. Figure 20C is a cross-sectional view showing the manufacturing process following Figure 20B. Figure 21A is a cross-sectional view showing the manufacturing process of the second manufacturing method according to an embodiment of the present invention. Figure 21B is a cross-sectional view showing the manufacturing process following Figure 21A. Figure 21C is a cross-sectional view showing the manufacturing process following Figure 21B. Figure 21D is a cross-sectional view showing the manufacturing process following Figure 21C. Figure 21E is a cross-sectional view showing the manufacturing process following Figure 21D. Figure 22A is a cross-sectional view showing the manufacturing process of the third manufacturing method according to an embodiment of the present invention. Figure 22B is a cross-sectional view showing the manufacturing process following Figure 22A. Figure 22C is a cross-sectional view showing the manufacturing process following Figure 22B. Figure 22D is a cross-sectional view showing the manufacturing process following Figure 22C. Figure 22E is a cross-sectional view showing the manufacturing process following Figure 22D. Figure 22F is a cross-sectional view showing the manufacturing process following Figure 22E. Figure 22G is a cross-sectional view showing the manufacturing process following Figure 22F. Figure 22H is a cross-sectional view showing the manufacturing process following Figure 22G. Figure 23 is a cross-sectional view showing another manufacturing method.

[0012] A semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. (First Embodiment) The semiconductor device according to the first embodiment of the present invention will be referred to as semiconductor device 1. Figure 1 is a cross-sectional view of semiconductor device 1 according to the first embodiment of the present invention. As shown in Figure 1, semiconductor device 1 comprises a semiconductor device 10, a connection portion 50, and a wiring device 30. The semiconductor device 10 is electrically connected to the wiring device 30 via the connection portion 50.

[0013] (Semiconductor Devices and Wiring Devices) The semiconductor device 10 is a semiconductor component in which semiconductor elements are formed on, for example, a silicon wafer. An example of the semiconductor device 10 is a semiconductor chip. The semiconductor device 10 comprises a first substrate 12 and a first electrode 16. The first substrate 12 is a substrate on which semiconductor elements are formed in the semiconductor device 10, such as a silicon wafer. An electrode formed on one surface of the semiconductor device 10 is defined as the first electrode 16. The surface on which the first electrode 16 is formed in the semiconductor device 10 is defined as the first main surface 14.

[0014] (Wiring Device) The wiring device 30 is a component on which a wiring layer is formed, for example, on a silicon wafer. An example of the wiring device 30 is an interposer. The wiring device 30 may also include semiconductor elements. Examples of the wiring device 30 include a semiconductor device that includes active elements such as semiconductor elements, a substrate consisting only of wiring and not including active elements such as a silicon interposer, and an RDL interposer on which a wiring layer is formed on a carrier made of glass or the like, and then peeled off from the carrier to leave only the wiring layer. The wiring device 30 includes a second substrate 32 and a second electrode 36. The second substrate 32 is a portion of the wiring device 30 that serves as the substrate on which a wiring layer is formed, for example, a silicon wafer. An electrode formed on one surface of the wiring device 30 is defined as the second electrode 36. The surface on which the second electrode 36 is formed in the wiring device 30 is defined as the second main surface 34.

[0015] A deep trench capacitor may be formed in the silicon interposer, and passive elements such as silicon capacitors and inductors may be built into the RDL interposer.

[0016] Furthermore, in structures where semiconductor devices are connected to wiring devices, forming a molded resin or silicon oxide film around the semiconductor device is preferable because it prevents stress concentration at the connection point between the semiconductor device and the wiring device, thereby improving connection reliability. The mold will be explained later with reference to the drawings.

[0017] (Connection part) The connection part 50 is the part that connects the semiconductor device 10 and the wiring device 30. The connection part 50 comprises a columnar metal electrode 54 and a resin part 52. The columnar metal electrode 54 is the part that electrically connects the first electrode 16 and the second electrode 36. The resin part 52 is the part made of resin that is arranged around the columnar metal electrode 54 in the connection part 50.

[0018] The resin portion 52 is made of an insulating resin. Examples of materials for the organic insulating material 80 include polyimide, polyamideimide, benzocyclobutene (BCB), and polybenzoxazole (PBO). Among these, polyimide having an imide ring is preferably used due to its high heat resistance and reliability. The presence or absence of an imide ring can be confirmed by FT-IR measurement.

[0019] The columnar metal electrode 54 can be formed from layers mainly composed of copper, layers mainly composed of tin, and so on. In the example shown in Figure 1, the columnar metal electrode 54 comprises a first electrode portion 61, a second electrode portion 62, and a third electrode portion 63. These are arranged in the order of the first electrode portion 61, the third electrode portion 63, and the second electrode portion 62, starting from the first main surface 14. The first electrode portion 61 is in contact with the first main surface 14. The second electrode portion 62 is in contact with the second main surface 34. The first electrode portion 61 and the second electrode portion 62 can be formed from different materials than the third electrode portion 63. For example, the first electrode portion 61 and the second electrode portion 62 can be formed from layers mainly composed of copper, and the third electrode portion 63 can be formed from a metal mainly composed of tin. As will be explained later, when joining the semiconductor device 10 and the wiring device 30 by hybrid bonding, the provision of a third electrode portion 63 made of a metal mainly composed of tin makes it possible to easily connect the first electrode 16 and the second electrode 36. The tin-based layer may contain voids. The inclusion of voids in the tin-based layer allows it to absorb stress when external stress is applied.

[0020] When a tin-based metal is melted, mutual diffusion of metal components from the copper-based layer and the tin-based layer may occur. Therefore, a barrier layer to suppress this diffusion may be provided between the copper-based layer and the tin-based layer. The material of the barrier layer is not particularly limited as long as it can suppress mutual diffusion between the copper-based layer and the tin, but nickel, cobalt, tantalum, tungsten, titanium, etc., can be used. The barrier layer may be formed between the first electrode portion 61 and the third electrode portion 63, and between the second electrode portion 62 and the third electrode portion 63.

[0021] It is preferable that an inorganic barrier layer is formed at the interface between the columnar metal electrode 54 and the organic insulating layer (resin part). The inorganic barrier layer prevents metal atoms contained in the copper-based layer or tin-based layer from diffusing into the organic insulating resin (organic insulating material) and causing short-circuit failures. The inorganic barrier layer can be a metal oxide film or metal film such as a silicon oxide film, silicon carbonitride film, silicon nitride film, tantalum nitride film, tantalum film, tungsten film, nickel film, titanium film, cobalt film, hafnium oxide film, or zirconium oxide film. It is preferable to use an insulating inorganic barrier layer such as a metal oxide film as the inorganic barrier layer. This makes it possible to improve the insulation between the columnar metal electrodes 54 even when the pitch between the columnar metal electrodes 54 is small. The barrier layer will be described later with reference to the drawings.

[0022] (Axial and Principal Surface Directions) The direction indicated by arrow 1010 in Figure 1 is defined as the axial direction 1010 of the columnar metal electrode 54. The axial direction 1010 is also the connection direction between the semiconductor device 10 and the wiring device 30. The direction indicated by arrow 1020 in Figure 1 is perpendicular to the axial direction 1010. The direction of arrow 1020 is defined as the principal surface direction 1020. The principal surface direction 1020 is parallel to the first principal surface 14 and the second principal surface 34.

[0023] (Electrode Pitch) The length D201 shown in Figure 1 is the pitch of the first electrode 16 in the main surface direction 1020. The length D202 shown in Figure 1 is the pitch of the second electrode 36 in the main surface direction 1020. Both length D201 and length D202 are preferably 25 μm or less, and more preferably 5 μm or less. In other words, for both the first electrode 16 and the second electrode 36, the pitch in the main surface direction 1020 is preferably 25 μm or less, and more preferably 5 μm or less.

[0024] The length D203 shown in Figure 1 is the pitch of the columnar metal electrode 54 in the main surface direction 1020. The length D203 is preferably 25 μm or less, and more preferably 5 μm or less. In other words, the pitch of the columnar metal electrode 54 in the main surface direction 1020 is preferably 25 μm or less, and more preferably 5 μm or less.

[0025] The pitches of the first electrode 16, the second electrode 36, and the columnar metal electrode 54 in the main surface direction 1020 correspond to each other. Here, "corresponding" means that they are substantially the same.

[0026] (Pitch) The length D201 shown in Figure 1 is defined as the pitch D201.

[0027] (Area-equivalent diameter of columnar metal electrode) The area-equivalent diameter (diameter) of the columnar metal electrode 54 in a cross section perpendicular to the axial direction 1010 is defined as the area-equivalent diameter (area-equivalent diameter of circle). The area-equivalent diameter (area-equivalent diameter of circle) is the value of the diameter of a perfect circle having an area equal to the area of ​​the cross section of the columnar metal electrode 54.

[0028] The area-equivalent diameter of the columnar metal electrode 54 is preferably less than 12 μm. More preferably, the area-equivalent diameter is 3 μm or less. The area-equivalent diameter may also be 2.5 μm or less.

[0029] The area-equivalent diameter is preferably 2 / 3 or less of the arrangement pitch D201. The area-equivalent diameter may also be half or less of the arrangement pitch D201.

[0030] As described above, in the semiconductor device 1 of this embodiment, the area-equivalent diameter of the columnar metal electrodes 54 is small. Therefore, even when the arrangement pitch D201 is small, the first electrode 16 and the second electrode 36 can be connected without causing short circuits or other problems between adjacent columnar metal electrodes 54.

[0031] The cross-sectional shape of the columnar metal electrode 54 in a cross-section perpendicular to the axial direction 1010 is not particularly limited. The cross-sectional shape can be, for example, circular or rectangular.

[0032] (Axial length of columnar metal electrode) The length D211 in Figure 1 represents the axial length 1010 of the columnar metal electrode 54. Length D211 is defined as the axial length D211. The axial length D211 is approximately equal to the axial distance 1010 between the first main surface 14 and the second main surface 34. The axial length D211 is more than twice the arrangement pitch D201.

[0033] The axial length D211 of the columnar metal electrode 54 is preferably 10 μm or more. More preferably, the axial length D211 is 15 μm or more. The axial length D211 of the columnar metal electrode 54 may be 8 μm or more.

[0034] As described above, in the semiconductor device 1 of this embodiment, when viewed in a cross-section parallel to the axial direction 1010 and the main surface direction 1020, the length of the columnar metal electrode 54 in the axial direction 1010 is considerably longer than the length of the columnar metal electrode 54 in the main surface direction 1020. In other words, when viewed in a cross-section parallel to the axial direction 1010 and the main surface direction 1020, the columnar metal electrode 54 has an elongated shape in the axial direction 1010. Therefore, even when the arrangement pitch is small, the volume of the columnar metal electrode 54 can be secured without causing short circuits between adjacent columnar metal electrodes 54. Thus, even when the arrangement pitch is small, a highly reliable metal connection can be obtained.

[0035] (Minimum length of resin portion) The length D205 in Figure 1 represents the length of the resin portion 52 in the main surface direction 1020, which is positioned between adjacent columnar metal electrodes 54. Here, if the length D205 of the resin portion 52 in the main surface direction 1020 differs depending on the position in the axial direction 1010, the shortest length D205 is defined as the minimum length of the resin portion D205. The area equivalent diameter of the columnar metal electrode 54 is preferably smaller than the minimum length of the resin portion D205. This makes it possible to make a high-density connection while ensuring the insulation of adjacent columnar metal electrodes 54.

[0036] (Linearity of columnar metal electrodes) The linearity of the columnar metal electrode 54 will be explained. The linearity of the columnar metal electrode 54 is how close to a straight line the line representing the side surface 56 of the columnar metal electrode 54 is in a cross section parallel to the axial direction 1010 and the main surface direction 1020. The linearity of the columnar metal electrode 54 can also be described as the flatness of the side surface 56. The linearity of the columnar metal electrode 54 will be explained below from the perspective of the outer diameter dimension D207 of the columnar metal electrode 54.

[0037] (Outer Diameter Dimension) The length D207 shown in Figure 1 is the length in the main surface direction 1020 of the columnar metal electrode 54 in a cross section parallel to the axial direction 1010 and the main surface direction 1020. If the columnar metal electrode 54 has a rectangular cross-section, the length D207 corresponds to the side dimension. If the columnar metal electrode 54 has a circular cross-section, the length D207 corresponds to the outer diameter dimension. Hereafter, the length D207 will be defined as the outer diameter dimension D207.

[0038] In the semiconductor device 1 of this embodiment, the outer diameter dimension D207 of the columnar metal electrode 54 at the point where it contacts the first main surface 14 is substantially the same as the outer diameter dimension D207 of the columnar metal electrode 54 at the point where it contacts the second main surface 34. The outer diameter dimension D207 of the columnar metal electrode 54 at the point where it contacts the first main surface 14 is defined as the first outer diameter dimension D2071. The outer diameter dimension D207 of the columnar metal electrode 54 at the point where it contacts the second main surface 34 is defined as the second outer diameter dimension D2072. The first outer diameter dimension D2071 and the second outer diameter dimension D2072 are substantially the same. "Substantially identical" means that the second outer diameter dimension D2072 is 95% to 105% of the outer diameter dimension D207 of the first outer diameter dimension D2071, and the first outer diameter dimension D2071 is 95% to 105% of the outer diameter dimension D207 of the second outer diameter dimension D2072.

[0039] Preferably, the outer diameter dimension D207 is substantially the same from the portion where the columnar metal electrode 54 contacts the first main surface 14 to the portion where the columnar metal electrode 54 contacts the second main surface 34. Here, the outer diameter dimension D207 at the central position between the first main surface 14 and the second main surface 34 is defined as the reference outer diameter dimension D2073. The outer diameter dimension D207 being substantially the same from the portion where the columnar metal electrode 54 contacts the first main surface 14 to the portion where the columnar metal electrode 54 contacts the second main surface 34 means that the outer diameter dimension D207 at any position between the portion where the columnar metal electrode 54 contacts the first main surface 14 and the portion where the columnar metal electrode 54 contacts the second main surface 34 is 95% or more and 105% or less of the reference outer diameter dimension D2073.

[0040] As described above, in the semiconductor device 1 of this embodiment, the outer diameter dimension D207 of the columnar metal electrode 54 does not change significantly from the portion in contact with the first main surface 14 to the portion in contact with the second main surface 34. This indicates that the columnar metal electrode 54 has high linearity. In the semiconductor device 1 of this embodiment, because the linearity of the columnar metal electrode 54 is high, the spacing between adjacent columnar metal electrodes 54 in the main surface direction 1020 can be narrowed. As a result, high-density wiring can be realized. Furthermore, even when the arrangement pitch is small, the volume of the columnar metal electrode 54 can be secured without causing short circuits between adjacent columnar metal electrodes 54. Therefore, even when the arrangement pitch is small, a highly reliable metal connection can be obtained.

[0041] (Arithmetic mean roughness of the side surface of the columnar metal electrode) The arithmetic mean roughness of the side surface 56 of the columnar metal electrode 54 will be explained. The side surface 56 of the columnar metal electrode 54 can be said to be the interface between the columnar metal electrode 54 and the resin part 52. In a cross-section along the axial direction 1010 of the columnar metal electrode 54, the arithmetic mean roughness Ra of the side surface 56 of the columnar metal electrode 54 is 0.03 μm or less. When the arithmetic mean roughness Ra of the side surface 56 is 0.03 μm or less, it is difficult for a gap to form between the resin part 52 and the side surface 56 of the columnar metal electrode 54, and therefore the durability of the semiconductor device 1 can be improved.

[0042] (Rectangularity of the longitudinal section of the columnar metal electrode) The rectangularity of the columnar metal electrode 54 in the longitudinal section along the axial direction 1010 of the columnar metal electrode 54, as shown in Figure 1, will be described. Here, rectangularity means (area inside the contour / area of ​​the circumscribing rectangle of the contour). To explain the rectangularity of the columnar metal electrode 54 of this disclosure in more detail, the rectangularity is the area formed by the contour of the columnar metal electrode 54 in the longitudinal section of the columnar metal electrode 54 divided by the minimum rectangular area that is circumscribing the contour of the columnar metal electrode 54 and is formed such that its area is minimized. For example, the rectangularity is calculated based on the longitudinal section of the columnar metal electrode 54 that passes through the center (centroid) of the cross section perpendicular to the axial direction 1010 of the columnar metal electrode 54. In the longitudinal section of the columnar metal electrode 54, the rectangularity of the columnar metal electrode 54 of this embodiment is 0.95 or more. By having a rectangularity of 0.95 or greater in the longitudinal cross-section of the columnar metal electrode 54, even when the outer diameter dimension D207 is small and the arrangement pitch is small, the volume of the columnar metal electrode 54 can be secured without causing short circuits between adjacent columnar metal electrodes 54. Therefore, a highly reliable metal connection can be obtained even when the arrangement pitch is small. However, it is difficult to make the rectangularity of the longitudinal cross-section of a columnar metal electrode placed in a recess processed by photolithography high, and it will be less than 0.9.

[0043] (Second Embodiment) The semiconductor device of the second embodiment of the present invention is referred to as semiconductor device 2. Figure 2 is a cross-sectional view of semiconductor device 2. The configuration of semiconductor device 2 will be described based on Figure 2. The semiconductor device 1 shown in Figure 1 had a three-layer structure consisting of a semiconductor device 10, a connection portion 50, and a wiring device 30. In contrast, the semiconductor device 2 shown in Figure 2 has a five-layer structure consisting of two layers each of the wiring device 30 and the connection portion 50. The following description will mainly focus on the differences between semiconductor device 2 and semiconductor device 1 shown in Figure 1.

[0044] The semiconductor device 2 shown in FIG. 2 has a structure in which a semiconductor device 10, a first connection part 501, a first wiring device 301, a second connection part 502, and a second wiring device 302 are stacked in the axial direction 1010 in order from the semiconductor device 10. The first connection part 501 and the second connection part 502 have the same configuration as the connection part 50 shown in FIG. 1. In contrast, the first wiring device 301 and the second wiring device 302 have a configuration different from the wiring device 30 shown in FIG. 1. Through electrodes are formed in the first wiring device 301 and the second wiring device 302, which is different from the wiring device 30. The through electrode formed in the first wiring device 301 is defined as a first through electrode 71. The through electrode formed in the second wiring device 302 is defined as a second through electrode 72. By forming the through electrodes, the first wiring device 301 and the second wiring device 302 of the semiconductor device 2 can function as three-dimensional stacked devices or interposers.

[0045] The layer configuration will be described in order from the semiconductor device 10. The first main surface 14 of the semiconductor device 10 is in contact with the third main surface 511 of the first connection part 501. At the interface between the first main surface 14 and the third main surface 511, the first electrode 16 of the semiconductor device 10 is electrically connected to the columnar metal electrode 54 of the first connection part 501.

[0046] The fourth main surface 512 of the first connection part 501 is in contact with the fifth main surface 311 of the first wiring device 301. At the interface between the fourth main surface 512 and the fifth main surface 311, the columnar metal electrode 54 of the first connection part 501 is electrically connected to the first through electrode 71 of the first wiring device 301.

[0047] The sixth main surface 312 of the first wiring device 301 is in contact with the seventh main surface 521 of the second connection part 502. At the interface between the sixth main surface 312 and the seventh main surface 521, the first through electrode 71 of the first wiring device 301 is electrically connected to the columnar metal electrode 54 of the second connection part 502.

[0048] The eighth main surface 522 of the second connection part 502 is in contact with the ninth main surface 321 of the second wiring device 302. At the interface between the eighth main surface 522 and the ninth main surface 321, the columnar metal electrode 54 of the second connection part 502 is electrically connected to the second through electrode 72 of the second wiring device 302.

[0049] On the tenth main surface 322 of the second wiring device 302, connection terminals 60 such as metal balls mainly composed of tin are provided at positions electrically contacting the second through electrode 72. The semiconductor device 1 is connected to, for example, an interposer or a printed wiring board via the connection terminals 60.

[0050] As shown in FIG. 2, by forming through electrodes in the wiring device, the semiconductor device 2 can include a plurality of layers of wiring devices. Thereby, more complicated wiring routing becomes possible.

[0051] (Manufacturing method) The manufacturing method of the semiconductor device 1 will be described based on FIGS. 3A to 3J. FIGS. 3A to 3J are diagrams for explaining the manufacturing method of the semiconductor device 1, and are diagrams showing a cross-section etc. of the first substrate 12. The manufacturing process proceeds in order from FIGS. 3A to 3J. FIGS. 3A to 3J are merely diagrams for explaining the outline of the manufacturing process. Therefore, in FIGS. 3A to 3J, illustration of those which do not have a great influence on the manufacturing process such as electrodes and wirings is omitted. Also, description thereof is omitted.

[0052] (Semiconductor device preparation process) FIG. 3A is a diagram showing a cross-section of the semiconductor device 10. In the semiconductor device preparation process, semiconductor elements, wirings, electrodes, etc. are formed on the first substrate 12 of the semiconductor device 10. The semiconductor elements, wirings, electrodes, etc. are not shown in FIG. 3A. The first substrate 12 can be, for example, a silicon substrate.

[0053] (Organic insulating material formation process) Figure 3B shows the state in which an organic insulating material 80 has been formed on the semiconductor device 10. In the organic insulating material formation process, the organic insulating material 80 is formed on the first main surface 14 of the first substrate 12. The organic insulating material 80 is formed by coating the first main surface 14 with an insulating resin, etc. The material of the organic insulating material 80 can be, for example, polyimide, polyamideimide, benzocyclobutene (BCB), polybenzoxazole (PBO), etc.

[0054] Among these, polyimides having imide rings are preferred due to their high heat resistance and reliability. In particular, non-photosensitive polyimides that do not contain photosensitive components are preferred because they provide high reliability. The presence or absence of imide rings can be confirmed by measurement using FT-IR. The organic insulating material may contain inorganic particles such as silica, alumina, zeolite, aluminum nitride, boron nitride, and silicon nitride, and may also contain organic particles such as crosslinked rubber particles, crosslinked or non-crosslinked polyimide particles, crosslinked polymer particles, polystyrene, polymethyl methacrylate, and polyurethane. By including these particles, the physical properties of the organic insulating material, such as elastic modulus, coefficient of linear expansion, thermal conductivity, dielectric constant, and dielectric loss, can be changed, enabling stress control, warping control, and heat dissipation control.

[0055] An example of a method for forming the organic insulating material 80 will be specifically described. When a liquid resin is used as the material for the organic insulating material 80, the liquid resin is applied to a first substrate 12 such as a semiconductor wafer, semiconductor chip, or silicon substrate by methods such as spin coating, slit coating, or spray coating, dried, and solidified by heating or light irradiation. When a film-like resin is used, the film-like resin is attached to the first substrate 12 and solidified by heating or light irradiation. When a solid resin is used, the solid resin is heated and melted to form a film on the first substrate 12.

[0056] (Resist Film Formation Process) Figure 3C shows the state in which a resist film 84 has been formed on the organic insulating material 80. The surface of the organic insulating material 80 is defined as the organic insulating material surface 82. In the resist film formation process, the resist film 84 is formed on the organic insulating material surface 82. The resist film 84 can be formed by a coating method or a printing method. The material of the resist film 84 is not particularly limited as long as it is a photosensitive resist material.

[0057] (Lithography Processing Process) Figure 3D shows the state of the resist film 84 after lithography processing. In the lithography processing process, the resist film 84 is processed by lithography to form predetermined intervals, predetermined size, predetermined shape, etc. The resist film 84 is removed in a predetermined pattern, and recesses, or holes, are formed in the resist film 84. Recesses are also called vias. The recesses formed in the resist film 84 shown in Figure 3D are defined as the first recesses 90. Inside the first recesses 90, the organic insulating material surface 82 of the organic insulating material 80 is exposed.

[0058] (Dry Etching Process) Figure 3E shows the state after the resist film 84 and organic insulating material 80 have been dry-etched. In the dry etching process, the organic insulating material 80 is dry-etched through the first recess 90 formed in the lithography process. This dry etching creates recesses that penetrate the resist film 84 and organic insulating material 80. The recess penetrating the resist film 84 and organic insulating material 80 shown in Figure 3E is defined as the second recess 92. Inside the second recess 92, the first main surface 14 of the semiconductor device 10 is exposed. Dry etching is performed in a vacuum chamber by introducing a gas mixed with oxygen to generate plasma. A parallel plate type, ICP type, microwave type, or a combination thereof can be used as the plasma generator.

[0059] In the dry etching process, in addition to the organic insulating material 80, a portion of the resist film 84 is also etched. The length of the resist film 84 in the axial direction 1010 shown in Figure 3D is defined as length D111. The length of the resist film 84 in the axial direction 1010 shown in Figure 3E is defined as length D112. As shown in Figures 3D and 3E, length D112 is shorter than length D111. In the examples shown in Figures 3D and 3E, length D112 is about half the length D111.

[0060] (Cross-sectional shape of the third recess) The second recess 92 is formed by dry etching. Therefore, the cross-sectional shape of the second recess 92 in the plane parallel to the axial direction 1010 and the main surface direction 1020 is closer to a rectangle than that of the first recess 90 shown in Figure 3D. Note that recesses processed by photolithography may be schematically depicted as rectangles in the cross-section along the axial direction of the recess in drawings, but in reality the degree of rectangularity is low, less than 0.9 or lower. Specifically, recesses processed by photolithography have rounded edges on both the via top and via bottom, as shown in Figure 3D, for example, resulting in a low degree of rectangularity in the cross-section along the axial direction of the recess. On the other hand, dry etching can form a recess with a very high degree of rectangularity in the cross-section along the axial direction of the recess. Specifically, recesses processed by dry etching have very sharp via tops and via bottoms, as shown in Figure 3F, resulting in a very high degree of rectangularity in the cross-section along the axial direction of the recess. As a result, the rectangularity of the cross-section of the columnar metal electrode 54 formed by the process described later, along the axial direction 1010 of the columnar metal electrode 54, can be made 0.95 or greater.

[0061] (Resist Removal Process) Figure 3F shows the state after the resist film 84 has been removed. In the resist removal process, the resist film 84 remaining after dry etching is removed. With the resist film 84 removed, only the patterned organic insulating material 80 remains on the semiconductor device 10. The recesses formed in the organic insulating material 80 are defined as the third recesses 94. The third recesses 94 are a part of the second recess 92 shown in Figure 3E on the first main surface 14 side. The resist can be removed using methods such as chemical solutions or oxygen plasma.

[0062] The process for forming the third recess 94 described above can be summarized as follows: An organic insulating material 80, which is the film on which the third recess 94, or via, is formed, is provided. Via formation through the organic insulating material 80 is performed by dry etching. Specifically, a photosensitive resist film 84 is formed on the organic insulating material 80, and only the photosensitive resist film 84 in the areas where via opening is to be performed on the organic insulating material 80 is removed by photolithography. Afterward, via opening is performed using a plasma etching apparatus. Etching gases that can be used include oxygen, argon, nitrogen, sulfur hexafluoride, nitrogen trifluoride, carbon tetrafluoride, methane fluoride, and hexafluorobutadiene.

[0063] The method for forming the third recess is not limited to the method described above. Alternatively, a metal film, such as a copper-based layer, can be formed on the organic insulating material by sputtering, a photosensitive resist film can be formed on top of it, and only the photosensitive resist in the areas where vias are to be made in the organic insulating material can be removed by photolithography. Subsequently, the metal film in the areas where the photosensitive resist has been removed can be removed by wet etching using an acid or alkali solution or by the aforementioned dry etching. After that, the organic insulating material can be dry-etched, and then the photosensitive resist and metal film on the surface of the organic insulating material can be removed. This makes it possible to form vias similar to the third recess. These removals can be performed by chemical dissolution or physical grinding or polishing.

[0064] Via formation can also be performed using imprinting methods, which involve pressing a needle-shaped mold into the uncured organic insulating material to create holes. In addition, holes can be created in the organic insulating film by irradiating it with laser light, such as an ultraviolet laser or an excimer laser. An example of a manufacturing method will be explained later with reference to the drawings.

[0065] (Cross-sectional shape of the third recess) The third recess 94 is a part of the second recess 92 formed by dry etching. Therefore, the cross-sectional shape of the third recess 94 in the plane parallel to the axial direction 1010 and the main surface direction 1020 is closer to a rectangle than that of the first recess 90 shown in Figure 3D.

[0066] (Aspect Ratio of the Third Recess) In Figure 3F, the length of the third recess 94 in the axial direction 1010 is shown as length D121. The length of the third recess 94 in the main surface direction 1020 is shown as length D122. The aspect ratio of the third recess 94, i.e., length D121 / length D122, can be greater than 1. It is more preferable that length D121 / length D122 is 4 or greater. The third recess 94 is formed by dry etching. Therefore, the aspect ratio of length D121 / length D122, that is, the aspect ratio of the third recess 94 in the cross section parallel to the axial direction 1010 and the main surface direction 1020, can be increased. In addition, the rectangularity of the cross section of the third recess 94 parallel to the axial direction 1010 and the main surface direction 1020 can be increased.

[0067] The length D251 in Figure 3F indicates the pitch D251 of the third recess 94 in the main surface direction 1020. In the semiconductor device 1 of this embodiment, as described above, the aspect ratio and rectangularity of the third recess 94 are large, so the pitch D251 can be reduced. Furthermore, even when the arrangement pitch is small, the volume of the plated electrode layer 88 which becomes the columnar metal electrode 54 can be secured.

[0068] (Inorganic Barrier Layer Formation Process) The inorganic barrier layer can be formed by depositing a film on the organic insulating material after via processing. The method is not limited, but CVD, PVD, ALD, etc., can be used. In these methods, a film is also deposited on the bottom of the via, so in the case of an insulating inorganic barrier layer in particular, it is necessary to remove the film formed on the bottom of the via. Dry etching removal can be performed using gases such as oxygen, nitrogen, argon, carbon fluoride, and sulfur fluoride. The inorganic barrier layer will be explained later with reference to the drawings.

[0069] (Seed sputtering process: Formation process of seed layer by sputtering method) When an inorganic barrier layer is used, the seed layer is formed by sputtering method after the inorganic barrier layer is formed. When an inorganic barrier layer is not used, the seed layer is formed by sputtering method after via formation on the organic insulating material. Figure 3G shows the state in which the seed layer 86 has been formed on the surface 82 of the organic insulating material and on the inner surface of the third recess 94. The seed layer 86 is formed by the seed layer sputtering method.

[0070] In the seed sputtering process, a seed layer 86 is formed by sputtering on the surface 82 of the organic insulating material, the inner surface of the third recess 94, and the first main surface 14 exposed by the third recess 94. The formed seed layer 86 becomes an electrode in the next step, the electroplating process. The conductive material used for the seed layer 86 is not particularly limited.

[0071] (Electroplating Process) Figure 3H shows the state in which an electrode layer 88 has been formed in the third recess 94 and the like. In the electroplating process, electroplating is performed using the seed layer 86 formed in the seed sputtering process as an electrode. By this electroplating, a plating electrode layer 88 is formed inside the third recess 94 and on the surface 82 of the organic insulating material. The material of the plating electrode layer 88 is not particularly limited. The material of the plating electrode layer 88 can be, for example, a layer mainly composed of copper, or a metallic material mainly composed of tin. It is preferable that the material of the plating electrode layer 88 comprises at least a metallic material mainly composed of tin. In addition, in the plating electrode layer 88, a layer mainly composed of copper and a layer mainly composed of tin may be laminated. When a layer mainly composed of copper and a layer mainly composed of tin are laminated, they may be laminated in the order of a layer mainly composed of copper, then a layer mainly composed of tin, starting from the first substrate 12. Furthermore, if a layer mainly composed of copper and a layer mainly composed of tin are laminated, the tin-based layer may be placed on the surface of the plating electrode layer 88.

[0072] As described above, the columnar metal electrode 54 shown in Figure 1 and other figures is formed to fill the third recess 94, or via, formed in the organic insulating material 80. The method of forming this columnar metal electrode 54 is not particularly limited as long as it fills the via. Methods include forming it with metal paste, forming it with electroless plating, and forming it with electroplating. In this embodiment, the case of performing electroplating is described as an example. When performing electroplating, a seed layer made of metal is formed on the surface of the organic insulating material 80 with the vias formed, and then electroplating is performed by applying current based on this seed layer until the vias are filled. The method and material of forming the seed layer are not particularly limited, but one method is to form a Ti layer and a layer mainly composed of copper in that order using a sputtering method.

[0073] (CMP Planarization Process) Figure 3I shows the state in which the organic insulating material surface 82, which is the surface of the organic insulating material 80, has been planarized. In the CMP (Chemical Mechanical Polishing) planarization process, the surface of the organic insulating material 80 and the like is planarized. In the planarization process, not only CMP but also a fly cutter can be used. The metal layer formed by electroplating, that is, the plated electrode layer 88, is also formed on the surface of the organic insulating material 80, so this is removed by the CMP treatment (CMP planarization process). During polishing, the thickness of the polishing is adjusted so that the columnar metal electrode 54 described above is realized. This polishing makes it possible to join the part shown in Figure 3I with other parts that also have a planarized organic insulating material surface 82 by hybrid bonding. When hybrid bonding two parts, it is preferable that the material of the organic insulating material 80 of each part is the same. In this planarization process, the plating electrode layer 88, which will become the columnar metal electrode 54, is polished so that the axial length D261 from the portion in contact with the first main surface 14, which is one of the main surfaces of the semiconductor device, to the organic insulating material surface 82, which is the polished surface, is greater than or equal to the arrangement pitch D201. Alternatively, the length D261 is polished so that the length remaining is greater than or equal to the diameter equivalent to the area of ​​the cross-section of the plating electrode layer 88, which will become the columnar metal electrode 54.

[0074] It is preferable that the maximum pitch between the formed columnar metal electrodes is 10 times or less, and particularly 3 times or less, the minimum pitch, as this facilitates achieving overall wafer flatness in the CMP process.

[0075] In regions where columnar metal electrodes are not formed, it is preferable that a layer mainly composed of copper, or a dummy pad made of tin, be formed on the surface of the semiconductor device and / or connected object, as this facilitates the achievement of overall wafer flatness in the CMP process. It is also preferable that the maximum pitch of the dummy pad formed on the surface of the semiconductor device and / or connected object is 10 times or less the minimum pitch, and more preferably 3 times or less. The dummy pad will be described later with reference to the drawings.

[0076] (Bonding Process) Figure 3J shows the state in which the semiconductor device 10 is bonded to the wiring device 30. In the bonding process, the semiconductor device 10 is aligned and connected to other components that have the same organic insulating material 80 and plating electrode layer 88 as the semiconductor device 10 shown in Figure 3I. Figure 3J shows the state in which the semiconductor device 10 and the wiring device 30 are bonded.

[0077] The organic insulating material 80 of the semiconductor device 10 and the organic insulating material 80 of the wiring device 30 are joined at their respective organic insulating material surfaces 82. In addition, the plated electrode layer 88 of the semiconductor device 10 and the plated electrode layer 88 of the wiring device 30 are joined.

[0078] The organic insulating material 80 of the semiconductor device 10 and the organic insulating material 80 of the wiring device 30 are joined together, and the plated electrode layer 88 of the semiconductor device 10 and the plated electrode layer 88 of the wiring device 30 are joined together to form a connection portion 50. More specifically, the organic insulating material 80 of the semiconductor device 10 and the organic insulating material 80 of the wiring device 30 are joined together to form a resin portion 52 of the connection portion 50. Preferably, the organic insulating material 80 of the semiconductor device 10 and the organic insulating material 80 of the wiring device 30 are joined together by hybrid bonding. The plated electrode layer 88 of the semiconductor device 10 and the plated electrode layer 88 of the wiring device 30 are joined together to form a columnar metal electrode 54.

[0079] The bonding described above will now be explained in detail. In order to bond semiconductor wafers together, semiconductor chips together, and semiconductor chips together and semiconductor wafers without voids, the surface of the organic insulating material 80 needs to be highly smooth. If the arithmetic mean roughness Ra of the surface of the organic insulating material, as measured by an atomic force microscope, is 1 nm or less, it becomes easier to suppress the generation of voids during bonding. Furthermore, if Ra is 0.5 nm or less, it becomes easier to suppress the generation of voids even when bonding at low pressure.

[0080] When bonding semiconductor wafers together, using a wafer bonding device makes it possible to align opposing columnar metal electrodes with high precision. When bonding semiconductor chips together or a semiconductor chip to a semiconductor wafer, using a flip-chip bonder makes it possible to align them with high precision.

[0081] The above-described manufacturing method can be modified in various ways. For example, in the above description, one plated electrode layer 88 was formed in the third recess 94. Multiple electrode layers 88 can also be formed in the third recess 94. For example, two types of electrode layers can be formed sequentially in the axial direction 1010 from the first main surface 14. In this case, one layer in contact with the main surface corresponds to the first electrode portion 61 or the second electrode portion 62 as described earlier based on Figure 1. The other layer corresponds to the third electrode portion 63. This makes it possible to form a columnar metal electrode 54 having a first electrode portion 61, a second electrode portion 62, and a third electrode portion 63, as shown in Figure 1. In this case, the third electrode portion 63 is formed by joining one electrode layer to be joined with the other electrode layer to be joined.

[0082] When forming multiple electrode layers 88 in the third recess 94, one layer in contact with the main surface can be formed from a copper-based layer, and the remaining layer can be formed from a tin-based metal material. This allows for the formation of the columnar metal electrodes 54, that is, the connection of the electrodes, to be carried out using a tin-based metal connection process such as reflow soldering.

[0083] Specifically, in order to form a tin-based metal layer at the tip of the columnar metal in the third recess 94, the copper-based layer located below the tin-based metal layer is formed first in the electroplating process, keeping the thickness of the copper-based layer in the via (third recess 94) below the depth of the via layer, and then the electroplating of the tin-based metal layer is performed. By setting (thickness of the copper-based layer) = (via depth) - (desired thickness of the tin-based metal layer), the required thickness of the copper-based layer can be obtained. A thickness of 3 μm or more for the tin-based metal layer is preferable because it achieves a tin-based metal connection of sufficient strength.

[0084] Furthermore, if the thickness of the tin-based metal layer is greater than or equal to the diameter of the columnar metal, even if particles become trapped in the joint, they are more easily absorbed by the deformation of the tin-based metal layer and the organic insulating material, regardless of the size of the particles, which is preferable.

[0085] When performing the above-described joining process, the joining is carried out by aligning the parts to be joined, applying pressure at a temperature below the melting point of the tin-based metal, and then heating to a temperature above the melting point of the tin-based metal. The pair of columnar metal electrode layers to be joined may have a tin-based metal layer formed at only one end, or tin-based metal layers formed at both ends. When heating at a temperature below the melting point of the tin-based metal, it is preferable to do so at a temperature above the glass transition temperature of the organic insulating material, as this reduces the likelihood of void formation and makes it easier for the resin surrounding the columnar metal electrode layers to deform in the film thickness direction, i.e., in the height direction of the column, thus facilitating the joining of the columnar metal electrode layers.

[0086] To summarize one aspect of semiconductor device 1 described above, it can be said that one important means of improving the performance of semiconductor systems is to use a semiconductor package structure that can increase the bandwidth of signal transmission between semiconductor chips, such as logic semiconductor chips and logic semiconductor chips, and logic semiconductor chips and memory semiconductor chips. There are two ways to increase the bandwidth of signal transmission: increasing the transfer rate per signal line and increasing the number of signal lines. Increasing the length of signal lines is effective in increasing the transfer rate per signal line in order to reduce loss during signal transmission. And adopting a structure in which semiconductor chips are stacked in three dimensions is effective for this. As a means of increasing the number of signal lines, it is effective to make the signal lines thinner and reduce the pitch between signal lines. Microbump technology is effective as a means of stacking semiconductor chips in three dimensions, making the signal wiring thinner and reducing the pitch between signal lines. This technology is a technology that electrically connects semiconductor chips stacked in three dimensions using columnar metal electrodes made of metal with a small cross-sectional area and short length.

[0087] As columnar metal electrodes, layers mainly composed of copper, metals mainly composed of tin, and metals with a tin-based metal formed at the tip of a copper-based layer can be used. Since high temperatures of 350°C or higher are required for bonding copper-based layers, it is effective to use a tin-based metal material for columnar metal electrodes. Using temperatures above 350°C may damage semiconductor performance, exceed the heat resistance limit of the materials used, or cause problems such as increased warping of the semiconductor package.

[0088] In bonding electrodes using a tin-based metal material, the tin-based metal material is melted during the bonding process. This process presents a challenge: if the pitch between bump electrodes is narrow, the tin-based metal material can short-circuit adjacent columnar metal electrodes. To prevent this, it is effective to fill the spaces between columnar metal electrodes with an insulating resin material before bonding the semiconductor chips. In this method, it is crucial that the insulating resin material is solidified before bonding to prevent flow during the bonding process. Furthermore, since both the columnar metal electrodes and the insulating resin need to be bonded during the bonding process, the surface of the insulating resin must be smoothed beforehand.

[0089] By reducing the cross-sectional area and pitch of columnar metal electrodes and arranging them at a high density, the number of signal lines connecting semiconductor chips can be increased, thereby increasing the bandwidth.

[0090] The Shore line of UCIe-1.0, the interface standard for chiplets, is 388.8 μm. With the currently implemented technology using a columnar metal electrode pitch of 55 μm, 57 rows of electrodes are required from the five chip edges into the interior. In contrast, if the array pitch is 5 μm or less, only 5 rows or less are required, and the wiring length for inter-chip connections can be shortened by 4 mm or more. This enables a significant reduction in power consumption and a large increase in the transfer rate per electrode. By setting the electrode cross-sectional area to 30 square μm or less, connection failures due to misalignment during semiconductor chip bonding become less likely. By setting the electrode cross-sectional area to 20 square μm or less, sufficient gaps can be secured between columnar metal electrodes, ensuring the insulation reliability between columnar metal electrodes.

[0091] A formation pitch of 25 μm or less is preferable because it enables high-density connection between chiplets in accordance with the UCIe-A standard. A formation pitch of 5 μm or less is preferable because it enables high-bandwidth connection between memory chips and logic chips, and between logic chips themselves, in three-dimensional mounting.

[0092] If the length of the columnar metal electrodes of the bonded semiconductor chip is 10 μm or more, the thickness of the insulating resin layer can be increased, which enhances the absorption capacity of embedded particles during bonding of the semiconductor chip or semiconductor wafer. If the length of the columnar metal electrodes of the semiconductor chip is 8 μm or more, brittle degradation of the columnar metal electrodes due to interdiffusion between the tin-based metal material and the copper-based layer is more easily suppressed.

[0093] If the resin contains at least one of polyimide, polybenzoxazole, and benzocyclobutene, degassing, degradation, and delamination due to the heat applied during metal electrode bonding become less likely to occur. Furthermore, since bonding of semiconductor wafers or semiconductor chips becomes possible at low pressure, it is preferable that the glass transition temperature of the resin material be below the melting point of the tin-based metal material.

[0094] As a tin-based metal material, metal Sn, Sn-Ag, Sn-Bi, Sn-Cu, and Sn-Ag-Cu alloys can be preferably used.

[0095] The method for manufacturing a semiconductor device according to this disclosure, for example, a semiconductor device in which two or more semiconductor chips are stacked, the semiconductor chips are electrically connected to each other via columnar metal electrodes containing a metal material mainly composed of tin, the gaps between the semiconductor chips other than the columnar metal electrodes are filled with resin, the length / diameter of the columnar metal electrodes is 4 or more, the close-packed arrangement pitch of the columnar metal electrodes is 5 μm or less, the cross-sectional area is 30 square μm or less, and the length is 10 μm or more, is not particularly limited, but can be realized by forming an organic insulating material on the surface of a semiconductor wafer or semiconductor chip, processing the organic insulating material to create vias that reach the surface of the semiconductor wafer by a dry etching method, then filling the vias with a metal material to produce metal electrodes, then performing a planarization process on the surface of the organic insulating material, and finally joining the metal electrodes and organic insulating material to semiconductor wafers or semiconductor chips that have been similarly manufactured so that their metal electrodes face each other.

[0096] The semiconductor device and the method for manufacturing the semiconductor device described above can also be expressed as follows.

[0097] (1) A semiconductor device in which a first semiconductor device and a connected object which is a second semiconductor device or a wiring device are electrically connected by a plurality of columnar metal electrodes, wherein the columnar metal electrodes have at least a layer mainly composed of tin and a layer mainly composed of copper, and an organic insulating material is arranged around the columnar metal electrodes.

[0098] (2) A method for manufacturing a semiconductor device comprises the steps of: preparing a semiconductor device having one main surface on which electrodes are arranged at a spacing pitch of 5 μm or less; forming an organic insulating film on one main surface on the semiconductor device; curing the organic insulating film; forming holes in the organic insulating film on the electrodes at locations corresponding to the positions of the electrodes (spacing of the electrodes) by dry etching; filling the holes with metal to form columnar metal electrodes; and aligning the semiconductor device with other wiring devices and connecting them by flip-chip (thermocompression bonding) connection.

[0099] (3) In the above-described method for manufacturing a semiconductor device, the area equivalent diameter of the cross-section perpendicular to the axial direction of the hole formed in the hole forming step is smaller than the arrangement pitch, and the area equivalent diameter of the cross-section perpendicular to the axial direction of the columnar metal electrode formed in the columnar metal electrode forming step is smaller than the arrangement pitch.

[0100] (4) In the method for manufacturing the semiconductor device described above, between the step of filling with the metal and the step of connecting by flip-chip (thermocompression bonding), the method includes a step of flattening the organic insulating film formed on one main surface and the columnar metal electrode.

[0101] (5) In the semiconductor device manufacturing method described above, in the planarization step, the columnar metal electrode is polished such that a length equal to or greater than the arrangement pitch remains as the axial length of the columnar metal electrode from the portion in contact with one main surface of the semiconductor device to the polished surface.

[0102] (6) In the method for manufacturing a semiconductor device as described above, in the planarization step, the columnar metal electrode is polished such that the axial length of the columnar metal electrode from the portion in contact with one main surface of the semiconductor device to the polished surface is equal to or greater than the diameter equivalent to the area of ​​the cross-section of the columnar metal electrode.

[0103] (Third Embodiment) A semiconductor device 3 according to an embodiment of the present invention will be described with reference to the drawings. Figure 4A is a cross-sectional view of the semiconductor device 3 according to an embodiment of the present invention. As shown in Figure 4A, the semiconductor device 3 has a configuration in which two semiconductor chips 127 are stacked and bonded together. One of the semiconductor chips 127 is called the first semiconductor chip 127A. The other semiconductor chip 127 is called the second semiconductor chip 127B. The semiconductor chips 127 are formed on a substrate such as a silicon wafer.

[0104] (Semiconductor Chip) The semiconductor chip 127 will be described with reference to Figure 5. Figure 5 is a cross-sectional view of the semiconductor chip 127.

[0105] (Semiconductor Chip Body) The semiconductor chip 127 includes the semiconductor chip body 110 and the bonding layer 130. The semiconductor chip body 110 is the portion on which semiconductor elements are formed on a silicon substrate or the like. The bonding layer 130 is the portion that joins the semiconductor chips 127 to each other when laminating and bonding two silicon substrates.

[0106] (Crimping Layer) The crimping layer 130 is formed on one main surface 112 of the semiconductor chip 127. The crimping layer 130 includes a metal crimping portion 134 and a resin crimping portion 136. The metal crimping portion 134 is a portion formed of a metal material. The metal material can be a material that constitutes an electrode. The resin crimping portion 136 is a portion formed of an organic insulating material. The organic insulating material can be a thermosetting type organic insulating material. The metal crimping portion 134 and the resin crimping portion 136 are formed continuously on the main surface 112 at predetermined intervals in a cross-sectional view on a plane perpendicular to the main surface 112 shown in Figure 5.

[0107] The following mainly describes the crimping layer 130. In the description, each part is denoted by the following symbols. The first semiconductor chip 127A and the second semiconductor chip 127B shown in Figure 4A have similar configurations. Therefore, for each part related to the semiconductor chip 127, the name of the first semiconductor chip 127A is given the prefix "first" and the symbol "A". Similarly, the name of the second semiconductor chip 127B is given the prefix "second" and the symbol "B".

[0108] (Joint) As shown in Figure 4A, the stack bonding of the first semiconductor chip 127A and the second semiconductor chip 127B is performed by bonding the first semiconductor chip body 110A and the second semiconductor chip body 110B via the joint 120.

[0109] The joint 120 is formed by the pressing of the first layer to be pressed 130A and the second layer to be pressed 130B together.

[0110] The joint portion 120 includes a metal joint portion 121 and a resin joint portion 122. The metal joint portion 121 is formed by the crimping of a first metal crimped portion 134A and a second metal crimped portion 134B. The resin joint portion 122 is formed by the crimping of a first resin crimped portion 136A and a second resin crimped portion 136B.

[0111] (Fourth Embodiment) Referring to Figure 4B, another configuration of the semiconductor device 3 of the third embodiment of the present invention will be described. Figure 4B is a diagram showing a cross-section of a semiconductor device 4 of another configuration of the embodiment of the present invention. Figure 4A shows an example of the configuration of the semiconductor device 3 in which a first semiconductor chip 127A and a second semiconductor chip 127B are stacked and bonded. Various modifications of the configuration of the semiconductor device 3 are possible. For example, as shown in Figure 4B, one of the two semiconductor chips 127 can be an interposer 115. In the example shown in Figure 4B, the first semiconductor chip 127A is replaced with an interposer 115 in the semiconductor device 3 shown in Figure 4A. In other words, the semiconductor device 4 shown in Figure 4B is configured by stacking and bonding an interposer 115 and a second semiconductor chip 127B.

[0112] The interposer 115 includes an interposer body 116 and a first crimpable layer 130A. The interposer body 116 is a portion on a silicon substrate or the like where vias such as through-silicon vias (TSVs), electrodes, and wiring layers are formed. These are not shown in Figure 4B. The first crimpable layer 130A included in the interposer 115 can be the same as the first crimpable layer 130A included in the first semiconductor chip 127A. In the semiconductor device 4 shown in Figure 4B, the first semiconductor chip body 110A is replaced by the interposer body 116. When the first semiconductor chip body 110A is replaced by the interposer body 116, the joint portion 120 may be provided on a part of the main surface 117 of the interposer body 116. This is because, as shown in Figure 4B, the size of the interposer 115 may be larger than that of the second semiconductor chip 127B.

[0113] (Method of Manufacturing Semiconductor Device) The method of manufacturing the semiconductor device 3 will be described below in order. As mentioned above, the semiconductor device 3 has a configuration in which a first semiconductor chip 127A and a second semiconductor chip 127B are stacked and bonded together. The first semiconductor chip 127A and the second semiconductor chip 127B are processed into a wafer with microbumps attached, that is, a microbump-formed wafer (also called an embedded microbump wafer), before being stacked and bonded together. The microbump-formed wafer has a configuration in which a bonding layer 130 is formed on the semiconductor chip body 110. The microbump-formed wafer is shown in Figure 6J. The microbump-formed wafer is also called an embedded microbump wafer.

[0114] First, the method for forming the bonding layer 130 on the semiconductor chip body 110 will be explained. After that, the method for bonding semiconductor chips together will be explained.

[0115] Before stacking and bonding, the microbump-forming wafer for the first semiconductor chip 127A and the microbump-forming wafer for the second semiconductor chip 127B have similar configurations. Hereinafter, the method for manufacturing the semiconductor device 3 will be described without distinguishing between the first semiconductor chip 127A and the second semiconductor chip 127B.

[0116] Figures 6A to 6J are cross-sectional views of the semiconductor chip body 110 and other components for illustrating the manufacturing method of the semiconductor device 3. Figures 6A to 6J are arranged in order of the manufacturing process.

[0117] Figure 8 is a flowchart showing the manufacturing method of the semiconductor device 3 according to this embodiment. In Figure 8 and the following description, S1 indicates step 1. The same applies to S2 and subsequent steps.

[0118] (Process for forming the resin-bonded portion) The resin-bonded portion formation process S1 will be explained based on Figures 6A to 6E. S1 is the process of forming the resin-bonded portion 136 on the semiconductor chip body 110.

[0119] (Organic insulating layer) As shown in Figure 6A, a polyimide layer 140 is formed on one main surface 112 of the semiconductor chip body 110. The organic insulating layer 140 is made of polyimide or polybenzoxazole. Polyimide is an example of a thermosetting organic insulating material. As the organic insulating material, a thermosetting type that does not have photosensitive function can be preferably used. To impart photosensitive function, it is necessary to include a photosensitive agent, and the photosensitive agent may cause a decrease in electrical and bonding reliability. An example of the thickness of the cured polyimide layer 140 is 8 μm.

[0120] The thermosetting organic insulating material used has a glass transition temperature of 140°C to 180°C. This allows for a lower temperature for the temporary crimping process, which will be explained later. It also helps to suppress a decrease in the reliability of the semiconductor device 3.

[0121] The glass transition temperature of the organic insulating material is more preferably 160°C or lower. This allows for a lower temperature during the initial crimping process.

[0122] (Upward direction) The upward direction 1500 is defined as the direction perpendicular to one main surface 112 of the semiconductor chip 127, away from that main surface 112. In the following description, up and down are based on the upward direction 1500.

[0123] (Photoresist layer) Next, as shown in Figure 6B, a photoresist layer 150 is formed on the organic insulating material layer 140.

[0124] (Pores in the photoresist layer) Next, as shown in Figure 6C, photoresist layer pores 152 are formed in the photoresist layer 150. The photoresist layer pores 152 are holes that penetrate the photoresist layer 150. The photoresist layer pores 152 can be formed, for example, using photolithography techniques involving exposure and development. An example of the shape of the photoresist layer pores 152 is cylindrical.

[0125] (Dry Etching) Next, as shown in Figure 6D, dry etching is performed using the photoresist layer 150 as a mask. An example of an etching gas used during dry etching is an oxygen-containing gas. By dry etching the organic insulating material layer 140, organic insulating material layer pores 142 are formed in the organic insulating material layer 140. The organic insulating material layer pores 142 are holes that penetrate the organic insulating material layer 140. An example of the shape of the organic insulating material layer pores 142 is a cylindrical shape.

[0126] (Resist Removal) Next, as shown in Figure 6E, the photoresist layer 150 remaining on the organic insulating material layer 140 is removed. The photoresist layer 150 can be removed, for example, by cleaning with acetone. As a result, a resin-bonded portion 136 with the organic insulating material layer 140 processed is formed on the semiconductor chip body 110.

[0127] (Metal-bonded portion formation process) The metal-bonded portion formation process S2 will be explained based on Figures 6F to 6I. S2 is the process of forming a metal-bonded portion 134 on the semiconductor chip body 110.

[0128] (Seed layer) As shown in Figure 6F, a seed layer 160 is formed on the surface of the organic insulating material layer 140. The seed layer 160 can consist of two layers, for example, a titanium seed layer and a copper seed layer, starting from the organic insulating material layer 140. The titanium seed layer and the copper seed layer can be formed, for example, by sputtering. An example of the thickness of the titanium seed layer is 50 nm. An example of the thickness of the copper seed layer is 150 nm.

[0129] (Copper layer) Next, as shown in Figure 6G, a copper layer 170 is formed in the pores 142 of the organic insulating material layer. The copper layer 170 is also called a copper post. The copper layer 170 can be formed by electrolytic copper plating. During electrolytic copper plating, the seed layer 160 is used as the electrode for electrolytic plating. An example of the thickness D70 of the copper layer 170 is 3 μm.

[0130] (Solder layer) Next, as shown in Figure 6H, a solder layer 180 is formed on the copper layer 170. The material of the solder layer 180 is not particularly limited, and alloys of tin and bismuth can be used, but it is preferable that the main component is tin and that the layer contains silver. A silver content of about 2 to 3% is preferable from the viewpoint of reliability and metallic bonding. The solder layer 180 can be formed by electroplating. An example of a solder layer 180 with a thickness D80 is 3 μm. A layer containing nickel or cobalt may be formed between the copper layer and the solder layer to suppress the mutual diffusion of copper and solder material.

[0131] In this way, a copper layer 170 as a copper post and a solder layer 180 as a solder layer are formed in order within the holes 142 of the organic insulating material layer. The metal layer formed within the holes 142 of the organic insulating material layer is called the metal layer 192. In the example shown in Figure 6H, the metal layer 192 includes the seed layer 160, the copper layer 170, and the solder layer 180. The metal layer 192 is formed not only within the holes 142 of the organic insulating material layer but also on the surface of the organic insulating material layer 140.

[0132] (Removal of copper and solder layers) Next, as shown in Figure 6I, the metal layer 192 formed on the organic insulating material layer 140, i.e., the seed layer 160, the copper layer 170, and the solder layer 180 are removed by grinding. This grinding can be done, for example, using a fry cutter. As a result, a metal crimped portion 134 with the copper layer 170 and solder layer 180 processed is formed on the semiconductor chip body 110.

[0133] (Surface polishing process) The surface polishing process S3 will be explained based on Figure 6J. S3 is a process of polishing the surfaces of the organic insulating material layer 140 and the metal layer 192.

[0134] (Chemical Mechanical Polishing) As shown in Figure 6J, the organic insulating layer 140 and the metal layer 192 are polished by the CMP (Chemical Mechanical Polishing) method. In the example shown in Figure 6J, the solder layer 180 in particular is polished in the metal layer 192. The thickness of the organic insulating layer 140 after polishing is defined as thickness D40. The sum of the thickness of the copper layer 170 and the thickness of the solder layer 180 after polishing is defined as the thickness D92 of the metal layer 192. Polishing can be made to make the thickness D40 of the organic insulating layer 140 and the thickness D92 of the metal layer 192 the same.

[0135] (Microbump-formed wafer) Within the holes 142 of the organic insulating material layer, the portion where a solder layer 180 is formed on the surface of the copper layer 170 is called a bump 190. The bump 190 is a metal joint portion 121 formed within the holes 142 of the organic insulating material layer.

[0136] Through the processing described above, a microbump-formed wafer 125 can be obtained in which the surface of the organic insulating material layer 140 is exposed and bumps 190 are embedded in the holes 142 of the organic insulating material layer. The microbump-formed wafer 125 is also called an embedded microbump wafer.

[0137] (Semiconductor Chip) The microbump-formed wafer 125 is diced to obtain a semiconductor chip 127. Dividing can be done, for example, by dicing. Examples of semiconductor chip 127 sizes include 7 mm x 7 mm and 10 mm x 10 mm. However, these sizes are illustrative. The size of the semiconductor chip 127 is not limited to these.

[0138] (Layer bonding by pressure) The layer bonding of semiconductor chips 127 will be explained with reference to Figures 7A to 7C. Two semiconductor chips 127 are layer-bonded by pressure bonding. In other words, two semiconductor chips 127 are bonded by pressure bonding.

[0139] The sizes of the two semiconductor chips 127 to be stacked and bonded may be the same or different. For example, a 7 mm x 7 mm semiconductor chip 127 and a 10 mm x 10 mm semiconductor chip 127 may be stacked and bonded. Alternatively, two 7 mm x 7 mm semiconductor chips 127, or two 10 mm x 10 mm semiconductor chips 127, may be stacked and bonded.

[0140] Referring to Figures 7A to 7C, the method for crimping semiconductor chips 127 together will be described. The crimping process includes, in order, an alignment step S4, a preliminary crimping step S5, and a final crimping step S6.

[0141] (Alignment Process) First, the alignment process S4 will be explained with reference to Figure 7A. Figure 7A is a cross-sectional view of the semiconductor chip body 110, etc., for explaining the alignment process.

[0142] (Surface direction and crimping direction) As shown in Figure 7A, the direction parallel to the main surface 112 is called the surface direction 1510. The direction perpendicular to the surface direction 1510 is called the crimping direction 1520.

[0143] In alignment step S4, the first semiconductor chip 127A and the second semiconductor chip 127B are aligned in the planar direction 1510. First, the first semiconductor chip body 110A and the second semiconductor chip body 110B are placed so that their main surfaces 112 face each other.

[0144] Next, the relative positions of the first semiconductor chip body 110A and the second semiconductor chip body 110B are adjusted so that at least one of the positions in the planar direction 1510 of the corresponding first metal crimped portion 134A and the second metal crimped portion 134B, and the positions of the corresponding first resin crimped portion 136A and the second resin crimped portion 136B coincide.

[0145] As shown in Figure 7A, in the alignment process S4, the first semiconductor chip 127A and the second semiconductor chip 127B are not in contact in the crimping direction 1520.

[0146] (Temporary Crimping Process) After the alignment process, the process proceeds to the temporary crimping process S5. The temporary crimping process S5 will be explained with reference to Figure 7B. In the temporary crimping process S5, the first resin crimping portion 136A and the second resin crimping portion 136B are heat-pressed together.

[0147] As shown in Figure 7B, the first semiconductor chip 127A and the second semiconductor chip 127B are placed on the thermal compression bonder 194 after alignment and are pressed together in the bonding direction 1520 by the thermal compression bonder 194. An example of the pressure applied during the initial bonding is 300 N. An example of the temperature during the initial bonding is 140 °C. In the initial bonding step S5, the first resin-bonded portion 136A and the second resin-bonded portion 136B are heat-bonded. This forms the resin joint portion 122 in the joint portion 120.

[0148] In the temporary crimping process, the first metal crimping portion 134A and the second metal crimping portion 134B are not crimped together. Therefore, the metal joint portion 121 is not formed in the temporary crimping process.

[0149] Furthermore, the temporary crimping temperature mentioned above is an example. The temporary crimping temperature can be, for example, between 100°C and 210°C.

[0150] (Main Crimping Process) After the preliminary crimping process S5, the process proceeds to the main crimping process S6. The main crimping process S6 will be explained with reference to Figure 7C. In the main crimping process S6, the first metal crimping portion 134A and the second metal crimping portion 134B are heat-pressed together.

[0151] As shown in Figure 7C, the first semiconductor chip 127A and the second semiconductor chip 127B, having completed temporary bonding, are placed on the thermal compression bonder 196 and bonded in the bonding direction 1520 by the thermal compression bonder 196. The thermal compression bonder used in this bonding step S6 may be the same as or different from the thermal compression bonder used in the temporary bonding step S5.

[0152] As described above, the resin joint 122 is formed in the temporary bonding step S5. Therefore, the first semiconductor chip 127A and the second semiconductor chip 127B are, so to speak, temporarily fixed in place. For this reason, even if a different thermal compression bonder is used in the main bonding step S6 than the one used in the temporary bonding step S5, the first semiconductor chip 127A and the second semiconductor chip 127B can be moved to the different thermal compression bonder without causing any problems such as misalignment.

[0153] The temperature for this crimping can be different from the temperature for the initial crimping, specifically higher than the initial crimping temperature. For example, the temperature for this crimping can be above 210°C, specifically 250°C. An example of the pressure applied during this crimping is 300 N.

[0154] In this crimping process, the first metal crimping portion 134A and the second metal crimping portion 134B are crimped together. As a result, a metal joint portion 121 is formed. This forms a joint portion 120 including the metal joint portion 121 and the resin joint portion 122.

[0155] With the above steps completed, the semiconductor device 3 is formed, and the flow diagram for the manufacturing method of the semiconductor device 3 in this embodiment is finished.

[0156] The semiconductor device and method for manufacturing the semiconductor device described above are examples of the present invention. A more detailed explanation of the semiconductor device and method for manufacturing the semiconductor device, as well as examples of modifications, will be provided below. The following explanation will use the case of joining semiconductor chips together as an example. However, the following explanation also applies to cases where a semiconductor chip is joined to an interposer or other substrate.

[0157] (Preliminary crimping and final crimping) As mentioned above, preliminary crimping and final crimping may be performed consecutively in a single device, or in separate devices. In the semiconductor device and method for manufacturing the semiconductor device according to the embodiment of the present invention, the semiconductor chip after preliminary crimping is less prone to misalignment. Therefore, it is easy to move the semiconductor chip to another device after preliminary crimping.

[0158] Preliminary and final crimping are relatively time-consuming processes. Performing these processes using different equipment can improve the productivity of semiconductor equipment.

[0159] Furthermore, if temporary and final crimping are performed using different devices, multiple semiconductor chips may be temporarily crimped onto a single semiconductor chip, and then the entire set of semiconductor chips may be crimped together using a separate device. This can further improve the productivity of semiconductor devices.

[0160] (Alignment) The alignment process before temporary bonding is explained below. Alignment can be performed while the two semiconductor chips are held in the bonding head of the thermal compression bonder. Alignment is performed by recognizing the alignment marks that have been pre-applied to both semiconductor chips. Through alignment, the bumps on the electronic semiconductor chips to be bonded are aligned.

[0161] (Temporary Crimping) After alignment, the semiconductor chips are temporarily crimped together. When performing temporary crimping, the temperature T1 of the crimping area should be below the melting point of the metal material contained in the bump.

[0162] (Crimping section) The crimping section refers to the part where the corresponding resin bonding sections of each semiconductor chip are pressed together. Specifically, the crimping section refers to the part where the first resin-bonded section 136A and the second resin-bonded section 136B are pressed together.

[0163] The smaller the difference between the temperature T1 and room temperature, the easier it is to achieve high positional accuracy during temporary crimping. In other words, it is possible to reduce positional deviations that occur during temporary crimping.

[0164] (When temporary and permanent bonding are performed consecutively in a single device) When temporary and permanent bonding are performed consecutively in a single device, after temporary bonding, the head temperature of the thermal compression bonder is increased while the semiconductor chip is still held in place. Then, metal bonding is performed by setting the temperature T2 of the contact area between the bumps on both semiconductor chips to the temperature at which atomic diffusion occurs between the metals of the two bumps. Temperature T2 can be, for example, the temperature at which the metal material contained in the bumps melts.

[0165] (Contact area) Here, the contact area refers to the part where the corresponding metal bonding areas of each semiconductor chip are pressed together. Specifically, the contact area refers to the part where the first metal crimped portion 134A and the second metal crimped portion 134B are pressed together.

[0166] (When temporary bonding and final bonding are performed in separate devices) When temporary bonding and final bonding are performed in separate devices, the temporarily bonded semiconductor chip is heated and pressurized by a bonding head in a final bonding device separate from the temporary bonding device to perform final bonding. Even when final bonding is performed in a separate device from temporary bonding, the temperature T2 at the contact area of ​​the bumps on both semiconductor chips must be such that atomic diffusion between the metals of both bumps occurs.

[0167] (In the case of solder) When solder material is used at the tip of the bump, a metal joint can be formed in a short time by setting the temperature T2 to be above the melting point of the solder material. In the microbump-forming wafer 125 illustrated in Figure 6J, the bump 190 in the pore 142 of the polyimide layer contains two layers: a copper layer 170 and a solder layer 180. The solder layer 180, which is the solder material, is located on the front side of the bump 190, that is, at the tip of the bump 190.

[0168] In this configuration, by setting the temperature T2 to be above the melting point of the solder layer 180, an efficient and reliable connection with the mating bump can be achieved.

[0169] The material of the bumps 190 within the polyimide layer pores 142 is not limited to the example shown in Figure 6J. For example, materials other than tin and silver can be used as soldering material. Also, the bumps 190 can be formed using only one type of metal material, such as copper only or soldering material only.

[0170] For example, when forming the bump 190 using only copper, electroplating can be performed so that (111)-oriented nanotwin forms when the copper is formed in the pores 142 of the polyimide layer.

[0171] Alternatively, when forming the bump 190 using only solder material, it is preferable to form a barrier layer against the solder material on the inner wall of the polyimide layer pore 142. By forming a barrier layer, it is possible to suppress the diffusion of the solder material into the semiconductor chip body 110. An example of a barrier layer is a nickel layer.

[0172] In Figure 7C, length D25 indicates the length of the metal joint 121 in the planar direction 1510 in the cross-section of the semiconductor device 3. In Figure 7C, length D26 indicates the length of the metal joint 121 in the crimping direction 1520 in the cross-section of the semiconductor device 3.

[0173] As bumps become smaller, their length D25 tends to decrease. On the other hand, in order to ensure a reliable connection with the mating bump, it is preferable that the volume of metal material contained in bump 190 be above a certain value.

[0174] Therefore, in the semiconductor device 3 of this embodiment, even if the length D25 becomes smaller, by keeping D26 at 3 μm or more, it becomes easier to ensure a reliable connection with the mating bump while miniaturizing the bump 190.

[0175] In Figure 7C, length D27 indicates the distance between the centers of adjacent metal joints 121. In the semiconductor device 3 of this embodiment, length D27 can be 20 micrometers or less. Preferably, length D27 can be 10 micrometers or less, and more preferably, length D27 can be 5 micrometers or less. This is because the semiconductor device 3 of this embodiment can suppress the solder overflow described earlier. By setting length D27 within the above range, it becomes possible to increase the density of connections.

[0176] (Substrate, etc.) The semiconductor chips and interposers used in the semiconductor device 3 only need to have embedded microbumps formed in predetermined positions, and these may be formed on silicon or on a different material. Furthermore, the size of the semiconductor chips and interposers, as well as the motherboard before they are cut out, is not particularly limited.

[0177] (Through-silicon vias) When semiconductor chips and interposers are formed on a silicon substrate, using a silicon substrate with through-silicon vias (TSVs) formed on it enables three-dimensional stacking of semiconductor chips. As a result, it becomes easier to achieve high-speed and high-density connectivity.

[0178] (Number of Layers) The above describes an example of stacking and bonding two semiconductor chips. However, the number of semiconductor chips stacked in the semiconductor device of this embodiment is not limited to two. For example, three semiconductor chips may be stacked and bonded in order to form three layers. Also, for example, two semiconductor chips may be stacked and bonded at different positions on a single interposer.

[0179] (Organic insulating material) The organic insulating material is not limited to the polyimide mentioned above. The organic insulating material can also be, for example, polybenzoxazole.

[0180] (Surface polishing process and temporary crimping process) As explained with reference to Figure 6J, the manufacturing method of the semiconductor device 3 of this embodiment includes a surface polishing process. In the surface polishing process, the organic insulating material layer 140 and the metal layer 192 are polished by chemical mechanical polishing (CMP) or the like. For example, after chemical mechanical polishing, the position 1500 upward on the surface of the organic insulating material layer 140 and the position 1500 upward on the surface of the metal layer 192 do not need to coincide. In other words, the surface of the crimped layer 130 does not need to be flat.

[0181] The organic insulating material forming the resin joint 122, such as the organic insulating layer 140, and the metal material forming the metal joint 121, such as the metal layer 192, have different coefficients of linear expansion. Generally, organic insulating materials have a higher coefficient of linear expansion than metal materials. Therefore, heating during the temporary crimping process causes the resin joint 122 to expand more than the metal joint 121.

[0182] Therefore, as shown in Figure 6J, for example, even if the surface of the microbump-forming wafer 125 is smooth, that is, the height of the resin bonding portion 122 (first resin-bonded portion 136A, second resin-bonded portion 136B) and the metal bonding portion 121 (first metal-bonded portion 134A, second metal-bonded portion 134B) is the same, as shown in Figure 7B, the first resin-bonded portion 136A and the second resin-bonded portion 136B can be bonded in the temporary bonding process without bonding the first metal-bonded portion 134A and the second metal-bonded portion 134B.

[0183] This prevents the metal material forming the metal-bonded portion 134 from protruding into the resin-bonded portion 136. This is because, in the preliminary bonding process, the joining of the first resin-bonded portion 136A and the second resin-bonded portion 136B is completed. Therefore, when the metal material melts in the main bonding process, no gap is formed between the first resin-bonded portion 136A and the second resin-bonded portion 136B.

[0184] As described above, the surface of the crimped layer 130 after the surface polishing process does not have to be flat. Also, if the surface of the crimped layer 130 is not flat, the resin joint portion 122 (first resin crimped portion 136A, second resin crimped portion 136B) may be higher than the metal joint portion 121 (first metal crimped portion 134A, second metal crimped portion 134B). In other words, the thickness D40 of the organic insulating material layer 140 may be thicker than the thickness D92 of the metal layer 192. Even in this case, in the temporary crimping process, the first resin crimped portion 136A and the second resin crimped portion 136B can be joined without joining the first metal crimped portion 134A and the second metal crimped portion 134B.

[0185] Furthermore, if the surface of the crimped layer 130 after the surface polishing process is not flat, the metal joint portion 121 (first metal crimped portion 134A, second metal crimped portion 134B) may be higher than the resin joint portion 122 (first resin crimped portion 136A, second resin crimped portion 136B). In other words, the thickness D92 of the metal layer 192 may be thicker than the thickness D40 of the organic insulating material layer 140. Even in this case, in the temporary crimping process, the first resin crimped portion 136A and the second resin crimped portion 136B can be joined without joining the first metal crimped portion 134A and the second metal crimped portion 134B. This will be explained with reference to Figures 9A and 9B. Note that the surface shape of the crimped layer 130 can be adjusted, for example, by appropriately changing the slurry in CMP. Specifically, by adjusting, for example, the material and particle size distribution of the abrasive particles contained in the slurry, the relative sizes of the thickness D92 of the metal layer 192 (height of the metal-bonded portion 134) and the thickness D40 of the organic insulating material layer 140 (height of the resin-bonded portion 136) shown in Figure 6J can be adjusted.

[0186] Figures 9A and 9B show modified examples of the manufacturing method of the semiconductor device 3 according to this embodiment. Figure 9A corresponds to Figure 6J described earlier. Figure 9B corresponds to Figure 7A described earlier.

[0187] In the example shown in Figure 6J, the thickness D40 of the organic insulating layer 140 and the thickness D92 of the metal layer 192 were equal. In contrast, in the example shown in Figure 9A, the thickness D92 of the metal layer 192 is greater than the thickness D40 of the organic insulating layer 140. The thickness D100 shown in Figure 9A represents the difference between the thickness D92 and the thickness D40.

[0188] As shown in Figure 9B, when the microbump-forming wafers 125 shown in Figure 9A are placed facing each other for alignment, the distance D36 between the first resin-bonded portion 136A and the second resin-bonded portion 136B is longer than the distance D34 between the first metal-bonded portion 134A and the second metal-bonded portion 134B. This is because there is a difference of thickness D100 between the thickness D92 and the thickness D40.

[0189] However, if temporary crimping is performed after alignment, the first resin crimping portion 136A and the second resin crimping portion 136B can be joined without joining the first metal crimping portion 134A and the second metal crimping portion 134B, as shown in Figure 7B. This is because the resin joint portion 122 expands more than the metal joint portion 121 due to heating during the temporary crimping process.

[0190] As described above, in the semiconductor device 3 of this embodiment, it is not necessary to flatten the surface of the bonded layer 130 after the surface polishing process. Therefore, it is not necessary to strictly control the polishing conditions in the surface polishing process.

[0191] Furthermore, the thickness D100 must satisfy the following equation: D100 < Expansion amount when the temperature rises from the time of D100 measurement in the crimping direction 1520 of the organic insulating material to the temporary crimping temperature - Expansion amount when the temperature rises from the time of D100 measurement in the crimping direction 1520 of the metal material to the temporary crimping temperature

[0192] The embodiments of the present invention have been described above. The present invention is not limited to the embodiments described above, and various modifications, variations, and combinations are possible.

[0193] Thermosetting organic insulating materials exhibit a decrease in elastic modulus above their glass transition temperature. Therefore, bonding of organic insulating materials becomes easy and strong. Furthermore, reliability decreases below 130°C, so the glass transition temperature of organic insulating materials must be 130°C or higher.

[0194] When using copper pillars (copper posts) with solder formed on their tips as metal electrode materials, it is necessary to prevent short circuits between adjacent metal electrodes due to the flow of molten solder during metal joint formation. Therefore, it is important to complete the bonding of the organic insulating material before the solder melts, thereby completely sealing the metal electrodes with the organic insulating material.

[0195] To achieve a strong bond between organic insulating materials, bonding must be performed at a temperature above the glass transition temperature. However, at temperatures above 180°C, diffusion between solder and copper becomes more likely. When mutual diffusion between solder and copper occurs, the melting point of that area rises significantly or melting stops altogether, making it difficult to form a metal bond at normal soldering temperatures, or resulting in a smaller bond area and a weaker bond.

[0196] Against this background, the semiconductor device 3 and the method for manufacturing the semiconductor device 3 of this embodiment can achieve desired characteristics at a low bonding temperature by setting the glass transition temperature of the organic insulating material to an appropriate range and performing the crimping in stages of preliminary crimping and final crimping.

[0197] Furthermore, the glass transition temperature of organic insulating materials can be adjusted as needed, for example, in the case of polyimide, by changing the structure of the parts that form the backbone of the molecular structure, such as aromatic rings, the length of the side chains, and the type of modifying groups.

[0198] The semiconductor device and the method for manufacturing the semiconductor device described above can also be expressed as follows.

[0199] <1> A semiconductor device in which two or more semiconductor chips are laminated and bonded with a metal material for electrodes and a thermosetting organic insulating material, wherein the glass transition temperature of the organic insulating material is 140°C or more and 180°C or less, the metal material includes solder, and includes a resin joint formed of the organic insulating material in contact with the metal material, and the area where the resin joint is formed is the same as or inside the outer shape of the smaller of the laminated semiconductor chips.

[0200] <2> The semiconductor device according to <1>, wherein the organic insulating material does not have a photosensitive function.

[0201] <3> The semiconductor device according to <1> or <2>, wherein the surface of the metal material for the electrode that is in contact with the organic insulating material contains titanium. <4> A semiconductor device in which a semiconductor chip and an interposer are laminated and bonded with a metal material for electrodes and a thermosetting organic insulating material, wherein the glass transition temperature of the organic insulating material is 140°C or more and 180°C or less, the metal material includes solder, and includes a resin joint formed of the organic insulating material in contact with the metal material, and the formation area of ​​the resin joint is the same as or inside the outer shape of the semiconductor chip.

[0202] <5> The semiconductor device according to <4>, wherein the organic insulating material does not have a photosensitive function.

[0203] <6> The semiconductor device according to <4> or <5>, wherein the surface of the metal material for the electrode that is in contact with the organic insulating material contains titanium.

[0204] <7> The semiconductor device according to any one of <1> to <6>, wherein the organic insulating material is polyimide or polybenzoxazole.

[0205] <8> The semiconductor device according to any one of <1> to <7>, wherein the metal material contains copper.

[0206] <9> A semiconductor device according to any one of <1> to <8>, comprising a structure in which a metal joint is formed of the metal material, and the distance between the centers of adjacent metal joints is 20 micrometers or less.

[0207] <10> A method for manufacturing a semiconductor device comprising laminating and bonding two semiconductor chips with a metal material for electrodes and a thermosetting organic insulating material, the method comprising: a resin-bonded portion forming step of forming resin-bonded portions made of the organic insulating material on the main surface of each semiconductor chip at predetermined intervals in cross-sectional view; a metal-bonded portion forming step of forming metal-bonded portions made of the metal material between adjacent resin-bonded portions; an alignment step of aligning the two semiconductor chips so that at least one of the positions of the corresponding resin-bonded portions of each semiconductor chip and the corresponding metal-bonded portions of each semiconductor chip coincides; a temporary bonding step of bonding at least the corresponding resin-bonded portions of each semiconductor chip; and a final bonding step of bonding at least the corresponding metal-bonded portions of each semiconductor chip.

[0208] <11> The glass transition temperature of the organic insulating material is 140°C or more and 180°C or less, the metal material includes solder, and when the portion where the corresponding resin-bonded portions of each semiconductor chip are pressed together is called the bonded portion, in the preliminary bonding step, the semiconductor chip is heated so that the temperature of the bonded portion is 100°C or more and 210°C or less, and in the main bonding step, the semiconductor chip is heated so that the temperature of the bonded portion exceeds 210°C, the method for manufacturing a semiconductor device according to <10>.

[0209] <12> A method for manufacturing a semiconductor device according to <10> or <11>, comprising a surface polishing step of polishing at least one of the resin-bonded portion and the metal-bonded portion after the metal-bonded portion forming step and before the alignment step, wherein, when the direction away from the main surface of the semiconductor chip is the height direction, the polishing in the surface polishing step is performed such that the height of the metal-bonded portion becomes higher than the height of the resin-bonded portion.

[0210] <13> The method for manufacturing a semiconductor device according to <10> or <11>, wherein the temporary crimping step and the main crimping step are performed using different devices, in the temporary crimping step a plurality of semiconductor chips are temporarily crimped onto the semiconductor chip, and in the main crimping step the plurality of semiconductor chips temporarily crimped onto the semiconductor chip are all crimped together.

[0211] (Fifth Embodiment) Referring to Figure 10A, a semiconductor device of the fifth embodiment of the present invention will be described. The semiconductor device of the fifth embodiment will be referred to as semiconductor device 5. Figure 10A is a cross-sectional view of semiconductor device 5. Regarding semiconductor device 5, the differences from semiconductor device 1 will be mainly described. Matters not specifically described for semiconductor device 5 can be the same as those of semiconductor device 1.

[0212] As shown in Figure 1, semiconductor device 1 has a structure in which a semiconductor device 10 (first semiconductor device) and a wiring device 30 correspond to each other via a connection portion 50. In contrast, semiconductor device 5, as shown in Figure 10A, has a structure in which a semiconductor device 10 (first semiconductor device) and a connected object 40 correspond to each other via a connection portion 50.

[0213] Here, the connected object 40 includes a semiconductor device such as a semiconductor chip (second semiconductor device), a wiring device 30 (shown in Figure 1), and a substrate such as a wiring board. In other words, the semiconductor device 5 includes a configuration in which semiconductor chips are connected to each other via a connection portion 50.

[0214] In the example of semiconductor device 1 shown in Figure 1, the dimensions in the main plane direction 1020 are the same for the semiconductor device 10, the connection portion 50, and the wiring device 30. In semiconductor device 5, the dimensions in the main plane direction 1020 of the connected object 40 may differ from the dimensions in the main plane direction 1020 of the semiconductor device 10 and the dimensions in the main plane direction 1020 of the connection portion 50. In the example of semiconductor device 5 shown in Figure 10A, the dimensions in the main plane direction 1020 of the connected object 40 are longer than the dimensions in the main plane direction 1020 of the semiconductor device 10 and the dimensions in the main plane direction 1020 of the connection portion 50.

[0215] Furthermore, in the example of the semiconductor device 5 shown in Figure 10A, the end faces of the semiconductor device 10, the connector 50, and the connected object 40 in the main plane direction 1020 are not located on the same plane. The end face of the connected object 40 in the main plane direction 1020 is located outward in the main plane direction 1020 than the end faces of the semiconductor device 10 and the connector 50. This is because the dimension of the connected object 40 in the main plane direction 1020 is longer than the dimension of the semiconductor device 10 in the main plane direction 1020 and the dimension of the connector 50 in the main plane direction 1020.

[0216] Thus, in the semiconductor device 5, the dimensions of the connected object 40 in the main surface direction 1020, the dimensions of the semiconductor device 10 in the main surface direction 1020, and the dimensions of the connecting portion 50 in the main surface direction 1020 do not necessarily have to be the same. Furthermore, in the semiconductor device 5, the end faces of the semiconductor device 10 in the main surface direction 1020, the end faces of the connecting portion 50 in the main surface direction 1020, and the end faces of the connected object 40 in the main surface direction 1020 do not necessarily have to be located on the same plane.

[0217] Figure 10B is a cross-sectional view of the comparative semiconductor device 101. The columnar metal electrode 54 of the semiconductor device 5, like the semiconductor device 1, includes at least a layer mainly composed of copper and a layer mainly composed of tin. For example, the first electrode portion 61 and the second electrode portion 62 can be made of layers mainly composed of copper, and the third electrode portion 63 can be made of a layer mainly composed of tin. In contrast, the electrode portion 65 included in the columnar metal electrode 54 of the comparative semiconductor device 101 is composed of, for example, only a layer mainly composed of copper. That is, the columnar metal electrode 54 of the semiconductor device 101 is composed of an electrode portion 65 formed of a single material.

[0218] Thus, the columnar metal electrode 54 of the semiconductor device 5 includes, in this order, a layer mainly composed of copper and a layer mainly composed of tin, from at least one main surface of the semiconductor device 10 and the connected object 40.

[0219] When copper is used as an electrode in a semiconductor device, if foreign matter such as dust or particles gets caught between the electrode and other electrodes that are joined to it, connection failure may occur.

[0220] In the semiconductor device 5, the semiconductor device 10 and the connected object 40, which is either a semiconductor device or a substrate, are electrically connected by a plurality of columnar metal electrodes 54. The columnar metal electrodes 54 include a layer mainly composed of tin and a layer mainly composed of copper.

[0221] In the semiconductor device 5, solder is used to connect the electrodes. Specifically, the electrodes of the semiconductor device 10 and the electrodes of the connected object 40 are connected in such a manner that a layer mainly composed of tin contained in the columnar metal electrode 54 is included at least at one of the connection interfaces. Therefore, even if foreign matter gets caught between the opposing electrodes, i.e., between the electrodes being connected, the material constituting the tin-based layer, such as the solder material, can deform. Also, the solder material melts during connection. As a result, the solder material envelops the foreign matter, making it less likely for the connection to be hindered by the foreign matter. Consequently, in the semiconductor device 5, electrical connection can be achieved and delamination can be prevented.

[0222] Organic insulating material is placed around the columnar metal electrode 54. The semiconductor device 10 and the connected object 40 are joined by the organic insulating material in areas other than the columnar metal electrode 54. Therefore, even if foreign matter gets caught between the organic insulating material of the semiconductor device 10 and the organic insulating material of the connected object 40, the organic insulating material will enclose the foreign matter. As a result, interference with the connection between the semiconductor device 10 and the connected object 40 due to foreign matter getting caught is less likely to occur.

[0223] As described above, in the semiconductor device 5, the columnar metal electrode 54 includes at least a layer mainly composed of tin, and an organic insulating material is placed in the parts other than the columnar metal electrode 54, thereby making the connection between the semiconductor device 10 and the connected object 40 more reliable.

[0224] Furthermore, it is preferable that the area equivalent diameter of the tin-based layer perpendicular to the axial direction 1010 of the columnar metal electrode 54 and the area equivalent diameter of the copper-based layer are approximately the same. In particular, it is preferable that the area equivalent diameter of the portion containing solder perpendicular to the axial direction 1010 of the columnar metal electrode 54 and the area equivalent diameter of the portion consisting only of copper are approximately the same.

[0225] By having the area equivalent diameter of the tin-based layer perpendicular to the axial direction 1010 of the columnar metal electrode 54 and the area equivalent diameter of the copper-based layer be approximately the same, it becomes easier to increase the density of connections at the connection portion 50 and ensure connection reliability. This is because it becomes easier to secure the connection area between electrodes while suppressing an increase in the area equivalent diameter perpendicular to the axial direction 1010 of the columnar metal electrode 54.

[0226] Furthermore, it is preferable that the cross-sectional shape of the tin-based layer on a plane perpendicular to the axial direction 1010 and the cross-sectional shape of the copper-based layer on a plane perpendicular to the axial direction 1010 are substantially the same. This makes it possible to reduce the arrangement pitch of the columnar metal electrodes 54 and increase the arrangement density of the columnar metal electrodes 54.

[0227] Furthermore, the resin portion 52 is preferably formed of an organic insulating material. The organic insulating material is preferably a resin containing an imide ring. An example of an organic material is polyimide.

[0228] Furthermore, it is preferable that the organic insulating material contains inorganic particles. Examples of inorganic particles are fillers formed from silica or alumina.

[0229] (Sixth Embodiment) A semiconductor device of the sixth embodiment of the present invention will be described with reference to Figure 10C. The semiconductor device of the sixth embodiment will be referred to as semiconductor device 6. Figure 10C is a cross-sectional view of semiconductor device 6. Regarding semiconductor device 6, the differences from semiconductor device 5 will be mainly described. Matters not specifically described for semiconductor device 6 can be the same as those of semiconductor device 5.

[0230] As shown in Figure 10C, the semiconductor device 6 differs from the semiconductor device 5 in the axial dimension 1010 of the second electrode portion 62 and the third electrode portion 63.

[0231] In semiconductor device 5, the axial dimension 1010 of the first electrode portion 61 and the axial dimension 1010 of the second electrode portion 62 are approximately the same. In contrast, in semiconductor device 6, the axial dimension 1010 of the second electrode portion 62 is shorter than the axial dimension 1010 of the first electrode portion 61. Specifically, the axial dimension 1010 of the first electrode portion 61 of semiconductor device 6 is the same as the dimension in Embodiment 1, and the axial dimension 1010 of the second electrode portion 62 of semiconductor device 6 is smaller than the dimension in Embodiment 1. Furthermore, in the sixth embodiment, the axial dimension 1010 of the third electrode portion 63 is increased by the amount that the axial dimension 1010 of the second electrode portion 62 has decreased.

[0232] Thus, the axial dimensions 1010 of the first electrode portion 61, the second electrode portion 62, and the third electrode portion 63 included in the columnar metal electrode 54 can be changed as appropriate. Furthermore, the ratio of the axial dimensions 1010 of the first electrode portion 61, the second electrode portion 62, and the third electrode portion 63 in the axial dimension 1010 of the columnar metal electrode 54 can be changed as appropriate.

[0233] In the example shown in Figure 10C, the axial dimension 1010 of the second electrode portion 62 can be, for example, 1 μm or more and 5 μm or less.

[0234] In the semiconductor device 6 illustrated in Figure 10C, the axial dimension 1010 of the second electrode portion 62 is smaller than the axial dimension 1010 of the first electrode portion 61. The dimensions of each electrode portion in the semiconductor device 6 are not limited to the example shown in Figure 10C. For example, the axial dimension 1010 of the first electrode portion 61 may be smaller than the axial dimension 1010 of the second electrode portion 62.

[0235] (Seventh Embodiment) A semiconductor device of the seventh embodiment of the present invention will be described with reference to Figures 11A to 11C. The semiconductor device of the seventh embodiment will be referred to as semiconductor device 7. Figures 11A to 11C are cross-sectional views of semiconductor device 7. Regarding semiconductor device 7, the differences from semiconductor device 5 will be mainly described. Matters not specifically described for semiconductor device 7 can be the same as those of semiconductor device 5.

[0236] The semiconductor device 7 differs from the semiconductor device 5 in that it includes a barrier metal layer 400. The barrier metal layer 400 is laminated in the columnar metal electrode 54 in contact with a layer mainly composed of copper, particularly a layer made of copper, in the axial direction 1010. "In contact with the axial direction 1010" means in contact with a surface perpendicular to the axial direction 1010. In a cross section parallel to the axial direction 1010 and the main surface direction 1020, the barrier metal layer 400 extends in the main surface direction 1020.

[0237] When melting a metal primarily composed of tin, interdiffusion can occur between the copper-based layer and the tin-based layer. Therefore, a barrier metal layer 400 to suppress this interdiffusion may be provided, for example, between the copper-based layer and the tin-based layer.

[0238] Figures 11A, 11B, and 11C each show barrier metal layers 400 at different positions in the axial direction 1010. These will be explained in order below.

[0239] Figure 11A shows a first barrier metal layer 401, which is an example of a barrier metal layer 400. The first barrier metal layer 401 is a barrier metal layer 400 provided between a first electrode portion 61 or a second electrode portion 62, which is a layer mainly composed of copper, and a third electrode portion 63, which is a layer mainly composed of tin.

[0240] The material of the barrier metal layer 400 is not particularly limited, as long as it is a material that can suppress the interdiffusion between the metal components contained in the copper-based layer and the metal components contained in the tin-based layer. Examples of materials for the barrier metal layer 400 include nickel, cobalt, tantalum, tungsten, and titanium.

[0241] The position where the barrier metal layer 400 is formed is not limited to the position of the first barrier metal layer 401, that is, between the copper-based layer and the tin-based layer. The barrier metal layer 400 is not particularly limited as long as it is in a position that can suppress the mutual diffusion between the metal components contained in the copper-based layer and the metal components contained in the tin-based layer. Below, Figures 11B and 11C show a barrier metal layer 400 that is in a different position in the axial direction 1010 from the first barrier metal layer 401 shown in Figure 11A.

[0242] Figure 11B shows a second barrier metal layer 402, which is another example of the barrier metal layer 400. The barrier metal layer 400 may be formed at an intermediate position in the axial direction 1010 of the second electrode portion 62, as in the second barrier metal layer 402. Alternatively, the second barrier metal layer 402 may be formed at an intermediate position in the axial direction 1010 of the first electrode portion 61, although this is not shown. In other words, the barrier metal layer 400 may be formed at an intermediate position in the axial direction 1010 of a layer mainly composed of copper. Here, an intermediate position means a position in the layer other than an interface.

[0243] Thus, the barrier metal layer 400 does not need to be formed at the interface between the copper-based layer and the tin-based layer in the axial direction 1010. In particular, when the second barrier metal layer 402 is formed near the interface between the copper-based layer and the tin-based layer, interdiffusion between the metal components contained in the copper-based layer and the metal components contained in the tin-based layer can be efficiently suppressed. Furthermore, the second barrier metal layer 402 can promote the formation of a thin intermetallic compound. This makes the second barrier metal layer 402 more stable. For example, an intermetallic compound of copper and tin may be present between the first electrode portion 61 or the second electrode portion 62, which is a copper-based layer, and the third electrode portion 63, which is a tin-based layer. The region in which the intermetallic compound is formed is restricted by the barrier layer 400. For example, the intermetallic compound of copper and tin is formed at a position closer to the third electrode portion 63 than to the barrier layer 400. By forming a thin intermetallic compound while its formation range is restricted by the barrier layer 400, further interdiffusion between metals can be suppressed.

[0244] Figure 11C shows a third barrier metal layer 403, which is another example of the barrier metal layer 400. The barrier metal layer 400 can also be formed at or near the interface of the second electrode portion 62 with the connected object 40, as in the third barrier metal layer 403. Alternatively, the third barrier metal layer 403 may be formed at or near the interface of the first electrode portion 61 with the semiconductor device 10, although this is not shown. This suppresses the diffusion of metal into the semiconductor device 10 or the connected object 40, in addition to the interdiffusion of metal components contained in the copper-based layer and the tin-based layer.

[0245] (Eighth Embodiment) Referring to Figure 11D, a semiconductor device of the eighth embodiment of the present invention will be described. The semiconductor device of the eighth embodiment will be referred to as semiconductor device 8. Figure 11D is a cross-sectional view of semiconductor device 8. Regarding semiconductor device 8, the differences from semiconductor device 5 will be mainly described. Matters not specifically described for semiconductor device 8 can be the same as those of semiconductor device 5.

[0246] The semiconductor device 8 differs from the semiconductor device 5 in that it includes an inorganic barrier layer 410. The inorganic barrier layer 410 is a barrier formed at the interface between the columnar metal electrode 54 and the organic insulating material. Specifically, the inorganic barrier layer 410 is a barrier formed at the interface between the columnar metal electrode 54 and the resin portion 52.

[0247] The barrier metal layer 400 shown in Figures 11A, 11B, and 11C extends in the main surface direction 1020 in a cross section parallel to the axial direction 1010 and the main surface direction 1020. In contrast, the inorganic barrier layer 410 extends in the axial direction 1010 in a cross section parallel to the axial direction 1010 and the main surface direction 1020.

[0248] As shown in Figure 11D, it is preferable that an inorganic barrier layer 410 is formed at the interface between the columnar metal electrode 54 and the layer made of organic insulating material. The inorganic barrier layer 410 prevents the metal components contained in the copper-based layer and the tin-based layer from diffusing into the organic insulating material such as organic insulating resin, thereby preventing short-circuit failures.

[0249] In addition to suppressing the migration of metal atoms, the inorganic barrier layer 410 can improve the adhesion between copper and organic insulating materials, particularly between copper and polyimide.

[0250] The inorganic barrier layer 410 can be formed using an inorganic film such as a silicon oxide film, silicon carbonitride film, silicon nitride film, tantalum nitride film, tantalum film, tungsten film, nickel film, titanium film, cobalt film, hafnium oxide film, or zirconium oxide film.

[0251] (Ninth Embodiment) A semiconductor device of the ninth embodiment of the present invention will be described with reference to Figure 12. The semiconductor device of the ninth embodiment will be referred to as semiconductor device 9. Figure 12 is a cross-sectional view of semiconductor device 9. Regarding semiconductor device 9, the differences from semiconductor device 5 will be mainly described. Matters not specifically described for semiconductor device 9 can be the same as those of semiconductor device 5.

[0252] The semiconductor device 9 differs from the semiconductor device 5 in that it includes a molded portion 420. Furthermore, the semiconductor device 9 differs from the semiconductor device 5 in that it includes two element units. Here, the portion of the semiconductor element consisting of one semiconductor device 10 and the connected object 40 is referred to as the element unit U.

[0253] As shown in Figure 12, the semiconductor device 9 comprises two semiconductor devices 10, a first device 10A and a second device 10B. The element unit U formed from the first device 10A and the connected object 40 is designated as the first element unit U1. The element unit U formed from the second device 10B and the connected object 40 is designated as the second element unit U2. Thus, the semiconductor device 9 comprises two element units U, the first element unit U1 and the second element unit U2.

[0254] In the semiconductor device 9, the outer periphery of the semiconductor device 10 and the connection portion 50 is covered with molding resin. The portion formed from this molding resin is referred to as the molded portion 420. The molded portion 420 covers the outer periphery of the first element unit U1 and the second element unit U2 in the main surface direction 1020.

[0255] The molded portion 420 includes a first molded portion 421, a second molded portion 422, and a third molded portion 423. The first molded portion 421 is a molded portion 420 formed between the first element unit U1 and the second element unit U2 in the main surface direction 1020. The second molded portion 422 is a molded portion 420 formed on the outer circumference of the first element unit U1 on the side not facing the second element unit U2. The third molded portion 423 is a molded portion 420 formed on the outer circumference of the second element unit U2 on the side not facing the first element unit U1.

[0256] In a structure in which a semiconductor device 10 is connected to a connected object 40 such as a wiring device, forming a molded portion 420 so as to cover the semiconductor device 10 with molded resin prevents stress concentration at the connection point between the semiconductor device 10 and the connected object 40. As a result, connection reliability can be improved.

[0257] Furthermore, in the semiconductor device 9, a silicon oxide film may be formed instead of the molded portion 420. By forming a silicon oxide film, stress concentration at the connection portion between the semiconductor device 10 and the connected object 40 can be prevented, similar to the case where a molded portion 420 made of molded resin is formed. As a result, connection reliability can be improved.

[0258] (Tenth Embodiment) Referring to Figure 13A, a semiconductor device of the tenth embodiment of the present invention will be described. The semiconductor device of the tenth embodiment will be referred to as semiconductor device 210. Figure 13A is a cross-sectional view of semiconductor device 210. Regarding semiconductor device 210, mainly the differences from semiconductor device 5 will be described. Matters of semiconductor device 210 that are not specifically described can be the same as those of semiconductor device 5.

[0259] The semiconductor device 210 differs from the semiconductor device 5 in the shape of both ends of the connection portion 50 in the main surface direction 1020. In the semiconductor device 5, both ends of the connection portion 50 in the main surface direction 1020 are flat. In contrast, in the semiconductor device 210, both ends of the connection portion 50 in the main surface direction 1020 are not flat. There are steps at both ends.

[0260] In the semiconductor device 210, as explained in semiconductor device 5, the dimension of the connected object 40 in the main surface direction 1020 is longer than the dimension of the semiconductor device 10 in the main surface direction 1020. Corresponding to this difference in dimensions, the dimension of the main surface direction 1020 differs between the resin portion 52 located on the semiconductor device 210 side and the resin portion 52 located on the connected object 40 side.

[0261] In the resin portion 52, the part of the resin portion 52 that is formed on the connected body 40 is designated as the first resin portion 52A. The part of the resin portion 52 that is formed on the semiconductor device 10 is designated as the second resin portion 52B. In the example shown in Figure 13A, the part of the resin portion 52 having dimensions similar to the dimensions of the main surface direction 1020 of the connected body 40 is the first resin portion 52A. Similarly, the part of the resin portion 52 having dimensions similar to the dimensions of the main surface direction 1020 of the semiconductor device 10 is the second resin portion 52B.

[0262] As the dimension of the connected body 40 in the main surface direction 1020 is longer than the dimension of the semiconductor device 10 in the main surface direction 1020, the dimension of the first resin part 52A in the main surface direction 1020 is shorter than the dimension of the second resin part 52B in the main surface direction 1020.

[0263] The line indicating the joint surface between the first resin part 52A and the second resin part 52B is defined as the resin part boundary line L1. However, it is usually difficult to observe the boundary line between the first resin part 52A and the second resin part 52B. This is because it is difficult to observe the joint interface when the first resin part 52A and the second resin part 52B are joined together.

[0264] However, in cases such as the semiconductor device 210, where the dimensions of the first resin part 52A in the main surface direction 1020 differ from those of the second resin part 52B in the main surface direction 1020, the resin part boundary line L1 can be inferred from the position of the step in the resin part 52 observed in the cross-section.

[0265] In the semiconductor device 210, the resin portion boundary line L1 is located at the boundary between the third electrode portion 63 and the second electrode portion 62. In other words, the step in the resin portion 52 is located at the boundary between the third electrode portion 63 and the second electrode portion 62 in the axial direction 1010.

[0266] However, in semiconductor devices having a configuration similar to semiconductor device 210, various configurations are possible regarding the position of the resin boundary line L1 in the axial direction 1010 of each electrode portion of the columnar metal electrode 54. Examples of such configurations will be described below.

[0267] (Eleventh and Twelfth Embodiments) Referring to Figures 13B and 13C, the semiconductor device of the eleventh embodiment and the semiconductor device of the twelfth embodiment of the present invention will be described. The semiconductor device of the eleventh embodiment will be referred to as semiconductor device 211. The semiconductor device of the twelfth embodiment will be referred to as semiconductor device 212. Figure 13B is a cross-sectional view of semiconductor device 211. Figure 13C is a cross-sectional view of semiconductor device 212. Regarding semiconductor device 211 and semiconductor device 212, the differences from semiconductor device 210 will be mainly described. Matters not specifically described for semiconductor device 211 and semiconductor device 212 can be the same as those for semiconductor device 210.

[0268] The semiconductor devices 211 and 212 differ from semiconductor device 210 in that the resin boundary line L1 is located at a specific position in the axial direction 1010 of each electrode portion on the columnar metal electrode 54.

[0269] In semiconductor device 210, the resin boundary line L1 is located at the boundary between the third electrode portion 63 and the second electrode portion 62. In contrast, in semiconductor device 211, the resin boundary line L1 is located at an intermediate position in the third electrode portion 63. In other words, the step in the resin portion 52 is located at an intermediate position in the third electrode portion 63 in the axial direction 1010.

[0270] Furthermore, in the semiconductor device 212, the resin portion boundary line L1 is located at the boundary between the first electrode portion 61 and the third electrode portion 63. In other words, the step in the resin portion 52 is located at the boundary between the first electrode portion 61 and the third electrode portion 63 in the axial direction 1010.

[0271] As shown in semiconductor devices 210, 211, and 212, the resin boundary line L1 can be set at any position in the axial direction 1010 of the columnar metal electrode 54.

[0272] The portion including the connected object 40 and the resin portion 52 and columnar metal electrode 54 formed on the connected object 40 side is defined as the first joint P1. The portion including the semiconductor device 10 and the resin portion 52 and columnar metal electrode 54 formed on the semiconductor device 10 side is defined as the second joint P2. Semiconductor devices 210, 211, and 212 can be formed by joining the first joint P1 and the second joint P2.

[0273] By arbitrarily setting the thickness of a portion of the resin portion 52 and the shape of a portion of the columnar metal electrode 54, which are formed in advance before joining the first joint portion P1 and the second joint portion P2, the resin portion boundary line L1 can be set at any position in the axial direction 1010 of the columnar metal electrode 54. In other words, the resin portion boundary line L1 can be set at any position in the axial direction 1010 of the first electrode portion 61, the second electrode portion 62, and the third electrode portion 63.

[0274] (Third Embodiment) Referring to Figure 14, a semiconductor device of the thirteenth embodiment of the present invention will be described. The semiconductor device of the thirteenth embodiment will be referred to as semiconductor device 213. Figure 14 is a cross-sectional view of semiconductor device 213. Regarding semiconductor device 213, mainly the differences from semiconductor device 5 will be described. Matters not specifically described for semiconductor device 213 can be the same as those of semiconductor device 5.

[0275] The dimensions of the electrode portions in the main surface direction 1020 differ between semiconductor device 213 and semiconductor device 5. In semiconductor device 5, the dimensions of the first electrode portion 61, the second electrode portion 62, and the third electrode portion 63 in the main surface direction 1020 are the same. In contrast, in semiconductor device 5, the dimension of the third electrode portion 63 in the main surface direction 1020 is longer than the dimensions of the first electrode portion 61 and the second electrode portion 62 in the main surface direction 1020.

[0276] By making the dimension of the third electrode portion 63 in the main surface direction 1020 longer than the dimension of the first electrode portion 61 and the second electrode portion 62 in the main surface direction 1020, alignment becomes easier when joining the first joint portion P1 and the second joint portion P2. In other words, the tolerance for alignment can be increased.

[0277] Figure 14 shows a configuration in which the dimension of the third electrode portion 63 in the main surface direction 1020 is longer than the dimension of the first electrode portion 61 and the second electrode portion 62 in the main surface direction 1020. However, the dimensions of the first electrode portion 61, the second electrode portion 62, and the third electrode portion 63 in the main surface direction 1020 can be arbitrarily set in various ways. For example, instead of the third electrode portion 63 shown in Figure 14, the dimension of the first electrode portion 61 in the main surface direction 1020 can be made longer than the dimensions of the second electrode portion 62 and the third electrode portion 63 in the main surface direction 1020.

[0278] (14th, 15th, and 16th Embodiments) The semiconductor devices of the 14th, 15th, and 16th embodiments of the present invention will be described with reference to Figures 15A, 15B, and 15C. The semiconductor device of the 14th embodiment will be referred to as semiconductor device 214, the semiconductor device of the 15th embodiment as semiconductor device 215, and the semiconductor device of the 16th embodiment as semiconductor device 216. Figure 15A is a cross-sectional view of semiconductor device 214, Figure 15B is a cross-sectional view of semiconductor device 215, and Figure 15C is a cross-sectional view of semiconductor device 216. Semiconductor devices 214, 215, and 216 are obtained by changing the length of the electrode portion in the main surface direction 1020 compared to semiconductor devices 210, 211, and 212, respectively. Semiconductor devices 214 and 215 are obtained by increasing the dimensions of the second electrode portion 62 compared to semiconductor devices 210 and 211, respectively. Furthermore, the semiconductor device 216 is an improved version of the semiconductor device 212 in which the dimensions of the second electrode portion 62 and the third electrode portion 63 are enlarged.

[0279] As illustrated in part in the fifth to sixteenth embodiments, the dimensions of the first resin portion 52A and the second resin portion 52B in the main surface direction 1020 and the axial direction 1010, the dimensions of the first electrode portion 61, the second electrode portion 62, and the third electrode portion 63 in the main surface direction 1020 and the axial direction 1010, and the position of the resin portion boundary line L1 in the axial direction 1010 can be changed in various ways. Furthermore, each semiconductor device 1 can be manufactured using a corresponding manufacturing method according to these settings. In other words, the configuration of the first joint portion P1 and the second joint portion P2 can be changed according to the configuration of the semiconductor device 1.

[0280] (Embodiments 17 to 20) Semiconductor devices of the 17th to 20th embodiments of the present invention will be described with reference to Figures 16A to 17B. The semiconductor device of the 17th embodiment will be referred to as semiconductor device 217, the semiconductor device of the 18th embodiment as semiconductor device 218, the semiconductor device of the 19th embodiment as semiconductor device 219, and the semiconductor device of the 20th embodiment as semiconductor device 220. Figure 16A is a cross-sectional view of semiconductor device 217, Figure 16B is a cross-sectional view of semiconductor device 218, Figure 17A is a cross-sectional view of semiconductor device 219, and Figure 17B is a cross-sectional view of semiconductor device 220.

[0281] In semiconductor devices 217, 218, 219, and 220, the portion corresponding to the first resin portion 52A in semiconductor devices 210, 211, 214, and 215, respectively, is formed of an inorganic insulating material instead of an organic insulating material. The portion corresponding to the first resin portion 52A that is formed of an inorganic insulating material is referred to as the inorganic insulating portion 58.

[0282] Figure 16A and others show an example in which the portion corresponding to the first resin portion 52A is formed of an inorganic insulating material. Instead of the first resin portion 52A, the portion corresponding to the second resin portion 52B may be formed of an inorganic insulating material. The portion corresponding to the second resin portion 52B that is formed of an inorganic insulating material is also considered an inorganic insulating portion. Here, the inorganic insulating material can be, for example, silicon dioxide, silicon carbonitride, and silicon nitride.

[0283] Thus, at least a portion of the insulating portion formed around the columnar metal electrode 54 can be made of an inorganic insulating material. However, it is preferable that the area around the interface between the tin-based layer and the copper-based layer in the columnar metal electrode 54 be covered with an organic insulating material. Specifically, for example, it is preferable that the area around the interface between the first electrode portion 61 and the second electrode portion 62, or the area around the interface between the third electrode portion 63 and the second electrode portion 62, be covered with an organic insulating material.

[0284] (Modification of the 10th Embodiment) Referring to Figure 18A, a modification of the semiconductor device 210 of the 10th embodiment shown in Figure 13A will be described. Figure 18A is a cross-sectional view of a semiconductor device 210' showing a modification of the semiconductor device 210. Unlike the semiconductor device 210 shown in Figure 13A, the semiconductor device 210' shown in Figure 18A has a second electrode portion 62 that includes a protrusion 62T.

[0285] The second electrode portion 62 of the semiconductor device 210' includes a base portion 62B and a protrusion portion 62T. In contrast, the second electrode portion 62 of the semiconductor device 210 includes only the portion corresponding to the base portion 62B of the semiconductor device 210' and does not include the portion corresponding to the protrusion portion 62T.

[0286] The protrusion 62T projects from the main surface of the base 62B on the semiconductor device 10 side toward the semiconductor device 10. The dimension of the protrusion 62T in the main surface direction 1020 is shorter than the dimension of the base 62B in the main surface direction. Furthermore, the protrusion 62T is located approximately in the center of the main surface of the base 62B on the semiconductor device 10 side in the main surface direction 1020.

[0287] The protrusion 62T penetrates the third electrode portion 63. This strengthens the connection between the second electrode portion 62 and the third electrode portion 63 because the contact area between the second electrode portion 62 and the third electrode portion 63 increases.

[0288] The protrusion 62T penetrates, forming a recess in the third electrode portion 63. At least a portion of the protrusion 62T is covered with the material that forms the third electrode portion 63.

[0289] Furthermore, for the protrusion 62T to penetrate the third electrode portion 63, it is preferable that the protrusion 62T is harder than the third electrode portion 63. For example, by forming the second electrode portion 62 from a material mainly composed of copper and the third electrode portion 63 from a material mainly composed of tin, the protrusion 62T can be made harder than the third electrode portion 63.

[0290] In the state where the protrusion 62T is inserted into the third electrode portion 63, the cross-sectional area of ​​the protrusion 62T is larger than the cross-sectional area of ​​the third electrode portion 63 in a cross section parallel to the axial direction 1010 and the main surface direction 1020.

[0291] In the state where the protrusion 62T is inserted into the third electrode portion 63, it is preferable that the entire outer edge of the protrusion 62T in a cross section parallel to the axial direction 1010 and the main surface direction 1020 is in contact with the third electrode portion 63.

[0292] The above explanation is based on the example where the second electrode portion 62 has a protrusion. However, the first electrode portion 61 may have a protrusion, and the third electrode 63, which is positioned on the side of the second electrode 62, may have a recess. When the first electrode portion 61 has a protrusion, the protrusion extends from the base of the first electrode portion 61 toward the connected object 40.

[0293] (Modifications of the 14th, 17th, and 19th embodiments) Above, a configuration in which the second electrode portion 62 has a protrusion 62T has been described using modifications of the semiconductor device 210 of the 10th embodiment as an example. The protrusion 62T may also include the second electrode portion 62 and the first electrode portion 61 other than those of the 10th embodiment.

[0294] Figure 18B is a cross-sectional view of a semiconductor device 214', which is a modified example of the semiconductor device 214 of the 14th embodiment. As shown in Figure 18B, the second electrode portion 62 can have a protrusion 62T even if the dimension of the base portion 62B in the main surface direction 1020 is longer than the dimension of the third electrode portion 63 in the main surface direction 1020. When the dimension of the base portion 62B in the main surface direction 1020 is long, it becomes easier to form the protrusion 62T.

[0295] Figure 19A is a cross-sectional view of a semiconductor device 217', which is a modified example of the semiconductor device 217 of the 17th embodiment. Figure 19B is a cross-sectional view of a semiconductor device 219', which is a modified example of the semiconductor device 219 of the 19th embodiment. The 17th and 19th embodiments are semiconductor devices in which the first resin portion 52A in the 10th and 14th embodiments is replaced by an inorganic insulating portion 58, respectively. As shown in Figures 19A and 19B, the second electrode portion 62 may have a protrusion 62T regardless of whether the insulating material covering the periphery of the second electrode portion 62 is an organic insulating material or an inorganic insulating material.

[0296] (First Manufacturing Method) Various methods are possible for manufacturing the semiconductor device 1. First, the first manufacturing method will be described. The first manufacturing method includes the following steps (1) to (5) in order.

[0297] (1) A step of depositing an organic insulating film on one main surface of a semiconductor device. (2) A step of curing the deposited organic insulating film. (3) A step of forming holes in the organic insulating film on the electrode at locations corresponding to the electrode positions of the semiconductor device by dry etching. (4) A step of filling the formed holes with a metal mainly composed of copper and a metal mainly composed of tin to form columnar metal electrodes. (5) A step of performing a process (polishing, grinding, cutting) to improve the flatness of the surfaces of the organic insulating film and columnar metal electrodes. (6) A step of aligning the semiconductor device with a connected object which is another semiconductor device or wiring device and connecting them by flip-chip (thermocompression bonding) connection.

[0298] The first manufacturing method may include a step of forming a seed metal after the step of forming holes and before the step of forming columnar metal electrodes. Alternatively, it may include a step of forming a barrier layer after the step of forming holes and before the step of forming the seed metal.

[0299] The general flow of the first manufacturing method will be explained based on Figures 20A to 20C. Figures 20A to 20C are, in order, cross-sectional views showing the manufacturing process of the first manufacturing method.

[0300] (Insulator Pattern Formation Process) Figure 20A shows the state after the completion of process (3) described above. As shown in Figure 20A, in the state after the completion of process (3), a patterned insulator layer 620 is formed on the main surface of the substrate 601 on the stacking direction 1601 side. Also, insulator layer openings 621 are formed between the patterns of adjacent insulator layers 620. The insulator layer openings 621 correspond to holes at locations corresponding to the electrode positions described above. The substrate 601 corresponds to, for example, the first substrate 12 in the semiconductor device 10.

[0301] (First Conductor Formation Process) Figure 20B shows the state in which the insulating layer opening 621 is filled with a metal mainly composed of copper. As shown in Figure 20B, a first conductor portion 610, which is a conductor portion filled with a metal mainly composed of copper, is formed in the insulating layer opening 621. The first conductor portion 610 corresponds to, for example, the first electrode portion 61 in the semiconductor device 10. In the state in which the first conductor portion 610 is formed, a part of the insulating layer opening 621 on the stacking direction 1601 side of the first conductor portion 610 remains unfilled with metal. This part of the insulating layer opening 621 is made into the second insulating layer opening 622.

[0302] (Second Conductor Formation Process) Figure 20C shows the state in which the insulator layer opening 621, specifically the second insulator layer opening 622, is filled with a metal mainly composed of tin. As shown in Figure 20C, a second conductor portion 640, which is a conductor portion filled with a metal mainly composed of tin, is formed in the second insulator layer opening 622. The second conductor portion 640 corresponds to, for example, a third electrode portion 63. This forms a columnar metal electrode including the first conductor portion 610 and the second conductor portion 640.

[0303] (Second Manufacturing Method) Next, the second manufacturing method will be described. The second manufacturing method includes the following steps (1) to (7) in order.

[0304] (1) A step of forming a resist film on one main surface of a semiconductor device. (2) A step of forming holes in the resist film at locations corresponding to the electrode positions of the semiconductor device by exposure and development. (3) A step of filling the holes with a metal mainly composed of copper and a metal mainly composed of tin to form columnar metal electrodes. (4) A step of removing the resist film. (5) A step of arranging an organic insulating film so as to cover the periphery of the columnar metal electrodes. (6) A step of performing a process (polishing, grinding, cutting) to improve the flatness of the surfaces of the organic insulating film and the columnar metal electrodes. (7) A step of aligning the semiconductor device with a connected object which is another semiconductor device or wiring device and connecting them by flip-chip (thermocompression bonding).

[0305] The second manufacturing method may include a step of forming a seed metal before the step of forming a resist film.

[0306] The general flow of the second manufacturing method will be explained based on Figures 21A to 21E. Figures 21A to 21E are, in order, cross-sectional views showing the manufacturing process of the second manufacturing method.

[0307] (Resist Pattern Formation Process) Figure 21A shows the state after the completion of process (2) described above. As shown in Figure 21A, in the state after the completion of process (2), a patterned resist film 720 is formed on the main surface of the substrate 601 on the stacking direction 1601 side. In addition, resist film openings 721 are formed between the patterns of adjacent resist films 720. The resist film openings 721 correspond to holes at locations corresponding to the electrode positions described above.

[0308] (First Conductor Formation Process) Figure 21B shows the state in which a first conductor portion 610, which is a conductor portion formed by filling a resist film opening 721 with a metal mainly composed of copper, is formed. The first conductor portion 610 corresponds to, for example, the first electrode portion 61 in the semiconductor device 10. In the state in which the first conductor portion 610 is formed in the resist film opening 721, a part of the resist film opening 721 on the stacking direction 1601 side of the first conductor portion 610 remains unfilled with metal. This part of the resist film opening 721 is made into the second resist film opening 722.

[0309] (Second Conductor Formation Process) Figure 21C shows the state in which a metal mainly composed of tin is filled into the resist film opening 721, specifically the second resist film opening 722. As shown in Figure 21C, a second conductor portion 640, which is a conductor portion filled with a metal mainly composed of tin, is formed in the second resist film opening 722. The second conductor portion 640 corresponds to, for example, a third electrode portion 63. This forms a columnar metal electrode including the first conductor portion 610 and the second conductor portion 640.

[0310] (Resist film removal process) Figure 21D shows the state after the resist film 720 has been removed. This creates a gap between adjacent columnar metal electrodes (first conductor portion 610 and second conductor portion 640).

[0311] (Insulator layer formation process) Figure 21E shows the state in which an organic insulating film is placed in the gap between adjacent columnar metal electrodes, and an insulating layer 620 is formed. As a result, an organic insulating film is placed around the columnar metal electrodes.

[0312] The second manufacturing method is more specifically as follows: First, bumps of a desired diameter and height are formed on a semiconductor device wafer, that is, a substrate such as the first substrate (hereinafter referred to as the wafer substrate). Bump formation is performed by forming a photosensitive resist film on the wafer, exposing and developing it, and creating holes in the resist at the bump formation locations.

[0313] Next, a seed metal is formed by sputtering, followed by electroplating to form a copper-based metal layer and a tin-based metal layer. After this electroplating process, the resist is removed to form bumps.

[0314] In this case, when forming a barrier layer, the barrier layer material is formed on the bump surface using sputtering or CVD. This allows for the formation of a barrier layer. This barrier layer becomes an inorganic barrier layer formed between the columnar metal electrode and the organic insulating material.

[0315] Next, a film made of organic insulating material is formed on the bumped wafer substrate. In the case of liquid materials, this film formation is carried out by coating using methods such as spin coating, slit coating, or spray coating. Subsequently, the film is formed by drying under heating or reduced pressure and curing by heat treatment.

[0316] In the case of film materials, this can be done by laminating them onto the surface of a bumped wafer using a diaphragm laminator or roll laminator, and then curing them with heat treatment.

[0317] After forming a film made of organic insulating material, the bumps covered by the organic insulating material are exposed, flattened, and the organic insulating material is flattened. In the bump exposure process, the barrier layer formed on the bump heads is removed. This can be done by fly cutting or CMP processing.

[0318] After planarization, two semiconductor devices are connected using a flip-chip (thermocompression bonding) connection.

[0319] (Third Manufacturing Method) Next, the third manufacturing method will be described. The third manufacturing method includes the following steps in order: (1) A step of forming a first resist film on one main surface of the semiconductor device. (2) A step of forming holes in the resist film at locations corresponding to the electrode positions of the semiconductor device by exposure and development. (3) A step of filling the holes with a metal mainly composed of copper to form the first part of a columnar metal electrode. (4) A step of removing the first resist film. (5) A step of arranging an organic insulating film so as to cover the periphery of the first part of the columnar metal electrode. (6) A step of forming a second resist film on the organic insulating film. (7) A step of forming holes in the second resist film at locations corresponding to the positions of the first part of the columnar metal electrode by exposure and development. (8) A step of forming holes in the organic insulating film at locations corresponding to the positions of the first part of the columnar metal electrode by dry etching. (9) A step of removing the second resist film. (10) A step of filling the holes with a metal mainly composed of tin to form the second part of a columnar metal electrode. (11) A step of performing a process to improve the surface flatness of the first portion of the organic insulating film and columnar metal electrode. (12) A step of aligning the semiconductor device with the connected object, which is another semiconductor device or wiring device, and connecting them by flip-chip (thermocompression bonding).

[0320] The general flow of the third manufacturing method will be explained with reference to Figures 22A to 22H. Figures 22A to 22H are, in order, cross-sectional views showing the manufacturing process of a semiconductor device.

[0321] (Copper Pad Formation Process) First, as shown in Figure 22A, a first conductor portion 610 (the first portion of a columnar metal electrode) is formed on the main surface of the substrate 601 in the stacking direction 1601. The substrate 601 and the first conductor portion 610 correspond to, for example, the first substrate 12 and the first electrode portion 61 in the semiconductor device 10. Alternatively, the substrate 601 and the first conductor portion 610 correspond to, for example, the second substrate 32 and the second electrode portion 62 in the connected body 40. The first conductor portion 610 can be formed using, for example, photolithography and plating techniques. The first conductor portion 610 can be formed mainly of copper. When forming a barrier layer, the barrier layer material is formed on the copper pad surface by sputtering or CVD. This allows the barrier layer to be formed.

[0322] (Polymer Film Formation Process) Next, as shown in Figure 22B, an organic insulating material is placed to cover the main surface of the substrate 601 on the lamination direction 1601 side and the surface of the first conductor portion 610, forming an insulating layer 620 (organic insulating film). The insulating layer 620 is the portion that will become the resin portion 52 of the connection portion 50 after subsequent formation. The organic insulating material can be a polymer material.

[0323] (Resist film formation process) Next, as shown in Figure 22C, a resist layer 630 (second resist film) is formed on the main surface of the insulating layer 620 on the stacking direction 1601 side.

[0324] (Exposure and Development Process) Next, as shown in Figure 22D, the resist layer 630 is exposed and developed to form the resist openings 632.

[0325] (Dry Etching Process) Next, as shown in Figure 22E, the insulating layer 620 at the position corresponding to the resist opening 632 (hole) is removed by dry etching. At this time, the barrier layer on the head portion of the copper pad that is exposed after the insulating layer is removed may also be removed.

[0326] (Polymer etching completed) As shown in Figure 22F, the dry etching described above exposes the surface of the first conductor portion 610 on the stacking direction 1601 side, and forms an insulating layer hole 623 (hole).

[0327] (Resist residue removal process) Next, as shown in Figure 22G, the residual film of the resist layer 630 is removed.

[0328] (Solder layer filling process) Next, as shown in Figure 22H, a conductor is filled into the insulator layer hole 623 to form a second conductor portion 640 (second portion of the columnar metal electrode). The second conductor portion 640 corresponds to, for example, a part of the third electrode portion 63. The conductor filling can be carried out by methods such as plating and coating. The conductor to be filled can be solder material, for example, a material mainly composed of tin.

[0329] After filling with conductors, the surfaces of the insulating layer 620 and the second conductor portion 640 may be polished, for example, by a CMP process. This allows for the creation of a smooth bonding surface. Note that this process to improve surface flatness is not limited to polishing; for example, grinding or cutting can also be used.

[0330] The semiconductor device 1 can be formed by joining two substrates 601, processed as described above, such that the insulating layer 620 and the second conductor portion 640 formed on each substrate 601 are in contact with each other. In other words, they can be connected by flip-chip (thermocompression bonding) connection.

[0331] The above explains the general flow of the manufacturing process. More specifically, the manufacturing process can be carried out as follows:

[0332] First, copper-based bumps of a desired diameter and height are formed on the semiconductor device wafer. These bumps are formed by sputtering a seed metal, then a photosensitive resist film is formed on the semiconductor device wafer, and exposure and development are performed to create holes in the resist at the bump formation locations.

[0333] Subsequently, a metal primarily composed of copper is formed by electroplating. Afterward, the resist is removed with a chemical solution. If a barrier layer is to be formed, the barrier layer material is formed on the bump surface using sputtering or CVD. This allows for the formation of a barrier layer.

[0334] Next, a film made of an organic insulating material is formed on a copper-based bump-formed wafer. In the case of liquid materials, this film formation is carried out by coating using methods such as spin coating, slit coating, or spray coating, followed by drying under heating or reduced pressure and heat treatment to harden the film.

[0335] In the case of film materials, this can be done by laminating them onto the surface of a bumped wafer using a diaphragm laminator or roll laminator, and then curing them with heat treatment.

[0336] Next, a photosensitive resist film is formed again, and exposure development and etching are performed to create holes in the resist and organic insulating material at the bump formation locations.

[0337] Subsequently, after removing the residual resist layer, the seed metal is formed by sputtering, followed by the formation of a tin-based metal by electroplating. If a barrier layer on the bump side is to be formed with a material other than the seed metal, the barrier layer material is formed by sputtering or CVD before the seed metal is formed. After that, the resist is removed with a chemical solution. If necessary, the barrier layer formed at the bottom of the hole may be removed by dry etching or other methods. If necessary, a copper-based metal may be formed again by electroplating before the electroplating process of the tin-based metal.

[0338] The bumps and organic insulating material are flattened and smoothed. This can be done by fly cutting or CMP processing.

[0339] As described above, using a method that performs bump formation in two stages has the advantage of making the thickness of the metal layer formed on the organic insulating material thinner, thus facilitating the planarization and smoothing processes. In other words, when filling the insulating layer holes 623 shown in Figure 22G with conductors, the thickness of the conductor deposited on the side of the insulating layer 620 in the lamination direction 1601 can be reduced. Therefore, the amount of polishing required in subsequent processes such as the CMP process can be reduced.

[0340] The above manufacturing method is merely an example and can be modified in various ways depending on the configuration of the semiconductor device 1 being manufactured.

[0341] For example, as shown in Figure 10C, when the thickness of the third electrode portion 63 is reduced, the dimensions of the first conductor portion 610 formed on the substrate 601 in the stacking direction 1601 are reduced.

[0342] Furthermore, for example, when increasing the thickness of the second electrode portion 62, as in the semiconductor device 6 shown in Figure 10C, the dimension of the insulating layer hole 623 in the stacking direction 1601 is increased.

[0343] Figure 23 is a cross-sectional view showing another manufacturing method of this embodiment. As described above, after forming the second conductor portion 640, the surfaces of the insulating layer 620 and the second conductor portion 640 may be polished by a CMP process or the like. When polishing the surface with a CMP process, if the conductors are uniformly arranged on the surface to be polished, surface flatness is more easily achieved.

[0344] However, depending on the design of the electrodes and wiring, the conductors may not be uniformly arranged on the surface. Figure 23 shows an example in which the second conductor portion 640 is not uniformly arranged on the surface of the insulating layer 620 on the lamination direction 1601 side. In the example shown in Figure 23, the electrode portions are densely arranged near the center in the main surface direction 1020, as shown by electrode portions E1 to E4. On the other hand, no electrode portions are arranged near both ends in the main surface direction 1020.

[0345] Therefore, the second conductor portion 640 is densely arranged on the surface near the center in the main surface direction 1020 compared to the areas near both ends. On the other hand, the second conductor portion 640 is not arranged near the areas near both ends in the main surface direction 1020.

[0346] In such cases, achieving surface flatness through polishing in the CMP process becomes difficult. Therefore, dummy conductors 640' are formed near both ends in the main surface direction 1020. This reduces the difference in conductor distribution density across different regions of the surface. As a result, surface flatness achieved through polishing in the CMP process can be improved.

[0347] The dummy conductor 640' can be formed, for example, from the material that forms the first conductor portion 610 or the material that forms the second conductor portion 640. Specifically, the dummy conductor 640' can be formed from a material mainly composed of tin or a material mainly composed of copper. Furthermore, it is preferable that the material forming the dummy conductor 640' is the same as the metal of the other exposed electrodes. The dummy conductor 640' may also have the same layer structure as the columnar metal electrode. In this case, the dummy conductor 640' can be provided by forming the columnar metal electrode structure on the unwired dummy pad in the same way as the other columnar metal electrodes.

[0348] The arrangement of the dummy conductor 640' will be explained in more detail. It is preferable that the maximum pitch of the formed second conductor portion 640 in the main surface direction 1020 is 10 times or less, particularly 3 times or less, the minimum pitch of the formed second conductor portion 640 in the main surface direction 1020, as this facilitates the achievement of overall wafer flatness in the CMP process. In other words, in the semiconductor device state, it is preferable that the maximum pitch of the formed columnar metal electrodes in the main surface direction 1020 is 10 times or less, particularly 3 times or less, the minimum pitch, as this facilitates the achievement of overall wafer flatness in the CMP process.

[0349] In contrast, in regions where the conductor filling portion is not formed, or in regions with low density, it is preferable that a layer mainly composed of copper, or a dummy conductor 640' made of tin, is formed on the surface, as this facilitates the achievement of overall wafer flatness in the CMP process. The maximum pitch of the dummy pads formed on the surface of the formed second conductor portion 640 in the main surface direction 1020 is preferably 10 times or less, and more preferably 3 times or less, the minimum pitch.

[0350] As described above, in one embodiment of the present disclosure, the insulating layer is made of an organic material, the shape of the connecting electrode is columnar, and the connecting electrode is formed from at least solder and copper.

[0351] Specifically, one embodiment of the present disclosure is a semiconductor device in which a semiconductor device and a connected object, which is a semiconductor device or wiring device, are electrically connected by a plurality of columnar metal electrodes, wherein the columnar metal electrodes consist of a layer mainly composed of tin and copper, an organic insulating material is arranged around the columnar metal electrodes, and the area equivalent diameter of the portion including solder perpendicular to the axial direction of the columnar metal electrodes and the area equivalent diameter of the portion mainly composed of copper can be substantially the same. Furthermore, a barrier metal layer may be formed at the interface between the columnar metal electrodes and the organic insulating material.

[0352] A semiconductor device is a semiconductor device in which a semiconductor device and a connected object, which is a semiconductor device or a wiring device, are electrically connected by a plurality of columnar metal electrodes, wherein the columnar metal electrodes consist of a layer mainly composed of tin and copper, an organic insulating material is arranged around the columnar metal electrodes, and the area equivalent diameter of the portion containing solder perpendicular to the axial direction of the columnar metal electrodes and the area equivalent diameter of the portion mainly composed of copper may be substantially the same.

[0353] Furthermore, the semiconductor device may be formed from an organic insulating material made of a resin containing an imide ring.

[0354] Furthermore, the semiconductor device may contain inorganic particles in its organic insulating material.

[0355] Furthermore, the semiconductor device may have a structure in which columnar metal electrodes are stacked in the axial direction in the order of a layer mainly composed of copper, a layer mainly composed of tin, and a layer mainly composed of copper.

[0356] Furthermore, the semiconductor device may have a structure in which columnar metal electrodes are stacked in the axial direction, in contact with a layer in which a barrier metal layer is mainly composed of copper.

[0357] Furthermore, the semiconductor device may have an inorganic barrier layer formed at the interface between the columnar metal electrode and the organic insulating material.

[0358] Furthermore, the semiconductor device may have a maximum pitch between the columnar metal electrodes formed thereon that is 10 times or less, and particularly 3 times or less, the minimum pitch.

[0359] Furthermore, in regions where columnar metal electrodes are not formed, the semiconductor device may have a layer mainly composed of copper or a dummy pad made of tin formed on the surface of the semiconductor device and / or the connected object.

[0360] Furthermore, the semiconductor device may have a maximum pitch of dummy pads formed on the surface of the semiconductor device and / or connected object that is 10 times or less, particularly 3 times or less, the minimum pitch.

[0361] Furthermore, the semiconductor device may have a columnar metal electrode formation pitch of 25 μm or less.

[0362] Furthermore, the semiconductor device may have a columnar metal electrode formation pitch of 5 μm or less.

[0363] Furthermore, the semiconductor device may have an RDL interposer substrate.

[0364] Furthermore, the semiconductor device may have its outer periphery, which includes the semiconductor device and organic insulating material, covered with molding resin or silicon dioxide.

[0365] Furthermore, the method for manufacturing a semiconductor device includes the steps of: forming an organic insulating film on one main surface of a semiconductor device; curing the organic insulating film; forming holes in the organic insulating film on the electrodes by dry etching at a pitch corresponding to the electrode arrangement pitch; filling the holes with a layer mainly composed of copper and a metal mainly composed of tin to form columnar metal electrodes; and aligning the semiconductor device with a connected object which is another semiconductor device or wiring device and connecting them by flip-chip (thermocompression bonding).

[0366] The embodiments of the present invention have been described above. The present invention is not limited to the embodiments described above, and various modifications, variations, and combinations are possible.

[0367] (1) A semiconductor device in which a first semiconductor device and a connected object which is a second semiconductor device or a wiring device are electrically connected by a plurality of columnar metal electrodes, wherein the columnar metal electrodes have at least a layer mainly composed of tin and a layer mainly composed of copper, and an organic insulating material is arranged around the columnar metal electrodes.

[0368] (2) The semiconductor device according to (1), wherein the direction in which the columnar metal electrode extends is defined as the axial direction, and the area equivalent diameter of the portion containing a tin-based layer perpendicular to the axial direction is substantially the same as the area equivalent diameter of the portion containing a copper-based layer.

[0369] (3) The semiconductor device according to (1) or (2), further comprising a layer mainly composed of copper with a different area equivalent diameter from a layer mainly composed of tin on the first semiconductor device side or on the connected body side.

[0370] (4) The semiconductor device according to any one of (1) to (3), wherein the organic insulating material is made of a resin containing an imide ring.

[0371] (5) The semiconductor device according to any one of (1) to (4), wherein the organic insulating material contains (adds) at least one of inorganic particles and organic particles.

[0372] (6) A semiconductor device according to any one of (1) to (5), wherein the direction in which the columnar metal electrode extends is defined as the axial direction, and the columnar metal electrode is stacked in the axial direction in the order of a layer mainly composed of copper, a layer mainly composed of tin, and a layer mainly composed of copper.

[0373] (7) A semiconductor device according to any one of (1) to (6), wherein the direction in which the columnar metal electrode extends is defined as the axial direction, and in the columnar metal electrode, a barrier metal layer is laminated in contact with a layer mainly composed of copper in the axial direction.

[0374] (8) A semiconductor device according to any one of (1) to (7), wherein a barrier metal layer is located at the interface between a layer mainly composed of copper and a layer mainly composed of tin.

[0375] (9) A semiconductor device according to any one of (1) to (8), wherein the direction in which the columnar metal electrode extends is defined as the axial direction, and the barrier metal layer is arranged within a layer mainly composed of copper such that it divides the layer mainly composed of copper in the axial direction.

[0376] (10) The semiconductor device according to any one of (1) to (9), wherein the barrier metal layer is disposed at the interface between the layer mainly composed of copper and the electrode of the first semiconductor device or the connected object.

[0377] (11) The semiconductor device according to any one of (1) to (10), wherein an inorganic barrier layer is formed at the interface between the columnar metal electrode and the organic insulating material.

[0378] (12) The semiconductor device according to any one of (1) to (11), wherein the maximum pitch between the columnar metal electrodes is three times or less the minimum pitch between the columnar metal electrodes.

[0379] (13) A semiconductor device according to any one of (1) to (12), wherein in a region where the columnar metal electrode is not formed, a dummy pad consisting of a layer mainly composed of copper or a layer mainly composed of tin is formed on the surface of at least one of the first semiconductor device and the connected object.

[0380] (14) The semiconductor device according to any one of (1) to (13), wherein the maximum pitch of the dummy pads formed on the surface of at least one of the first semiconductor device and the connected object is three times or less the minimum pitch between the columnar metal electrodes formed thereon.

[0381] (15) The semiconductor device according to any one of (1) to (14), wherein the wiring device is an interposer including a rewiring layer.

[0382] (16) The semiconductor device according to any one of (1) to (15), wherein the outer periphery of the first semiconductor device and the organic insulating material is covered with a molding resin or silicon dioxide.

[0383] (17) A method for manufacturing a semiconductor device, comprising the steps of: forming an organic insulating film on one main surface of a semiconductor device; forming holes in the organic insulating film on the electrodes at locations corresponding to the positions of electrodes on the semiconductor device; sequentially filling the holes with a metal mainly composed of copper and a metal mainly composed of tin to form columnar metal electrodes; and aligning the semiconductor device with a connected object which is another semiconductor device or wiring device and connecting them by flip-chip (thermocompression bonding) connection.

[0384] (18) A method for manufacturing a semiconductor device, comprising the steps of: forming a resist film on one main surface of a semiconductor device; forming holes in the resist film at locations corresponding to the positions of electrodes on the semiconductor device by exposure and development; filling the holes with a metal mainly composed of copper and a metal mainly composed of tin to form columnar metal electrodes; removing the resist film; arranging an organic insulating film so as to cover the periphery of the columnar metal electrodes; performing a process to improve the flatness of the surfaces of the organic insulating film and the columnar metal electrodes; and aligning the semiconductor device with a connected object which is another semiconductor device or wiring device and connecting them by flip-chip (thermocompression bonding).

[0385] (19) A step of forming a first resist film on one main surface of a semiconductor device; a step of forming holes in the first resist film at locations corresponding to the positions of electrodes of the semiconductor device by exposure and development; a step of filling the holes with a metal mainly composed of copper to form a first portion of a columnar metal electrode; a step of removing the first resist film; a step of arranging an organic insulating film so as to cover the periphery of the first portion of the columnar metal electrode; a step of forming a second resist film on the organic insulating film; a step of forming holes in the second resist film at locations corresponding to the positions of the first portion of the columnar metal electrode by exposure and development; a step of forming holes in the organic insulating film at locations corresponding to the positions of the first portion of the columnar metal electrode by dry etching; a step of removing the second resist film; a step of filling the holes with a metal mainly composed of tin to form a second portion of a columnar metal electrode; a step of performing a process to improve the flatness of the surface of the organic insulating film and the first portion of the columnar metal electrode. A method for manufacturing a semiconductor device, comprising the steps of aligning the semiconductor device with a connected object which is another semiconductor device or wiring device, and connecting them by flip-chip (thermocompression bonding).

[0386] (20) A method for manufacturing a semiconductor device, comprising the steps of: forming a first portion of a columnar metal electrode made of a metal mainly composed of copper; arranging an organic insulating film so as to cover the periphery of the first portion of the columnar metal electrode; forming a hole in the organic insulating film at a location corresponding to the position of the first portion of the columnar metal electrode; filling the hole with a metal mainly composed of tin to form a second portion of the columnar metal electrode; performing a process to improve the flatness of the surface of the organic insulating film and the first portion of the columnar metal electrode; and aligning the semiconductor device with a connected object which is another semiconductor device or wiring device and connecting them by flip-chip (thermocompression bonding).

[0387] 1 Semiconductor device 2 Semiconductor device 3 Semiconductor device 4 Semiconductor device 5 Semiconductor device 6 Semiconductor device 7 Semiconductor device 8 Semiconductor device 9 Semiconductor device 10 Semiconductor device 10A First device 10B Second device 12 First substrate 14 First main surface 16 First electrode 30 Wiring device 32 Second substrate 34 Second main surface 36 Second electrode 40 Connected object 50 Connection part 52 Resin part 52A First resin part 52B Second resin part 54 Columnar metal electrode 56 Side surface 58 Inorganic insulating part 60 Connection terminal 61 First electrode part 62 Second electrode part 62B Base part 62T Protrusion part 63 Third electrode part 65 Electrode part 71 First through electrode 72 Second through electrode 80 Organic insulating material 82 Surface of organic insulating material 84 Resist film 86 Seed layer 88 Electrode layer 90 First recess 92 Second recess 94 Third recess 101 Semiconductor device 110 Semiconductor chip body 110A First semiconductor chip body 110B Second semiconductor chip body 112 Main surface 115 Interposer 116 Interposer body 117 Main surface 120 Bonding portion 121 Metal bonding portion 122 Resin bonding portion 125 Microbump-formed wafer 127 Semiconductor chip 127A First semiconductor chip 127B Second semiconductor chip 130 Layer to be bonded 130A First layer to be bonded 130B Second layer to be bonded 134 Metal bonding portion 134A First metal bonding portion 134B Second metal bonding portion 136 Resin bonding portion 136A First resin-bonded portion 136B Second resin-bonded portion 140 Organic insulating material layer (polyimide layer) 142 Organic insulating material layer pores (polyimide layer pores) 150 Photoresist layer 152 Photoresist layer pores 160 Seed layer 170 Copper layer 180 Solder layer 190 Bump 192 Metal layer 194 Thermal compression bonder 196 Thermal compression bonder 210 Semiconductor device 211 Semiconductor device 212 Semiconductor device 213 Semiconductor device 214 Semiconductor device 215 Semiconductor device 216 Semiconductor device 217 Semiconductor device 218 Semiconductor device 219 Semiconductor device 220 Semiconductor device 301 First wiring device 302 Second wiring device 311 Fifth main surface 312 Sixth main surface321 Ninth main surface 322 Tenth main surface 400 Barrier metal layer 401 First barrier metal layer 402 Second barrier metal layer 403 Third barrier metal layer 410 Inorganic barrier layer 420 Molded part 421 First molded part 422 Second molded part 423 Third molded part 501 First connection part 502 Second connection part 511 Third main surface 512 Fourth main surface 521 Seventh main surface 522 Eighth main surface 601 Substrate 610 First conductor part 620 Insulator layer 621 Insulator layer opening 622 Second insulator layer opening 622 Insulator layer opening 623 Insulator layer hole 630 Resist layer 632 Resist opening 640' Dummy conductor 640 Second conductor part 720 Resist film 721 Resist film opening 722 Second resist film opening 1010 Axial direction 1020 Main surface direction 1500 Upward direction 1510 Surface direction 1520 Pressing direction 1601 Lamination direction

Claims

A semiconductor device in which a first semiconductor device and a connected object which is a second semiconductor device or a wiring device are electrically connected by a plurality of columnar metal electrodes, The columnar metal electrode has at least a layer mainly composed of tin and a layer mainly composed of copper, and an organic insulating material is arranged around the columnar metal electrode. Semiconductor equipment. 　 The direction in which the columnar metal electrode extends is defined as the axial direction, The area equivalent diameter of the portion containing the tin-based layer perpendicular to the axial direction and the area equivalent diameter of the portion containing the copper-based layer are substantially the same. The semiconductor device according to claim 1. 　 The first semiconductor device side, or the connected object side, further includes a layer mainly composed of tin and a layer mainly composed of copper with a different area equivalent diameter, The semiconductor device according to claim 1. 　 The aforementioned organic insulating material is made of a resin containing an imide ring. The semiconductor device according to claim 1. 　 The aforementioned organic insulating material contains at least one of inorganic particles and organic particles. The semiconductor device according to claim 1. 　 The direction in which the columnar metal electrode extends is defined as the axial direction, The columnar metal electrode is constructed by stacking layers in the axial direction, in the order of a layer mainly composed of copper, a layer mainly composed of tin, and a layer mainly composed of copper. The semiconductor device according to claim 1. 　 The direction in which the columnar metal electrode extends is defined as the axial direction, In the columnar metal electrode, the barrier metal layer is laminated in contact with a layer mainly composed of copper in the axial direction. The semiconductor device according to claim 1. 　 A barrier metal layer is placed at the interface between a layer mainly composed of copper and a layer mainly composed of tin. The semiconductor device according to claim 1. 　 The direction in which the columnar metal electrode extends is defined as the axial direction, The barrier metal layer is arranged within a layer mainly composed of copper, such that it divides the copper-based layer in the axial direction. The semiconductor device according to claim 1. 　 The barrier metal layer is disposed at the interface between the copper-based layer and the electrode of the first semiconductor device or the connected object. The semiconductor device according to claim 1. 　 An inorganic barrier layer is formed at the interface between the columnar metal electrode and the organic insulating material. The semiconductor device according to claim 1. 　 The maximum pitch between the columnar metal electrodes is three times or less the minimum pitch between the columnar metal electrodes. The semiconductor device according to claim 1. 　 In a region where the columnar metal electrode is not formed, a dummy pad consisting of a layer mainly composed of copper or a layer mainly composed of tin is formed on the surface of at least one of the first semiconductor device and the connected object. The semiconductor device according to claim 1. 　 The maximum pitch of the dummy pads formed on at least one of the first semiconductor device and the connected object is three times or less the minimum pitch between the columnar metal electrodes formed thereon. The semiconductor device according to claim 1. 　 The wiring device is an interposer including a rewiring layer. The semiconductor device according to claim 1. 　 The outer periphery of the first semiconductor device and the organic insulating material is covered with a molding resin or silicon dioxide. The semiconductor device according to claim 1. 　 A process for depositing an organic insulating film on one main surface of a semiconductor device, The process of forming holes in the organic insulating film on the electrode at locations corresponding to the positions of the electrodes of the semiconductor device, The process of forming a columnar metal electrode by sequentially filling the aforementioned hole with a metal mainly composed of copper and a metal mainly composed of tin, The process includes aligning the semiconductor device with another semiconductor device or wiring device, and connecting them by thermocompression bonding. A method for manufacturing a semiconductor device. 　 A process of forming a resist film on one main surface of a semiconductor device, The process involves forming holes in the resist film at locations corresponding to the electrode positions of the semiconductor device by exposure and development, A step of filling the aforementioned hole with a metal mainly composed of copper and a metal mainly composed of tin to form a columnar metal electrode, The step of removing the resist film, A step of arranging an organic insulating film so as to cover the periphery of the columnar metal electrode, A step of performing a process to improve the flatness of the surface of the organic insulating film and the columnar metal electrode, The process includes aligning the semiconductor device with another semiconductor device or wiring device, and connecting them by thermocompression bonding. A method for manufacturing a semiconductor device. 　 A step of forming a first resist film on one main surface of a semiconductor device, The first resist film is subjected to exposure and development to form holes at locations corresponding to the electrode positions of the semiconductor device, A step of filling the aforementioned hole with a metal mainly composed of copper to form the first part of a columnar metal electrode, A step of removing the first resist film, A step of arranging an organic insulating film so as to cover the periphery of the first portion of the columnar metal electrode, A step of forming a second resist film on the aforementioned organic insulating film, The process of forming holes in the second resist film at locations corresponding to the positions of the first portion of the columnar metal electrode by exposure and development, The process of forming holes in the organic insulating film at locations corresponding to the position of the first portion of the columnar metal electrode by dry etching, A step of removing the second resist film, The process of filling the aforementioned hole with a metal mainly composed of tin to form the second part of the columnar metal electrode, A step of performing a process to improve the flatness of the surface of the first portion of the organic insulating film and the columnar metal electrode, The process includes aligning the semiconductor device with another semiconductor device or wiring device, and connecting them by thermocompression bonding. A method for manufacturing a semiconductor device.

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