Capacitor wiring structure, method for manufacturing capacitor wiring structure, wiring layer with capacitor, laminated wiring board with capacitor, and semiconductor device

Abstract

This capacitor wiring structure is provided with a capacitor body including a power supply electrode, a ground electrode, a power supply electrode terminal, a ground electrode terminal connected to the ground electrode, and a dielectric layer, and a wiring part including a signal line penetrating, in the capacitor body, the power supply electrode, the dielectric layer, and the ground electrode, and a signal line connection terminal to which the signal line is connected. The power supply electrode terminal, the ground electrode terminal, and the signal line connection terminal are configured in such a manner that, in a planar view, the shape obtained by connecting the central axes thereof together by straight lines is a polygonal shape, and that at least two of the distances between the central axes are equal.

Description

Capacitor wiring structure, method for manufacturing a capacitor wiring structure, capacitor-equipped wiring layer, capacitor-equipped multilayer wiring substrate, and semiconductor device.

[0001] This disclosure relates to a capacitor wiring structure, a method for manufacturing a capacitor wiring structure, a capacitor-equipped wiring layer, a capacitor-equipped multilayer wiring substrate, and a semiconductor device.

[0002] Conventionally, a technique is known for placing a capacitor with a decoupling function within a high-speed semiconductor device (see, for example, Patent Document 1).

[0003] Japanese Patent Publication No. 2015-53350

[0004] The first capacitor wiring structure according to this disclosure comprises a capacitor body having a power electrode, a ground electrode, a power electrode terminal connected to the power electrode, a ground electrode terminal connected to the ground electrode, and a dielectric layer having a first surface on which the power electrode terminal is located and a second surface on which the ground electrode terminal is located opposite to the first surface, and a signal line section including a signal line penetrating the power electrode, the dielectric layer, and the ground electrode, and a signal line connection terminal to which the signal line is electrically connected, wherein in a plan view, the power electrode terminal, the ground electrode terminal, and the signal line connection terminal have a polygonal shape when their respective central axes are connected by a straight line, and the signal line connection terminal, the power electrode terminal, and the ground electrode terminal are configured such that at least two of the distances between the signal line connection terminal and the power electrode terminal, the power electrode terminal and the ground electrode terminal, and the signal line connection terminal and the ground electrode terminal are equal.

[0005] The second capacitor wiring structure according to this disclosure comprises a capacitor body having a power electrode, a ground electrode, a power electrode terminal connected to the power electrode, a ground electrode terminal connected to the ground electrode, and a dielectric layer having a first surface on which the power electrode terminal is located and a second surface on which the ground electrode terminal is located opposite to the first surface, and a signal line section including a signal line penetrating the power electrode, the dielectric layer, and the ground electrode, and a signal line connection terminal to which the signal line is electrically connected, wherein in a plan view, the power electrode terminal, the ground electrode terminal, and the signal line connection terminal have a polygonal shape when their respective central axes are connected by a straight line, and the number of power electrode terminals is different from the number of ground electrode terminals, and the signal line connection terminal, the power electrode terminal, and the ground electrode terminal are configured such that at least two of the distances between the signal line connection terminal and the power electrode terminal, the power electrode terminal and the ground electrode terminal, and the signal line connection terminal and the ground electrode terminal are equal.

[0006] The third capacitor wiring structure according to this disclosure comprises a capacitor body having a power electrode, a ground electrode, a power electrode terminal connected to the power electrode, a ground electrode terminal connected to the ground electrode, and a dielectric layer having a first surface on which the power electrode terminal is located and a second surface on which the ground electrode terminal is located opposite to the first surface; and a signal line section including a signal line penetrating the power electrode, the dielectric layer, and the ground electrode, and a signal line connection terminal to which the signal line is electrically connected. In a plan view, the power electrode terminal, the ground electrode terminal, and the signal line connection terminal have a regular hexagonal shape when their respective central axes are connected by a straight line, and the signal line connection terminal, the power electrode terminal, and the ground electrode terminal are configured such that at least two of the following distances are equal: the distance between the signal line connection terminal and the power electrode terminal, the distance between the power electrode terminal and the ground electrode terminal, and the distance between the signal line connection terminal and the ground electrode terminal.

[0007] The capacitor-equipped wiring layer according to this disclosure includes the capacitor wiring structure described above and a wiring portion laminated on the capacitor wiring structure.

[0008] The capacitor-equipped multilayer wiring board according to this disclosure includes the capacitor wiring structure described above, a wiring portion laminated on the capacitor wiring structure, and a base substrate on which the capacitor wiring structure and the wiring portion are mounted.

[0009] The semiconductor device according to this disclosure includes the capacitor wiring structure described above, a wiring portion laminated on the capacitor wiring structure, a base substrate on which the capacitor wiring structure and the wiring portion are mounted, and a semiconductor element mounted on the wiring portion.

[0010] A method for manufacturing a capacitor wiring structure according to the present disclosure includes the steps of: forming an adhesive layer on a base substrate; laminating and bonding a first metal foil on the adhesive layer; forming a dielectric layer on the first metal foil; laminating and bonding a second metal foil on the dielectric layer; forming an insulating layer on the second metal foil; preparing a capacitor wiring structure precursor by forming the adhesive layer, the first metal foil, the dielectric layer, the second metal foil, and the insulating layer; forming through holes; and forming via conductors in the through holes, wherein the step of forming via conductors in the through holes includes the step of positioning the via conductors such that, in a plan view, the shape when the central axes of the via conductors are connected by straight lines is a polygon, and at least two of the distances between the central axes are equal.

[0011] The purposes, features, and advantages of this disclosure will become clearer from the detailed description and drawings below. A perspective view showing a capacitor wiring structure of the first embodiment of this disclosure. A cross-sectional view showing a semiconductor device comprising the capacitor wiring structure. A plan view showing the via arrangement of the capacitor wiring structure. A plan view showing the power electrode. A plan view showing the ground electrode. A plan view showing the power electrode and ground electrode superimposed. A plan view showing the via arrangement of the capacitor wiring structure of the second embodiment. A plan view showing the power electrode of the capacitor wiring structure. A plan view showing the ground electrode of the capacitor wiring structure. A plan view showing the power electrode and ground electrode superimposed. A plan view showing the arrangement structure of the power electrode terminal, ground electrode terminal, and signal line connection terminal of the capacitor wiring structure of the third embodiment of this disclosure. A plan view showing the arrangement structure of the power electrode terminal, ground electrode terminal, and signal line connection terminal of a comparative example. A plan view showing a hexagonal capacitance acquisition area. A plan view showing a square capacitance acquisition area. A plan view showing a capacitance acquisition area in which the power electrode terminal, ground electrode terminal, and signal line connection terminal of the fourth embodiment are arranged in an irregular hexagonal shape. This is a cross-sectional view showing the via array type capacitor body of the fifth embodiment. This is a cross-sectional view showing the stacked via array capacitor body of the sixth embodiment. This is a perspective view showing the capacitor wiring structure of the seventh embodiment. This is a cross-sectional view showing the first application example of the capacitor wiring structure of the eighth embodiment. This is a cross-sectional view showing the second application example of the capacitor wiring structure of the ninth embodiment. This is a cross-sectional view showing the third application example of the capacitor wiring structure of the tenth embodiment. This is a flowchart for explaining the manufacturing method of an interposer substrate, which is the first application example of the capacitor wiring structure of Figure 12A. This is a cross-sectional view for explaining the second step of the manufacturing method of the interposer substrate. This is a cross-sectional view for explaining the third step of the manufacturing method of the interposer substrate. This is a cross-sectional view for explaining the fourth step of the manufacturing method of the interposer substrate. This is a cross-sectional view for explaining the fifth step of the manufacturing method of the interposer substrate. This is a cross-sectional view for explaining the sixth step of the manufacturing method of the interposer substrate. This is a cross-sectional view for explaining the seventh step of the manufacturing method of the interposer substrate.This is a cross-sectional view illustrating the eighth step in the method for manufacturing an interposer substrate. This is a cross-sectional view illustrating the ninth step in the method for manufacturing an interposer substrate. This is a cross-sectional view illustrating the tenth step in the method for manufacturing an interposer substrate. This is a cross-sectional view illustrating the eleventh step in the method for manufacturing an interposer substrate.

[0012] In high-speed semiconductor devices, malfunctions and performance degradation due to fluctuations in signal and power supply voltages are problematic. To address these issues, a technique is known in which a capacitor with a decoupling function is placed within the semiconductor device. The capacitor is configured to bridge the gap between the power line and the ground line connected to the integrated circuit (LSI) that constitutes the semiconductor device. Patent document 1 describes a technique in which a capacitor is placed in the wiring substrate directly beneath the integrated circuit in order to enhance the decoupling effect of the capacitor.

[0013] In the technology described in Patent Document 1, as the number of transistors in an integrated circuit increases, the integration density increases, the number of input / output terminals in the integrated circuit increases, and the distance between input / output terminals decreases, it becomes necessary to reduce the distance between the positive and negative electrodes of the capacitor formed in the wiring board. Furthermore, since the capacitor is positioned to bridge the gap between the power line and the ground line, it is necessary to arrange a large number of signal lines in the wiring board. Arranging a large number of signal lines in the wiring board can reduce the capacitance per unit area of ​​the capacitor. There is a need for a capacitor wiring structure, a method for manufacturing a capacitor wiring structure, a wiring layer with a capacitor, a multilayer wiring board with a capacitor, and a semiconductor device that can reduce the decrease in capacitance even when signal lines are formed in the wiring board.

[0014] Embodiments of this disclosure will be described below with reference to the drawings. In each drawing, the same or substantially the same elements or parts are denoted by the same reference numeral, and redundant descriptions are omitted or simplified. The drawings used in the following description are schematic, and the dimensional ratios, shapes, etc. shown in the drawings do not necessarily correspond to those of the actual objects.

[0015] Figure 1 is a perspective view showing a capacitor wiring structure according to a first embodiment of the present disclosure, and Figure 2 is a cross-sectional view showing a semiconductor device equipped with the capacitor wiring structure. In the figures, the reference numeral "G" indicates a ground path, the reference numeral "S" indicates a signal path, and the reference numeral "P" indicates a power path. In this embodiment, the capacitor-equipped wiring layer 4 is composed of a capacitor wiring structure 1 and a wiring section (i.e., a build-up layer) 3. The capacitor-equipped multilayer wiring substrate 6 comprises a wiring section 3, a capacitor wiring structure 1, and a base substrate 7 located on the opposite side of the wiring section 3 from the capacitor wiring structure 1. The semiconductor device 8 is configured in which a semiconductor element 9 is mounted on the wiring section 3 of the capacitor-equipped multilayer wiring substrate 6.

[0016] The wiring section 3 has multiple through holes, and the first via 18, the second via 19, the third via (hereinafter sometimes referred to as "signal line") 16, and the fourth via 21 are each located within the multiple through holes.

[0017] In Figures 1 and 2, the semiconductor element 9 is mounted on the capacitor wiring structure 1 via the wiring section 3, but the semiconductor element 9 may also be mounted directly on the capacitor wiring structure 1. Also, Figures 1 and 2 show a part of the capacitor wiring structure 1. That is, the capacitor wiring structure 1 shows a configuration in which the capacitor body 2 and the wiring section 3 are wide in the lateral direction, but it may also be a configuration having multiple capacitor wiring structures 1 as constituent units. The constituent unit of the capacitor wiring structure 1 may be a region with a rectangular or hexagonal shape in plan view, formed by tracing the power electrode terminals 11, ground electrode terminals 12, and signal line connection terminals 13 which are arranged facing each other in the thickness direction with the dielectric layer 10 in between. Furthermore, the capacitance of the capacitor wiring structure 1 may extend to the outside of its constituent unit in part. This is due to the electric field distribution caused by the insulating effect of the capacitor, where the dielectric layer 10 is sandwiched between two power electrodes 14 and ground electrode 15.

[0018] The semiconductor device 8, the capacitor-equipped wiring layer 4, and the capacitor wiring structure 1 are wired such that the power electrode 14 connected to the power line connected to the external power supply is the positive electrode, and the ground electrode 15 connected to the ground wiring is the negative electrode. The function of this semiconductor device 8 is to discharge the superimposed noise (AC current) of the current (DC current) supplied from the power line to the semiconductor element 9 through the capacitor-equipped wiring layer 4 or the capacitor-equipped multilayer wiring board 6 to the grounded power supply through the ground wiring.

[0019] In the capacitor wiring structure 1 or the capacitor-equipped wiring layer 4, it is preferable that most of the signal lines 16 are arranged within a region that includes the outline formed by the connection of the via conductor for power electrode junction and the via conductor for ground electrode. Although only one signal line 16 is shown in Figures 1 and 2, it goes without saying that a number of signal lines 16 corresponding to the number of gates in the semiconductor device 8 will be formed.

[0020] The capacitor-equipped wiring layer 4 of this embodiment includes a capacitor body 2 and a wiring section 3. The capacitor body 2 comprises a power electrode 14, a ground electrode 15, a power electrode terminal 11 connected to the power electrode 14, a ground electrode terminal 12 connected to the ground electrode 15, and a dielectric layer 10. The dielectric layer 10 has a first surface 10a on which the power electrode terminal 11 is located, and a second surface 10b located on the opposite side from the first surface 10a on which the ground electrode 15 is located.

[0021] The capacitor wiring structure 1 comprises a power electrode 14, a dielectric layer 10, a ground electrode 15, a signal line 16 that penetrates the ground electrode 15, and a signal line section 17 including a signal line connection terminal 13 to which the signal line 16 is connected.

[0022] The power electrode terminal 11, the ground electrode terminal 12, and the signal line connection terminal 13 are arranged such that, in a plan view, the shape formed by connecting the central axes L1, L2, and L3 of the power electrode terminal 11, the ground electrode terminal 12, and the signal line connection terminal 13 with straight lines is a polygon. The signal line 16 is electrically connected to the signal line connection terminal 13 and is positioned so that it can be replaced by at least one of the power electrode terminal 11 and the ground electrode terminal 12. The signal line connection terminal 13, the power electrode terminal 11, and the ground electrode terminal 12 are configured such that at least two of the distances between the signal line connection terminal 13 and the power electrode terminal 11, the power electrode terminal 11 and the ground electrode terminal 12, and the signal line connection terminal 13 and the ground electrode terminal 12 are equal.

[0023] With this configuration, the capacitor body 2 can maintain its inherently obtainable capacitance while the signal line 16 can be placed within the region of the capacitor body 2. Therefore, even if the signal line portion 17 is formed in the wiring portion 3 of the capacitor body 2, a capacitor wiring structure 1, a capacitor-equipped wiring layer 4, a capacitor-equipped multilayer wiring substrate 6, and a semiconductor device 8 can be obtained that can minimize the decrease in capacitance.

[0024] Figure 3A is a plan view showing the via arrangement of the capacitor wiring structure, and Figure 3B is a plan view showing the power supply electrode. Figure 3C is a plan view showing the ground electrode, and Figure 3D is a plan view showing the power supply electrode and the ground electrode superimposed. The capacitor wiring structure 1 shown in Figures 3A to 3D has a first via 18 connected to the power supply electrode terminal 11, a second via 19 connected to the ground electrode terminal 12, a third via 16 connected to the signal line connection terminal 13, and a fourth via 21 connected to the second power supply electrode terminal.

[0025] The power electrode 14 shown in Figure 3B has a first notch 22a for electrically connecting the first via 18 and the power electrode 14, a second notch 23a for electrically insulating the second via 19 and the power electrode 14, a third notch 24a for insulating the third via 16 and the power electrode 14, and a fourth notch 25a for electrically connecting the fourth via 21 and the power electrode 14. These first to fourth notches 22a to 25a are quarter-circular in shape in plan view, the second notch 23a and the third notch 24a each have a radius to ensure a distance sufficient to insulate the power electrode 14 from the second via 19 and the third via 16, and the first notch 22a and the fourth notch 25a each have a radius that allows for electrical connection to the first via 18 and the fourth via 21.

[0026] The ground electrode 15 shown in Figure 3C has a first notch 22b for insulating the first via 18 from the ground electrode 15, a second notch 23b for electrically connecting the second via 19 from the ground electrode 15, a third notch 24b for insulating the third via 16 from the ground electrode 15, and a fourth notch 25b for electrically insulating the fourth via 21 from the ground electrode 15. These first to fourth notches 22b to 25b are quarter-circular in shape in plan view, and the first notch 22b, the third notch 24b, and the fourth notch 25b each have radii for insulating the first via 18, the third via 16, and the fourth via 21 from the ground electrode 15, while the second notch 23b has a radius that allows for the electrical connection of the second via 19 from the ground electrode 15.

[0027] The signal line, via 3 via 16, is connected to BaTiO ３ It is preferable that the dielectric layer 10 does not come into contact with the signal line, the third via 16. ３ When the dielectric layer 10 is in contact with the signal line via, a parasitic capacitance is formed between the third via 16, which is a signal line via, and the power supply electrode 14 and the ground electrode 15, with the dielectric layer 10 acting as a capacitor. Therefore, BaTiO ３The dielectric constant of the dielectric layer 10, which is formed from ceramic materials such as [material name], is high, and the parasitic capacitance C value increases unnecessarily, resulting in a mismatch in characteristic impedance Z0. This mismatch may degrade signal transmission. Therefore, in a capacitor-embedded multilayer wiring board and its manufacturing method, in which sintered ceramic material is laid as a thin-film capacitor layer across the entire substrate, it becomes necessary to reduce the degradation of signal transmission due to parasitic capacitance caused by the capacitor dielectric film near the signal line vias. Structures in which the signal line 16 and the dielectric layer 10 do not come into contact will be described later with reference to Figure 11.

[0028] With the capacitor wiring structure 1 equipped with the power electrode 14 and ground electrode 15 configured in this way, as shown in Figure 3D, an overlapping region (hatched area) of the power electrode 14 and ground electrode 15 is obtained, thereby reducing the decrease in capacitance and eliminating noise in the wiring section 3.

[0029] The capacitor wiring structure 1 shown in Figures 4A to 4D includes a first via 18 connected to the power electrode terminal 11, a second via 19 connected to the ground electrode terminal 12, a third via 16 connected to the signal line connection terminal 13, and a fourth via 21 connected to the signal line connection terminal 13. Figure 4A is a plan view showing the via arrangement of the capacitor wiring structure of the second embodiment, Figure 4B is a plan view showing the power electrode of the capacitor wiring structure, Figure 4C is a plan view showing the ground electrode of the capacitor wiring structure, and Figure 4D is a plan view showing the power electrode and ground electrode superimposed. The same reference numerals are used for parts corresponding to the previously described embodiments, and redundant explanations are omitted. Compared to the via arrangement shown in Figure 3A, the capacitor wiring structure 1 of this embodiment has a fourth via 21 connected to the signal line connection terminal 13 instead of the fourth via 21 connected to the second power electrode terminal. Therefore, as shown in Figure 4C, a large-diameter fourth notch 25a is formed in the power supply electrode 14, and as shown in Figure 4D, when the power supply electrode 14 and the ground electrode 15 overlap, an overlapping region (hatched area) identical or similar to that in the embodiments of Figures 3A to 3D is obtained.

[0030] Figure 5 is a plan view showing the arrangement of power electrode terminals, ground electrode terminals, and signal line connection terminals of a capacitor wiring structure according to the third embodiment of the present disclosure, and Figure 6 is a plan view showing the arrangement of power electrode terminals, ground electrode terminals, and signal line connection terminals of a comparative example. The capacitor wiring structure 1 of this embodiment has a first via 18 connected to the power electrode terminal 11, a second via 19 connected to the ground electrode terminal 12, a third via 16 connected to the signal line connection terminal 13, and a fourth via 21 connected to the second signal line connection terminal.

[0031] The power electrode 14 shown in Figure 4B has a first notch 22a for electrically connecting the first via 18 and the power electrode 14, a second notch 23a for electrically insulating the second via 19 and the power electrode 14, a third notch 24a for electrically insulating the third via 16 and the power electrode 14, and a fourth notch 25a for insulating the fourth via 21 and the power electrode 14.

[0032] The ground electrode 15 shown in Figure 4C has a first notch 22b for electrically insulating the first via 18 from the ground electrode 15, a second notch 23b for electrically connecting the second via 19 from the ground electrode 15, a third notch 24b for electrically insulating the third via 16 from the ground electrode 15, and a fourth notch 25b for insulating the fourth via 21 from the ground electrode 15. These first to fourth notches 22b to 25b are quarter-circular in shape. The first notch 23a and the second notch 24b have radii for electrically connecting the first via 18 from the power electrode 14 and the third via 16 from the ground electrode 15, respectively, while the other notches have radii for insulating from the ground electrode 15.

[0033] With the capacitor wiring structure 1 equipped with the power supply electrode 14 and ground electrode 15 configured in this way, as shown in Figure 4D, an overlapping region of the power supply electrode 14 and the ground electrode 15 is obtained, and since the overlapping region is the same as in Figure 3D, the decrease in capacitance is reduced and noise from the semiconductor power supply can be removed.

[0034] The first to fourth vias 18, 19, 16, and 21 described above are discussed below. Examples of via diameters in IC die interposers are as follows: Vias include microvias, standard vias, and through silicon vias (TSVs). Microvias have a diameter in the range of 10 μm to 50 μm. They can be used in high-density packaging (HDI) substrates and advanced packaging (e.g., 3DIC, system packages). Standard vias have a diameter in the range of 50 μm to 150 μm. They can be used in more general interposers or printed circuit boards (PCBs). Through silicon vias have a diameter in the range of 5 μm to 10 μm. They can be used in 3DIC stacking and silicon interposers. In particular, advanced packaging technology makes miniaturization to 10 μm or less possible.

[0035] Let's discuss the via pitch distance a. If the first to fourth vias 18, 19, 16, and 21 are microvias, the via pitch distance a for the microvias can be 40 μm to 50 μm. If the first to fourth vias 18, 19, 16, and 21 are standard vias, the via pitch distance a for the standard vias can be 100 μm to 150 μm.

[0036] The diameter 2r of the insulating region around vias in an IC die interposer can be set to a value obtained by adding several tens of micrometers to the via diameter. For microvias, a value obtained by adding approximately 10 to 20 micrometers to the via diameter can be used as the diameter 2r of the insulating region. For standard vias, a value obtained by adding approximately 20 to 40 micrometers to the via diameter can be used as the diameter 2r of the insulating region. For example, if the via diameter is 100 micrometers, the diameter 2r of the insulating region can be set to approximately 120 to 140 micrometers.

[0037] Describe the ratio between the number of electrode pads for signal input / output and the number of electrode pads for power supply. The electrode pads for signal input / output are related to the functions and communication interfaces of the IC chip, and the number thereof greatly depends on the functions and pin numbers of the IC. For example, in general-purpose ICs such as microprocessors or microcontrollers, the number of electrode pads for signal input / output often increases.

[0038] The electrode pads for power supply are used for power supply and connection to the ground power supply. Compared with the number of pads of the electrode pads for signal input / output, the relative number of pads is less. However, in high-performance digital ICs and analog ICs, the number of pads of the electrode pads for power supply may also increase.

[0039] As a specific ratio of the number of pads, it varies depending on the application and design of the IC. In general ICs, the number of electrode pads for signal input / output is more than the number of electrode pads for power supply. For example, a ratio of the number of electrode pads for signal input / output accounting for 70% of the total number of pads and the number of electrode pads for power supply accounting for 30% can be cited. The ratio between the number of electrode pads for signal input / output and the number of electrode pads for power supply can be approximately 2:1.

[0040] The capacitor wiring structure 1 of the third embodiment includes a capacitor body 2 having a dielectric layer 10 with a power electrode 14, a ground electrode 15, a power electrode terminal 11 connected to the power electrode 14, a ground electrode terminal 12 connected to the ground electrode 15, and a first surface 10a where the power electrode terminal 11 is provided, and a second surface 10b where the ground electrode terminal 12 is provided and is located on the side opposite to the first surface 10a, and a signal line portion 17 including a signal line 16 penetrating the power electrode 14, the dielectric layer 10, and the ground electrode 15, and a signal line connection terminal 13 to which the signal line 16 is connected.

[0041] The power electrode terminal 11, the ground electrode terminal 12, and the signal line connection terminal 13 are, in a plan view, polygonal in shape when the central axes L1, L2, and L3 of these power electrode terminal 11, ground electrode terminal 12, and signal line connection terminal 13 are connected by straight lines. The number of power electrode terminals 11 and the number of ground electrode terminals 12 are not limited to the same number and may be different. The signal line 16 is electrically connected to the signal line connection terminal 13 and is disposed at a position replaceable with at least one of the power electrode terminal 11 and the ground electrode terminal 12.

[0042] According to such a configuration, while ensuring the capacitance that the capacitor body 2 can originally obtain, the signal line 16 can be passed through the region of the capacitor body 2. Therefore, in the capacitor body 2, the power electrode terminal 11 and the ground electrode terminal 12 can be made numerically unbalanced, and as a result, the signal line 16 can be arranged so that the power electrode terminal 11 or the ground electrode terminal 12 with the smaller number is replaced by the signal line connection terminal 13. By this, even if the signal line 16 is formed in the wiring portion 3, the capacitor wiring structure 1 and the wiring layer 4 with a capacitor having a small decrease in capacitance can be obtained.

[0043] According to such a configuration, since the arrangement of the power electrode 14 and the ground electrode 15 in the capacitor body 2 can be adjusted to make the number of power electrodes 14 and the number of ground electrodes 15 close to each other, the electric field dispersion progresses, the electric field concentration degree is suppressed, and the equivalent series inductance (ESL) and the equivalent series resistance (ESR) can be reduced.

[0044] As shown in FIG. 5, in the capacitor wiring structure 1 of the fourth embodiment, when the signal line 16, the power electrode terminal 11, and the ground electrode terminal 12 are arranged in a polygonal shape at equal distances from each other, the shape when the central axes of the signal line 16, the power electrode terminal 11, and the ground electrode terminal 12 are connected by straight lines is a hexagon.

[0045] With this configuration, the shape of the plane on which the signal line 16, power electrode terminal 11, and ground electrode terminal 12 are arranged is hexagonal. As shown in Figures 5 and 6, when the distance a is reduced under the condition that distance a / 2 > radius r, the area in which the power electrode 14 and ground electrode 15 overlap across the dielectric layer 10 can be increased compared to the case where the shape of the plane on which the signal line 16, power electrode terminal 11, and ground electrode terminal 12 are arranged is square.

[0046] In this embodiment, the signal line connection terminal 13, the power electrode terminal 11, and the ground electrode terminal 12 are configured such that at least two of the following distances are equal: b1 between the signal line connection terminal 13 and the power electrode terminal 11, b2 between the power electrode terminal 11 and the ground electrode terminal 12, and b3 between the signal line connection terminal 13 and the ground electrode terminal 12. Therefore, the shape formed by connecting the central axes of the first via 18, the second via 19, and the third via 16 with straight lines is positioned as a polygon in plan view, and is set so that at least two of the distances b1, b2, and b3 between the central axes are equal. In other embodiments, unlike the number of power electrode terminals 11 and the number of ground electrode terminals 12, the signal line connection terminal 13, power electrode terminal 11, and ground electrode terminal 12 may be configured such that at least two of the distances b1 between the signal line connection terminal 13 and the power electrode terminal 11, b2 between the power electrode terminal 11 and the ground electrode terminal 12, and b3 between the signal line connection terminal 13 and the ground electrode terminal 12 are equal.

[0047] The ratio of the number of power pads for signal input / output to the number of power pads for power supply can easily be set to 2:1. For example, in a via configuration of six locations, one can be used as a power electrode terminal 11, one as a ground electrode terminal 12, and the other four as signal line connection terminals 13, thereby ensuring a high signal line connection terminal ratio without reducing capacitance. Furthermore, by increasing the number of signal line connection terminals 13 and arranging the signal line connection terminals 13, including the third via 16, in a hexagonal shape, the dispersion of the electric field distribution within the planes of the power electrode 14 and ground electrode 15 can be improved. This reduces the concentration of the electric field at either the power electrode 14 or the ground electrode terminal 12 within the capacitor body 2, thereby lowering the equivalent series inductance (ESL) and equivalent series resistance (ESR).

[0048] Figure 7A is a plan view showing a hexagonal capacitance acquisition region, and Figure 7B is a plan view showing a square capacitance acquisition region. Figures 7A and 7B show unit units of a capacitor wiring structure and are drawn as schematic diagrams to the same scale. The size of the power electrode terminal 11 and the ground electrode terminal 12, and the insulating regions surrounding them are the same size, and the area within the dashed-dotted line of the hexagon in Figure 7A and the area within the dashed-dotted lines of the two squares in Figure 7B are depicted as having the same area. In other words, each capacitor wiring structure 1, in which the unit units of Figures 7A and 7B are arranged in a matrix, has the same number of vias per unit area. However, the capacitance that can be acquired differs greatly between the two. As is clear from Figures 7A and 7B, the honeycomb grid arrangement can acquire more capacitance than the square grid arrangement. Therefore, the hexagonal via arrangement has a high noise removal capability for semiconductor power supplies.

[0049] Figure 8 is a simplified perspective view showing the capacitor wiring structure 1 in which the power electrode terminals, ground electrode terminals, and signal line connection terminals of the fourth embodiment are arranged in an irregular hexagonal shape. The power electrode terminals 11, ground electrode terminals 12, and signal line connection terminals 13 may be arranged in an irregular hexagonal shape with uneven side lengths and interior angles, as shown by the dashed line in Figure 8.

[0050] Figure 9 is a cross-sectional view showing the via array type capacitor body of the fifth embodiment. By adopting the via array type capacitor body 2, the capacitor body 2 contains via conductors (second via 19) that serve as power lines connecting the semiconductor element 9 to the power supply, and via conductors (first via 18) that serve as ground power lines connecting the semiconductor element 9 to the ground power supply. Thus, the power lines and ground power lines are arranged in a direction along the thickness direction of the substrate portion 3a of the wiring portion 3.

[0051] In the via array type capacitor body 2, as shown in Figures 7A and 7B, a hexagonal via arrangement allows for a greater capacitance to be obtained compared to a rectangular arrangement when comparing capacitor bodies 2 of the same area and number of vias, thereby more effectively reducing noise in power supply to ICs and the like.

[0052] Figure 10 is a cross-sectional view showing the main body of a stacked via array capacitor according to the sixth embodiment. The capacitor body 2 of this embodiment can improve capacitance and reduce internal resistance (inductance). By incorporating and arranging the stacked via array capacitor in the capacitor wiring structure 1, stabilization of the power supply to the IC can be expected. Furthermore, instead of the conventional square grid via matrix, a regular hexagonal grid via arrangement matrix may be adopted. With a regular hexagonal grid via arrangement matrix, the capacitance acquisition effect is greater as the pitch of the array becomes narrower.

[0053] Figure 11 is a perspective view showing a capacitor wiring structure of the seventh embodiment. In the capacitor wiring structure 1a of this embodiment, the third via 16, which is a signal line in the dielectric layer 10, is surrounded by a low dielectric constant portion 26 having a relative permittivity lower than that of the dielectric layer 10.

[0054] The signal line, via 3 via 16, is connected to BaTiO ３ When the dielectric layer 10 comes into contact with the signal line via, a parasitic capacitance is formed between the third via 16, which is a signal line via, and the power supply electrode 14 and the ground electrode 15, with the capacitor dielectric film acting as the capacitor film. Therefore, BaTiO ３The high dielectric constant of the capacitor dielectric film formed from ceramic materials such as [material name missing] unnecessarily increases the parasitic capacitance C value, resulting in a mismatch in characteristic impedance Z0, which may degrade signal transmission. Therefore, in a capacitor-embedded multilayer wiring board and its manufacturing method, in which sintered ceramic material is laid as a thin-film capacitor layer across the entire substrate, it becomes necessary to reduce the degradation of signal transmission due to parasitic capacitance caused by the capacitor dielectric film near the signal line vias. With the configuration shown in Figure 11, the parasitic capacitance formed between the third via 16 and the power electrode 14 and ground electrode 15 can be reduced, and the transmission characteristics of the third via 16 can be improved.

[0055] Figure 12A is a cross-sectional view showing a first application example of the capacitor wiring structure according to the eighth embodiment. In the eighth embodiment, the capacitor-equipped multilayer wiring board 6, which includes the capacitor wiring structure 1 of the present disclosure, may be inserted between the IC chip of the semiconductor element 9 and the wiring portion 3 in the form of an interposer substrate or interposer sheet. Since the capacitor wiring structure 1 is placed very close to the semiconductor element 9, it can exhibit high decoupling capability.

[0056] Figure 12B is a cross-sectional view showing a second application example of the capacitor wiring structure according to the ninth embodiment. In the ninth embodiment, a via array type capacitor 41 having the capacitor wiring structure 1 of the present disclosure is built into a circuit board 51. The via array type capacitor 41 may be a high-capacity capacitor board in which the capacitor wiring structure 1 is densely mounted on a substrate body.

[0057] Figure 12C is a cross-sectional view showing a third application example of the capacitor wiring structure, which is the tenth embodiment. The capacitor wiring structure 1 is not limited to the form of a wiring substrate as described above, but may also be formed on the surface of a semiconductor element 9, as in the tenth embodiment shown in Figure 12C. In this case, the capacitor wiring structure 1 may be formed in or on the upper surface of the redistribution layer 27 formed on the surface of the semiconductor element 9. Alternatively, the capacitor wiring structure 1 may be formed between the bump 28 layer and the wiring portion 3 of the redistribution layer 27 of the semiconductor element 9.

[0058] (Manufacturing Method) An example of a manufacturing method for an interposer substrate equipped with a capacitor wiring structure 1 is described below.

[0059] Figure 13 is a flowchart illustrating the manufacturing method of the interposer substrate shown in Figure 12A, and Figures 14A to 14J are cross-sectional views illustrating the second to eleventh steps S2 to S11 of the manufacturing method of the interposer substrate. The manufacturing process begins in the first step S1, and in the second step S2, as shown in Figure 14A, a laminate matrix 101 is created in which a dielectric layer 10 is sandwiched between two metal foils 14a and 15a. The material of the metal foils 14a and 15a may be a baked film of a metal mainly composed of Ni, Cu, Pd, Pt, Ag, or Au, or an alloy thereof.

[0060] The laminated substrate 101 is formed by laminating a dielectric layer 10 on a metal foil 15a and laminating a metal foil 14a on the dielectric layer 10. The dielectric layer 10 is made of barium titanate (BaTiO ３ A dielectric layer was formed on the metal foil 15a by chemical vapor deposition (CVD). When the metal foil 15a is Cu, the dielectric layer 10 formed on the copper foil is dense. In this case, as a physical film formation method, for example, sputtering, molecular beam epitaxy (MBE), or atomic layer deposition (ALD) may be used. In addition to the above, the material of the dielectric layer 10 may be one selected from the group including titanium dioxide, strontium titanate, and calcium titanate. It may also be a solid solution system containing some different alkaline earth elements.

[0061] As the material for the dielectric layer 10, barium titanate (BaTiO) ３ When using ), a thin film can be formed by the sol-gel method. When a thin film formed by the sol-gel method is dried and calcined at 350°C or below, the dielectric constant tends to be lower than that of ordinary bulk materials. The specific dielectric constant depends greatly on the thickness of the thin film, crystallinity, calcination temperature, and film formation method, and is the case for BaTiO that has been dried and calcined at 350°C or below. ３The relative permittivity in the case of a thin film is about 100 to 300. This is because the crystallinity of the thin film is not perfect and there are many defects due to low-temperature processing. When a high relative permittivity is required, post-treatment such as a higher firing temperature and annealing treatment can be performed to improve the crystallinity and obtain a high relative permittivity.

[0062] Also, when BaTiO ３ is formed by the sputtering method, the relative permittivity is usually in the range of 50 to 500. This value varies depending on the crystallinity or structure of the thin film and the sputtering conditions (such as the purity of the target material, substrate temperature, film formation rate, etc.).

[0063] In another embodiment, as the material of the dielectric layer 10, calcium zirconate (CaZrO ３ ) may be used instead of the above-mentioned barium titanate (BaTiO ３ ).

[0064] As a method for forming the dielectric layer 10, a single metal foil (also referred to as the first metal foil) 15a is prepared, and a film of a metal oxide that becomes the dielectric layer 10 is formed on its surface. Next, a metal foil (also referred to as the second metal foil) 14a is formed on the surface of the metal oxide film opposite to the surface in contact with the first metal foil 15a. For the formation of the second metal foil 14a, the above-mentioned sputtering method, MBE, CVD, or ALD, etc. may be used, or an electroless plating method may also be used. In this case, the second metal foil 14a and the first metal foil 15a become the power supply electrode 14 and the ground electrode 15, respectively.

[0065] Next, as shown in FIG. 14B, in the third step S3, in the above-mentioned laminated substrate 101, in order to form the portions that become via conductors of each of the vias 16, 18, 19, 21, first, a through hole 30 is formed in the first metal foil 15a by etching.

[0066] Furthermore, in the fourth step S4, as shown in Figure 14C, a first insulating layer 31 is laid on the substrate portion 3a having a first via 18, a second via 19, and a third via 16 to form the wiring portion 3. For the first insulating layer 31, a raw sheet or semi-cured sheet of organic resin was used. As the raw sheet or semi-cured sheet of organic resin, one containing an inorganic filler such as silica was used to reduce the coefficient of thermal expansion. After the raw sheet or semi-cured sheet of organic resin was placed on the substrate portion 3a, it was heated to approximately 200 to 300°C to cure the raw sheet or semi-cured sheet of organic resin.

[0067] Next, in the fifth step S5, as shown in Figure 14D, the wiring section 3 on which the first insulating layer 31 is formed and the laminated substrate 101 on which the through-holes 30 are formed are bonded together, and the laminated substrate 101 is placed on the wiring section 3. In the sixth step S6, after the fifth step S5, as shown in Figure 14E, the second metal foil 14a is etched to form through-holes 36. In the seventh step S7, after the sixth step S6, as shown in Figure 14F, the second insulating layer 37 is formed on the second metal foil 14a. In the eighth step S8, after the seventh step S7, as shown in Figure 14G, through-holes 38 are formed in the laminated substrate 101 and the second insulating layer 37. The through-holes 38 may be drilled by irradiating with a UV laser beam. Subsequently, in the ninth step S9, as shown in Figure 14H, the low dielectric resin 40 is filled into the through holes 38 and cured, and as shown in Figure 14I, through holes 39 are formed in the cured low dielectric resin 40, and through holes 42 are formed in the second insulating layer 37 and the laminated substrate 101. Next, in the tenth step S10, as shown in Figure 14J, via conductors 43 and 44 are formed in the through holes 39 and 42, respectively, and in the eleventh step S11, via-plated wiring 45, 46, and 47 are formed.

[0068] In this way, an interposer substrate equipped with the capacitor wiring structure 1 is manufactured, and the manufacturing process is completed in step 12 S12.

[0069] The method for manufacturing such an interposer substrate includes the steps of: forming a first insulating layer 31 on a base substrate 7 (S4); laminating and bonding a first metal foil 15a on the first insulating layer 31 (S5); forming a dielectric layer 10 on the first metal foil 15a (S5); laminating and bonding a second metal foil 14a on the dielectric layer 10 (S5); forming a second insulating layer 37 on the second metal foil 14a (S6); forming through holes 39 and 42 in the first insulating layer 31, the first metal foil 15a, the dielectric layer 10, the second metal foil 14a, and the second insulating layer 37 (S9); and forming via conductors 43 and 44 in the through holes 39 and 42 (S10). If the first insulating layer 31 is not required, the step of forming the first insulating layer 31 (S4) may be omitted.

[0070] The step of forming via conductors 43 and 44 in through holes 39 and 42 includes positioning the via conductors 43 and 44, which will become the first via 18, the second via 19, and the third via 16, such that, in a plan view, the shape formed when the central axes of the via conductors 43 and 44 are connected by straight lines is a polygon, and at least two of the distances b1, b2, and b3 (see Figure 5) between the central axes are equal.

[0071] According to this manufacturing method, since the via conductor 43, which is the signal line 16, is formed within the through hole 39, the via conductor 43 can be formed without contacting the dielectric layer 10, thereby reducing the occurrence of crosstalk. Furthermore, even while including a step to ensure that the via conductor 43, which is the signal line, is insulated from the dielectric layer 10, the via conductors of the power electrode terminal 11, the ground electrode terminal 12, and the signal line connection terminal 13 can be formed in a single step, thereby reducing the manufacturing man-hours for the capacitor wiring structure 1 and reducing the burden of manufacturing.

[0072] Although the above-described embodiment of the manufacturing method for the capacitor wiring structure 1 has been described in terms of application to an interposer substrate, it can also be easily applied to capacitor-equipped wiring layers 4, capacitor-equipped multilayer wiring substrates 6, and semiconductor devices 8 by those skilled in the art.

[0073] This disclosure can be implemented with the following configurations (1) to (11).

[0074] (1) A capacitor wiring structure comprising: a capacitor body comprising a power electrode, a ground electrode, a power electrode terminal connected to the power electrode, a ground electrode terminal connected to the ground electrode, and a dielectric layer having a first surface on which the power electrode terminal is located and a second surface on which the ground electrode terminal is located opposite to the first surface; and a signal line section comprising a signal line penetrating the power electrode, the dielectric layer, and the ground electrode, and a signal line connection terminal to which the signal line is electrically connected, wherein in a plan view, the power electrode terminal, the ground electrode terminal, and the signal line connection terminal have a polygonal shape when their respective central axes are connected by a straight line, and at least two of the distances between the signal line connection terminal and the power electrode terminal, the power electrode terminal and the ground electrode terminal, and the signal line connection terminal and the ground electrode terminal are equal.

[0075] (2) A capacitor wiring structure comprising: a capacitor body comprising a power electrode, a ground electrode, a power electrode terminal connected to the power electrode, a ground electrode terminal connected to the ground electrode described above, and a dielectric layer having a first surface on which the power electrode terminal is arranged and a second surface on which the ground electrode terminal is arranged and is located on the opposite side from the first surface; and a signal line section comprising a signal line penetrating the power electrode, the dielectric layer, and the ground electrode, and a signal line connection terminal to which the signal line is electrically connected, wherein in a plan view, the shape of the power electrode terminal, the ground electrode terminal, and the signal line connection terminal is polygonal when their respective central axes are connected by straight lines, the number of power electrode terminals is different from the number of ground electrode terminals, and the signal line connection terminal, the power electrode terminal, and the ground electrode terminal are equal in at least two of the following distances: the distance between the signal line connection terminal and the power electrode terminal, the distance between the power electrode terminal and the ground electrode terminal, and the distance between the signal line connection terminal and the ground electrode terminal.

[0076] (3) A capacitor wiring structure comprising: a capacitor body comprising a power electrode, a ground electrode, a power electrode terminal connected to the power electrode, a ground electrode terminal connected to the ground electrode, and a dielectric layer having a first surface on which the power electrode terminal is provided and a second surface on which the ground electrode terminal is provided and located on the opposite side from the first surface; and a signal line section comprising a signal line penetrating the power electrode, the dielectric layer, and the ground electrode, and a signal line connection terminal to which the signal line is electrically connected, wherein in a plan view, the shape of the power electrode terminal, the ground electrode terminal, and the signal line connection terminal is a regular hexagon when their respective central axes are connected by a straight line, and at least two of the distances between the signal line connection terminal and the power electrode terminal, the power electrode terminal and the ground electrode terminal, and the signal line connection terminal and the ground electrode terminal are equal.

[0077] (4) A capacitor wiring structure according to any of the above configurations (1) to (3), wherein the capacitor body is a multilayer capacitor.

[0078] (5) A capacitor wiring structure according to any of the above configurations (1) to (3), wherein the capacitor body is a via array type capacitor.

[0079] (6) A capacitor wiring structure according to any of the above configurations (1) to (3), wherein the capacitor body is a via array type multilayer capacitor.

[0080] (7) The capacitor wiring structure according to any one of the above configurations (1) to (6), wherein the signal line in the dielectric layer is surrounded by a low dielectric constant portion having a relative dielectric constant lower than that of the dielectric layer.

[0081] (8) A capacitor-equipped wiring layer comprising a capacitor wiring structure according to any of the above configurations (1) to (7), and a wiring portion laminated on the capacitor wiring structure.

[0082] (9) A capacitor-equipped laminated wiring board comprising: a capacitor wiring structure according to any of the above configurations (1) to (7); a wiring section laminated on the capacitor wiring structure; and a base substrate on which the capacitor wiring structure and the wiring section are mounted.

[0083] (10) A semiconductor device comprising: a capacitor wiring structure according to any of the above configurations (1) to (7); a wiring portion laminated on the capacitor wiring structure; a base substrate on which the capacitor wiring structure and the wiring portion are mounted; and a semiconductor element mounted on the wiring portion.

[0084] (11) A method for manufacturing a capacitor wiring structure, comprising the steps of: forming a first insulating layer on a base substrate; laminating and bonding a first metal foil on the first insulating layer; forming a dielectric layer on the first metal foil; laminating and bonding a second metal foil on the dielectric layer; forming a second insulating layer on the second metal foil; forming the first insulating layer, the first metal foil, the dielectric layer, the second metal foil, and the second insulating layer to prepare a capacitor wiring structure precursor; forming through holes; and forming via conductors in the through holes, wherein the step of forming via conductors in the through holes includes the step of positioning the via conductors such that, in a plan view, the shape when the central axes of the via conductors are connected by straight lines is a polygon, and at least two of the distances between the central axes are equal.

[0085] According to the capacitor wiring structure, capacitor-equipped wiring layer, capacitor-equipped multilayer wiring substrate, and semiconductor device of this disclosure, the decrease in capacitance can be reduced even when signal lines are formed in the wiring substrate. According to the method for manufacturing the capacitor wiring structure of this disclosure, a capacitor wiring structure can be manufactured that can reduce the decrease in capacitance even when signal lines are formed in the wiring substrate.

[0086] Although embodiments of this disclosure have been described in detail above, this disclosure is not limited to the embodiments described above, and various modifications and improvements are possible without departing from the gist of this disclosure. It goes without saying that all or part of each of the above embodiments can be combined as appropriate and in a non-contradictory manner.

[0087] 1, 1a Capacitor wiring structure 2 Capacitor body 3 Wiring section 3a Substrate section 4 Wiring layer with capacitor 6 Multilayer wiring board with capacitor 7 Base substrate 8 Semiconductor device 9 Semiconductor element 10 Dielectric layer 10a First surface 10b Second surface 11 Power electrode terminal 12 Ground electrode terminal 13 Signal line connection terminal 14 Power electrode 14a Metal foil (second metal foil) 15 Ground electrode 15a Metal foil (first metal foil) 16 Third via (signal line) 17 Signal line section 18 First via 19 Second via 21 Fourth via 22a, 22b First notch 23a, 23b Second notch 24a, 24b Third notch 25a, 25b Fourth notch 26 Low dielectric constant section 27 Rewiring layer 28 Bump 30 Through hole 31 First insulating layer 37 Second insulating layer 36, 38, 39 Through holes 40 Low dielectric constant resin 41 Via array type capacitor 42 Through holes 43 Via conductor 45, 46, 47 Via plated wiring 51 Circuit board 101 Laminated substrate L1, L2, L3 Central axis

Claims

1. A capacitor wiring structure comprising: a capacitor body comprising a power electrode, a ground electrode, a power electrode terminal connected to the power electrode, a ground electrode terminal connected to the ground electrode, and a dielectric layer having a first surface on which the power electrode terminal is located and a second surface on which the ground electrode terminal is located opposite to the first surface; and a signal line section comprising a signal line penetrating the power electrode, the dielectric layer, and the ground electrode, and a signal line connection terminal to which the signal line is electrically connected, wherein in a plan view, the power electrode terminal, the ground electrode terminal, and the signal line connection terminal have a polygonal shape when their respective central axes are connected by a straight line, and at least two of the distances between the signal line connection terminal and the power electrode terminal, the power electrode terminal and the ground electrode terminal, and the signal line connection terminal and the ground electrode terminal are equal.

2. A capacitor wiring structure comprising: a capacitor body comprising a power electrode, a ground electrode, a power electrode terminal connected to the power electrode, a ground electrode terminal connected to the ground electrode, and a dielectric layer having a first surface on which the power electrode terminal is located and a second surface on which the ground electrode terminal is located opposite to the first surface; and a signal line section comprising a signal line penetrating the power electrode, the dielectric layer, and the ground electrode, and a signal line connection terminal to which the signal line is electrically connected, wherein in a plan view, the shape of the power electrode terminal, the ground electrode terminal, and the signal line connection terminal is polygonal when their respective central axes are connected by straight lines, the number of power electrode terminals is different from the number of ground electrode terminals, and the signal line connection terminal, the power electrode terminal, and the ground electrode terminal are equal in at least two of the following distances: the distance between the signal line connection terminal and the power electrode terminal, the distance between the power electrode terminal and the ground electrode terminal, and the distance between the signal line connection terminal and the ground electrode terminal.

3. A capacitor wiring structure comprising: a capacitor body comprising a power electrode, a ground electrode, a power electrode terminal connected to the power electrode, a ground electrode terminal connected to the ground electrode, and a dielectric layer having a first surface on which the power electrode terminal is located and a second surface on which the ground electrode terminal is located opposite to the first surface; and a signal line section comprising a signal line penetrating the power electrode, the dielectric layer, and the ground electrode, and a signal line connection terminal to which the signal line is electrically connected, wherein in a plan view, the power electrode terminal, the ground electrode terminal, and the signal line connection terminal have a regular hexagonal shape when their respective central axes are connected by a straight line, and at least two of the distances between the signal line connection terminal and the power electrode terminal, the power electrode terminal and the ground electrode terminal, and the signal line connection terminal and the ground electrode terminal are equal.

4. The capacitor wiring structure according to any one of claims 1 to 3, wherein the capacitor body is a multilayer capacitor.

5. The capacitor wiring structure according to any one of claims 1 to 3, wherein the capacitor body is a via array type capacitor.

6. The capacitor wiring structure according to any one of claims 1 to 3, wherein the capacitor body is a via array type multilayer capacitor.

7. The capacitor wiring structure according to any one of claims 1 to 6, wherein the signal line in the dielectric layer is surrounded by a low dielectric constant portion having a relative dielectric constant lower than that of the dielectric layer.

8. A capacitor-equipped wiring layer comprising a capacitor wiring structure according to any one of claims 1 to 7, and a wiring portion laminated on the capacitor wiring structure.

9. A capacitor-equipped laminated wiring board comprising: a capacitor wiring structure according to any one of claims 1 to 7; a wiring section laminated on the capacitor wiring structure; and a base substrate on which the capacitor wiring structure and the wiring section are mounted.

10. A semiconductor device comprising: a capacitor wiring structure according to any one of claims 1 to 7; a wiring portion laminated on the capacitor wiring structure; a base substrate on which the capacitor wiring structure and the wiring portion are mounted; and a semiconductor element mounted on the wiring portion.

11. A method for manufacturing a capacitor wiring structure, comprising the steps of: forming a first insulating layer on a base substrate; laminating and bonding a first metal foil on the first insulating layer; forming a dielectric layer on the first metal foil; laminating and bonding a second metal foil on the dielectric layer; forming a second insulating layer on the second metal foil; forming the first insulating layer, the first metal foil, the dielectric layer, the second metal foil, and the second insulating layer to prepare a capacitor wiring structure precursor; forming through holes; and forming via conductors in the through holes, wherein the step of forming via conductors in the through holes includes positioning such that, in a plan view, the shape when the central axes of the via conductors are connected by straight lines is a polygon, and at least two of the distances between the central axes are equal.

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