Semiconductor device

Abstract

This semiconductor device includes: an SiC layer; a first semiconductor region of a first conductivity type formed in the SiC layer; a second semiconductor region of a second conductivity type in contact with the first semiconductor region in the SiC layer; a third semiconductor region of the first conductivity type in contact with the second semiconductor region in the SiC layer; an insulating film formed on the surface of the SiC layer so as to cover at least the second semiconductor region; and a control electrode which faces the second semiconductor region via the insulating film and to which a voltage is applied, the voltage forming a first conductivity-type channel that enables conduction between the first semiconductor region and the third semiconductor region. A first profile of a first conductivity-type impurity in a depth direction from an SiC interface between the SiC layer and the insulating film toward the interior of the second semiconductor region has a maximum value or an inflection point in a range extending to a depth of 20 nm from the SiC interface.

Description

Semiconductor equipment Related applications

[0001] This application corresponds to Japanese Patent Application No. 2024-167433, filed with the Japan Patent Office on 26 September 2024, and the full disclosure of this application is incorporated herein by reference.

[0002] This disclosure relates to semiconductor devices.

[0003] Patent document 1 (US2021 / 0280707A1) discloses a semiconductor device comprising a silicon carbide substrate, an epitaxial layer, and a buffer layer. The epitaxial layer is laminated on the silicon carbide substrate, and the buffer layer has the same concentration as the silicon carbide substrate and is interposed between the silicon carbide substrate and the epitaxial layer.

[0004] U.S. Patent Application Publication No. 2021 / 0280707

[0005] [Summary] This disclosure provides a semiconductor device comprising: a SiC layer; a first semiconductor region of a first conductivity type formed within the SiC layer; a second semiconductor region of a second conductivity type in contact with the first semiconductor region within the SiC layer; a third semiconductor region of a first conductivity type in contact with the second semiconductor region within the SiC layer; an insulating film formed on the surface of the SiC layer so as to cover at least the second semiconductor region; and a control electrode to which a voltage is applied, facing the second semiconductor region via the insulating film and forming a channel of a first conductivity type that conducts the first semiconductor region and the third semiconductor region, wherein the first profile of a first conductivity type impurity in the depth direction from the SiC interface between the SiC layer and the insulating film toward the interior of the second semiconductor region has a maximum value or inflection point in the range from the SiC interface to a depth of 20 nm.

[0006] Figure 1 is a plan view showing a semiconductor device according to the first embodiment. Figure 2 is a cross-sectional view along the line II-II shown in Figure 1. Figure 3 is an enlarged plan view showing a key part of the first main surface. Figure 4 is a cross-sectional view along the line IV-IV shown in Figure 3. Figure 5 is a cross-sectional view along the line VV shown in Figure 3. Figure 6 is a cross-sectional view along the line VI-VI shown in Figure 1. Figure 7 is an enlarged plan view showing a key part of the first main surface of a semiconductor device according to the second embodiment. Figure 8 is a cross-sectional view along the line VIII-VIII shown in Figure 7. Figure 9 is a cross-sectional view along the line IX-IX shown in Figure 7. Figure 10 is a cross-sectional view along the line XX shown in Figure 7. Figure 11 is a cross-sectional view along the line XI-XI shown in Figure 7. Figure 12 is a cross-sectional perspective view showing the first key part of the active region. Figure 13 is a cross-sectional perspective view showing the second key part of the active region. Figure 14 is a cross-sectional perspective view showing the third key part of the active region. Figure 15 is a cross-sectional perspective view showing the fourth key part of the active region. Figure 16 is a horizontal cross-sectional view along the line XVI-XVI shown in Figure 8. Figure 17 is a horizontal cross-sectional view along the line XVII-XVII shown in Figure 8. Figure 18 is an enlarged plan view showing a key part of the first main surface of the semiconductor device according to the third embodiment. Figure 19 is a cross-sectional view along the line XIX-XIX shown in Figure 18. Figure 20 is a cross-sectional view of the outer peripheral region of the semiconductor device in Figure 18. Figure 21 is a cross-sectional view showing the semiconductor device according to the fourth embodiment. Figure 22 is a cross-sectional view showing the periphery of the channel region of the semiconductor device. Figure 23 is a diagram showing the concentration distribution of the channel regions of samples 1 to 3. Figure 24 is a diagram showing the concentration distribution of the channel region of sample 1. Figure 25 is a diagram showing the concentration distribution of the channel region of sample 2. Figure 26 is a diagram showing the concentration distribution of the channel region of sample 4. Figure 27 is a cross-sectional view of a key part of the torrent gate structure. Figure 28 is a cross-sectional view of a key part of the torrent gate structure. Figure 29 is a cross-sectional view of a key part of the planar gate structure. Figures 30A and 30B show the donor concentration profile in the depth direction from the SiC interface at point A. Figure 31 shows the donor concentration profile in the depth direction from the SiC interface at point B. Figure 32 is a diagram illustrating the configuration of a SiC epitaxial growth apparatus. Figure 33 is a schematic diagram showing a wafer used in the manufacture of a semiconductor device. Figure 34 is a flowchart showing a method for manufacturing a semiconductor device having a trench gate structure.Figure 35A is a cross-sectional view showing a method for manufacturing a semiconductor device having a trench gate structure. Figure 35B is a cross-sectional view showing a step after Figure 35A. Figure 35C is a cross-sectional view showing a step after Figure 35B. Figure 35D is a cross-sectional view showing a step after Figure 35C. Figure 35E is a cross-sectional view showing a step after Figure 35D. Figure 35F is a cross-sectional view showing a step after Figure 35E. Figure 36A is a cross-sectional view showing a modified example of the manufacturing process for the interface semiconductor region. Figure 36B is a cross-sectional view showing a step after Figure 36A. Figure 37 is a flowchart showing a method for manufacturing a semiconductor device having a planar gate structure. Figure 38A is a cross-sectional view showing a method for manufacturing a semiconductor device having a planar gate structure. Figure 38B is a cross-sectional view showing a step after Figure 38A. Figure 38C is a cross-sectional view showing a step after Figure 38B. Figure 38D is a cross-sectional view showing a step after Figure 38C. Figure 38E is a cross-sectional view showing a step after Figure 38D. Figure 38F is a cross-sectional view showing a step after Figure 38E. Figure 39A is a cross-sectional view showing a modified example of the manufacturing process of the interfacial semiconductor region. Figure 39B is a cross-sectional view showing a process after Figure 39A. Figure 40 is a cross-sectional view showing the periphery of the channel region of a semiconductor device according to a reference example. Figure 41 is a diagram for illustrating the field-effect mobility of a semiconductor device. Figure 42 is a diagram for illustrating the C-V characteristics of a semiconductor device. Figure 43 is an enlarged view of the area enclosed by XLIII in Figure 42. Figure 44 is an enlarged view of the area enclosed by XLIV in Figure 42. Figure 45 is a cross-sectional view showing the periphery of the channel region of a semiconductor device. Figures 46A and 46B show acceptor concentration profiles of the semiconductor region. Figure 47 is a cross-sectional view of the main part of the torrent gate structure. Figure 48 is a cross-sectional view of the main part of the torrent gate structure. Figure 49 is a cross-sectional view of the main part of the planar gate structure. Figures 50A and 50B show the donor concentration profile in the depth direction at point A. Figure 51 shows the donor concentration profile in the depth direction at point B. Figure 52 is an enlarged view of the main part of the outer peripheral region. Figures 53A and 53B show the donor concentration profile in the depth direction from the SiC interface at point A. Figure 54 shows the donor concentration profile in the depth direction from the SiC interface at point B.

[0007] [Detailed Explanation] The specific form is described in detail below with reference to the attached drawings. The attached drawings are all schematic diagrams and are not strictly accurate; relative positions, scales, ratios, angles, etc., do not necessarily match. Corresponding structures in the attached drawings are given the same reference numerals, and redundant explanations are omitted or simplified. For structures whose explanations are omitted or simplified, the explanation given before the omission or simplification applies.

[0008] In this specification, open language terms such as "including" and "having" are described as encompassing closed language terms such as "consisting of." When the term "substantially" is used in this specification, it includes not only numerical values ​​(forms) that are equal to the numerical value (form) being compared, but also numerical errors (form errors) within a range of ±10% relative to the numerical value (form) being compared.

[0009] This specification uses terms such as "First," "Second," and "Third," but these are symbols attached to the names of each structure to clarify the order of explanation, and are not intended to limit the names of each structure.

[0010] In this specification, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may be referred to as the "first conductivity type" and "n-type" as the "second conductivity type."

[0011] "P-type" is a conductivity type derived from trivalent elements, while "n-type" is a conductivity type derived from pentavalent elements. Trivalent elements are at least one of boron, aluminum, gallium, and indium. Pentavalent elements are at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0012] (1) Structural diagram 1 of the semiconductor device 1A is a plan view showing the semiconductor device 1A according to the first embodiment. Figure 2 is a cross-sectional view taken along the line II-II shown in Figure 1. Figure 3 is an enlarged plan view showing a key part of the first main surface 3. Figure 4 is a cross-sectional view taken along the line IV-IV shown in Figure 3. Figure 5 is a cross-sectional view taken along the line VV shown in Figure 3. Figure 6 is a cross-sectional view taken along the line VI-VI shown in Figure 1.

[0013] Semiconductor device 1A is a semiconductor switching device having an insulated gate type transistor structure Tr as an example of a device structure (functional device). The transistor structure Tr has a trench gate type vertical structure.

[0014] In this embodiment, the semiconductor device 1A includes a chip 2 which contains a single crystal of a wide-bandgap semiconductor. The semiconductor device 1A is a "wide-bandgap semiconductor device." The chip 2 may also be referred to as a "semiconductor chip," "wide-bandgap semiconductor chip," etc.

[0015] Wide-bandgap semiconductors are semiconductors that have a bandgap greater than that of silicon (Si). Examples of wide-bandgap semiconductors include gallium nitride (GaN), silicon carbide (SiC), and diamond (C). In this configuration, chip 2 is a "SiC chip" containing a hexagonal SiC single crystal as an example of a wide-bandgap semiconductor. Semiconductor device 1A is a "SiC semiconductor device".

[0016] Hexagonal SiC single crystals have multiple polytypes, including 2H (Hexagonal)-SiC single crystals, 4H-SiC single crystals, and 6H-SiC single crystals. In this embodiment, an example is shown in which chip 2 contains a 4H-SiC single crystal, but chip 2 may contain other polytypes. Of course, chip 2 may also contain cubic or polycrystalline materials. For example, chip 2 may contain a 3C (Cubic)-SiC single crystal or a 3C-SiC polycrystalline material.

[0017] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connected to the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a rectangular shape when viewed from the vertical direction Z (hereinafter simply referred to as "plan view"). The vertical direction Z is also the thickness direction of the chip 2.

[0018] The first main surface 3 and the second main surface 4 are formed by the c-planes of the SiC single crystal. The first main surface 3 may be formed by the silicon plane ((0001) plane) of the SiC single crystal, and the second main surface 4 may be formed by the carbon plane ((000-1) plane) of the SiC single crystal.

[0019] The first side surface 5A extends in the first direction X. The second side surface 5B is connected to the first side surface 5A and extends in the second direction Y, which intersects (specifically, is perpendicular to) the first direction X. The third side surface 5C is connected to the second side surface 5B and extends in the first direction X. The fourth side surface 5D is connected to the first side surface 5A and the third side surface 5C and extends in the second direction Y.

[0020] In this configuration, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. Alternatively, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal. Hereafter, the direction extending along the first principal surface 3 may be referred to as the "horizontal direction". The horizontal direction is also the XY plane (horizontal plane) formed by the first direction X and the second direction Y, and is perpendicular to the vertical direction Z.

[0021] The chip 2 (first main surface 3 and second main surface 4) has an off-angle θ that is inclined at a predetermined angle in a predetermined off-direction with respect to the c-plane of the SiC single crystal. In other words, the c-axis ((0001) axis) of the SiC single crystal is inclined by the off-angle from the vertical line along the vertical direction Z in the off-direction. Also, the c-plane of the SiC single crystal is inclined by the off-angle θ with respect to the horizontal plane.

[0022] The off-direction is preferably the a-axis direction of the SiC single crystal (the second direction Y in this embodiment). The off-angle θ may be greater than 0° and 10° or less. The off-angle θ may have a value that falls within at least one of the following ranges: greater than 0° and 1° or less, 1° or more and 2.5° or less, 2.5° or more and 5° or less, 5° or more and 7.5° or less, and 7.5° or more and 10° or less.

[0023] The off-angle θ is preferably 5° or less. The off-angle θ is particularly preferably 2° or more and 4.5° or less. The off-angle θ is typically set in the range of 4° ± 0.1°. This specification does not exclude a configuration in which the off-angle θ is 0° (i.e., a configuration in which the first principal surface 3 is just plane to the c-plane).

[0024] Chip 2 includes an n-type first semiconductor layer 6 (substrate). The first semiconductor layer 6 may also be referred to as the "first semiconductor region," etc. The first semiconductor layer 6 forms part of the second main surface 4 of chip 2 and the first to fourth side surfaces 5A to 5D of chip 2. The first semiconductor layer 6 includes a single crystal of a wide-bandgap semiconductor.

[0025] In this embodiment, the first semiconductor layer 6 is a "SiC substrate" containing a hexagonal SiC single crystal. In this embodiment, the first semiconductor layer 6 contains a 4H-SiC single crystal and has the aforementioned off-direction and off-angle θ. Of course, the first semiconductor layer 6 may also contain other polytypes. For example, the first semiconductor layer 6 may contain a 3C-SiC polycrystal. In this case, the second main surface 4 is formed by the crystal planes of the 3C-SiC polycrystal.

[0026] The first semiconductor layer 6 has a first thickness T1. The first thickness T1 may be greater than 0 μm and 500 μm or less. The first thickness T1 may have a value that falls within at least one of the following ranges: greater than 0 μm and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 250 μm or less, 250 μm or more and 300 μm or less, 300 μm or more and 350 μm or less, 350 μm or more and 400 μm or more and 400 μm or more and 450 μm or more and 500 μm or less.

[0027] The first semiconductor layer 6 may have a uniform n-type impurity concentration in the thickness direction. The impurity concentration of the first semiconductor layer 6 is 1×10 －３ , , －３ , －３ , －３ , －３ , －３ , －３ , , －３ , －３ , －３ , ２０ , １９ , ２０ ,

[0028] , １９ ,

[0029] , １９ , ２１ , １９ , ２０ , ２０ cm －３ or more and 1×10 ２１ cm －３ or less. The impurity concentration of the first semiconductor layer 6 is 1×10 １７ cm －３ or more and 5×10 １７ cm －３ or less, 5×10 １７ cm －３ or more and 1×10 １８ cm －３ or less, 1×10 １８ cm －３ or more and 5×10 １８ cm －３ or less, 5×10 １８ cm －３ or more and 1×10 １９ cm －３ or less, 1×10 １９ cm －３ or more and 5×10 １９ cm －３ or less, 5×10 １９ cm －３ or more and 1×10 ２０ cm －３ or less, 1×10 ２０ cm －３ or more and 5×10 ２０ cm －３ or less, and 5×10 ２０ cm －３ or more and 1×10 ２１ cm －３ or less, and may have a value belonging to at least one of the following ranges.

[0028] The impurity concentration of the first semiconductor layer 6 may be adjusted by a single type or a plurality of types of pentavalent elements. It is preferable that the impurity concentration of the first semiconductor layer 6 is adjusted by a single type of pentavalent element. The impurity concentration of the first semiconductor layer 6 may be adjusted by nitrogen as a pentavalent element.

[0029] Chip 2 includes an n-type second semiconductor layer 7 stacked on a first semiconductor layer 6. The second semiconductor layer 7 may also be referred to as the "second semiconductor region," etc. The second semiconductor layer 7 forms part of the first main surface 3 and the first to fourth side surfaces 5A to 5D of Chip 2. The second semiconductor layer 7 includes a single crystal of a wide-bandgap semiconductor.

[0030] In this embodiment, the second semiconductor layer 7 is a "SiC semiconductor layer" containing a hexagonal SiC single crystal. In this embodiment, the second semiconductor layer 7 consists of an epitaxial layer (SiC epitaxial layer). In this embodiment, the second semiconductor layer 7 contains a 4H-SiC single crystal and has the aforementioned off-direction and off-angle θ. Of course, the second semiconductor layer 7 may also contain other polytypes.

[0031] The second semiconductor layer 7 has a second thickness T2 that is less than the first thickness T1 of the first semiconductor layer 6 with respect to the stacking direction. The second thickness T2 may be greater than 0 μm and 50 μm or less. The second thickness T2 may have a value that falls within at least one of the following ranges: greater than 0 μm and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, 25 μm or more and 30 μm or less, 30 μm or more and 35 μm or less, 35 μm or more and 40 μm or less, 40 μm or more and 45 μm or more and 50 μm or less.

[0032] The second semiconductor layer 7 has an impurity concentration of n-type impurities that is less than that of the first semiconductor layer 6. The second semiconductor layer 7 may have a uniform n-type impurity concentration in the thickness direction. The second semiconductor layer 7 may have an n-type impurity concentration that gradually increases from the first semiconductor layer 6 toward the first main surface 3. The impurity concentration of the second semiconductor layer 7 is 1 × 10⁻⁶. １５ cm －３ The above 1 x 10 １９ cm －３ The following is also acceptable.

[0033] The impurity concentration of the second semiconductor layer 7 is 1 × 10⁻⁶ １５ cm －３ The above 5 x 10 １５ cm －３ Below, 5 x 10 １５ cm－３ The above 1 x 10 １６ cm －３ Below, 1 x 10 １６ cm －３ The above 5 x 10 １６ cm －３ Below, 5 x 10 １６ cm －３ The above 1 x 10 １７ cm －３ Below, 1 x 10 １７ cm －３ The above 5 x 10 １７ cm －３ Below, 5 x 10 １７ cm －３ The above 1 x 10 １８ cm －３ The following, and 1 x 10 １８ cm －３ The above 5 x 10 １９ cm －３ It may have a value that falls within at least one of the following ranges.

[0034] The impurity concentration of the second semiconductor layer 7 may be adjusted by a single or multiple pentavalent elements. Preferably, the impurity concentration of the second semiconductor layer 7 is adjusted by a single pentavalent element. The impurity concentration of the second semiconductor layer 7 may also be adjusted by nitrogen as the pentavalent element.

[0035] The semiconductor device 1A includes an active region 20 provided in the second semiconductor layer 7. The active region 20 includes a device structure (transistor structure Tr) and is a region where an output current (drain current) is generated. Referring to Figure 6, the active region 20 is set in the inner part of the second semiconductor layer 7, spaced apart from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. The active region 20 may also be a region covered by a source electrode 43, which will be described later.

[0036] Referring to Figure 1, the active region 20 is set to a polygonal shape (a quadrilateral in this form) having four sides parallel to the periphery of the first main surface 3 in a plan view. The active region 20 has a quadrilateral recessed portion along the central part of the fourth side surface 5D toward the second side surface 5B.

[0037] The ratio of the surface area of ​​the active region 20 to the surface area of ​​the first main surface 3 (area ratio) may be 0.5 or more and 0.95 or less. The area ratio may have a value that falls within at least one of the following ranges: 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, and 0.9 or more and 0.95 or less.

[0038] The semiconductor device 1A includes an outer peripheral region 21 set outside the active region 20 in the second semiconductor layer 7. The outer peripheral region 21 is a region that does not include the device structure (transistor structure Tr). The outer peripheral region 21 is set at the periphery of the second semiconductor layer 7. In other words, the outer peripheral region 21 is provided in the region between the periphery of the first main surface 3 and the active region 20 in a plan view. In a plan view, the outer peripheral region 21 extends in a band shape along the active region 20 and is set in a polygonal ring (a quadrilateral ring in this form) that surrounds the active region 20.

[0039] Referring to Figures 4 to 6, the semiconductor device 1A includes an impurity region 9 formed on the surface of the first main surface 3 in the active region 20 (inner part of the first main surface 3). In this configuration, the impurity region 9 is formed as a p-type body region 22. The body region 22 may also be called a "channel region" or the like. A source potential may be applied to the body region 22. The source potential may be a reference potential that serves as the basis for circuit operation. The reference potential may also be the ground potential.

[0040] The body region 22 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 7, and replaces the conductivity type of the second semiconductor layer 7 from n-type to p-type. The body region 22 is formed in the active region 20 with a gap from the periphery of the first main surface 3, and is not formed in the outer peripheral region 21. In this configuration, the body region 22 is formed over the entire area of ​​the active region 20. The body region 22 is formed on the surface of the second semiconductor layer 7 and extends in layers along the first main surface 3.

[0041] The body region 22 is formed with a gap from the depth position in the middle of the second semiconductor layer 7 toward the first main surface 3. The body region 22 forms a pn junction with the second semiconductor layer 7. This forms a body diode structure (pn junction diode structure) as a diode structure Di having the body region 22 as the anode region and the second semiconductor layer 7 as the cathode region. When a reverse bias voltage is applied, the body region 22 expands a depletion layer in the second semiconductor layer 7. The depletion layer, starting from the body region 22, expands horizontally and in the thickness direction within the second semiconductor layer 7.

[0042] The semiconductor device 1A includes a plurality of trench-type (trench electrode type) gate structures 25 formed in the inner part of the first main surface 3. The gate structures 25 may also be called "trench structures," "trench gate structures," etc. A gate potential (gate signal) is applied to the plurality of gate structures 25 as a control potential. The plurality of gate structures 25 control the inversion and non-inversion of the channel region 24 within the body region 22 in response to the gate potential.

[0043] Multiple gate structures 25 are formed in the active region 20 at intervals from the periphery of the first main surface 3, but not in the outer peripheral region 21. In a plan view, the multiple gate structures 25 are arranged at intervals in the first direction X (= m-axis direction) and extend in a strip-like manner in the second direction Y (= a-axis direction). In a plan view, the multiple gate structures 25 are arranged in a stripe-like manner extending in the second direction Y.

[0044] The extension direction of the multiple gate structures 25 coincides with the off-direction of the SiC single crystal. With respect to the second direction Y, both ends of the multiple gate structures 25 are located inward from the periphery of the body region 22. The ends of the multiple gate structures 25 may also be located outward from the periphery of the body region 22. The multiple gate structures 25 may be arranged at intervals in the second direction Y in a plan view and each may extend in a strip-like manner in the first direction X.

[0045] Multiple gate structures 25 penetrate the body region 22 so as to reach the second semiconductor layer 7. The multiple gate structures 25 may be formed at intervals from the depth position in the middle of the second semiconductor layer 7 toward the first main surface 3. The multiple gate structures 25 are formed substantially perpendicular to the first main surface 3. The multiple gate structures 25 may be formed in a tapered shape toward the first semiconductor layer 6.

[0046] The side walls (long sides) of the multiple gate structures 25 are formed by the m-plane ((1-100) plane) of the SiC single crystal. The side walls (long sides) of the multiple gate structures 25 may also be formed by the a-plane ((11-20) plane) of the SiC single crystal, depending on the direction of extension of the gate structure 25. The side walls of the multiple gate structures 25, together with the first main surface 3, define the arc-shaped (circular arc-shaped) curved open end.

[0047] The bottom walls of the multiple gate structures 25 are formed by the c-planes (Si planes) of the SiC single crystal. Preferably, the bottom walls of the multiple gate structures 25 extend almost flat along the horizontal direction. The bottom walls of the multiple gate structures 25 may also be curved in an arc towards the second main surface 4.

[0048] The inclination angle (absolute value) of the side wall (long side) of the gate structure 25 with respect to the vertical line may be 85° or more and 95° or less. The inclination angle may have a value that falls within at least one of the following ranges: 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95° or less. Preferably, the inclination angle is 87° or more and 93° or less.

[0049] The gate structure 25 may have a width of 0.1 μm or more and 2 μm or less. The width of the gate structure 25 may have a value that falls within at least one of the following ranges: 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less. The width of the gate structure 25 is preferably 1 μm or less.

[0050] The gate structure 25 may have a depth of 0.1 μm or more and 3 μm or less. The depth of the gate structure 25 is the depth with respect to the first main surface 3. The depth of the gate structure 25 may have a value that falls within at least one of the following ranges: 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or more and 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. Preferably, the depth of the gate structure 25 is 0.5 μm or more and 1.5 μm or less.

[0051] The gate structure 25 may have an aspect ratio of 1 to 3. The aspect ratio of the gate structure 25 is the ratio of the depth of the gate structure 25 to the width of the gate structure 25. The aspect ratio may have a value that falls within at least one of the following ranges: 1 to 1.25, 1.25 to 1.5, 1.5 to 1.75, 1.75 to 2, 2 to 2.25, 2.25 to 2.5, 2.5 to 2.75, and 2.75 to 3. The aspect ratio is preferably 1.5 to 2.5.

[0052] Multiple gate structures 25 may be arranged at intervals of 0.1 μm or more and 2 μm or less. The interval between gate structures 25 is the horizontal distance (first direction X) between multiple gate structures 25. The interval between gate structures 25 may have a value that belongs to at least one of the following ranges: 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less. Preferably, the interval between gate structures 25 is 1 μm or less.

[0053] The multiple gate structures 25 each include a trench 26, an insulating film 27, and an embedded electrode 28. The trench 26 may be referred to as a "gate trench," the insulating film 27 as a "gate insulating film," and the embedded electrode 28 as a "gate electrode." The trench 26 is formed on the first main surface 3 and defines the wall surfaces (side walls and bottom walls) of the gate structure 25.

[0054] The insulating film 27 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The insulating film 27 may include a silicon oxide film containing the oxide of the second semiconductor layer 7. The insulating film 27 may include a silicon oxide film containing an oxide other than the oxide of the second semiconductor layer 7.

[0055] The insulating film 27 covers the wall surface of the trench 26. In this embodiment, the insulating film 27 has an upper end located on the bottom wall side of the trench 26 with respect to the height position of the first main surface 3, and a portion of the chip 2 is exposed from the wall surface of the open end of the trench 26. Preferably, the upper end of the insulating film 27 is located on the opening side of the trench 26 with respect to the depth position of the middle part of the trench 26.

[0056] The thickness of the insulating film 27 that covers the side walls of the trench 26 may be greater than the thickness of the insulating film 27 that covers the bottom walls of the trench 26. The thickness of the insulating film 27 may be between 10 nm and 250 nm.

[0057] The thickness of the insulating film 27 may have a value that falls within at least one of the following ranges: 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, 125 nm to 150 nm, 150 nm to 175 nm, 175 nm to 200 nm, 200 nm to 225 nm, and 225 nm to 250 nm.

[0058] The embedded electrode 28 may contain either p-type conductive polysilicon or n-type conductive polysilicon, or both. Preferably, the embedded electrode 28 is made of n-type conductive polysilicon. The embedded electrode 28 is embedded in the trench 26 with an insulating film 27 in between, and faces the second semiconductor layer 7 and the body region 22 with the insulating film 27 in between.

[0059] The embedded electrode 28 has an electrode surface exposed from the trench 26. The electrode surface is located on the bottom wall side of the trench 26, spaced apart from the height of the first main surface 3. The electrode surface is located on the first main surface 3 side with respect to the depth of the middle part of the trench 26. The electrode surface may also be located on the bottom wall side of the trench 26 with respect to the depth of the middle part of the trench 26. The electrode surface may have a recess that is indented toward the bottom wall side of the trench 26.

[0060] The semiconductor device 1A includes a plurality of mesa portions 29 demarcated on the first main surface 3 in the active region 20. Each of the plurality of mesa portions 29 is demarcated in regions between adjacent gate structures 25. The plurality of mesa portions 29 are demarcated with spacing in the first direction X, following the layout of the plurality of gate structures 25, and each extends in a strip-like manner in the second direction Y. The plurality of mesa portions 29 extend in a stripe-like manner in the second direction Y. The width of each mesa portion 29 corresponds to the spacing between the plurality of gate structures 25.

[0061] The semiconductor device 1A includes a plurality of p-type well regions 30 formed within the second semiconductor layer 7. The plurality of well regions 30 are also a form of impurity region 9. The plurality of well regions 30 have a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 7, and replace the conductivity type of the second semiconductor layer 7 from n-type to p-type. A source potential is applied to the plurality of well regions 30.

[0062] The multiple well regions 30 are formed within the second semiconductor layer 7, spaced apart from each other in the horizontal direction (first direction X), in regions below (specifically, directly below) the multiple gate structures 25. The multiple well regions 30 are formed within the thickness range between the first semiconductor layer 6 and the bottom walls of the multiple gate structures 25, and overlap with the multiple gate structures 25 in a one-to-one correspondence in the thickness direction.

[0063] The multiple well regions 30 each extend in a strip-like manner in the second direction Y, following the extension direction of the corresponding gate structure 25 in a plan view. The multiple well regions 30 are arranged in a stripe-like pattern extending in the second direction Y in a plan view. The extension direction of the multiple well regions 30 coincides with the off-direction of the SiC single crystal.

[0064] With respect to the second direction Y, both ends of the multiple well regions 30 may be located on the inner side of the multiple gate structures 25 with respect to both ends of the multiple gate structures 25, or they may be located on the peripheral side of the active region 20. The multiple well regions 30 may extend in the first direction X according to the extending direction of the multiple gate structures 25. In this case, the multiple well regions 30 intersect (specifically orthogonally) in the off direction.

[0065] In this configuration, the multiple well regions 30 extend vertically in the thickness direction of the second semiconductor layer 7. The multiple well regions 30 are formed at intervals from the first semiconductor layer 6 towards the bottom wall side of the multiple gate structures 25, and face the first semiconductor layer 6 with a portion of the second semiconductor layer 7 in between. The multiple well regions 30 each have an upper end located on the bottom wall side of the corresponding gate structure 25 and a bottom located on the first semiconductor layer 6 side.

[0066] The upper ends of the multiple well regions 30 are formed with a gap between them and the bottom wall of the corresponding gate structure 25, extending from the bottom of the body region 22. The upper ends of the multiple well regions 30 are connected to the bottom wall of the corresponding gate structure 25 and face the embedded electrode 28 via an insulating film 27.

[0067] The upper ends of the multiple well regions 30 may have portions that follow the side walls of the corresponding gate structures 25. In other words, the multiple well regions 30 may face the embedded electrodes 28 via the insulating film 27 at the side walls of the corresponding gate structures 25. The upper ends of the multiple well regions 30 may be formed with a gap between them and the bottom wall of the corresponding gate structures 25 towards the first semiconductor layer 6.

[0068] The bottoms of the multiple well regions 30 may be located on the bottom wall side of the multiple gate structures 25 or on the first semiconductor layer 6 side with respect to the depth position of the intermediate portion of the second semiconductor layer 7. The bottoms of the multiple well regions 30 are directly connected to the second semiconductor layer 7.

[0069] The multiple well regions 30 may form a superjunction structure together with the second semiconductor layer 7 in the region below the gate structure 25. In this case, the depletion layers originating from the multiple well regions 30 are connected to each other in the regions between the multiple well regions 30.

[0070] In this embodiment, the depth of the well region 30 relative to the bottom wall of the gate structure 25 is smaller than the depth of the gate structure 25 relative to the first main surface 3. The depth of the well region 30 may also be larger than the depth of the gate structure 25 relative to the first main surface 3.

[0071] The depth of the well region 30 may be 0.5 μm or more and 5 μm or less. The depth of the well region 30 may have a value that falls within at least one of the following ranges: 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0072] The multiple well regions 30 each include a first well region 31 located on the bottom wall side of the gate structure 25 and a second well region 32 located on the first semiconductor layer 6 side. The first well region 31 is located on the bottom wall side of the gate structure 25 with respect to the depth position of the middle part of the well region 30 and forms the upper end of the well region 30.

[0073] With respect to the second direction Y, both ends of the first well region 31 may be located on the inward side of the gate structure 25 relative to both ends of the gate structure 25, or they may be located on the peripheral side of the active region 20. The first well region 31 may face the embedded electrode 28 via the insulating film 27. The first well region 31 may have a portion along the side wall of the gate structure 25. That is, it may face the embedded electrode 28 via the insulating film 27 at the side wall of the gate structure 25.

[0074] The ratio of the depth of the first well region 31 to the depth of the well region 30 (first depth ratio) may be greater than 0 and 0.5 or less. The first depth ratio may have a value that falls within at least one of the following ranges: greater than 0 and 0.1 or less, 0.1 or more and 0.2 or less, 0.2 or more and 0.3 or less, 0.3 or more and 0.4 or less, and 0.4 or more and 0.5 or less. Preferably, the first depth ratio is less than 0.5.

[0075] The depth of the first well region 31 is less than the depth of the gate structure 25. The depth of the first well region 31 may be greater than 0 μm and 1 μm or less. The depth of the first well region 31 may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.3 μm or less, 0.3 μm or more and 0.4 μm or less, 0.5 μm or more and 0.6 μm or less, 0.6 μm or more and 0.7 μm or less, 0.7 μm or more and 0.8 μm or less, 0.8 μm or more and 0.9 μm or less, and 0.9 μm or more and 1 μm or less. Preferably, the depth of the first well region 31 is 0.5 μm or less.

[0076] The second well region 32 is located on the first semiconductor layer 6 side relative to the first well region 31 and forms the bottom of the well region 30. The second well region 32 extends in a strip shape in the second direction Y, following the extending direction of the gate structure 25. With respect to the second direction Y, both ends of the second well region 32 may be located on the inward side of the gate structure 25 relative to both ends of the gate structure 25, or they may be located on the peripheral side of the active region 20.

[0077] In this configuration, the second well region 32 has a portion located on the bottom wall side of the gate structure 25 corresponding to the depth position of the intermediate part of the well region 30, and a portion located on the first semiconductor layer 6 side with respect to the depth position of the intermediate part of the well region 30.

[0078] The depth of the second well region 32 is obtained by subtracting the depth of the first well region 31 from the depth of the well region 30. The depth of the second well region 32 is the depth relative to the bottom of the first well region 31. The ratio of the depth of the second well region 32 to the depth of the well region 30 (second depth ratio) is calculated by "1 - first depth ratio".

[0079] The second depth ratio is preferably 0.5 or greater. The second depth ratio is particularly preferably greater than 0.5. In this embodiment, the depth of the second well region 32 is smaller than the depth of the gate structure 25. The depth of the second well region 32 may be larger than the depth of the gate structure 25.

[0080] The depth of the second well region 32 may be 0.5 μm or more and 5 μm or less. The depth of the second well region 32 may have a value that falls within at least one of the following ranges: 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0081] The semiconductor device 1A includes a plurality of n-type source regions 33 formed within the body region 22 in the active region 20. The source regions 33 have an n-type impurity concentration higher than the p-type impurity concentration of the body region 22, and replace the conductivity type of the body region 22 from p-type to n-type. The n-type impurity concentration of the source regions 33 is higher than the n-type impurity concentration of the second semiconductor layer 7.

[0082] Multiple source regions 33 are formed in multiple mesa portions 29 on the surface of the body region 22. In this configuration, the multiple source regions 33 are formed in a one-to-many correspondence with respect to the multiple mesa portions 29, spaced apart in the second direction Y, and are adjacent to two gate structures 25 corresponding to the first direction X. In this configuration, the multiple source regions 33 extend in a strip-like manner in the second direction Y, following the direction of extension of the multiple gate structures 25 in a plan view.

[0083] Multiple source regions 33 on one side of the first direction X are each opposite multiple source regions 33 on the other side of the first direction X, separated by a corresponding gate structure 25. In other words, the multiple source regions 33 are arranged in a line in the first direction X in a plan view. In this configuration, the multiple source regions 33 are arranged in a matrix with spacing in the first direction X and the second direction Y in a plan view.

[0084] Multiple source regions 33 on one side of the first direction X may each face the region between the multiple source regions 33 on the other side of the first direction X, separated by a corresponding gate structure 25. In other words, the multiple source regions 33 may be arranged in a staggered pattern with spacing in the first direction X and the second direction Y in a plan view.

[0085] Each of the multiple source regions 33 has a thickness (depth) less than the thickness (depth) of the body region 22 and is formed with a gap between it and the first main surface 3 from the bottom of the body region 22. The multiple source regions 33 face the second semiconductor layer 7 with a part (bottom) of the body region 22 in between.

[0086] Each of the multiple source regions 33 has a portion located on the bottom wall side of the multiple trenches 26 with respect to the electrode surfaces of the multiple embedded electrodes 28, and a portion located on the first main surface 3 side with respect to the electrode surfaces of the multiple embedded electrodes 28. Each of the multiple source regions 33 has a portion that faces the corresponding embedded electrode 28 horizontally, with the corresponding insulating film 27 in between.

[0087] The source region 33 has a thickness (depth) greater than the thickness between the bottom of the body region 22 and the bottom of the source region 33. The thickness of the source region 33 may be less than the thickness between the bottom of the body region 22 and the bottom of the source region 33. Multiple source regions 33, together with the second semiconductor layer 7, define a channel region 24 that serves as a current path on the bottom side of the body region 22.

[0088] The channel may have a channel length greater than 0 nm and less than or equal to 500 nm. The channel length is the distance between the bottom of the body region 22 and the bottom of the source region 33. The channel length may have a value that falls within at least one of the following ranges: greater than 0 nm and less than or equal to 50 nm, 50 nm to 100 nm, 100 nm to 150 nm, 150 nm to 200 nm, 200 nm to 250 nm, 250 nm to 300 nm, 300 nm to 350 nm, 350 nm to 400 nm, 400 nm to 450 nm, and 450 nm to 500 nm. Preferably, the channel length is 300 nm or less.

[0089] The semiconductor device 1A includes a plurality of contact regions 34 formed within the second semiconductor layer 7 in the active region 20. A source potential is applied to the contact regions 34. The contact regions 34 have a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 7. The p-type impurity concentration of the contact regions 34 is higher than the p-type impurity concentration of the body region 22.

[0090] The p-type impurity concentration in the contact region 34 is higher than the p-type impurity concentration in the second well region 32. The p-type impurity concentration in the contact region 34 may be higher or lower than the p-type impurity concentration in the first well region 31. The p-type impurity concentration in the contact region 34 may be higher or lower than the n-type impurity concentration in the source region 33.

[0091] The multiple contact regions 34 are formed in regions along the multiple gate structures 25, spaced apart from the first semiconductor layer 6 toward the first main surface 3. The multiple contact regions 34 are formed in a one-to-many correspondence with respect to the multiple gate structures 25, spaced apart in the second direction Y. Specifically, the multiple contact regions 34 are interposed in the regions between the multiple source regions 33.

[0092] Multiple contact regions 34 may be connected to multiple source regions 33 in the second direction Y. Multiple contact regions 34 may be formed at intervals from multiple source regions 33 in the second direction Y. In this case, multiple contact regions 34 may face multiple source regions 33 with a part of the body region 22 in between.

[0093] Multiple contact regions 34 along one gate structure 25 are opposite to multiple contact regions 34 along the other gate structure 25 in the first direction X when viewed from above. In other words, the multiple contact regions 34 are arranged in a matrix with spacing in the first direction X and the second direction Y when viewed from above.

[0094] One set of contact regions 34 may be facing the region between the other set of contact regions 34 in the first direction X when viewed from above. In other words, the set of contact regions 34 may be arranged in a staggered pattern with spacing between them in the first direction X and the second direction Y when viewed from above.

[0095] The multiple contact regions 34 may extend in a strip-like manner in the second direction Y, following the direction of extension of the multiple gate structures 25 in a plan view. The lengths of the multiple contact regions 34 in the second direction Y may be equal to or different from each other. The lengths of the multiple contact regions 34 in the second direction Y are adjusted according to the channel area to be formed.

[0096] The channel area is the total area of ​​the portion of the multiple source regions 33 that is exposed from the region between the multiple gate structures 25. In other words, the channel area increases or decreases in proportion to the increase or decrease in the ratio of the total planar area of ​​the multiple contact regions 34. It is preferable that the total planar area of ​​the multiple contact regions 34 is less than the channel area. That is, in the region between the multiple gate structures 25, it is preferable that the total planar area of ​​the multiple contact regions 34 is less than the total planar area of ​​the multiple source regions 33.

[0097] The length of the contact region 34 may be greater than or less than the width of the gate structure 25. The length of the contact region 34 may be greater than or less than the spacing between the multiple gate structures 25 (width of the mesa portion 29). The spacing between the multiple contact regions 34 may be greater than or less than the width of the gate structure 25. The spacing between the contact regions 34 may be greater than or less than the spacing between the multiple gate structures 25.

[0098] Each of the multiple contact regions 34 has a first region 34A, a second region 34B, and a third region 34C, respectively. The first region 34A is the portion that extends along the bottom wall of the corresponding gate structure 25. The first region 34A is interposed in the region between the bottom wall of the corresponding gate structure 25 and the bottom of the corresponding well region 30, and is connected to the bottom wall of the corresponding gate structure 25 and the corresponding well region 30. The first region 34A faces the embedded electrode 28 via an insulating film 27.

[0099] The first region 34A has a thickness greater than the thickness of the first well region 31 and has a bottom located on the bottom side of the second well region 32 relative to the depth position of the lower end (bottom) of the first well region 31. The thickness of the first region 34A is the thickness of the first region 34A in the vertical direction Z with respect to the bottom wall of the gate structure 25.

[0100] The bottom of the first region 34A is formed with a gap between it and the bottom wall of the gate structure 25, and faces the second semiconductor layer 7 across a portion of the second well region 32. The bottom of the first region 34A may be located on the bottom wall side of the gate structure 25 with respect to the depth position of the middle part of the second well region 32. The bottom of the first region 34A may be located on the bottom side of the second well region 32 with respect to the depth position of the middle part of the second well region 32.

[0101] The first region 34A has a width greater than the width of the gate structure 25 and extends horizontally from the region directly below the corresponding gate structure 25 to both sides of the corresponding gate structure 25. The first region 34A is connected to the first well region 31 and the second well region 32, and increases the p-type impurity concentration in the first well region 31 and the p-type impurity concentration in the second well region 32.

[0102] The first region 34A may have a thickness less than the thickness of the first well region 31 and may be formed at a distance from the depth position of the lower end of the first well region 31 toward the bottom wall side of the gate structure 25. In this case, the first region 34A may face the second well region 32 with a part of the first well region 31 in between.

[0103] The second region 34B is a portion that extends along the side wall of the gate structure 25. The second region 34B faces the embedded electrode 28 via the insulating film 27. The second region 34B has a thickness less than the thickness of the first region 34A. The thickness of the second region 34B is the horizontal thickness of the second region 34B with respect to the side wall of the gate structure 25. The second region 34B is connected to the first region 34A on the bottom wall side of the gate structure 25 and connected to the body region 22 on the first main surface 3 side.

[0104] In other words, the second region 34B electrically connects the corresponding well region 30 to the body region 22. This suppresses the well region 30 from becoming electrically detached, and improves the electrical response characteristics of the well region 30.

[0105] The third region 34C extends in layers along the first main surface 3 in the surface layer of the first main surface 3 and is the portion exposed from the first main surface 3. In other words, the third region 34C forms the upper end of the contact region 34. In this embodiment, the upper end of the third region 34C is exposed from the side wall of the trench 26 at the opening end of the trench 26.

[0106] The third region 34C is formed integrally with the third region 34C of the adjacent contact region 34. In other words, multiple contact regions 34 are electrically connected to each other via multiple third regions 34C. The third region 34C has a thickness (depth) less than the thickness (depth) of the body region 22 and faces the second semiconductor layer 7 with a part (bottom) of the body region 22 in between. The thickness of the third region 34C is the thickness of the third region 34C in the vertical direction Z with respect to the first main surface 3.

[0107] The third region 34C has a bottom portion located on the bottom side of the body region 22 with respect to the height of the electrode surfaces of the multiple embedded electrodes 28. Specifically, the third region 34C has a portion located on the bottom wall side of the multiple trenches 26 with respect to the electrode surfaces of the multiple embedded electrodes 28, and a portion located on the first main surface 3 side with respect to the electrode surfaces of the multiple embedded electrodes 28. The third region 34C has a portion facing the corresponding embedded electrode 28 across the corresponding insulating film 27.

[0108] The thickness of the third region 34C is greater than the thickness of the second region 34B. The thickness of the third region 34C may be approximately equal to the thickness of the first region 34A. The thickness of the third region 34C may be greater than or less than the thickness of the first region 34A. The thickness of the third region 34C is less than the thickness (depth) of the source region 33. The third region 34C has a bottom that is located on the first main surface 3 side relative to the bottom of the source region 33.

[0109] The thickness of the third region 34C may be greater than the thickness of the source region 33. The thickness of the third region 34C may be less than the thickness between the bottom of the body region 22 and the bottom of the third region 34C. The thickness of the third region 34C may be less than the thickness between the bottom of the body region 22 and the bottom of the third region 34C.

[0110] Referring to Figures 2 and 6, the semiconductor device 1A includes a p-type outer well region 35 formed on the surface layer of the first main surface 3 in the outer peripheral region 21 (periphery of the first main surface 3). The outer well region 35 is also a form of the impurity region 9. A source potential is applied to the outer well region 35. The outer well region 35 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 7. The p-type impurity concentration of the outer well region 35 may be higher or lower than the p-type impurity concentration of the body region 22.

[0111] The p-type impurity concentration in the outer well region 35 is lower than the p-type impurity concentration in the contact region 34. The p-type impurity concentration in the outer well region 35 is lower than the p-type impurity concentration in the first well region 31. The p-type impurity concentration in the outer well region 35 may be higher or lower than the p-type impurity concentration in the second well region 32.

[0112] The outer well region 35 is formed on the surface of the second semiconductor layer 7 and extends in layers along the first main surface 3. The outer well region 35 is formed with gaps between it and the multiple gate structures 25 from the periphery of the first main surface 3. In a plan view, the outer well region 35 extends in a band shape along the periphery of the first main surface 3 (the periphery of the active region 20).

[0113] In this configuration, the outer well region 35 is formed as a polygonal ring (a quadrilateral ring in this configuration) with four sides parallel to the periphery of the first main surface 3 in a plan view, and surrounds the inner part (active region 20) of the first main surface 3. In other words, the outer well region 35 surrounds multiple gate structures 25 together.

[0114] The outer well region 35 may have an edge portion that connects a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in an arc shape (preferably a quarter arc shape). The outer well region 35 has an inner edge portion on the side of the multiple gate structures 25 and an outer edge portion on the peripheral edge side of the first main surface 3. The inner edge portion of the outer well region 35 demarcates the boundary between the active region 20 and the outer peripheral region 21.

[0115] Referring to Figure 6, the inner edge of the outer well region 35 is connected to the ends of the multiple gate structures 25 in the portion extending in the first direction X. The inner edge of the outer well region 35 faces the embedded electrode 28 across the insulating film 27.

[0116] The inner edge of the outer well region 35 may be located on the inward side of the gate structures 25, beyond the ends of the gate structures 25. The inner edge of the outer well region 35 may have a portion located in the region between the gate structures 25 and may be connected to the body region 22. The outer edge of the outer well region 35 is formed at a distance from the periphery of the first main surface 3 and extends substantially parallel to the inner edge of the outer well region 35.

[0117] The outer well region 35 may have a width greater than 0 μm and 300 μm or less. The width of the outer well region 35 may have a value that falls within at least one of the following ranges: greater than 0 μm and 25 μm or less, 25 μm or more and 50 μm or less, 50 μm or more and 75 μm or less, 75 μm or more and 100 μm or less, 100 μm or more and 125 μm or less, 125 μm or more and 150 μm or less, 150 μm or more and 175 μm or less, 175 μm or more and 200 μm or less, 200 μm or more and 225 μm or less, 225 μm or more and 250 μm or less, 250 μm or more and 275 μm or more and 300 μm or less.

[0118] The outer well region 35 is formed with a gap between it and the first main surface 3 from the first semiconductor layer 6, and faces the first semiconductor layer 6 with a portion of the second semiconductor layer 7 in between. The outer well region 35 may be formed with a gap between it and the first main surface 3 from the depth position of the middle part of the second semiconductor layer 7, or it may have a portion located on the first semiconductor layer 6 side with respect to the depth position of the middle part of the second semiconductor layer 7.

[0119] In this configuration, the outer well region 35 is formed at a distance from the depth position of the bottom wall of the multiple gate structures 25 toward the first main surface 3. The depth of the outer well region 35 may be greater or less than the depth of the body region 22.

[0120] The outer well region 35 may have a portion located on the first semiconductor layer 6 side with respect to the depth position of the bottom wall of the plurality of gate structures 25. In this case, the outer well region 35 may be connected to either or both of the first well region 31 and the second well region 32.

[0121] The outer well region 35 forms a pn junction with the second semiconductor layer 7. When a reverse bias voltage is applied, the outer well region 35 expands a depletion layer in the second semiconductor layer 7. The depletion layer of the outer well region 35 expands in the horizontal and thickness directions and integrates with the depletion layers expanding from the body region 22 and the well region 30. The outer well region 35 extends the depletion layers expanding from the body region 22 and the well region 30 toward the periphery of the first main surface 3, thereby mitigating the electric field strength (electric field concentration) at the periphery (outer outer region 21) of the first main surface 3.

[0122] Referring to Figure 6, the semiconductor device 1A includes a p-type outer contact region 36 formed on the surface of the outer well region 35. The outer contact region 36 has a higher p-type impurity concentration than the outer well region 35. The p-type impurity concentration of the outer contact region 36 is higher than the p-type impurity concentration of the body region 22.

[0123] The p-type impurity concentration in the outer contact region 36 may be approximately equal to that of the contact region 34. The p-type impurity concentration in the outer contact region 36 may be higher or lower than that of the contact region 34.

[0124] The outer contact region 36 is formed with a gap from the bottom of the outer well region 35 toward the first main surface 3, and faces the second semiconductor layer 7 across a portion of the outer well region 35. In a plan view, the outer contact region 36 extends in a strip shape along the outer well region 35 (active region 20).

[0125] In this embodiment, the outer contact region 36 is formed as a polygonal ring (a quadrangular ring in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view, and surrounds a plurality of gate structures 25 (active regions 20). The outer contact region 36 may have an edge portion that connects a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in an arc shape (preferably a quarter-circular arc shape).

[0126] The semiconductor device 1A may include a plurality of outer contact regions 36 arranged at intervals following the extending direction of the outer well region 35 so as to surround a plurality of gate structures 25. In this case, the plurality of outer contact regions 36 may each extend in a strip shape along the extending direction of the outer well region 35.

[0127] The outer contact region 36 has a width less than the width of the outer well region 35 and is formed within the outer well region 35. The outer contact region 36 is formed in the inner part of the outer well region 35, spaced apart from both edges of the outer well region 35. The outer contact region 36 is biased toward the outer edge side of the outer well region 35 relative to the middle part of the outer well region 35. The outer contact region 36 may also be formed in the middle part of the outer well region 35.

[0128] Referring to Figures 2 and 6, the semiconductor device 1A includes at least one (or more in this embodiment) p-type field regions 37 formed on the surface layer of the first main surface 3 in the peripheral region 21 (the peripheral edge of the first main surface 3). The multiple field regions 37 are also a form of impurity region 9. The multiple field regions 37 may be formed in an electrically floating state. The multiple field regions 37 may be fixed to the source potential.

[0129] The number of field regions 37 is arbitrary. The number of field regions 37 may be between 1 and 20. The number of field regions 37 may be a value that falls within at least one of the following ranges: between 1 and 5, between 5 and 10, between 10 and 15, and between 15 and 20. Typically, the number of field regions 37 is between 1 and 8. In this embodiment, semiconductor device 1A includes 6 field regions 37.

[0130] Multiple field regions 37 are formed on the surface of the second semiconductor layer 7, spaced apart from each other. The multiple field regions 37 are formed in the region between the periphery of the first main surface 3 and the multiple gate structures 25 (active regions 20), spaced apart from the periphery of the first main surface 3. Specifically, the multiple field regions 37 are formed in the region between the periphery of the first main surface 3 and the outer well region 35.

[0131] The multiple field regions 37 extend in a strip-like manner along the multiple gate structures 25 (active regions 20) in a plan view. Specifically, the multiple field regions 37 extend in a strip-like manner along the outer well region 35. Each of the multiple field regions 37 has a portion that extends in a strip-like manner in a first direction X and a portion that extends in a strip-like manner in a second direction Y.

[0132] In this embodiment, the multiple field regions 37 are formed in a polygonal ring shape (a quadrilateral ring shape in this embodiment) surrounding the multiple gate structures 25 (active regions 20) in a plan view. The multiple field regions 37 may have edge portions that connect the portions extending in a strip shape in a first direction X and the portions extending in a strip shape in a second direction Y in an arc shape (preferably a quarter-circular arc shape).

[0133] Multiple field regions 37 are formed with a gap between them and the first main surface 3 side from the first semiconductor layer 6, and face the first semiconductor layer 6 with a part of the second semiconductor layer 7 in between. The multiple field regions 37 may be formed with a gap between them and the first main surface 3 side from the depth position of the middle part of the second semiconductor layer 7, or they may have a portion located on the first semiconductor layer 6 side with respect to the depth position of the middle part of the second semiconductor layer 7.

[0134] In this embodiment, the multiple field regions 37 are formed at intervals from the depth position of the bottom wall of the multiple gate structures 25 toward the first main surface 3. The depth of the multiple field regions 37 may be greater or less than the depth of the body region 22. The multiple field regions 37 may have portions located toward the first semiconductor layer 6 with respect to the depth position of the bottom wall of the multiple gate structures 25.

[0135] Multiple field regions 37 form a pn junction with the second semiconductor layer 7. When a reverse bias voltage is applied, the multiple field regions 37 expand a depletion layer in the second semiconductor layer 7. The depletion layer of the multiple field regions 37 expands in the horizontal and thickness directions and integrates with the depletion layer extending from the body region 22 and the outer well region 35.

[0136] The multiple field regions 37 extend the depletion layer extending from the body region 22 and the outer well region 35 toward the periphery of the first main surface 3, thereby mitigating the electric field strength (electric field concentration) at the periphery (outer outer region 21) of the first main surface 3.

[0137] The width, depth, spacing, and p-type impurity concentration of the multiple field regions 37 are arbitrary and can take various values ​​depending on the electric field to be relaxed. The width of the multiple field regions 37 may be approximately constant or non-uniform. The width of the multiple field regions 37 may gradually increase toward the periphery of the first main surface 3. The width of the multiple field regions 37 may gradually decrease toward the periphery of the first main surface 3.

[0138] The depths of the multiple field regions 37 may be approximately constant or non-uniform. The depths of the multiple field regions 37 may gradually increase toward the periphery of the first main surface 3. The depths of the multiple field regions 37 may gradually decrease toward the periphery of the first main surface 3. Of course, the multiple field regions 37 may have relatively shallow areas and deeper areas that are deeper than the shallow areas. The shallow areas may be formed on the inner side and the deeper areas on the periphery side. The shallow areas may be formed on the periphery side and the deeper areas on the inner side.

[0139] The spacing between the multiple field regions 37 may be approximately constant or non-uniform. The spacing between the multiple field regions 37 may gradually increase toward the periphery of the first main surface 3. The spacing between the multiple field regions 37 may gradually decrease toward the periphery of the first main surface 3.

[0140] The multiple field regions 37 may have a p-type impurity concentration that is approximately equal to the p-type impurity concentration of the multiple body regions 22. The p-type impurity concentration of the multiple field regions 37 may be higher or lower than the p-type impurity concentration of the multiple body regions 22.

[0141] Multiple field regions 37 may have a p-type impurity concentration approximately equal to that of the contact region 34. The p-type impurity concentrations of the multiple field regions 37 may be higher or lower than the p-type impurity concentration of the contact region 34.

[0142] Multiple field regions 37 may have a p-type impurity concentration approximately equal to that of the outer well region 35. The p-type impurity concentrations in the multiple field regions 37 may be higher or lower than the p-type impurity concentration of the outer well region 35.

[0143] The semiconductor device 1A includes a main surface insulating film 38 that selectively coats the first main surface 3. The main surface insulating film 38 may also be called a "surface insulating film," "external insulating film," etc. The main surface insulating film 38 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The main surface insulating film 38 may include a silicon oxide film containing the oxide of the second semiconductor layer 7. The main surface insulating film 38 may include a silicon oxide film containing oxides other than the oxide of the second semiconductor layer 7.

[0144] The main surface insulating film 38 selectively covers the first main surface 3 in the active region 20 and the peripheral region 21. The main surface insulating film 38 coats the first main surface 3 in a film-like manner in the active region 20. The main surface insulating film 38 is connected to the insulating films 27 of the multiple gate structures 25, exposing the embedded electrodes 28.

[0145] The main surface insulating film 38 covers the outer well region 35, the outer contact region 36, and a plurality of field regions 37 in the outer peripheral region 21. The main surface insulating film 38 is continuous with the first to fourth side surfaces 5A to 5D. The main surface insulating film 38 may be formed with an inward gap from the first to fourth side surfaces 5A to 5D, exposing the peripheral edge of the first main surface 3.

[0146] The main surface insulating film 38 may have a thickness of 10 nm or more and 250 nm or less. The thickness of the main surface insulating film 38 may have a value that falls within at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, 175 nm or more and 200 nm or less, 200 nm or more and 225 nm or more and 250 nm or less.

[0147] Referring to Figure 6, the semiconductor device 1A includes one or more (one in this embodiment) gate wirings 39 arranged on the first main surface 3 in the outer peripheral region 21. The gate wirings 39 provide gate potentials to the multiple gate structures 25. The gate wirings 39 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. Preferably, the gate wirings 39 have the same conductivity type as the embedded electrodes 28.

[0148] The gate wiring 39 is arranged on the main surface insulating film 38. The gate wiring 39 is selectively routed from the periphery of the first main surface 3 towards the multiple gate structures 25, spaced apart on the main surface insulating film 38, and faces the outer well region 35 across the main surface insulating film 38.

[0149] The gate wiring 39 extends in a strip shape along the multiple gate structures 25. The gate wiring 39 has a portion that extends in a strip shape in a first direction X and a portion that extends in a strip shape in a second direction Y. The gate wiring 39 extends in a strip shape so as to intersect (specifically, perpendicular to) the ends (both ends in this embodiment) of the multiple gate structures 25.

[0150] In this embodiment, the gate wiring 39 is formed as an endless polygonal ring (for example, a quadrangular ring) having four sides parallel to the periphery of the first main surface 3, and surrounds a plurality of gate structures 25 (active regions 20). Of course, the gate wiring 39 may also be formed as an ended strip. The gate wiring 39 may have an edge portion that connects the portion extending in a strip shape in the first direction X and the portion extending in a strip shape in the second direction Y in an arc shape (preferably a quarter-circular arc shape) in a plan view.

[0151] The gate wiring 39 has an inner edge portion on the inner side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the gate wiring 39 covers the ends (both ends in this embodiment) of the plurality of gate structures 25 and is mechanically and electrically connected to the plurality of gate structures 25. Specifically, the inner edge portion of the gate wiring 39 is mechanically and electrically connected to the plurality of embedded electrodes 28. In this embodiment, the inner edge portion of the gate wiring 39 is formed integrally with the plurality of embedded electrodes 28 as an exit portion for the plurality of embedded electrodes 28.

[0152] The inner edge of the gate wiring 39 has a portion located in the region between the multiple gate structures 25, and faces either or both of the body region 22 and the outer well region 35 across the main surface insulating film 38. The inner edge of the gate wiring 39 is formed at a distance from the outermost multiple source regions 33 and multiple contact regions 34 toward the periphery of the first main surface 3.

[0153] The outer edge of the gate wiring 39 is positioned on the main surface insulating film 38 with a gap between it and the multiple field regions 37 towards the multiple gate structures 25. With this configuration, shielding of the electric field dispersion path by the gate wiring 39 is suppressed, and the electric field (electric field lines) is appropriately dispersed by the multiple field regions 37.

[0154] The outer edge of the gate wiring 39 is formed with a gap between it and the outer edge of the outer well region 35, towards the multiple gate structures 25. The outer edge of the gate wiring 39 is formed with a gap between it and the inner edge of the outer contact region 36, towards the multiple gate structures 25, and faces the outer well region 35 across the main surface insulating film 38.

[0155] The semiconductor device 1A may include a plurality of gate wirings 39. In this case, the plurality of gate wirings 39 may be arranged at both ends of at least a plurality of gate structures 25. One gate wiring 39 may have a portion that extends in a strip shape in a first direction X and intersect (specifically, orthogonally) with one end of the plurality of gate structures 25. The other gate wiring 39 may have a portion that extends in a strip shape in the first direction X and intersect (specifically, orthogonally) with the other end of the plurality of gate structures 25. Of course, the plurality of gate wirings 39 may also have portions that extend in a second direction Y.

[0156] Referring to Figures 2 and 4 to 6, the semiconductor device 1A includes an interlayer film 10 that covers the first main surface 3. In this embodiment, the interlayer film 10 selectively covers the first main surface 3 via a main surface insulating film 38 in the active region 20 and the outer peripheral region 21. The interlayer film 10 covers a plurality of gate structures 25 in a film-like manner in the active region 20. The interlayer film 10 covers the embedded electrode 28 and electrically insulates the embedded electrode 28.

[0157] The interlayer film 10 covers the outer well region 35, the outer contact region 36, and a plurality of field regions 37 via the main surface insulating film 38 in the outer peripheral region 21. The interlayer film 10 directly covers the gate wiring 39 in the outer peripheral region 21. The interlayer film 10 is continuous with the first to fourth side surfaces 5A to 5D. The interlayer film 10 may be formed with a gap inward from the first to fourth side surfaces 5A to 5D, exposing the peripheral edge of the first main surface 3.

[0158] The interlayer film 10 has a thickness greater than the thickness of the main surface insulating film 38. The thickness of the interlayer film 10 may be 0.1 μm or more and 5 μm or less. The thickness of the interlayer film 10 may be 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or less and 5 μm or less.

[0159] The semiconductor device 1A includes a plurality of source openings 40 formed in the interlayer film 10 in the active region 20. The plurality of source openings 40 penetrate the main surface insulating film 38 and the interlayer film 10, exposing a plurality of mesa portions 29 (regions between a plurality of gate structures 25). Each of the plurality of source openings 40 is formed in a one-to-one correspondence with the plurality of mesa portions 29. Each of the plurality of source openings 40 extends in a strip shape in the second direction Y, following the extending direction of the corresponding mesa portion 29.

[0160] The multiple source openings 40 expose multiple source regions 33 and multiple contact regions 34 in the corresponding mesa portion 29, respectively. The multiple source openings 40 may each have an arc-shaped curved opening end.

[0161] The multiple source openings 40 may be formed in a one-to-many correspondence with respect to the corresponding mesa portion 29. In this case, the multiple source openings 40 may be formed at intervals along the corresponding mesa portion 29. In this case, the multiple source openings 40 may be formed in a square, rectangular (strip-shaped), circular, or the like in a plan view.

[0162] Referring to Figure 6, the semiconductor device 1A includes one or more (in this embodiment, more than one) gate openings 41 formed in the interlayer film 10 in the outer peripheral region 21. The multiple gate openings 41 penetrate the interlayer film 10 and selectively expose the gate wiring 39. In this embodiment, the multiple gate openings 41 extend in a strip shape following the direction of extension of the gate wiring 39.

[0163] The multiple gate openings 41 may be formed at intervals along the extending direction of the gate wiring 39. The multiple gate openings 41 may be formed in a polygonal or circular shape in a plan view. For example, the multiple gate structures 25 may be formed in a square or hexagonal shape in a plan view.

[0164] The multiple gate openings 41 may have portions that extend in a strip shape in a first direction X and portions that extend in a strip shape in a second direction Y when viewed from above. The multiple gate openings 41 may have edge portions that connect the portions that extend in a strip shape in the first direction X and portions that extend in a strip shape in the second direction Y in an arc shape (preferably a quarter-circular arc shape) when viewed from above.

[0165] Referring to Figure 6, the semiconductor device 1A includes at least one (one in this embodiment) outer opening 42 formed in the interlayer film 10 in the outer peripheral region 21. The outer opening 42 is formed with a gap from the gate wiring 39 toward the peripheral edge of the first main surface 3. The outer opening 42 penetrates the main surface insulating film 38 and the interlayer film 10, exposing the outer contact region 36.

[0166] The outer opening 42 has a width less than the width of the outer contact region 36, and exposes the inner portion of the outer contact region 36 at a distance from the inner and outer edges of the outer contact region 36. The outer opening 42 may also expose the outer well region 35.

[0167] In this embodiment, the outer opening 42 extends in a band shape following the direction of extension of the outer contact region 36. In this embodiment, the outer opening 42 is formed as a polygonal ring (a quadrangular ring in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view, and surrounds a plurality of gate structures 25 (active regions 20). The outer contact region 36 may have an edge portion that connects the portion extending in a band shape in the first direction X and the portion extending in a band shape in the second direction Y in an arc shape (preferably a quarter-circular arc shape).

[0168] The semiconductor device 1A may have a plurality of outer openings 42. In this case, the plurality of outer openings 42 may be formed at intervals following the extending direction of the outer contact region 36. The plurality of outer openings 42 may each extend in a strip shape following the extending direction of the outer contact region 36.

[0169] The semiconductor device 1A includes a first electrode 12 disposed on a first main surface 3. The first electrode 12 may have a single-layer or multilayer structure comprising at least one of a Ti-based metal film (barrier electrode film) and an Al-based metal film. The Ti-based metal film may comprise either a Ti film or a Ti alloy film, or both. For example, the Ti-based metal film may have a single-layer or multilayer structure comprising either a Ti film or a TiN film, or both.

[0170] The Al-based metal film may include at least one of an Al film and an Al alloy film. For example, the Al-based metal film may include at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film.

[0171] In this embodiment, the first electrode 12 includes a source electrode 43, a source finger electrode 44, a gate electrode 45, and a gate finger electrode 46. The source electrode 43 may also be referred to as the "first main surface electrode," "first terminal (electrode)," or "first pad (electrode)." The gate electrode 45 may also be referred to as the "second main surface electrode," "second terminal (electrode)," or "second pad (electrode)."

[0172] The source electrode 43 is positioned on the first main surface 3 via an interlayer film 10. In this embodiment, the source electrode 43 includes a main source electrode 43A, a first sub-source electrode 43B, and a second sub-source electrode 43C.

[0173] The main source electrode 43A has a relatively large surface area and forms the main body of the source electrode 43. In this configuration, the main source electrode 43A is formed in a polygonal shape (a quadrilateral shape in this configuration) with four sides parallel to the periphery of the first main surface 3 in a plan view, and is offset towards the second side surface 5B relative to the central part of the first main surface 3.

[0174] The first sub-source electrode 43B has a planar area less than that of the main source electrode 43A and extends in a strip-like (square-shaped) manner from one end of the main source electrode 43A in the second direction Y (the end on the first side surface 5A side) toward the fourth side surface 5D. The second sub-source electrode 43C has a planar area less than that of the main source electrode 43A and extends in a strip-like (square-shaped) manner from the other end of the main source electrode 43A in the second direction Y (the end on the third side surface 5C side) toward the fourth side surface 5D, and faces the first sub-source electrode 43B in the second direction Y.

[0175] The planar area of ​​the second sub-source electrode 43C may be approximately equal to the planar area of ​​the first sub-source electrode 43B. The planar area of ​​the second sub-source electrode 43C may be larger or smaller than the planar area of ​​the first sub-source electrode 43B. Either or both of the first sub-source electrode 43B and the second sub-source electrode 43C may be used as monitor electrodes for current monitoring.

[0176] The main source electrode 43A, the first sub-source electrode 43B, and the second sub-source electrode 43C do not necessarily have to be formed integrally. At least one or all of the main source electrode 43A, the first sub-source electrode 43B, and the second sub-source electrode 43C may be physically separated.

[0177] The source electrode 43 does not necessarily have both the first sub-source electrode 43B and the second sub-source electrode 43C at the same time. The source electrode 43 may have only one of the first sub-source electrode 43B and the second sub-source electrode 43C. The source electrode 43 may consist only of the main source electrode 43A and not have both the first sub-source electrode 43B and the second sub-source electrode 43C.

[0178] The source electrode 43 collectively covers the region of the interlayer film 10 where multiple source openings 40 are formed, and extends from above the interlayer film 10 into the source openings 40. The source electrode 43 has a portion that covers the interlayer film 10 and a portion that covers the first main surface 3 within the source openings 40.

[0179] The source electrode 43 is electrically insulated from the multiple gate structures 25 by the interlayer film 10 and is electrically connected to the first main surface 3 within the multiple source openings 40. Specifically, the source electrode 43 is mechanically and electrically connected to the multiple source regions 33 and the multiple contact regions 34 within the multiple source openings 40.

[0180] Referring to Figure 6, the peripheral edge of the source electrode 43 may extend from the active region 20 to the outer peripheral region 21 and face a portion of the gate wiring 39 across the interlayer film 10. The peripheral edge of the source electrode 43 may also have a portion facing the outer well region 35 via the gate wiring 39 and the main surface insulating film 38.

[0181] The peripheral edge of the source electrode 43 is formed with a gap between it and the multiple gate structures 25 from the multiple field regions 37. Specifically, the peripheral edge of the source electrode 43 is formed with a gap between it and the multiple gate structures 25 from the outer edge of the outer well region 35. The peripheral edge of the source electrode 43 is formed with a gap between it and the multiple gate structures 25 from the inner edge of the outer contact region 36.

[0182] The peripheral edge of the source electrode 43 is formed with a gap between the outer edge of the gate wiring 39 and the inner edge of the gate wiring 39. The peripheral edge of the source electrode 43 may also be formed with a gap between the middle portion of the gate wiring 39 and the inner edge of the gate wiring 39. The peripheral edge of the source electrode 43 may be positioned inward from the inner edge of the gate wiring 39 towards the first main surface 3.

[0183] The gate electrode 45 is positioned on the first main surface 3 at a distance from the source electrode 43. The gate electrode 45 is positioned in the region on the fourth side surface 5D side with respect to the main source electrode 43A, and faces the central part of the fourth side surface 5D and the main source electrode 43A in the first direction X. The gate electrode 45 is interposed in the region between the first sub-source electrode 43B and the second sub-source electrode 43C, and faces both the first sub-source electrode 43B and the second sub-source electrode 43C in the second direction Y.

[0184] The gate electrode 45 is formed in a polygonal shape (a quadrilateral in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view. The gate electrode 45 has a planar area less than that of the source electrode 43. The gate electrode 45 has a planar area less than that of the main source electrode 43A. The gate electrode 45 may also have a planar area less than that of the first sub-source electrode 43B (second sub-source electrode 43C).

[0185] The gate electrode 45 faces the outer well region 35 across the interlayer film 10. In this embodiment, the gate electrode 45 is formed at a distance from the ends (both ends) of the multiple gate structures 25. In other words, the gate electrode 45 does not face the multiple gate structures 25 in the stacking direction. The gate structures 25 may have portions that face a part of the gate structure 25 (for example, the ends) across the interlayer film 10.

[0186] In this embodiment, the gate electrode 45 does not have a connection to the gate wiring 39. Of course, the gate electrode 45 may be mechanically and electrically connected to the gate wiring 39 via one or more gate openings 41.

[0187] The gate finger electrode 46 is drawn out from the gate electrode 45 onto the first main surface 3 and transmits the gate potential applied to the gate electrode 45 to other regions. The gate finger electrode 46 is drawn out onto the portion of the interlayer film 10 that covers the gate wiring 39 and extends in a strip shape between the periphery of the first main surface 3 and the source electrode 43. In a plan view, the gate finger electrode 46 has a portion that extends in a strip shape in a first direction X and a portion that extends in a strip shape in a second direction Y.

[0188] In this embodiment, the gate finger electrode 46 is formed in the shape of an ended strip having four sides parallel to the periphery of the first main surface 3, and surrounds the source electrode 43. The gate finger electrode 46 is positioned closer to the periphery of the first main surface 3 than the ends of the plurality of gate structures 25. The gate finger electrode 46 may have an edge portion that connects the portion extending in a strip shape in the first direction X and the portion extending in a strip shape in the second direction Y in an arc shape (preferably a quarter-circular arc shape).

[0189] Referring to Figure 6, the gate finger electrode 46 enters the multiple gate openings 41 from above the interlayer film 10 and is mechanically and electrically connected to the gate wiring 39 within the multiple gate openings 41. As a result, the gate finger electrode 46 transmits the gate potential applied to the gate electrode 45 to the multiple gate structures 25.

[0190] The gate finger electrode 46 has an inner edge portion on the inner side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the gate finger electrode 46 is formed with a gap between the ends of the multiple gate structures 25 and the peripheral side of the first main surface 3. In other words, the gate finger electrode 46 does not face the multiple gate structures 25 in the stacking direction.

[0191] The inner edge of the gate finger electrode 46 is positioned on the gate wiring 39 and faces the peripheral edge of the source electrode 43 in the horizontal direction. The outer edge of the gate finger electrode 46 is drawn out from above the gate wiring 39 toward the peripheral edge of the first main surface 3 and is positioned on the interlayer film 10 in the region outside the gate wiring 39. In other words, the outer edge of the gate finger electrode 46 does not face the gate wiring 39 in the stacking direction.

[0192] The outer edge of the gate finger electrode 46 is positioned at a distance from the innermost field region 37 toward the inward side of the first main surface 3. The outer edge of the gate finger electrode 46 is positioned at a distance from the outer edge of the outer well region 35 toward the inward side of the first main surface 3, and faces the outer well region 35 across the main surface insulating film 38 and the interlayer film 10. The outer edge of the gate finger electrode 46 may be positioned on the peripheral side of the first main surface 3 relative to the outer edge of the outer well region 35, and may face the second semiconductor layer 7 in the stacking direction.

[0193] The semiconductor device 1A includes a source finger electrode 44 drawn out from a source electrode 43 onto the first main surface 3. The source finger electrode 44 transmits the source potential applied to the source electrode 43 to other regions. The source finger electrode 44 is drawn out from the source electrode 43 onto the portion of the interlayer film 10 that covers the outer contact region 36.

[0194] The source finger electrode 44 is routed in a strip-like manner in the region between the periphery of the first main surface 3 and the source electrode 43, spaced apart from the gate electrode 45 and the gate finger electrode 46. In a plan view, the source finger electrode 44 has a portion that extends in a strip-like manner in a first direction X and a portion that extends in a strip-like manner in a second direction Y.

[0195] In this embodiment, the source finger electrode 44 is formed in a polygonal annular shape (quadrilateral annular shape) having four sides parallel to the periphery of the first main surface 3, and surrounds the source electrode 43 and the gate finger electrode 46. The outer well region 35 may have an edge portion that connects a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in an arc shape (preferably a quarter-circular arc shape).

[0196] Referring to Figure 6, the source finger electrode 44 enters into a plurality of outer openings 42 from above the interlayer film 10 and is mechanically and electrically connected to the outer contact region 36 within the plurality of outer openings 42. As a result, the source finger electrode 44 transmits the source potential applied to the source electrode 43 to the outer contact region 36 (outer well region 35).

[0197] The source finger electrode 44 has an inner edge portion on the inner side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the source finger electrode 44 is positioned at a distance from the gate finger electrode 46 towards the peripheral side of the first main surface 3 and faces the gate finger electrode 46 in the horizontal direction.

[0198] The inner edge of the source finger electrode 44 is formed with a gap between the middle portion of the outer contact region 36 and the peripheral edge of the first main surface 3. The inner edge of the source finger electrode 44 may be positioned on the outer well region 35 or on the outer contact region 36.

[0199] The outer edge of the source finger electrode 44 is drawn out from above the outer contact region 36 towards the periphery of the first main surface 3 and is positioned on the interlayer film 10 in the region outside the outer contact region 36. The outer edge of the source finger electrode 44 is positioned at a distance from the innermost field region 37 towards the inward side of the first main surface 3.

[0200] The outer edge of the source finger electrode 44 is positioned at a distance from the outer edge of the outer well region 35 toward the inward side of the first main surface 3, and faces the outer well region 35 with the main surface insulating film 38 and the interlayer film 10 in between. The outer edge of the source finger electrode 44 may also be drawn out from the outer edge of the outer well region 35 toward the peripheral side of the first main surface 3, and face the second semiconductor layer 7 with the main surface insulating film 38 and the interlayer film 10 in between.

[0201] The semiconductor device 1A includes an uppermost film 13 that selectively covers the first main surface 3. In Figure 1, the uppermost film 13 is shown by hatching. The uppermost film 13 has portions that selectively cover the source electrode 43, portions that selectively cover the gate electrode 45, portions that selectively cover the gate finger electrode 46, portions that selectively cover the source finger electrode 44, and portions that selectively cover the interlayer film 10. The uppermost film 13 covers the entire area of ​​the gate finger electrode 46 and the entire area of ​​the source finger electrode 44.

[0202] The uppermost film 13 has a source inner edge on the source electrode 43 side, a gate inner edge on the gate electrode 45 side, and an outer edge on the peripheral side of the first main surface 3. The source inner edge of the uppermost film 13 covers the peripheral and inner portions of the source electrode 43 and defines one or more (in this embodiment, more) source pad openings 47 that serve as pad openings 14 for selectively exposing the source electrode 43.

[0203] The multiple source pad openings 47 include a first source pad opening 47 that selectively exposes the main source electrode 43A, a second source pad opening 47 that selectively exposes the first sub-source electrode 43B, and a third source pad opening 47 that selectively exposes the second sub-source electrode 43C.

[0204] The multiple source pad openings 47 are each divided into a rectangular shape in a plan view. The second source pad opening 47 and the third source pad opening 47 each have a smaller planar area than the first source pad opening 47.

[0205] The inner gate edge of the uppermost film 13 covers the peripheral edge of the gate electrode 45 and defines a gate pad opening 48, which serves as a pad opening 14 that selectively exposes the inner portion of the gate electrode 45. The outer edge of the uppermost film 13 is positioned on the interlayer film 10 at a distance from the periphery of the first main surface 3, exposing the periphery of the interlayer film 10.

[0206] The gate pad opening 48 is partitioned into a rectangular shape in plan view and has a smaller planar area than the first source pad opening 47. The planar area of ​​the gate pad opening 48 may be smaller or larger than the planar area of ​​the second source pad opening 47 (third source pad opening 47).

[0207] The top layer 13 has a laminated structure including an inorganic film 15 and an organic film 16 stacked in this order. The top layer 13 does not necessarily have to have a laminated structure including an inorganic film 15 and an organic film 16, and may have a single-layer structure consisting of either the inorganic film 15 or the organic film 16.

[0208] The inorganic film 15 may also be called an "inorganic insulating film." The organic film 16 may also be called an "organic insulating film," a "resin film," etc. The top film 13 does not necessarily have to have a laminated structure including the inorganic film 15 and the organic film 16, and may have a single-layer structure consisting of either the inorganic film 15 or the organic film 16.

[0209] The inorganic film 15 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. Preferably, the inorganic film 15 contains an insulating material different from the insulating material of the interlayer film 10. The organic film 16 has a thickness smaller than the thickness of the first electrode 12.

[0210] The inorganic film 15 has portions that selectively cover the source electrode 43, portions that selectively cover the gate electrode 45, portions that selectively cover the gate finger electrode 46, portions that selectively cover the source finger electrode 44, and portions that selectively cover the interlayer film 10. In this embodiment, the inorganic film 15 covers the entire area of ​​the gate finger electrode 46 and the entire area of ​​the source finger electrode 44.

[0211] The inorganic film 15 has a source inner edge on the source electrode 43 side, a gate inner edge on the gate electrode 45 side, and an outer edge on the peripheral side of the first main surface 3. The source inner edge of the inorganic film 15 selectively covers the peripheral and inward portions of the source electrode 43 and partitions a portion of the multiple source pad openings 47. The gate inner edge of the inorganic film 15 covers the peripheral portion of the gate electrode 45 and partitions a portion of the gate pad opening 48. The outer edge of the inorganic film 15 is positioned on the interlayer film 10 at a distance from the periphery of the first main surface 3, exposing the periphery of the interlayer film 10.

[0212] The inorganic film 15 has portions that selectively cover the source electrode 43 on either side of the inorganic film 15, portions that selectively cover the gate electrode 45 on either side of the inorganic film 15, portions that selectively cover the gate finger electrode 46 on either side of the inorganic film 15, portions that selectively cover the source finger electrode 44 on either side of the inorganic film 15, and portions that selectively cover the interlayer film 10 on either side of the inorganic film 15.

[0213] The inorganic film 15 may have a thickness greater than 0 μm and less than or equal to 2 μm. The thickness of the inorganic film 15 may have a value that falls within at least one of the following ranges: greater than 0 μm and less than or equal to 0.1 μm, between 0.1 μm and 0.5 μm, between 0.5 μm and 1 μm, between 1 μm and 1.5 μm, and between 1.5 μm and 2 μm.

[0214] The organic film 16 may contain a transparent resin or a light-transmitting resin. The organic film 16 may contain a negative-type or positive-type photosensitive resin. The organic film 16 may contain at least one of a polyimide film, a polyamide film, and a polybenzoxazole film.

[0215] In this configuration, the organic film 16 covers the entire area of ​​the gate finger electrode 46 and the entire area of ​​the source finger electrode 44, with the inorganic film 15 in between. The organic film 16 has an inner source edge on the source electrode 43 side, an inner gate edge on the gate electrode 45 side, and an outer edge on the peripheral side of the first main surface 3.

[0216] The source inner edge of the organic film 16 selectively covers the peripheral and inner portions of the source electrode 43, sandwiching the inorganic film 15, and partitions a portion of the multiple source pad openings 47. In this configuration, the source inner edge of the organic film 16 exposes the source inner edge of the inorganic film 15. The source inner edge of the organic film 16 may also cover the source inner edge of the inorganic film 15.

[0217] The inner gate edge of the organic film 16 covers the peripheral edge of the gate electrode 45, sandwiching the inorganic film 15, and partitions a part of the gate pad opening 48. In this configuration, the inner gate edge of the organic film 16 exposes the inner gate edge of the inorganic film 15. The inner gate edge of the organic film 16 may also cover the inner gate edge of the inorganic film 15.

[0218] The outer edge of the organic film 16 is positioned on the interlayer film 10 at a distance from the periphery of the first main surface 3, exposing the periphery of the interlayer film 10. In this configuration, the outer edge of the organic film 16 exposes the outer edge of the inorganic film 15. The outer edge of the organic film 16 may also cover the outer edge of the inorganic film 15.

[0219] The organic film 16 has a thickness greater than the inorganic film 15. The thickness of the organic film 16 is greater than the thickness of the inorganic film 15. The organic film 16 may have a thickness of 1 μm or more and 25 μm or less. The thickness of the organic film 16 may have a value that falls within at least one of the following ranges: 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or more and 25 μm or less.

[0220] The semiconductor device 1A includes a second electrode 17 disposed on a second main surface 4. The second electrode 17 may have a single-layer structure or a multilayer structure comprising at least one of Al-based metal films, Cu-based metal films, Ti-based metal films, Ni-based metal films, Pd-based metal films, Au-based metal films, and Ag-based metal films. The Al-based metal film may comprise at least one of Al films and Al alloy films. For example, the Al-based metal film may comprise at least one of AlSi alloy films, AlCu alloy films, and AlSiCu alloy films.

[0221] Ti-based metal films may contain either a Ti film or a Ti alloy film, or both. Ni-based metal films may contain either a Ni film or a Ni alloy film, or both. Pd-based metal films may contain either a Pd film or a Pd alloy film, or both. Au-based metal films may contain either an Au film or an Au alloy film, or both. Ag-based metal films may contain either an Ag film or an Ag alloy film, or both.

[0222] If the second electrode 17 has a laminated structure, at least two of the following are laminated on the second main surface 4 in any order and combination: Al-based metal film, Cu-based metal film, Ti-based metal film, Ni-based metal film, Pd-based metal film, Au-based metal film, and Ag-based metal film.

[0223] For example, the second electrode 17 may have a laminated structure including an Al-based metal film, a Ti-based metal film, a Ni-based metal film, a Pd-based metal film, an Au-based metal film, and an Ag-based metal film, stacked in this order from the first semiconductor layer 6 side. In this case, at least one of the Al-based metal film, Ti-based metal film, Ni-based metal film, Pd-based metal film, Au-based metal film, and Ag-based metal film may be removed.

[0224] In this configuration, the second electrode 17 is formed as a drain electrode 49. The drain electrode 49 may also be referred to as the "third main surface electrode," "third terminal (electrode)," "third pad (electrode)," etc.

[0225] The drain electrode 49 may cover the entire area of ​​the second main surface 4 so as to be continuous with the periphery of the second main surface 4 (first to fourth side surfaces 5A to 5D). Alternatively, the drain electrode 49 may be formed at a distance from the periphery of the second main surface 4, leaving the periphery of the second main surface 4 exposed.

[0226] The drain electrode 49 is mechanically and electrically connected to the first semiconductor layer 6. The drain electrode 49 forms ohmic contact with the first semiconductor layer 6. Together with the source electrode 43, the drain electrode 49 forms a current path through the chip 2 (first semiconductor layer 6 and second semiconductor layer 7).

[0227] The breakdown voltage that can be applied between the source electrode 43 and the drain electrode 49 (between the first main surface 3 and the second main surface 4) may be 500V or more and 3000V or less. The breakdown voltage may have a value that falls within at least one of the following ranges: 500V or more and 750V or less, 750V or more and 1000V or less, 1000V or more and 1250V or less, 1250V or more and 1500V or less, 1500V or more and 1750V or less, 1750V or more and 2000V or less, 2000V or more and 2250V or more and 2250V or more and 2500V or more and 3000V or less.

[0228] (2) Structural diagram 7 of the semiconductor device 1B is an enlarged plan view showing a key part of the first main surface 3 of the semiconductor device 1B according to the second embodiment. Figure 8 is a cross-sectional view taken along the line VIII-VIII shown in Figure 7. Figure 9 is a cross-sectional view taken along the line IX-IX shown in Figure 7. Figure 10 is a cross-sectional view taken along the line XX shown in Figure 7. Figure 11 is a cross-sectional view taken along the line XI-XI shown in Figure 7. Figures 12 to 15 are cross-sectional perspective views showing the first to fourth key parts of the active region 20. Figure 16 is a horizontal cross-sectional view taken along the line XVI-XVI shown in Figure 8. Figure 17 is a horizontal cross-sectional view taken along the line XVII-XVII shown in Figure 8.

[0229] In the semiconductor device 1B, the multiple gate structures 25 are arranged at intervals in the second direction Y (= a-axis direction) in a plan view, and each extends in a strip-like shape in the first direction X (= m-axis direction). The multiple gate structures 25 are arranged in a stripe-like shape extending in the first direction X in a plan view.

[0230] In the semiconductor device 1B, multiple well regions 30 are formed in the first well region 31, and the second well region 32 is omitted. The multiple well regions 30 each extend in a strip-like manner in the first direction X when viewed from above, and are arranged with gaps in the second direction Y. The multiple well regions 30 are arranged in a stripe-like manner extending in the first direction X when viewed from above. The extension directions of the multiple well regions 30 intersect (specifically orthogonal to) the off-direction of the SiC single crystal.

[0231] The semiconductor device 1B includes a plurality of n-type first pillar regions 8 formed within the second semiconductor layer 7 in the inner portion (active region 20) of the first main surface 3. The first pillar regions 8 may also be referred to as "first regions," "first impurity regions," "first column regions," etc. The plurality of first pillar regions 8 have an n-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 7. The plurality of first pillar regions 8 may be considered as a part (a component) of the second semiconductor layer 7 as a high-concentration portion of the second semiconductor layer 7.

[0232] The n-type impurity concentrations in the multiple first pillar regions 8 are lower than the p-type impurity concentrations in the multiple well regions 30. The n-type impurity concentrations in the multiple first pillar regions 8 may be higher or lower than the p-type impurity concentrations in the body region 22.

[0233] Multiple first pillar regions 8 are formed in the active region 20 at intervals from the periphery of the first main surface 3, but not in the outer peripheral region 21. Of course, multiple first pillar regions 8 may also be formed in the outer peripheral region 21 within the second semiconductor layer 7. In a plan view, multiple first pillar regions 8 are arranged at intervals in the first direction X (= m-axis direction) and each extends in a strip shape in the second direction Y (= a-axis direction).

[0234] In other words, the multiple first pillar regions 8 are arranged in a stripe-like pattern extending in the second direction Y in a plan view, and intersect (specifically orthogonally) with the multiple gate structures 25. The direction of extension of the multiple first pillar regions 8 coincides with the off-direction of the SiC single crystal.

[0235] The first pillar region 8 may have a width greater than 0 μm and less than or equal to 3 μm. The width of the first pillar region 8 may be greater than or less than the width of the gate structure 25. The width of the first pillar region 8 may be greater than or less than the spacing of the gate structure 25.

[0236] The width of the first pillar region 8 may be greater than 0 μm and fall within at least one of the following ranges: 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less.

[0237] Multiple first pillar regions 8 may be formed at intervals greater than 0 μm and 3 μm or less. The spacing between the first pillar regions 8 may be greater than or less than the width of the first pillar regions 8. The spacing between the first pillar regions 8 may be greater than or less than the width of the gate structure 25. The spacing between the first pillar regions 8 may be greater than or less than the spacing of the gate structure 25.

[0238] The spacing of the first pillar region 8 may have a value that is greater than 0 μm and falls within at least one of the following ranges: 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less.

[0239] Multiple first pillar regions 8 are formed in a region below the bottom of the body region 22 and extend in a vertical columnar shape along the thickness direction Z. Multiple first pillar regions 8 are formed at intervals from the bottom of the second semiconductor layer 7 toward the first main surface 3 and face the first semiconductor layer 6 via a portion of the second semiconductor layer 7.

[0240] In this configuration, each of the multiple first pillar regions 8 is formed by a single n-type impurity region extending along the axial channel of the SiC single crystal (second semiconductor layer 7). The axial channel is a region (channel) with relatively wide interatomic distances in the SiC single crystal and is surrounded by rows of atoms that constitute the crystal axis extending in the stacking direction. In other words, the axial channel is a region in which a region with sparse interatomic distances (atomic density) in the horizontal direction extends in the thickness direction Z.

[0241] The axial channel is preferably a region surrounded by atomic rows along the low-index crystal axis among the crystal axes. The low-index crystal axis is a crystal axis in which the absolute values ​​of "a1", "a2", "a3", and "c" are all between 0 and 2 (preferably 1) with respect to Miller indices (a1, a2, a3, c).

[0242] In this configuration, the axial channel consists of a region surrounded by atomic rows along the c-axis ((0001) axis) of the SiC single crystal. In other words, the multiple first pillar regions 8 extend along the c-axis as the axial channel and have the aforementioned off-direction and off-angle. In other words, the multiple first pillar regions 8 are tilted by the off-angle from the vertical axis in the off-direction.

[0243] In this configuration, the extension direction (a-axis direction) of the multiple first pillar regions 8 coincides with the off-direction of the off-angle. Therefore, the multiple first pillar regions 8 extend almost perpendicularly in a cross-sectional view along the direction perpendicular to the off-direction (first direction X = a-axis direction) (second direction Y = m-axis direction).

[0244] The first pillar region 8 has a depth greater than the depth of the gate structure 25. The depth of the first pillar region 8 is less than the thickness of the second semiconductor layer 7. The depth of the first pillar region 8 may be greater than 0 μm and 5 μm or less.

[0245] The depth of the first pillar region 8 may be greater than 0 μm and fall within at least one of the following ranges: 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. Preferably, the depth of the first pillar region 8 is 1 μm or more.

[0246] The first pillar region 8 may have an aspect ratio of 1 or more and 10 or less. The aspect ratio of the first pillar region 8 is the ratio of the depth of the first pillar region 8 to the width of the first pillar region 8.

[0247] The aspect ratio of the first pillar region 8 may have a value that falls within at least one of the following ranges: 1 to 2, 2 to 3, 3 to 4, 4 to 5, 5 to 6, 6 to 7, 7 to 8, 8 to 9, and 9 to 10.

[0248] Each of the multiple first pillar regions 8 has a first upper region 8U located on the first main surface 3 side with respect to the bottom wall of the multiple gate structures 25, and a first lower region 8L located on the bottom side of the second semiconductor layer 7 with respect to the bottom wall of the multiple gate structures 25. The n-type impurity concentration in the multiple first pillar regions 8 is lower than the p-type impurity concentration in the multiple well regions 30 in both the first upper region 8U and the first lower region 8L.

[0249] The first upper region 8U is interposed in the region between the multiple gate structures 25 and extends in the second direction Y. The first upper region 8U is connected to the side walls of the multiple gate structures 25 and faces the embedded electrode 28 via the insulating film 27 of the multiple gate structures 25. The first upper region 8U has a first upper end connected to the body region 22.

[0250] In this embodiment, the first upper region 8U has a first constriction that is narrowed in the first direction X, and a first bulge that extends in the first direction X. The first constriction is formed in the thickness range between the bottom walls of the multiple gate structures 25 and the bottom of the body region 22, and is a portion in which the width in the first direction X gradually decreases toward the body region 22.

[0251] The first bulge is formed in the thickness range between the bottom of the body region 22 and the first constriction, and is a portion in which the width in the first direction X gradually increases toward the bottom of the body region 22. In this embodiment, the first bulge forms the first upper end connected to the body region 22.

[0252] The first lower region 8L extends in the second direction Y in the region below the bottom walls of the multiple gate structures 25, and intersects with the multiple gate structures 25 in three dimensions. In other words, the multiple first pillar regions 8 (first lower region 8L) are formed in the region directly below the gate structures 25, spaced apart in the first direction X following the direction of extension of the gate structures 25.

[0253] In this configuration, the first lower region 8L intersects with and connects to multiple well regions 30 in the region directly below the multiple gate structures 25. At the first intersection Cr1 of the well region 30 and the first lower region 8L (see Figure 16), the p-type impurity concentration in the well region 30 is offset (reduced) by the amount of the n-type impurity concentration (pentavalent element concentration) in the first lower region 8L.

[0254] The first lower region 8L has a first bottom portion 8B located below the depth position of the bottom walls of the multiple gate structures 25. The first bottom portion 8B has a portion that extends in the second direction Y in the region directly below the multiple gate structures 25, and a portion that extends in the second direction Y outside the region directly below the multiple gate structures 25.

[0255] The first bottom portion 8B is located below the bottoms of the multiple well regions 30. The first bottom portion 8B has a portion that extends in the second direction Y in the region directly below the multiple well regions 30, and a portion that extends in the second direction Y outside the region directly below the multiple well regions 30. The first bottom portion 8B faces the bottom walls of the multiple gate structures 25 via the multiple well regions 30.

[0256] The distance between the bottom of the well region 30 and the first bottom 8B is less than the distance between the bottom of the second semiconductor layer 7 and the first bottom 8B. The distance between the bottom wall of the gate structure 25 and the first bottom 8B is less than the distance between the bottom of the second semiconductor layer 7 and the first bottom 8B.

[0257] In this embodiment, the distance between the bottom wall of the gate structure 25 and the first bottom 8B is smaller than the depth of the gate structure 25. The distance between the bottom wall of the gate structure 25 and the first bottom 8B may be larger than the depth of the gate structure 25.

[0258] The first pillar region 8 does not necessarily have to include both the first constriction and the first bulge at the same time. The first pillar region 8 may have the first constriction but not the first bulge. In this case, the first constriction may be connected to the body region 22 as the first upper end. The first pillar region 8 may not have the first constriction but have the first bulge. In this case, the first bulge may be connected to the body region 22 as the first upper end.

[0259] The first pillar region 8 does not necessarily have both a first constriction and a first bulge. In this case, the first pillar region 8 may extend perpendicularly in the thickness direction Z. Of course, the first pillar region 8 may be formed in a tapered or tapered shape in the thickness direction Z.

[0260] The semiconductor device 1B includes a plurality of p-type second pillar regions 11 formed within the second semiconductor layer 7 in the inner portion (active region 20) of the first main surface 3. The second pillar regions 11 may also be referred to as "second regions," "second impurity regions," "second column regions," etc.

[0261] The multiple second pillar regions 11 have a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 7. The p-type impurity concentration of the multiple second pillar regions 11 is lower than the p-type impurity concentration of the multiple well regions 30. The p-type impurity concentration of the multiple second pillar regions 11 may be higher or lower than the p-type impurity concentration of the body region 22.

[0262] Multiple second pillar regions 11 are formed in the active region 20 at intervals from the periphery of the first main surface 3, but not in the outer peripheral region 21. Of course, multiple second pillar regions 11 may also be formed in the outer peripheral region 21 within the second semiconductor layer 7. In a plan view, the multiple second pillar regions 11 are arranged at intervals in the first direction X (= m-axis direction) and each extends in a strip shape in the second direction Y (= a-axis direction).

[0263] In other words, the multiple second pillar regions 11 are arranged in a stripe-like pattern extending in the second direction Y in a plan view, and intersect (specifically orthogonally) with the multiple gate structures 25. The direction of extension of the multiple second pillar regions 11 coincides with the off-direction of the SiC single crystal.

[0264] Multiple second pillar regions 11 are formed alternately with multiple first pillar regions 8 in the first direction X, and form pn junctions with the multiple first pillar regions 8. This forms a bipolar diode including multiple first pillar regions 8 as cathode regions and multiple second pillar regions 11 as anode regions.

[0265] The multiple second pillar regions 11 have a charge balance with respect to the multiple first pillar regions 8 and constitute a superjunction structure with the multiple first pillar regions 8. Charge balance refers to a state in which the depletion layers extending from the multiple second pillar regions 11 are connected within the multiple first pillar regions 8.

[0266] The second pillar region 11 has a width corresponding to the spacing of the first pillar region 8. The width of the second pillar region 11 may be approximately equal to the width of the first pillar region 8. The width of the second pillar region 11 may be greater than or less than the width of the first pillar region 8. The width of the second pillar region 11 may be greater than or less than the width of the gate structure 25. The width of the second pillar region 11 may be greater than or less than the spacing of the gate structure 25.

[0267] The width of the second pillar region 11 may be greater than 0 μm and 3 μm or less. The width of the second pillar region 11 may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less.

[0268] Multiple second pillar regions 11 are formed at intervals corresponding to the width of the first pillar region 8. The spacing between the second pillar regions 11 may be approximately equal to the width of the second pillar region 11. The spacing between the second pillar regions 11 may be greater or less than the width of the second pillar region 11.

[0269] The spacing of the second pillar regions 11 may be approximately equal to the spacing of the first pillar regions 8. The spacing of the second pillar regions 11 may be larger or smaller than the spacing of the first pillar regions 8. The spacing of the second pillar regions 11 may be larger or smaller than the width of the gate structure 25. The spacing of the second pillar regions 11 may be larger or smaller than the spacing of the gate structure 25.

[0270] The spacing of the second pillar regions 11 may be greater than 0 μm and less than or equal to 3 μm. The spacing of the second pillar regions 11 may have a value that falls within at least one of the following ranges: greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, and 2.5 μm to 3 μm.

[0271] Multiple second pillar regions 11 are formed in a region below the bottom of the body region 22 and extend in a vertical columnar shape along the thickness direction Z. Multiple second pillar regions 11 are formed at intervals from the bottom of the second semiconductor layer 7 toward the first main surface 3 and face the first semiconductor layer 6 via a portion of the second semiconductor layer 7.

[0272] In this configuration, each of the multiple second pillar regions 11 is formed by a single p-type impurity region extending along the axial channel of the SiC single crystal (second semiconductor layer 7). In other words, the multiple second pillar regions 11 extend along the c-axis as the axial channel and have the aforementioned off-direction and off-angle. To put it another way, the multiple second pillar regions 11 are inclined by the off-angle from the vertical axis in the off-direction.

[0273] In this configuration, the extension direction (a-axis direction) of the multiple second pillar regions 11 coincides with the off-direction of the off-angle. Therefore, the multiple second pillar regions 11 extend almost perpendicularly in a cross-sectional view along the direction perpendicular to the off-direction (first direction X = a-axis direction) (second direction Y = m-axis direction).

[0274] The second pillar region 11 has a depth greater than the depth of the gate structure 25. The depth of the second pillar region 11 is less than the thickness of the second semiconductor layer 7. The depth of the second pillar region 11 may be approximately equal to the depth of the first pillar region 8.

[0275] The depth of the second pillar region 11 may be greater than the depth of the first pillar region 8. The depth of the second pillar region 11 may be less than the depth of the first pillar region 8. The depth of the second pillar region 11 may be greater than 0 μm and 5 μm or less.

[0276] The depth of the second pillar region 11 may be greater than 0 μm and fall within at least one of the following ranges: 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. Preferably, the depth of the second pillar region 11 is 1 μm or more.

[0277] The aspect ratio of the second pillar region 11 may be approximately equal to that of the first pillar region 8. The aspect ratio of the second pillar region 11 is the ratio of the depth of the second pillar region 11 to its width. The aspect ratio of the second pillar region 11 may be greater than or less than that of the first pillar region 8.

[0278] The aspect ratio of the second pillar region 11 may be between 1 and 10. The aspect ratio of the second pillar region 11 may have a value that falls within at least one of the following ranges: 1 to 2, 2 to 3, 3 to 4, 4 to 5, 5 to 6, 6 to 7, 7 to 8, 8 to 9, and 9 to 10.

[0279] Each of the multiple second pillar regions 11 has a second upper region 11U located on the first main surface 3 side with respect to the bottom wall of the multiple gate structures 25, and a second lower region 11L located on the bottom side of the second semiconductor layer 7 with respect to the bottom wall of the multiple gate structures 25. The p-type impurity concentration in the multiple second pillar regions 11 is lower than the p-type impurity concentration in the multiple well regions 30 in both the second upper region 11U and the second lower region 11L.

[0280] The second upper region 11U is interposed in the region between the multiple gate structures 25 and extends in the second direction Y. The second upper region 11U is connected to the side walls of the multiple gate structures 25 and faces the embedded electrode 28 via the insulating film 27 of the multiple gate structures 25. The second upper region 11U has a second upper end connected to the body region 22.

[0281] The second upper region 11U is located between the multiple gate structures 25 and forms a pn junction with the first upper region 8U of the multiple first pillar regions 8. The second upper region 11U has a charge balance with the first upper region 8U in the region between the multiple gate structures 25 and forms a superjunction structure with the first upper region 8U.

[0282] In this embodiment, the second upper region 11U has a second bulge that extends in the first direction X, and a second constriction that narrows in the first direction X. The second bulge is formed along the first constriction of the first pillar region 8 in a thickness range between the bottom walls of the multiple gate structures 25 and the bottom of the body region 22, and is a portion in which the width in the first direction X gradually increases toward the body region 22.

[0283] The second constriction is formed along the first bulge of the first pillar region 8 in the region between the body region 22 and the second bulge, and is a portion in which the width in the first direction X gradually decreases toward the bottom of the body region 22. In other words, the irregularities of the second upper region 11U interlock with the irregularities of the first upper region 8U. In this embodiment, the second constriction forms a second upper end connected to the body region 22.

[0284] The second lower region 11L extends in the second direction Y in the region below the bottom walls of the multiple gate structures 25 and intersects with the multiple gate structures 25 in three dimensions. In other words, the multiple second pillar regions 11 (second lower region 11L) are formed in the region directly below the gate structures 25, spaced apart in the first direction X following the direction of extension of the gate structures 25. The multiple second pillar regions 11 are formed alternately with the multiple first pillar regions 8 in the region directly below the gate structures 25 in the first direction X.

[0285] In this configuration, the second lower region 11L intersects with and connects to the multiple well regions 30 in the region directly below the multiple gate structures 25. In other words, the multiple second pillar regions 11 are interposed between the body region 22 and the multiple well regions 30, electrically connecting the multiple well regions 30 to the body region 22. The multiple second pillar regions 11 are electrically interlocked with the body region 22 and the multiple well regions 30.

[0286] In the second intersection Cr2 of the well region 30 and the second lower region 11L (see Figure 16), the p-type impurity concentration in the well region 30 is increased by the amount of the p-type impurity concentration (trivalent element concentration) in the second lower region 11L. In other words, the p-type impurity concentration in the second intersection Cr2 is higher than the p-type impurity concentration in the first intersection Cr1.

[0287] The second lower region 11L forms a pn joint with the first lower region 8L of the multiple first pillar regions 8. Specifically, the second lower region 11L has a portion that forms a pn joint with the first lower region 8L in the region directly below the multiple gate structures 25, and a portion that forms a pn joint with the first lower region 8L outside the region directly below the multiple gate structures 25.

[0288] The second lower region 11L has a portion that forms a pn junction with the first lower region 8L in the region directly below the multiple well regions 30, and a portion that forms a pn junction with the first lower region 8L outside the region directly below the multiple well regions 30. The second lower region 11L has a charge balance with the first lower region 8L and constitutes a superjunction structure with the first lower region 8L.

[0289] The second lower region 11L has a second bottom portion 11B located below the depth position of the bottom walls of the multiple gate structures 25. The second bottom portion 11B has a portion that extends in the second direction Y in the region directly below the multiple gate structures 25, and a portion that extends in the second direction Y outside the region directly below the multiple gate structures 25.

[0290] The second bottom portion 11B is located below the bottoms of the multiple well regions 30. The second bottom portion 11B has a portion that extends in the second direction Y in the region directly below the multiple well regions 30, and a portion that extends in the second direction Y outside the region directly below the multiple well regions 30. The second bottom portion 11B faces the bottom walls of the multiple gate structures 25 via the multiple well regions 30.

[0291] The second bottom 11B may be located in the region directly beneath the multiple gate structures 25 at approximately the same depth as the first bottom 8B of the first pillar region 8. The second bottom 11B may be located below the first bottom 8B (towards the bottom of the second semiconductor layer 7) in the region directly beneath the multiple gate structures 25. The second bottom 11B may be located above the first bottom 8B (towards the bottom wall of the multiple gate structures 25 / towards the bottom of the multiple well regions 30) in the region directly beneath the multiple gate structures 25.

[0292] The distance between the bottom of the well region 30 and the second bottom 11B is less than the distance between the bottom of the second semiconductor layer 7 and the second bottom 11B. The distance between the bottom wall of the gate structure 25 and the second bottom 11B is less than the distance between the bottom of the second semiconductor layer 7 and the second bottom 11B.

[0293] In this embodiment, the distance between the bottom wall of the gate structure 25 and the second bottom 11B is less than the depth of the gate structure 25. The distance between the bottom wall of the gate structure 25 and the second bottom 11B may be greater than the depth of the gate structure 25.

[0294] The second pillar region 11 does not necessarily have to include both the second bulge and the second constriction simultaneously. The second pillar region 11 may have the second bulge but not the second constriction. In this case, the second bulge may be connected to the body region 22 as the second upper end. The second pillar region 11 may not have the second bulge but have the second constriction. In this case, the second constriction may be connected to the body region 22 as the second upper end.

[0295] The second pillar region 11 does not necessarily have both a second bulge and a second constriction. In this case, the second pillar region 11 may extend perpendicularly in the thickness direction Z. Of course, the second pillar region 11 may be formed in a tapered or tapered shape in the thickness direction Z.

[0296] Referring to Figures 16 and 17, the semiconductor device 1B includes a p-type mesh region 18 formed within the second semiconductor layer 7 in a horizontal cross-sectional view. The mesh region 18 extends in a mesh-like manner within the second semiconductor layer 7 at a thickness position spaced apart from the first main surface 3, in a first direction X (m-axis direction) and a second direction Y (a-axis direction) along the first main surface 3.

[0297] The mesh region 18 divides the second semiconductor layer 7 into multiple n-type inter-mesh regions 19, which serve as multiple current paths. The mesh region 18 narrows the current when the device is on and improves short-circuit withstand capability. The mesh region 18 is formed in a region below the depth position of the bottom of the body region 22. The mesh region 18 is formed in a region below the bottom walls of the multiple gate structures 25 (trenches 26).

[0298] The mesh region 18 integrally includes a plurality of p-shaped well regions 30 as a plurality of first regions (first stripe regions) extending in a strip shape in a first direction X, and a plurality of p-shaped second pillar regions 11 as a plurality of second regions (second stripe regions) extending in a strip shape in a second direction Y.

[0299] Multiple well regions 30 extend in a stripe-like pattern in the first direction X at thickness positions spaced apart from the first main surface 3 within the second semiconductor layer 7. Each of the multiple well regions 30 is formed in the region below (specifically directly beneath) the multiple gate structures 25, and overlaps with the multiple gate structures 25 in a one-to-one correspondence in the thickness direction Z.

[0300] Each of the multiple second pillar regions 11 has a p-type impurity concentration lower than the p-type impurity concentration of the multiple well regions 30. The multiple second pillar regions 11 extend in a stripe pattern in the second direction Y within the second semiconductor layer 7 so as to be connected to the multiple well regions 30 in a mesh-like manner, and demarcate the multiple well regions 30 and the multiple inter-mesh regions 19.

[0301] Multiple second pillar regions 11 are connected to multiple well regions 30 in a cross shape. Of course, multiple second pillar regions 11 may also be connected to multiple well regions 30 in a T shape. The second pillar regions 11 may have a width greater than the width of the well regions 30. The width of the second pillar regions 11 may be less than the width of the well regions 30. The width of the second pillar regions 11 may be approximately equal to the width of the well regions 30.

[0302] The multiple second pillar regions 11 extend vertically in the thickness direction Z of the second semiconductor layer 7 in a cross-sectional view, and each has a second upper region 11U (first portion) located above the multiple well regions 30, and a second lower region 11L (second portion) located below the multiple well regions 30. The second bottom portion 11B of the second lower region 11L is located below the bottom portion of the multiple well regions 30.

[0303] Multiple second upper regions 11U are connected to the body region 22, and multiple second lower regions 11L are connected to multiple well regions 30. In other words, the multiple second lower regions 11L form a mesh region 18 with the multiple well regions 30 and simultaneously partition multiple intermesh regions 19. Furthermore, the multiple second upper regions 11U are formed as connection parts that electrically connect the mesh region 18 to the body region 22.

[0304] The multiple intermesh regions 19 are partitioned in a row along the first direction X, following the direction of extension of the multiple well regions 30 (multiple gate structures 25) in a plan view. The multiple intermesh regions 19 are partitioned in a row along the second direction Y, following the direction of extension of the multiple second pillar regions 11 (multiple first pillar regions 8) in a plan view. In other words, the multiple intermesh regions 19 are partitioned in a matrix with spacing in the first direction X and the second direction Y in a plan view.

[0305] In this configuration, the multiple intermesh regions 19 are formed by multiple n-type first pillar regions 8 having an n-type impurity concentration higher than that of the second semiconductor layer 7, and extend in a vertically elongated columnar shape along the thickness direction Z. The multiple intermesh regions 19 form low-resistance current paths having a resistance value lower than that of the second semiconductor layer 7.

[0306] Each of the multiple mesh regions 19 comprises a first upper region 8U (first part) partitioned above the bottom walls of the multiple gate structures 25, and a first lower region 8L (second part) partitioned below the bottom walls of the multiple gate structures 25.

[0307] The first upper region 8U is partitioned by a plurality of gate structures 25 and a plurality of second pillar regions 11 (second upper region 11U). The first lower region 8L is partitioned by a mesh region 18. In other words, the first lower region 8L is partitioned by a plurality of well regions 30 and a plurality of second pillar regions 11 (second lower region 11L).

[0308] In the semiconductor device 1B, the multiple contact regions 34 are formed in a region that overlaps with the multiple first pillar regions 8 in the thickness direction Z via a part of the body region 22 (i.e., a region that overlaps with the multiple second pillar regions 11).

[0309] In this embodiment, the multiple contact regions 34 are formed at intervals in the first direction X from the multiple first pillar regions 8 in a plan view, and do not overlap with the first pillar regions 8 in the thickness direction Z. Of course, the multiple contact regions 34 may have portions that overlap with the first pillar regions 8 in the thickness direction Z.

[0310] In this configuration, the multiple contact regions 34 overlap with the multiple second pillar regions 11 in a one-to-one correspondence in the thickness direction Z. The multiple contact regions 34 are electrically connected to the multiple second pillar regions 11 via the body region 22. In other words, the multiple contact regions 34 are electrically connected to the multiple well regions 30 via the multiple second pillar regions 11.

[0311] In this form, the plurality of contact regions 34 are formed at a distance from the plurality of gate structures 25 in the second direction Y and are surrounded by the corresponding source regions 33. That is, the plurality of contact regions 34 face the plurality of gate structures 25 through a part of the corresponding source regions 33 in the second direction Y.

[0312] The plurality of contact regions 34 are formed deeper than the plurality of source regions 33 and have bottoms located on the bottom side of the body region 22 rather than the bottoms of the plurality of source regions 33. The plurality of contact regions 34 may be formed shallower than the plurality of source regions 33.

[0313] The plurality of contact regions 34 are formed at a distance from the depth position of the middle part of the plurality of gate structures 25 toward the first main surface 3 side. The plurality of contact regions 34 may have portions located on the bottom wall side of the plurality of gate structures 25 with respect to the depth position of the middle part of the plurality of gate structures 25.

[0314] The semiconductor device 1B includes a plurality of n-type cap regions 23 formed in the second semiconductor layer 7 in the inner part (active region 20) of the first main surface 3. The cap region 23 may be referred to as an "impurity region", a "high-concentration region", or the like.

[0315] The cap region 23 has an n-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 7. The n-type impurity concentration of the cap region 23 is higher than the p-type impurity concentration of the body region 22. The n-type impurity concentration of the cap region 23 may be higher or lower than the p-type impurity concentration of the well region 30.

[0316] The n-type impurity concentration of the cap region 23 is higher than the n-type impurity concentration of the first pillar region 8. The n-type impurity concentration of the cap region 23 is higher than the p-type impurity concentration of the second pillar region 11. The n-type impurity concentration of the cap region 23 may be higher or lower than the n-type impurity concentration of the source region 33.

[0317] The plurality of cap regions 23 are respectively formed in a region below the body region 22 between the plurality of gate structures 25. The plurality of cap regions 23 are formed at an interval from the depth position of the bottom wall of the plurality of gate structures 25 toward the first main surface 3 side. The plurality of cap regions 23 include a plurality of first cap regions 23A and a plurality of second cap regions 23B.

[0318] The plurality of first cap regions 23A are formed at intervals in the first direction X following the extending direction of the plurality of gate structures 25, and are adjacent to the plurality of gate structures 25 in the second direction Y. The plurality of first cap regions 23A are respectively formed in a one-to-one correspondence with the plurality of first pillar regions 8. The plurality of first cap regions 23A are connected to the first upper regions 8U of the plurality of first pillar regions 8, and increase the n-type impurity concentration of the first upper regions 8U.

[0319] The plurality of first cap regions 23A are located on the bottom wall side of the trench 26 with respect to the electrode surface of the buried electrode 28, and face the buried electrode 28 through the insulating film 27. The plurality of first cap regions 23A face the plurality of source regions 33 through a part of the body region 22 in the thickness direction Z. Thereby, the plurality of first cap regions 23A and the plurality of source regions 33 together form a first channel Ch1 along the plurality of gate structures 25 in the body region 22.

[0320] The plurality of second cap regions 23B are respectively interposed in regions between the plurality of first cap regions 23A adjacent to each other in the first direction X in the region between the plurality of gate structures 25. The plurality of second cap regions 23B extend in a strip shape in the first direction X along the side walls of the corresponding gate structures 25.

[0321] The plurality of second cap regions 23B are formed at intervals from each other in the second direction Y in a cross-sectional view along the second direction Y, and face each other in the second direction Y through a part of the corresponding second pillar regions 11 (see FIG. 9).

[0322] In other words, the multiple second cap regions 23B are interposed in the region between the side wall of the corresponding gate structure 25 and the corresponding second pillar region 11 in a cross-sectional view along the second direction Y (see Figure 9). Furthermore, the multiple second cap regions 23B are interposed in the thickness direction Z between the body region 22 and the corresponding second pillar region 11 in a cross-sectional view along the second direction Y (see Figure 9).

[0323] The multiple second cap regions 23B are each formed in the portion of the second upper region 11U of the multiple second pillar regions 11 that is interposed between the multiple first cap regions 23A. In this embodiment, the multiple second cap regions 23B are drawn out in a strip shape in the first direction X along the side walls of the multiple gate structures 25 from the multiple first cap regions 23A, and replace the conductivity type of a part of the second upper region 11U of the multiple second pillar regions 11 from p type to n type.

[0324] The multiple second cap regions 23B face the multiple source regions 33 in the thickness direction Z via a portion of the body region 22. Thus, the multiple second cap regions 23B, together with the multiple source regions 33, form a second channel Ch2 within the body region 22 along the multiple gate structures 25. The multiple second cap regions 23B may also have portions facing the multiple contact regions 34 in the thickness direction Z via a portion of the body region 22.

[0325] In this way, the multiple cap regions 23 extend the current path connecting the multiple first pillar regions 8 and the multiple source regions 33 through the first channel Ch1 originating from the first cap region 23A and the second channel Ch2 originating from the second cap region 23B.

[0326] (3) Figure 18, which is a structural diagram of the semiconductor device 1C, is an enlarged plan view showing a key part of the first main surface 3 of the semiconductor device 1C according to the third embodiment. Figure 19 is a cross-sectional view taken along the line XIX-XIX shown in Figure 18. Figure 20 is a cross-sectional view of the outer peripheral region 21 of the semiconductor device 1C.

[0327] Referring to Figures 18 to 20, semiconductor device 1C is a semiconductor switching device having an insulated gate type transistor structure Tr as an example of a device structure (functional device). The transistor structure Tr has a planar gate type vertical structure.

[0328] In the semiconductor device 1C, the multiple body regions 22 are formed in the inner part of the first main surface 3, spaced apart from the periphery of the first main surface 3, and are not formed in the outer peripheral region 21. In this configuration, the multiple body regions 22 are formed spaced apart in the first direction X and extend in a strip-like manner in the second direction Y. The multiple body regions 22 are arranged in a stripe-like pattern extending in the second direction Y. The direction of extension of the multiple body regions 22 coincides with the off-direction of the SiC single crystal. The multiple body regions 22 may also be formed spaced apart in the second direction Y and extend in a strip-like manner in the first direction X.

[0329] The semiconductor device 1C includes a plurality of n-type source regions 33, each formed on the surface of a plurality of body regions 22. The plurality of source regions 33 are formed with a gap between them, with respect to a first direction X, from both edges of the corresponding body region 22 to the inner part of the corresponding body region 22.

[0330] Multiple source regions 33 are formed at intervals in the first direction X on the surface of the corresponding body region 22 and extend in a strip-like manner in the second direction Y. The multiple source regions 33 may also be formed at intervals in the second direction Y, following the extending direction of the corresponding body region 22.

[0331] Multiple source regions 33 are formed with a gap inward from both ends of the corresponding body region 22 with respect to the second direction Y. Multiple source regions 33 are formed with a gap from the bottom of the corresponding body region 22 toward the first main surface 3, and face the second semiconductor layer 7 with a portion of the corresponding body region 22 in between.

[0332] The semiconductor device 1C includes a plurality of p-type contact regions 34 formed in a region different from the plurality of source regions 33 on the surface of the corresponding body region 22. The plurality of contact regions 34 are interposed in the region between the plurality of source regions 33 on the surface of the corresponding body region 22 and are electrically connected to the body region 22.

[0333] Multiple contact regions 34 extend in a strip-like shape along the extending direction of the corresponding body region 22 (source region 33). With respect to the second direction Y, the multiple contact regions 34 are formed with a gap inward from both ends of the corresponding body region 22. The multiple contact regions 34 are formed with a gap from the bottom of the corresponding body region 22 toward the first main surface 3 and face the second semiconductor layer 7 across a portion of the corresponding body region 22.

[0334] In this embodiment, the contact area 34 has a width less than the width of the multiple source areas 33. The width of the contact area 34 may be greater than the width of the multiple source areas 33. In this embodiment, the multiple contact areas 34 have a thickness greater than the thickness of the multiple source areas 33 and have a bottom that is located on the bottom side of the body area 22 than the bottom of the multiple source areas 33.

[0335] In the semiconductor device 1C, the multiple well regions 30 are formed within the second semiconductor layer 7, spaced apart from each other in the horizontal direction (first direction X), in regions below (specifically directly below) the multiple body regions 22. The multiple well regions 30 are formed in the thickness range between the first semiconductor layer 6 and the bottom of the multiple body regions 22, and overlap with the multiple body regions 22 in a one-to-one correspondence in the thickness direction.

[0336] The multiple well regions 30 each extend in a strip-like manner in the second direction Y, following the extension direction of the corresponding body region 22 in a plan view. The multiple well regions 30 are arranged in a stripe-like pattern extending in the second direction Y in a plan view. The extension direction of the multiple well regions 30 coincides with the off-direction of the SiC single crystal.

[0337] With respect to the second direction Y, the ends of the multiple well regions 30 may be located on the inner side of the multiple body regions 22 with respect to the ends of the multiple body regions 22, or they may be located on the peripheral side of the active region 20. The multiple well regions 30 may extend in the first direction X according to the extending direction of the multiple body regions 22. In this case, the multiple well regions 30 intersect (specifically orthogonally) in the off direction.

[0338] Each of the multiple well regions 30 has a width less than the width of the corresponding body region 22. Each of the multiple well regions 30 is formed with a gap between both edges of the corresponding body region 22 and the inner part of the corresponding body. The width of the multiple well regions 30 may be approximately equal to the width of the corresponding body region 22. The width of the multiple well regions 30 may be greater than the width of the corresponding body region 22.

[0339] The upper ends of the multiple well regions 30 are each connected to the corresponding body region 22. The upper ends of the multiple well regions 30 may be formed with a gap between them and the corresponding body region 22 towards the first semiconductor layer 6.

[0340] The bottoms of the multiple well regions 30 may be located on the bottom wall side of the multiple body regions 22 or on the first semiconductor layer 6 side with respect to the depth position of the intermediate portion of the second semiconductor layer 7. The multiple well regions 30 may form a superjunction structure together with the second semiconductor layer 7 in the region below the multiple body regions 22. In this case, the depletion layers originating from the multiple well regions 30 are connected to each other in the region between the multiple well regions 30.

[0341] In this embodiment, the depth of the well region 30 relative to the bottom of the body region 22 is greater than the depth of the body region 22 relative to the first main surface 3. The depth of the well region 30 may be 0.5 μm or more and 5 μm or less. The depth of the well region 30 may have a value that falls within at least one of the following ranges: 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0342] The semiconductor device 1C includes a plurality of n-type surface drift regions 51 formed on the surface of the first main surface 3. In this embodiment, each of the plurality of surface drift regions 51 consists of a part of the second semiconductor layer 7. Of course, the plurality of surface drift regions 51 may have an n-type impurity concentration higher than that of the second semiconductor layer 7, or they may have an n-type impurity concentration lower than that of the second semiconductor layer 7.

[0343] Multiple surface drift regions 51 are each demarcated in the region between multiple adjacent body regions 22 on the surface of the second semiconductor layer 7. In other words, the multiple surface drift regions 51 are arranged with spacing in the first direction X and extend in a strip-like manner in the second direction Y. That is, the multiple surface drift regions 51 are formed in a stripe-like shape extending in the second direction Y.

[0344] The semiconductor device 1C includes a plurality of p-type channel regions 52 formed on the surface layer of the first main surface 3. The plurality of channel regions 52 are partitioned in the area between a plurality of source regions 33 and a plurality of surface drift regions 51 (second semiconductor layer 7) on the surface layer of a plurality of body regions 22. The plurality of channel regions 52 form current paths that extend horizontally along the first main surface 3.

[0345] The semiconductor device 1C includes a plurality of planar-type (planar electrode-type) gate structures 55 arranged on the first main surface 3 in the active region 20. The plurality of gate structures 55 are arranged at intervals in the first direction X and each extends in a strip-like manner in the second direction Y. The plurality of gate structures 55 are arranged in a stripe-like manner extending in the second direction Y. The direction of extension of the plurality of gate structures 55 coincides with the off-direction of the SiC single crystal.

[0346] Each of the multiple gate structures 55 is positioned on at least one channel region 52 (the peripheral edge of the body region 22). Each of the multiple gate structures 55 covers at least one peripheral edge of the body region 22, at least one source region 33, and one surface drift region 51.

[0347] In this form, the plurality of gate structures 55 straddle the peripheries of two adjacent body regions 22 across one surface drift region 51 and cover the plurality of channel regions 52. Specifically, the plurality of gate structures 55 straddle the source regions 33 of the body region 22 on one side and the source regions 33 of the body region 22 on the other side, covering the two source regions 33, one surface drift region 51, and two channel regions 52.

[0348] The plurality of gate structures 55 each have a stacked structure including a planar insulating film 56 and a planar electrode 57. The planar insulating film 56 is referred to as a "gate insulating film", and the planar electrode 57 may be referred to as a "gate electrode" or a "planar gate electrode".

[0349] The planar insulating film 56 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this form, the planar insulating film 56 has a single-layer structure made of a silicon oxide film. The planar insulating film 56 preferably includes a silicon oxide film containing an oxide of the second semiconductor layer 7.

[0350] The planar insulating film 56 covers the first main surface 3 in a film shape. The planar insulating film 56 extends in a strip shape in the second direction Y. The planar insulating film 56 is disposed on at least one channel region 52 (the periphery of the body region 22). The planar insulating film 56 covers the periphery of at least one body region 22, at least one source region 33, and one surface drift region 51, respectively.

[0351] In this form, the planar insulating film 56 straddle the peripheries of two adjacent body regions 22 across one surface drift region 51 and cover the plurality of channel regions 52. Specifically, the planar insulating film 56 straddle the source regions 33 of the body region 22 on one side and the source regions 33 of the body region 22 on the other side, covering the two source regions 33, one surface drift region 51, and two channel regions 52.

[0352] The planar electrode 57 is placed on the planar insulating film 56. A gate potential is applied to the planar electrode 57 as a control potential. The planar electrode 57 may contain either or both of p-type conductive polysilicon and n-type conductive polysilicon.

[0353] The planar electrode 57 covers the first main surface 3 in a film-like manner via the planar insulating film 56 and faces at least one channel region 52 (periphery of the body region 22). The planar electrode 57 extends in a strip shape in the second direction Y. In this embodiment, the planar electrode 57 is formed with a gap inward from both ends of the planar insulating film 56 with respect to the second direction Y, exposing both ends of the planar insulating film 56.

[0354] The planar electrode 57 covers the peripheral edge of at least one body region 22, at least one source region 33, and one surface drift region 51 via the planar insulating film 56.

[0355] In this embodiment, the planar electrode 57 spans the periphery of two adjacent body regions 22 across one surface drift region 51 and faces multiple channel regions 52 via the planar insulating film 56. Specifically, the planar electrode 57 spans the source region 33 of one body region 22 and the source region 33 of the other body region 22 and faces two source regions 33, one surface drift region 51, and two channel regions 52 via the planar insulating film 56.

[0356] The semiconductor device 1C, like the semiconductor device 1A, includes a p-type outer well region 35 formed on the surface layer of the first main surface 3 in the outer peripheral region 21 (periphery of the first main surface 3). The outer well region 35 has a p-type impurity concentration lower than that of the contact region 34.

[0357] The p-type impurity concentration in the outer well region 35 may be approximately equal to the p-type impurity concentration in the body region 22. Of course, the p-type impurity concentration in the outer well region 35 may be less than the p-type impurity concentration in the body region 22, or it may be higher than the p-type impurity concentration in the body region 22.

[0358] The outer well region 35 is formed on the surface of the second semiconductor layer 7, similar to the case of semiconductor device 1A. The outer well region 35 extends in layers along the first main surface 3. In this embodiment, the inner edge of the outer well region 35 is connected to a plurality of body regions 22 in the portion extending in the first direction X. The inner edge of the outer well region 35 may also be connected to a plurality of well regions 30.

[0359] The inner edge of the outer well region 35 may be located on the inward side of the first main surface 3 than the ends of the multiple gate structures 55, or it may be located on the peripheral side of the first main surface 3 than the ends of the multiple gate structures 55. The outer edge of the outer well region 35 is formed at a distance from the periphery of the first main surface 3 and extends substantially parallel to the inner edge of the outer well region 35.

[0360] The outer well region 35 has a width greater than the width of the multiple body regions 22. The width of the outer well region 35 is in a direction perpendicular to the extension direction. Of course, the width of the outer well region 35 may be approximately equal to the width of the multiple body regions 22, or it may be less than the width of the multiple body regions 22.

[0361] The ratio of the width of the outer well region 35 to the width of the body region 22 may be between 1 and 50. The ratio of the width of the gate wiring 39 to the width of the planar electrode 57 may be between 1 and 50. The width ratio may have a value that falls within at least one of the following ranges: 1 to 10, 10 to 20, 20 to 30, 30 to 40, and 40 to 50. For other details of the outer well region 35, the above description applies.

[0362] The semiconductor device 1C, like the semiconductor device 1A, includes a p-type outer contact region 36 formed on the surface of the outer well region 35 and one or more (in this embodiment, more) p-type field regions 37. The description of the outer contact region 36 and the multiple field regions 37 is as described above.

[0363] The semiconductor device 1C, like the semiconductor device 1A, includes a main surface insulating film 38 that selectively covers the first main surface 3. The main surface insulating film 38 selectively covers the first main surface 3 in the active region 20 and the peripheral region 21. The main surface insulating film 38 covers the first main surface 3 in a film-like manner in the active region 20 and is connected to a plurality of planar insulating films 56. The main surface insulating film 38 is formed integrally with the plurality of planar insulating films 56, and together with the plurality of planar insulating films 56, forms a single insulating film.

[0364] The main surface insulating film 38 covers the outer well region 35, the outer contact region 36, and a plurality of field regions 37 in the outer peripheral region 21. The main surface insulating film 38 is continuous with the first to fourth side surfaces 5A to 5D. The main surface insulating film 38 may be formed with an inward gap from the first to fourth side surfaces 5A to 5D, exposing the peripheral edge of the first main surface 3.

[0365] The semiconductor device 1C, like the semiconductor device 1A, includes one or more (one in this embodiment) gate wirings 39 arranged on the first main surface 3 in the outer peripheral region 21. The gate wirings 39 apply gate potentials to a plurality of gate structures 55.

[0366] The gate wiring 39 may contain either or both of p-type conductive polysilicon and n-type conductive polysilicon. Preferably, the gate wiring 39 has the same conductivity type as the planar electrode 57. The gate wiring 39 has a thickness approximately equal to the thickness of the planar electrode 57. The thickness of the gate wiring 39 may be greater than or less than the thickness of the planar electrode 57.

[0367] The gate wiring 39 is arranged on the main surface insulating film 38. The gate wiring 39 is selectively routed on the main surface insulating film 38 from the periphery of the first main surface 3 toward the multiple gate structures 55 with spacing between them. The gate wiring 39 extends in a strip shape along the multiple gate structures 55. The gate wiring 39 has a portion that extends in a strip shape in a first direction X and a portion that extends in a strip shape in a second direction Y.

[0368] In this embodiment, the gate wiring 39 is formed as an endless polygonal ring (for example, a quadrangular ring) having four sides parallel to the periphery of the first main surface 3, and surrounds a plurality of gate structures 55 (active regions 20). Of course, the gate wiring 39 may also be formed as an ended strip. The gate wiring 39 may have an edge portion that connects a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in an arc shape (preferably a quarter-circular arc shape) in a plan view.

[0369] The gate wiring 39 has an inner edge portion on the inner side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the gate wiring 39 is mechanically and electrically connected to a plurality of planar electrodes 57 (gate structure 55) in the portion extending in the first direction X. In this embodiment, the gate wiring 39 is formed integrally with the plurality of planar electrodes 57.

[0370] The inner edge of the gate wiring 39 is formed with a gap between it and the outer edge of the outer well region 35 (the multiple body regions 22). In other words, the inner edge of the gate wiring 39 is formed with a gap between it and the multiple source regions 33 and the multiple contact regions 34, and does not face the multiple source regions 33 and the multiple contact regions 34 across the main surface insulating film 38.

[0371] The outer edge of the gate wiring 39 is positioned at a distance from the innermost field region 37 toward the active region 20, and does not face the field region 37 across the main surface insulating film 38. With this configuration, shielding of the electric field dispersion path by the gate wiring 39 is suppressed, and the electric field (electric field lines) is appropriately dispersed by the multiple field regions 37.

[0372] The outer edge of the gate wiring 39 is formed with a gap between it and the outer edge of the outer well region 35, towards the gate structure 55. The outer edge of the gate wiring 39 is formed with a gap between it and the inner edge of the outer contact region 36, towards the gate structure 55. The outer edge of the gate wiring 39 may be located on top of the outer contact region 36.

[0373] The gate wiring 39 has a width less than the width of the outer well region 35 and is positioned on the outer well region 35 at a distance from the inner and outer edges of the outer well region 35. The width of the gate wiring 39 is in the direction perpendicular to the extending direction. The width of the gate wiring 39 is greater than the width of the planar electrode 57. The width of the gate wiring 39 may be approximately equal to the width of the planar electrode 57, or it may be less than the width of the planar electrode 57.

[0374] The ratio of the width of the gate wiring 39 to the width of the planar electrode 57 may be between 1 and 50. The ratio of the widths may be a value that falls within at least one of the following ranges: 1 to 10, 10 to 20, 20 to 30, 30 to 40, and 40 to 50.

[0375] The semiconductor device 1C, like the semiconductor device 1A, includes an interlayer film 10 that selectively covers the first main surface 3 in the active region 20 and the peripheral region 21. The interlayer film 10 covers a plurality of gate structures 55 in the active region 20. Specifically, the interlayer film 10 covers a plurality of planar insulating films 56 and a plurality of planar electrodes 57, and electrically insulates the plurality of planar electrodes 57.

[0376] The interlayer film 10 covers the outer well region 35, the outer contact region 36, and a plurality of field regions 37 via the main surface insulating film 38 in the outer peripheral region 21. The interlayer film 10 directly covers the gate wiring 39 in the outer peripheral region 21. For other details of the interlayer film 10, the above description applies.

[0377] The semiconductor device 1C, like the semiconductor device 1A, includes a plurality of source openings 40, a plurality of gate openings 41, and an outer opening 42 formed in the interlayer film 10. The description of the plurality of gate openings 41 and outer openings 42 is as described above.

[0378] Multiple source openings 40 are formed in a one-to-one correspondence between the regions between the multiple planar electrodes 57, and each extends in a strip shape in the second direction Y, following the direction of extension of the multiple planar electrodes 57. Multiple source openings 40 penetrate the planar insulating film 56 and the interlayer film 10, exposing multiple source regions 33 and multiple contact regions 34, respectively. Multiple source openings 40 may each have an arc-shaped curved opening end.

[0379] Multiple source openings 40 may be formed in a one-to-many correspondence in the region between multiple planar electrodes 57. In this case, the multiple source openings 40 may be formed at intervals following the extending direction of the multiple planar electrodes 57. In this case, the multiple source openings 40 may be formed in a square, rectangular (strip-shaped), circular, or the like in a plan view.

[0380] (4) Figure 21, which is a structural diagram of semiconductor device 1D, is a cross-sectional view showing semiconductor device 1D according to the fourth embodiment. Referring to Figure 21, semiconductor device 1D has a configuration in which the well region 30 is removed from semiconductor device 1C. This configuration also produces the same effects as those of semiconductor device 1C.

[0381] Sections (5) to (15) below describe the characteristics of each part of the semiconductor device applicable to semiconductor devices 1A to 1D. If there is any overlap between the above description of the structure of semiconductor devices 1A to 1D and the following description of the characteristics of each part, the characteristics described below may be applied preferentially. For example, the concentration profiles of various impurity regions, the layer structures of various impurity regions, and the characteristics of the semiconductor device described below may be applied preferentially to each part of semiconductor devices 1A to 1D.

[0382] (5) Explanation of the impurity concentration profile in the channel region 50 Figure 22 is a cross-sectional view showing the periphery of the channel region 50 of the semiconductor device 1E. Figure 22 discloses an MIS (Metal-Insulator-Semiconductor) transistor structure Tr to explain the concentration distribution of n-type and p-type impurities in the channel region 50 of the semiconductor device 1E.

[0383] Referring to Figure 22, semiconductor device 1E is a SiC semiconductor switching device, similar to semiconductor devices 1A to 1D described above. Semiconductor device 1E includes an n-type source region and an n-type drain region (drift region), which are not shown, and the source-drain (S-D) is conductive through a channel formed in the channel region 50.

[0384] The semiconductor device 1E includes a semiconductor layer 53 and a control electrode 58 facing each other with an insulating film 54 in between. By applying an appropriate voltage to the control electrode 58, a channel is formed in the channel region 50 near the interface between the semiconductor layer 53 and the insulating film 54.

[0385] The semiconductor layer 53 corresponds to the second semiconductor layer 7 (SiC layer) mentioned above, and in this configuration, it consists of a SiC semiconductor layer.

[0386] The insulating film 54 is formed on the surface of the semiconductor layer 53 so as to be in contact with the surface of the semiconductor layer 53. The surface of the semiconductor layer 53 on which the insulating film 54 is formed is the exposed surface of the SiC crystal structure constituting the semiconductor layer 53, and may be referred to as the "SiC surface 59". The SiC surface 59 may be, for example, an exposed surface of SiC. The SiC surface 59 may correspond to, for example, the first main surface 3, the second main surface 4, the first to fourth side surfaces 5A to 5D, and the walls (side walls and bottom walls) of the trench 26 in the semiconductor devices 1A to 1D described above.

[0387] The insulating film 54 may correspond to the insulating film 27 and the planar insulating film 56 described above. The insulating film 54 may contain at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The insulating film 54 forms an interface with the SiC surface 59. This interface (insulating film / SiC interface) may be referred to as the SiC interface 60.

[0388] The control electrode 58 is formed on the insulating film 54 and faces the semiconductor layer 53 via the insulating film 54. The control electrode 58 may correspond to the embedded electrode 28 and the planar electrode 57 described above. The control electrode 58 may contain either or both of p-type conductive polysilicon and n-type conductive polysilicon.

[0389] The channel region 50 is a region where a channel is formed near the SiC interface 60. The channel region 50 is a region where an inversion layer is formed by applying a voltage to the control electrode 58, and both sides of the control electrode 58 (source-drain) in the direction along the channel length CL are electrically connected through the inversion layer formed in the channel region 50.

[0390] The channel region 50 includes a p-type semiconductor region 61 and an n-type interface semiconductor region 62. The semiconductor region 61 corresponds to a part of the body region 22 described above and is formed on the surface of the semiconductor layer 53. The interface semiconductor region 62 is located between the semiconductor region 61 and the insulating film 54. In this embodiment, the interface semiconductor region 62 may be exposed from the SiC surface 59 and form a SiC interface 60 between it and the insulating film 54. The semiconductor region 61 is covered by the insulating film 54 via the interface semiconductor region 62.

[0391] The thickness CT1 of the channel region 50 may be, for example, 1 nm or more and 20 nm or less from the SiC interface 60. The thickness CT1 of the channel region 50 may have a value that falls within at least one of the following ranges from the SiC interface 60: 1 nm or more and 5 nm or less, 1 nm or more and 10 nm or less, 1 nm or more and 15 nm or less, 3 nm or more and 8 nm or less, 3 nm or more and 10 nm or less, 3 nm or more and 15 nm or less, 5 nm or more and 8 nm or less, 5 nm or more and 10 nm or less, and 5 nm or more and 15 nm or less. Preferably, the thickness CT1 of the channel region 50 is 1 nm or more and 10 nm or less.

[0392] The thickness CT2 of the interface semiconductor region 62 may be, for example, 0 nm to 50 nm from the SiC interface 60. The thickness CT2 of the interface semiconductor region 62 may have a value that falls within at least one of the following ranges from 0 nm to 10 nm, 0 nm to 20 nm, 0 nm to 30 nm, and 0 nm to 40 nm from the SiC interface 60. Preferably, the thickness CT2 of the interface semiconductor region 62 is 5 nm to 20 nm. Depending on the size of the thickness CT2 of the interface semiconductor region 62, the inversion layer may not be formed in the semiconductor region 61 (body region 22), but only in the interface semiconductor region 62. In this case, the channel region 50 may be the interface semiconductor region 62.

[0393] The thickness CT3 of the semiconductor region 61 may be, for example, 0 nm or more and 20 nm or less from the interface 63 with the interface semiconductor region 62. The thickness CT3 of the semiconductor region 61 may have a value that falls within at least one of the following ranges from the interface 63: 0 nm or more and 5 nm or less, 0 nm or more and 10 nm or less, 0 nm or more and 15 nm or less, 3 nm or more and 8 nm or less, 3 nm or more and 10 nm or less, 3 nm or more and 15 nm or less, 5 nm or more and 8 nm or less, 5 nm or more and 10 nm or less, and 5 nm or more and 15 nm or less. Preferably, the thickness CT3 of the semiconductor region 61 is 0 nm or more and 10 nm or less.

[0394] Next, the distribution of n-type impurity concentrations (donor concentration) and p-type impurity concentrations (acceptor concentration) within the channel region 50 of the semiconductor device 1E was measured. Figures 23 to 26 show the measurement results. The concentration distribution measurement samples include Sample 1, Sample 2, Sample 3, and Sample 4. Samples 1 to 3 are the implementation samples for elucidating the concentration distribution in the channel region 50, while Sample 4 is a reference sample for comparison with Samples 1 to 3. Samples 1 to 3 were fabricated on a common SiC wafer and have the same device structure. The difference between Samples 1 to 3 is the introduction conditions for n-type impurity ions.

[0395] Figure 23 shows the concentration distribution of the channel region 50 for samples 1 to 3. Figure 24 shows the concentration distribution of the channel region 50 for sample 1. Figure 25 shows the concentration distribution of the channel region 50 for sample 2. Figure 26 shows the concentration distribution of the channel region 50 for sample 4.

[0396] In Figures 23 to 26, the horizontal axis represents the depth (nm) from the SiC interface 60, and the vertical axis represents the n-type and p-type impurity concentrations. Each profile shown in Figures 23 to 26 is a graph where the depth from the SiC interface 60 is the horizontal axis (x-axis), and the logarithmic values ​​of the n-type and p-type impurity concentrations are the vertical axis (y-axis).

[0397] Furthermore, there are differences in the calculation method for the numerical values ​​that form the basis of the line-shaped profiles showing the concentration distribution between Figure 23 and Figures 24-26.

[0398] The profile in Figure 23 shows the distribution of donor and acceptor concentrations based on the capacitance-voltage characteristics (C-V characteristics) between the control electrode 58 and the semiconductor region 61. For example, referring to Figure 22, the profile may be based on the C-V characteristics obtained when a voltage V2 is applied to the control electrode 58 and a voltage V1 is applied to the semiconductor region 61. By creating a profile from plots of donor and acceptor concentrations converted from the C-V characteristics, the activated donor and acceptor concentrations in the semiconductor layer 53 can be calculated with accuracy. On the other hand, the profiles in Figures 24 to 26 are created from plots of donor and acceptor concentrations based on secondary ion mass spectrometry (SIMS) results.

[0399] The donor concentrations shown in the profiles of Figures 23 to 26 represent N as a representative example, among N, P, As, Sb, and S. When multiple types of n-type impurities are contained in the channel region 50, the distribution of each n-type impurity concentration may be shown in mutually independent profiles. The acceptor concentrations shown in the profiles of Figures 23 to 26 represent Al as a representative example, among B, Al, Ga, and In. When multiple types of p-type impurities are contained in the channel region 50, the distribution of each p-type impurity concentration may be shown in mutually independent profiles.

[0400] Referring to Figure 23, the impurity concentration profiles of Sample 1, Sample 2, and Sample 3 based on the C-V characteristic results are explained. In Figure 23, the thick solid line is profile P1 showing the distribution of donor concentrations in the channel region 50 of Sample 1, the thick dashed line is profile P2 showing the distribution of donor concentrations in the channel region 50 of Sample 2, and the thick dashed line is profile P3 showing the distribution of donor concentrations in the channel region 50 of Sample 3. The thin solid line is profile CP of the acceptor concentration (background concentration) in the channel region 50 common to Samples 1 to 3.

[0401] Referring to Figure 23, profiles P1, P2, and P3 may be formed in a roughly mountain-like shape with peaks (maximum values ​​M1 to M3) at a certain depth from the SiC interface 60. Maximum value M1 is the peak of profile P1, maximum value M2 is the peak of profile P2, and maximum value M3 is the peak of profile P3.

[0402] In this case, profiles P1, P2, and P3 may each have a portion (increasing portion 65) where the donor concentration gradually increases from the SiC interface 60 side toward the maximum values ​​M1 to M3, and a portion (decreasing portion 66) where the donor concentration gradually decreases in the depth direction from the maximum values ​​M1 to M3. In other words, profiles P1, P2, and P3 may gradually decrease from the maximum values ​​M1 to M3 toward both the SiC interface 60 side and the opposite side. Profiles P1, P2, and P3 further include a concentration transition portion 67, which is a convex portion containing a series of concentration changes (inflection points) where the donor concentration changes from increasing (increasing trend) to decreasing (decreasing trend) across the maximum values ​​M1 to M3.

[0403] The maximum values ​​M1 to M3 are 1 × 10⁻⁶ in this form. １８ cm －３ The above 1 x 10 ２０ cm －３ The following is preferable: The maximum values ​​M1 to M3 are 1 × 10⁻⁶ １８ cm －３ The above 1 x 10 １９ cm －３ The following, and 1 x 10 １９ cm －３ The above 1 x 10 ２０ cm －３ It may have a value that falls within at least one of the following ranges.

[0404] In this embodiment, the maximum values ​​M1 to M3 are preferably located in the range from the SiC interface 60 to a depth of 20 nm. The maximum values ​​M1 to M3 may also be located in the range from the SiC interface 60 to a depth of 1 nm or more and 20 nm or less. The maximum values ​​M1 to M3 may have values ​​that belong to at least one of the following ranges from the SiC interface 60 to a depth of 3 nm or more and 20 nm or less, 3 nm or more and 15 nm or less, 3 nm or more and 10 nm or less, 5 nm or more and 20 nm or less, 5 nm or more and 15 nm or less, and 5 nm or more and 10 nm or less. The concentration transition section 67 including the maximum values ​​M1 to M3 may, for example, be in the range of 0.5 nm or more and 5 nm or less that spans the maximum values ​​M1 to M3 vertically in the depth direction.

[0405] The gradually increasing portion 65 may be in a range of 0.5 nm to 5 nm in the depth direction from the SiC interface 60. The range of donor concentrations in the gradually increasing portion 65 is smaller than the range of donor concentrations in the concentration transition portion 67.

[0406] Referring to Figure 23, profile CP may be formed in a roughly mountain shape with a peak (maximum value M4) at a certain depth from the SiC interface 60. Profile CP gradually increases in the depth direction from the SiC interface 60 side and intersects profiles P1, P2, and P3 at the tapering portion 66. The maximum value M4 is located at a depth greater than the intersection portion 68. The intersection portion 68 may be, for example, at a depth of 500 nm or less from the SiC interface 60.

[0407] The maximum value M4 in this form is 1 × 10⁻⁶ １７ cm －３ The above 1 x 10 １８ cm －３ The following is preferable: In this embodiment, the maximum value M4 is preferably located at a depth of 20 nm or more from the depth positions of the maximum values ​​M1 to M3.

[0408] Referring to Figure 23, at the intersection 68 between profiles P1, P2, P3 and profile CP, the donor concentration exceeds the acceptor concentration on the SiC interface 60 side. On the other hand, on the opposite side of the SiC interface 60 from the intersection 68 (the deeper side), the acceptor concentration exceeds the donor concentration.

[0409] Thus, n-type and p-type impurities are mixed throughout the channel region 50 in the depth direction from the SiC interface 60. However, based on the distribution of impurity concentrations, the channel region 50 may be distinguished into an interface semiconductor region 62 and a semiconductor region 61 (body region 22) as shown in Figure 22. For example, the depth position of the intersection 68 may be defined as the boundary 69, and the region containing the maximum values ​​M1 to M3 on the shallower side of the boundary 69 may be the interface semiconductor region 62, while the area on the deeper side of the boundary 69 may be the semiconductor region 61 (body region 22). Note that in Figure 23, for clarity, only the boundary 69 corresponding to the intersection 68 related to profile P1 is shown among the intersections 68 of profiles P1, P2, P3 and profile CP.

[0410] Next, with reference to Figure 24, the impurity concentration profile of Sample 1 based on the SIMS results will be explained. In Figure 24, the thick solid line is profile P1A, which shows the distribution of donor concentrations in the channel region 50 of Sample 1, and the thick dashed line is profile P1B, which shows the distribution of donor concentrations in the channel region 50 of Sample 1. The thin solid line is profile CP, which shows the acceptor concentration (background concentration) in the channel region 50 of Sample 1.

[0411] Profiles P1A and P1B are both concentration profiles of Sample 1, but they exhibit different trajectories due to differences in the processing methods applied to Sample 1. Profile P1A is the profile of a sample in which NO heat treatment was performed after forming the interface semiconductor region 62 by epitaxial growth (see Figures 35D, 36B, 38C, and 39B) during the manufacturing process of Sample 1. On the other hand, profile P1B is the profile of a sample in which the NO heat treatment after the formation of the interface semiconductor region 62 was omitted.

[0412] Referring to Figure 24, profiles P1A and P1B were obtained by synthesizing profile SP, which shows an impurity concentration that decreases monotonically from the SiC interface 60, with profile P1 of Figure 23 having a maximum value M1. In Figure 24, the synthesis of profile SP results in a portion of the gradually increasing portion 65 of profile P1 being cut off. The cut portion of the gradually increasing portion 65 is shown as a dashed line in Figure 24.

[0413] In Figure 24, the reason why profiles P1A and P1B are shown, where profile SP is synthesized with profile P1, is that profiles P1A and P1B are based on SIMS results. In the SIMS measurement process, unintended elements may be detected, such as elements that are not actually contained in the channel region 50, or inert elements that are present but do not contribute to the device characteristics.

[0414] Figure 23 shows profile P1, in which only activated impurities were evaluated based on the C-V characteristics. In contrast, Figure 24 shows profile SP near the SiC interface 60, as unintended elements are detected. Furthermore, in sample 1, since N (nitrogen) is used as the n-type impurity concentration, in addition to N as an activated impurity, inert N introduced near the SiC interface 60 by NO heat treatment may also be detected. Therefore, the concentration distribution of profile P1A, in which NO heat treatment was performed, is relatively larger than that of profile P1B, in which NO heat treatment was omitted.

[0415] Furthermore, if an impurity other than N (for example, P, As, Sb, S, etc.) is used as the n-type impurity, the profile obtained based on the SIMS results may have the same trajectory as profile P1, which has a maximum value M1. Also, since profile CP has the same trajectory as the profile shown in Figure 23, its explanation is omitted here (the same applies to Figures 25 and 26).

[0416] Referring to Figure 24, the trajectories of profiles P1A and P1B will be explained in more detail. In the following explanation, "upper side" and "lower side" refer to the upper and lower sides of the paper in Figure 24, respectively, and represent the "high concentration side" and "low concentration side" of the vertical axis. Therefore, "up" and "down" refer to the "direction from the low concentration side to the high concentration side" and the "direction from the high concentration side to the low concentration side," respectively (the same applies when explaining profiles with inflection points).

[0417] Profiles P1A and P1B include an upper curved section 70 and a lower curved section 71. The upper curved section 70 slopes downward from the high-concentration side to the low-concentration side. In this embodiment, the upper curved section 70 is formed as an upper convex section having a first curvatured section 72 that is convex toward the low-concentration side. The lower curved section 71 slopes downward from the high-concentration side to the low-concentration side in a deeper region than the upper curved section 70. In this embodiment, the lower curved section 71 is formed as a lower convex section having a second curvatured section 73 that is convex toward the high-concentration side.

[0418] The upper curved section 70 and the lower curved section 71 are continuous via an inflection point IP1. The inflection point IP1 may be the point where the curvature of profiles P1A and P1B changes from the first curvature section 72 to the second curvature section 73 (or, in other words, from the second curvature section 73 to the first curvature section 72).

[0419] More specifically, the inflection point IP1 may be the point where the sign of the second derivative of the function representing the trajectory of the upper curved section 70 and the function representing the trajectory of the lower curved section 71 changes. In this embodiment, the sign of the second derivative of the upper curved section 70 is positive (+), and the sign of the second derivative of the lower curved section 71 is negative (-). Therefore, the depth position where this sign changes and the impurity concentration at that depth position may be the inflection point IP1. The second derivative of each function is, for example, d ２ log(Nd) / dt ２ This can be calculated using the formula (Nd = donor concentration, t = depth from SiC interface 60).

[0420] The inflection point IP1 is located at approximately the same depth as the maximum value M1 in Figure 23. In this configuration, the inflection point IP1 is 1 × 10⁻⁶ １８cm －３ It is preferably 1×10 ２０ cm －３ or less. The inflection point IP1 may have a value belonging to at least one of the ranges of 1×10 １８ cm －３ or more and 1×10 １９ cm －３ or less, and 1×10 １９ cm －３ or more and 1×10 ２０ cm －３ or less.

[0421] In this form, the inflection point IP1 is preferably arranged in the range from the SiC interface 60 to a depth of 20 nm. The inflection point IP1 may be arranged in the range from a depth of 1 nm or more and 20 nm or less from the SiC interface 60. The inflection point IP1 may have a value belonging to at least one of the ranges of from a depth of 3 nm or more and 20 nm or less, 3 nm or more and 15 nm or less, 3 nm or more and 10 nm or less, 5 nm or more and 20 nm or less, 5 nm or more and 15 nm or less, and 5 nm or more and 10 nm or less from the SiC interface 60.

[0422] Next, referring to FIG. 25, the impurity concentration profile of sample 2 based on the SIMS results will be described. In FIG. 25, the thick solid line is the profile P2A showing the distribution of the donor concentration in the channel region 50 of sample 1, and the thick dashed-dotted line is the profile P2B showing the distribution of the donor concentration in the channel region 50 of sample 2. The thin solid line is the profile CP of the acceptor concentration (background concentration) in the channel region 50 of sample 2.

[0423] Referring to FIG. 25, the profiles P2A and P2B are the impurity concentration profiles of sample 2 based on the SIMS results, similar to the profiles P1A and P1B in FIG. 24. Therefore, by synthesizing the profile SP showing the impurity concentration monotonically decreasing from the SiC interface 60 with the profile P2 in FIG. 23, it is drawn as a locus having an inflection point IP2. The inflection point IP2 is arranged at approximately the same depth position as the maximum value M2 in FIG. 23. Since the method of obtaining the inflection point IP2, the concentration, the depth, etc. are the same as those of the inflection point IP1, the description here is omitted.

[0424] Next, with reference to Figure 26, the impurity concentration profile of sample 4 based on the SIMS results will be explained. In Figure 26, the thick solid line is the profile P4 showing the distribution of donor concentrations in the channel region 50 of sample 4, and the thin solid line is the profile CP showing the acceptor concentration (background concentration) in the channel region 50 of sample 4.

[0425] Profile P4 is the profile of a sample in which, in the manufacturing process of sample 4, the step of forming the interfacial semiconductor region 62 by epitaxial growth (see Figures 35D, 36B, 38C, and 39B) described later was omitted, and the insulating film 54 was formed by thermal oxidation, followed by NO heat treatment.

[0426] Referring to Figure 26, profile P4, unlike profiles P1-P3, P1A, P1B, and P2A, P2B mentioned above, does not have any maximum values ​​or inflection points, and only shows an impurity concentration that decreases monotonically from the SiC interface 60. This is thought to be because profile P4 is based on the results of SIMS, and inert N was unintentionally detected during the SIMS measurement process.

[0427] Figure 26 shows that sample 4, manufactured using a process that omits the formation step of the interfacial semiconductor region 62 (see Figures 35D, 36B, 38C, and 39B), does not have a maximum value or inflection point due to activated n-type impurities in the range from the SiC interface 60 to a depth of 20 nm. Although there is an intersection 68 between profile P4 and profile CP, the region on the SiC interface 60 side of the intersection 68 does not have a maximum value or inflection point, and therefore does not correspond to the interfacial semiconductor region 62 shown in Figures 23 to 25.

[0428] (6) Application to Trench Gate Structure Figures 27 and 28 are cross-sectional views of the main part of a trench gate structure, showing an example in which the interface semiconductor region 62 of Figure 22 is applied to semiconductor device 1A. Figure 27 is an enlarged view of the area enclosed by the dashed line XXVII in Figure 4, and Figure 28 is an enlarged view of the area enclosed by the dashed line XXVIII in Figure 5.

[0429] The MIS structure of semiconductor device 1E in Figure 22 can be applied to the trench-type gate structure 25 of semiconductor device 1A. In Figure 22, the semiconductor layer 53 may correspond to the second semiconductor layer 7, the insulating film 54 may correspond to the insulating film 27, the control electrode 58 may correspond to the embedded electrode 28, the semiconductor region 61 may correspond to the body region 22, and the channel region 50 may correspond to the channel region 24.

[0430] Referring to Figures 27 and 28, the drift region 64, body region 22, and source region 33, which are part of the second semiconductor layer 7, are arranged in this order from the bottom of the trench 26 toward the first main surface 3.

[0431] The trench 26 has a side surface 74 and a bottom surface 75. The side surface 74 and bottom surface 75 are exposed surfaces of the SiC crystal structure constituting the second semiconductor layer 7 and correspond to the aforementioned SiC surface 59. The side surface 74 and bottom surface 75 are covered with an insulating film 27, and the insulating film 27 forms a SiC interface 60 with the SiC surface 59 (side surface 74 and bottom surface 75). In this embodiment, the SiC interface 60 includes a side interface 76 between the side surface 74 of the trench 26 and the insulating film 27, and a bottom interface 77 between the bottom surface 75 of the trench 26 and the insulating film 27.

[0432] The MIS structure of semiconductor device 1E in Figure 22 is selectively applied to the side interface 76 of the SiC interface 60, out of the side interface 76 and bottom interface 77. More specifically, as shown in Figure 27, an interface semiconductor region 62 is formed on the side interface 76, which is formed by a stacked structure of a drift region 64, a body region 22, and a source region 33. On the other hand, as shown in Figure 28, even on the side interface 76, an interface semiconductor region 62 is not formed on the side interface 76, which is formed by a stacked structure of a drift region 64, a body region 22, and a contact region 34.

[0433] Referring to Figure 27, the interface semiconductor region 62 spans the drift region 64, the body region 22, and the source region 33 in the depth direction of the trench 26. In this embodiment, the interface semiconductor region 62 is formed over the entire length of the side surface 74 of the trench 26, from the upper end to the lower end, and has an upper end 78 and a lower end 79 at the upper and lower ends of the side surface 74, respectively. The upper end 78 is located within the source region 33, and the lower end 79 is located within the drift region 64. Although not shown, the interface semiconductor region 62 may be selectively formed on the side surface 74 of the trench 26 formed by the body region 22, in the stacked structure of the drift region 64, the body region 22, and the source region 33.

[0434] (7) Application to Planar Gate Structure Figure 29 is a cross-sectional view of the main part of a planar gate structure, showing an example in which the interface semiconductor region 62 of Figure 22 is applied to semiconductor device 1C. Figure 29 is an enlarged view of the area enclosed by the dashed line XXIX in Figure 19.

[0435] The MIS structure of semiconductor device 1E in Figure 22 can be applied to the planar gate structure 55 of semiconductor device 1C. In Figure 22, the semiconductor layer 53 may correspond to the second semiconductor layer 7, the insulating film 54 may correspond to the planar insulating film 56, the control electrode 58 may correspond to the planar electrode 57, the semiconductor region 61 may correspond to the body region 22, and the channel region 50 may correspond to the channel region 52.

[0436] Referring to Figure 29, the surface drift region 51, body region 22, and source region 33, which are part of the second semiconductor layer 7, are arranged in this order along the first main surface 3. Furthermore, a contact region 34 is arranged adjacent to the source region 33. The first main surface 3 is the exposed surface of the SiC crystal structure constituting the second semiconductor layer 7 and corresponds to the aforementioned SiC surface 59. A part of the first main surface 3 is covered with a planar insulating film 56, and the planar insulating film 56 forms a SiC interface 60 with the SiC surface 59 (first main surface 3).

[0437] In this embodiment, the SiC interface 60 includes a first interface 80, a second interface 81, and a third interface 82. The first interface 80 is the interface between the first main surface 3 and the planar insulating film 56 in the surface drift region 51. The second interface 81 is the interface between the first main surface 3 and the planar insulating film 56 in the body region 22. The third interface 82 is the interface between the source region 33 and the first main surface 3.

[0438] The MIS structure of the semiconductor device 1E in Figure 22 is selectively applied to the second interface 81 of the first interface 80, second interface 81, and third interface 82 of the SiC interface 60. More specifically, as shown in Figure 29, an interface semiconductor region 62 is formed at the second interface 81 in the body region 22. On the other hand, as shown in Figure 28, even at the SiC interface 60, no interface semiconductor region 62 is formed at the first interface 80 and the third interface 82. Furthermore, although it is not the SiC interface 60, no interface semiconductor region 62 is formed on the first main surface 3 in the contact region 34.

[0439] Referring to Figure 29, the interface semiconductor region 62 may include a protrusion 83 that projects above the first main surface 3 of the surface drift region 51 and the source region 33. The protrusion 83 may project from the first main surface 3 with a uniform thickness. The thickness of the protrusion 83 may be the same as the thickness of the interface semiconductor region 62 described above (for example, 50 nm or less).

[0440] The lower end of the interface semiconductor region 62 (interface 63 with the body region 22) may be, for example, at the height of interface 63A, which is coplanar with the first interface 80 and the third interface 82. The lower end of the interface semiconductor region 62 may be at the height of interface 63B, which is on the planar electrode 57 side (upper side) than the first interface 80 and the third interface 82, or at the height of interface 63C, which is on the opposite side (lower side) of the planar electrode 57.

[0441] The cross-sectional shape of the protrusion 83 of the interface semiconductor region 62 may be rectangular as shown in Figure 29, or it may be trapezoidal, with the width narrowing toward the planar electrode 57 side.

[0442] (8) Donor concentration distribution in trench gate structure and planar gate structure Next, the distribution of donor concentrations in trench gate structure and planar gate structure will be described with reference to Figures 30A, 30B and 31.

[0443] Figures 30A and 30B show the donor concentration profile PA in the depth direction from the SiC interface 60 towards the interior of the SiC layer at point A in Figures 27 to 29. Figure 31 shows the donor concentration profile PB in the depth direction from the SiC interface 60 towards the interior of the SiC layer at point B in Figures 27 to 29.

[0444] Figure 30A simplifies the shape characteristics of profiles P1 to P3 in Figure 23 and shows profile PA having a local maximum M (corresponding to local maximums M1 to M3). Figure 30B simplifies the shape characteristics of profiles P1A, P1B, P2A, and P2B in Figures 24 and 25 and shows profile PA having an inflection point IP (corresponding to inflection points IP1 and IP2). Figure 31 simplifies the shape characteristics of profile P4 in Figure 26 and shows profile PB having no local maximums or inflection points.

[0445] As shown in Figures 30A and 30B, at point A in Figures 27 to 29, a profile PA with a maximum value M or inflection point IP can be observed in the range from the SiC interface 60 to a depth of 20 nm. This is because an interface semiconductor region 62 is formed at point A.

[0446] Point A, in the trench gate structure, includes the side interfaces 76 in the drift region 64, the body region 22, and the source region 33, respectively, starting from the bottom of the trench 26 in Figure 27. In the trench gate structure, the profile PA has a maximum value M or inflection point IP in the range from the side interface 76 to a depth of 20 nm in the direction toward the interior of the mesa region 29.

[0447] Point A, in the planar gate structure, includes the second interface 81 between the first main surface 3 and the planar insulating film 56 in the body region 22 of Figure 28. In the planar gate structure, the profile PA has a maximum value M or inflection point IP in the range from the second interface 81 to a depth of 20 nm in the thickness direction of the second semiconductor layer 7.

[0448] On the other hand, as shown in Figure 31, at point B in Figures 27 to 29, a profile PB can be observed in the depth direction from the SiC interface 60 that does not have any maximum values ​​or inflection points. This is because an interface semiconductor region 62 is formed at point B.

[0449] Point B, in the trench gate structure, includes the bottom interface 77 of the trench 26 in Figures 27 and 28, and the side interface 76 in Figure 28. Point B, in the planar gate structure, includes the first interface 80 and the third interface 82 between the first main surface 3 and the planar insulating film 56 in the surface drift region 51 and source region 33 in Figure 28, and the first main surface 3 in the contact region 34.

[0450] (9) Method for manufacturing semiconductor device 1A Next, with reference to Figures 32 to 36B, the method for manufacturing semiconductor device 1A to which the MIS structure of semiconductor device 1E is applied will be described in detail.

[0451] Figure 32 is an illustrative diagram illustrating the configuration of a SiC epitaxial growth apparatus 84 used in the manufacture of semiconductor device 1A.

[0452] The SiC epitaxial growth apparatus 84 includes a reaction vessel 85, a susceptor 86, a heater 87, a rotary drive mechanism 88, and a raw material gas supply passage 89. As shown in Figure 32, the SiC epitaxial growth apparatus 84 may have the raw material gas flowing in the lateral direction of the reaction vessel 85, or it may have the raw material gas flowing in the vertical direction of the reaction vessel 85.

[0453] A susceptor 86 with a built-in heater 87 is placed inside the reaction vessel 85. The susceptor 86 is coupled to a rotating shaft 90, which is rotated by a rotational drive mechanism 88 located outside the reaction vessel 85. As a result, by having the susceptor 86 hold the wafer 91 to be processed, the wafer 91 can be heated to a predetermined temperature and rotated inside the reaction vessel 85.

[0454] The susceptor 86 is formed from a material having a softening temperature of less than 1500°C. In this embodiment, the susceptor 86 is formed from quartz or SiC. The susceptor 86 has a planar size capable of supporting a wafer 91 with a diameter of 300 mm or more for epitaxial growth.

[0455] The heater 87 built into the susceptor 86 may be a heating device suitable for a temperature limit of less than 1500°C. For example, the configurable upper limit of the heater 87 may be less than 1500°C. The heater 87 may be built into the susceptor 86 as shown in Figure 32, or it may be located separately from the susceptor 86. For example, the heater 87 may be located along the outer wall of the reaction vessel 85.

[0456] An exhaust pipe 92 is connected to the reaction vessel 85. The exhaust pipe 92 is connected to exhaust equipment such as a rotary pump. As a result, the pressure inside the reaction vessel 85 is maintained at 1 / 10 atmosphere to atmospheric pressure, and the atmosphere inside the reaction vessel 85 is constantly evacuated.

[0457] The reaction vessel 85 is equipped with a raw material gas supply channel 89 for supplying raw material gases to the surface of the wafer 91 held in the susceptor 86. The raw material gas supply channel 89 is connected to argon raw material piping 93, helium raw material piping 94, chlorine raw material piping 95, nitrogen raw material piping 96 (first supply line), hydrogen raw material piping 97, phosphorus raw material piping 98 (first supply line), silicon raw material piping 99 (Si gas supply line), boron raw material piping 100 (second supply line), aluminum raw material piping 101 (second supply line), and carbon raw material piping 102 (C gas supply line). Valves 103 are interposed in each of these raw material pipes 93 to 102.

[0458] The argon raw material piping 93 supplies argon (Ar) as a purge gas to the reaction vessel 85. The helium raw material piping 94 supplies helium (He) as a carrier gas to the reaction vessel 85. Hydrogen chloride (HCl) as chlorine gas is supplied to the reaction vessel 85. The nitrogen raw material piping 96 supplies nitrogen (N) as a raw material gas for n-type impurities. ２ ) is supplied to the reaction vessel 85. The hydrogen raw material piping 97 supplies hydrogen (H) as a carrier gas. ２ ) is supplied to the reaction vessel 85. The phosphorus raw material piping 98 supplies phosphine (PH) as the raw material gas for n-type impurities. ３ ) is supplied to the reaction vessel 85. The silicon raw material piping 99 supplies silane (SiH) as the raw material gas for silicon. ４ ) is supplied to the reaction vessel 85. The boron raw material piping 100 supplies diborane (B) as the raw material gas for p-type impurities. ２ H ６ The aluminum raw material piping 101 supplies trimethylaluminum (TMA) as a raw material gas for p-type impurities to the reaction vessel 85. The carbon raw material piping 102 supplies propane (C) as a raw material gas for carbon. ３ H ８ The fuel gases are supplied to the reaction vessel 85. Each fuel gas is supplied together with a carrier gas consisting of hydrogen, helium, or both.

[0459] The above source gases are merely examples and can be substituted with other source gases. For example, dichlorosilane (SiH) can be used as a source gas for silicon. ２ Cl ２ ), tetrachlorosilane (SiCl ４ ) and others may be used. For example, chloromethane (CH4) may be used as the raw material gas for carbon. ３ Cl), methyltrichlorosilane (CH ３ SiCl ３ ) etc. may also be used.

[0460] Figure 33 is a schematic diagram showing a wafer 91 used in the manufacture of semiconductor device 1A. The wafer 91 is the substrate for the first semiconductor layer 6 and contains a SiC single crystal. The wafer 91 is formed in the shape of a flat disc. Of course, the wafer 91 may also be formed in the shape of a flat rectangular parallelepiped. The wafer 91 has a first wafer main surface 104 on one side, a second wafer main surface 105 on the other side, and a wafer side surface 106 connecting the first wafer main surface 104 and the second wafer main surface 105.

[0461] The first wafer main surface 104 corresponds to the upper end of the first semiconductor layer 6, and the second wafer main surface 105 corresponds to the lower end of the first semiconductor layer 6. The first wafer main surface 104 and the second wafer main surface 105 are formed by the c-plane of a SiC single crystal. The first wafer main surface 104 is formed by the silicon plane of the SiC single crystal, and the second wafer main surface 105 is formed by the carbon plane of the SiC single crystal.

[0462] The wafer 91 has a marker 107 on the wafer side surface 106 that indicates the crystal orientation of the SiC single crystal. The marker 107 may include either an orientation flat or an orientation notch, or both. The orientation flat consists of a notch that is cut out in a straight line in a plan view. The orientation notch consists of a notch that is cut out in a concave shape (for example, tapered shape) toward the center of the first wafer main surface 104 in a plan view.

[0463] The marker 107 may include either or both a first orientation flat extending in the m-axis direction and a second orientation flat extending in the a-axis direction. The marker 107 may also include either or both an orientation notch recessed in the m-axis direction and an orientation notch recessed in the a-axis direction. In Figure 33, the orientation flat extending in the m-axis direction is shown in plan view.

[0464] For example, the wafer 91 has multiple device regions 108 and multiple cutting lines 113 marked by alignment marks or the like. Each device region 108 corresponds to a semiconductor device 1A. The multiple device regions 108 are each set to a rectangular shape in a plan view.

[0465] In this configuration, the multiple device regions 108 are arranged in a matrix along the first direction X and the second direction Y in a plan view. The multiple device regions 108 are each spaced inward from the periphery of the first wafer main surface 104 in a plan view. The multiple cutting lines 113 are arranged in a grid pattern extending along the first direction X and the second direction Y to partition the multiple device regions 108.

[0466] Figure 34 is a flowchart showing a method for manufacturing a semiconductor device 1A to which the MIS structure of semiconductor device 1E is applied. Figures 35A to 35F are cross-sectional views showing a method for manufacturing a semiconductor device 1A. Figures 35A to 35F show cross-sections corresponding to Figure 27.

[0467] First, referring to Figure 35A, the aforementioned wafer 91 (first semiconductor layer 6) is prepared, and epitaxial growth of the second semiconductor layer 7 (drift region 64) is carried out on the wafer 91 (step S1). First, the wafer 91 is held in the susceptor 86. After purging the inside of the reaction vessel 85 by supplying argon gas, the heater 87 is energized, and the wafer temperature is raised to 1200°C or higher and 1700°C or lower. Then, silane, propane, and nitrogen (or phosphine) are supplied to the reaction vessel 85 along with the carrier gas. As a result, an n-type second semiconductor layer 7 (drift region 64) is epitaxially grown on the main surface 104 of the first wafer. In this process, for example, the second semiconductor layer 7 grows at a growth rate of 0.1 μm / min or higher and 10 μm / min or lower. The epitaxial growth of the second semiconductor layer 7 may be carried out using the aforementioned SiC epitaxial growth apparatus 84, or it may be carried out using a different epitaxial growth apparatus depending on the apparatus specifications (for example, upper heating limit, available gas types, etc.).

[0468] Next, referring to Figure 35A, the process of forming the body region 22 is carried out (step S2). In the process of forming the body region 22, p-type impurities are introduced throughout the entire second semiconductor layer 7. As a result, the body region 22 is formed over the entire surface of the drift region 64.

[0469] Next, referring to Figure 35A, the process of forming the source region 33 is carried out (step S3). In the process of forming the source region 33, n-type impurities are selectively introduced into the second semiconductor layer 7 (the surface layer of the body region 22). As a result, the source region 33 is formed on the surface layer of the body region 22. At this time, the area where the contact region 34 is to be formed is selectively covered with a mask (not shown) to prevent the introduction of n-type impurities.

[0470] Next, referring to Figure 35B, a process for forming multiple trenches 26 is carried out. Unnecessary portions of the second semiconductor layer 7 are removed by an etching method using a mask (not shown) of a predetermined pattern. The etching method may be either a wet etching method or a dry etching method, or both. The etching method is preferably a Reactive Ion Etching (RIE) method. As a result, multiple trenches 26 are formed at the upper end of the second semiconductor layer 7 (step S4). At the same time, mesa portions 29 are formed between adjacent trenches 26.

[0471] The next step is the formation of the surface semiconductor layer 109. More specifically, epitaxial growth of the surface semiconductor layer 109 is carried out (step S5). First, the wafer 91 after the trench 26 has been formed is transported to the SiC epitaxial growth apparatus 84. The wafer 91 is held in the susceptor 86, and after purging the inside of the reaction vessel 85 by supplying argon gas, the heater 87 is energized. The wafer temperature is raised to 900°C or more and 1300°C or less (for example, 1100°C or more and 1200°C or less). After that, silane, propane and nitrogen are supplied to the reaction vessel 85 along with the carrier gas. As a result, an n-type surface semiconductor layer 109 is epitaxially grown on the first main surface 3 (first wafer main surface 104), the side surface 74 and bottom surface 75 of the trench 26. In this process, the surface semiconductor layer 109 grows at a growth rate of, for example, 0.1 nm / min to 50 nm / min. The thickness of the surface semiconductor layer 109 is, for example, 50 nm or less, preferably 5 nm to 50 nm, and more preferably 5 nm to 20 nm.

[0472] Next, referring to Figure 35D, a portion of the surface semiconductor layer 109 is removed by etch-back (step S6). More specifically, the surface semiconductor layer 109 on the first main surface 3 and the bottom surface 75 of the trench 26 is selectively removed. As a result, the surface semiconductor layer 109 on the side surface 74 of the trench 26 remains as the aforementioned interface semiconductor region 62.

[0473] As a result, a structure is formed that provides a profile PA having a maximum value M or inflection point IP in the range from the side surface 74 (SiC surface 59) of the trench 26 to a depth of 20 nm in the direction toward the interior of the mesa portion 29 (see Figures 30A and 30B). On the other hand, the surface semiconductor layer 109 is removed from the bottom surface 75 of the trench 26. As a result, a structure is formed on the bottom surface 75 of the trench 26 that provides a profile PB that does not have any maximum value or inflection point in the depth direction from the bottom surface 75.

[0474] Next, referring to Figure 35E, with the first main surface 3 covered by the mask 110, the process of forming multiple well regions 30 is carried out (step S7). In the process of forming the well regions 30, p-type impurities are selectively introduced into the second semiconductor layer 7 via the mask 110. As a result, well regions 30 are formed at the bottom of each trench 26.

[0475] More specifically, the process involves a first step in which p-type impurities are introduced with a relatively high first energy and a relatively low first dose, and a second step in which p-type impurities are introduced with a second energy lower than the first energy and a second dose higher than the first dose. First, the first step is performed, forming a second well region 32 at the bottom of the trench 26. Next, the second step is performed, forming a first well region 31 on the surface of the second well region 32.

[0476] Various ion implantation methods can be applied to form the well region 30. For example, the well region 30 may be formed by channeling ion implantation. The channeling implantation process is performed based on data (information) of the off-angle θo. With the channeling implantation process, the well region 30 can be selectively and easily formed at a deep position in the second semiconductor layer 7. When the well region 30 is formed by channeling ion implantation, the well region 30 may be formed before the body region 22. After that, the mask 110 is removed.

[0477] Next, although the cross-sectional view is omitted, a contact region 34 is formed (step S8). In this step, first, a mask (not shown) having a predetermined pattern is formed. Next, p-type impurities are introduced to the surface of the second semiconductor layer 7 by ion implantation through the mask. As a result, p-type impurities are introduced to the surface of the mesa portion 29 and the inner surface of the trench 26, and the contact region 34 is formed. In this configuration, oblique implantation is performed at a predetermined angle to the first main surface 3. As a result, ions can be implanted not only to the first main surface 3 and the bottom surface 75 of the trench 26, but also to the side surface 74 of the trench 26 (see Figure 28). Next, after the mask is removed, an annealing treatment is performed to activate the impurity region (step S9).

[0478] Next, with reference to Figure 35F, the process of forming the insulating film 27 is carried out. The insulating film 27 may be formed by either the CVD (Chemical Vapor Deposition) method or the oxidation treatment method, or both. In this embodiment, the insulating film 27 is formed by the CVD method. The insulating film 27 is formed in a film-like manner on the walls of the plurality of trenches 26 and is formed over the entire area of ​​the first main surface 3. After the formation of the insulating film 27, the wafer 91 may be subjected to thermal oxidation treatment in a NO (nitric oxide) gas atmosphere. This may cause the SiC interface 60 to be nitrided (interfacial nitrided).

[0479] Next, the process of forming the embedded electrode 28 is carried out. In this process, conductive polysilicon is embedded by the CVD method, and then any unnecessary portions of the conductive polysilicon are removed by etching. This forms a trench-type gate structure 25 (step S10).

[0480] Next, the interlayer film 10 formation process is carried out (step S11). In this process, an insulating material film is formed on the first main surface 3 by the CVD method, and then any unnecessary portions of the insulating material film are removed by etching. This forms an interlayer film 10 having openings such as a source opening 40.

[0481] Next, referring to Figure 35F, the process of forming the first electrode 12, including the source electrode 43, and the second electrode 17 is carried out (step S12). After that, the wafer 91 is cut along a plurality of planned cutting lines 113. Through the above process, a plurality of semiconductor devices 1A are manufactured from a single wafer 91.

[0482] Figures 36A to 36B show modified examples of the manufacturing process for the interface semiconductor region 62. The interface semiconductor region 62 can also be formed by performing the steps in Figures 36A to 36B in order, instead of the steps in Figures 35C to 35D.

[0483] For example, referring to Figure 36A, after the formation of the trench 26, the interfacial semiconductor region 62 is formed by ion implantation. More specifically, a mask (not shown) having a predetermined pattern is formed. The mask may cover the region where the contact region 34 is to be formed.

[0484] Next, n-type impurity ions are introduced into the surface layer of the second semiconductor layer 7 by ion implantation via the mask. In this configuration, the n-type impurity ions are implanted with an energy of 10 keV or less (for example, 0.1 keV to 10 keV). They are also implanted at an inclination angle θ of 30° or less relative to the side surface 74 of the trench 26. The implantation angle θ of the n-type impurity ions may be an angle with respect to the normal direction n of the first main surface 3. By implanting the n-type impurity ions at an angle, the n-type impurity ions can be efficiently implanted into the side surface 74 of the trench 26. This ion implantation forms an interface semiconductor region 62 on the first main surface 3 (first wafer main surface 104), the side surface 74 and bottom surface 75 of the trench 26.

[0485] Next, referring to Figure 36B, a portion of the interface semiconductor region 62 is removed by etch-back. More specifically, the interface semiconductor region 62 that forms the first main surface 3 and the bottom surface 75 of the trench 26 is selectively removed. As a result, the interface semiconductor region 62 on the side surface 74 of the trench 26 is selectively left intact.

[0486] As a result, a structure is formed that provides a profile PA having a maximum value M or inflection point IP in the range from the side surface 74 (SiC surface 59) of the trench 26 to a depth of 20 nm in the direction toward the interior of the mesa portion 29 (see Figures 30A and 30B). On the other hand, the surface semiconductor layer 109 is removed from the bottom surface 75 of the trench 26. As a result, a structure is formed on the bottom surface 75 of the trench 26 that provides a profile PB that does not have any maximum value or inflection point in the depth direction from the bottom surface 75.

[0487] (10) Method for Manufacturing Semiconductor Device 1C Next, with reference to Figures 37 to 39B, the method for manufacturing the semiconductor device 1C to which the MIS structure of the semiconductor device 1E is applied will be described in detail. Since the SiC epitaxial growth apparatus 84 and wafer 91 described above are also used in the manufacturing of the semiconductor device 1C, a detailed explanation of these will be omitted.

[0488] Referring to Figure 38A, the aforementioned wafer 91 (first semiconductor layer 6) is prepared, and epitaxial growth of the second semiconductor layer 7 (surface drift region 51) is carried out on the wafer 91 (step S1). The conditions for epitaxial growth are the same as those for the semiconductor device 1A.

[0489] Next, referring to Figure 38A, the body region 22 is formed (step S2). In the body region 22 formation process, p-type impurities are selectively introduced into the second semiconductor layer 7. Next, the source region 33 is formed (step S3). In the source region 33 formation process, n-type impurities are selectively introduced into the second semiconductor layer 7 (the surface layer of the body region 22). Next, the contact region 34 is formed (step S4).

[0490] Next, referring to Figure 38A, a process for forming multiple well regions 30 is carried out (step S5). In the process for forming the well regions 30, p-type impurities are selectively introduced into the second semiconductor layer 7 via a mask (not shown). This forms well regions 30 at the bottom of each body region 22. For example, the well regions 30 may be formed by channeling ion implantation.

[0491] The next step is the formation of the surface semiconductor layer 111. More specifically, epitaxial growth of the surface semiconductor layer 111 is carried out (step S6). First, the wafer 91 is transported to the SiC epitaxial growth apparatus 84. The wafer 91 is held in the susceptor 86, and after purging the inside of the reaction vessel 85 by supplying argon gas, the heater 87 is energized. The wafer temperature is raised to 900°C or more and 1300°C or less (for example, 1100°C or more and 1200°C or less). Then, silane, propane, and nitrogen are supplied to the reaction vessel 85 along with the carrier gas. As a result, an n-type surface semiconductor layer 111 is epitaxially grown over the entire first main surface 3 (first wafer main surface 104). In this process, the surface semiconductor layer 111 grows at a growth rate of, for example, 0.1 nm / min or more and 50 nm / min or less. The thickness of the surface semiconductor layer 111 is, for example, 50 nm or less, preferably 5 nm to 50 nm, and more preferably 5 nm to 20 nm.

[0492] Next, referring to Figure 38C, with the body region 22 (channel region 52) covered by the mask 112, a portion of the surface semiconductor layer 111 is removed by etch-back (step S7). More specifically, the surface semiconductor layer 111 on the surface drift region 51, the source region 33, and the contact region 34 is selectively removed. As a result, the surface semiconductor layer 111 on the body region 22 (channel region 52) remains as the aforementioned interface semiconductor region 62.

[0493] As a result, a structure is formed that provides a profile PA having a maximum value M or inflection point IP in the range from the first main surface 3 (SiC surface 59) in the body region 22 to a depth of 20 nm in the direction toward the interior of the body region 22 (see Figures 30A and 30B). On the other hand, the surface semiconductor layer 111 is removed from the surface drift region 51, the source region 33, and the contact region 34. As a result, the first main surface 3 of the surface drift region 51, the source region 33, and the contact region 34 is formed with a structure that provides a profile PB that does not have any maximum value or inflection point in the depth direction from the first main surface 3.

[0494] Next, after the mask 112 is removed, an annealing treatment is performed to activate the impurity region (step S8).

[0495] Next, with reference to Figure 38D, the process of forming the planar insulating film 56 is carried out. The planar insulating film 56 may be formed by either the CVD (Chemical Vapor Deposition) method or the oxidation treatment method, or both. In this embodiment, the planar insulating film 56 is formed by the thermal oxidation treatment method. After the formation of the planar insulating film 56, the wafer 91 may be heat-treated in a NO (nitric oxide) gas atmosphere. This may cause the SiC interface 60 to be nitrided (interfacial nitrided).

[0496] Next, the process of forming the planar electrode 57 is carried out. In this process, conductive polysilicon is deposited by CVD, and then any unnecessary portions of the conductive polysilicon are removed by etching. This forms a planar gate structure 55 (step S9).

[0497] Next, referring to Figure 38E, the process of forming the interlayer film 10 is carried out (step S10). In this process, after an insulating material film is formed on the first main surface 3 by the CVD method, the unnecessary portions of the insulating material film are removed by etching. This forms an interlayer film 10 having openings such as the source opening 40.

[0498] Next, referring to Figure 38F, the process of forming the first electrode 12, including the source electrode 43, and the second electrode 17 is carried out (step S11). After that, the wafer 91 is cut along a plurality of planned cutting lines 113. Through the above process, a plurality of semiconductor devices 1C are manufactured from a single wafer 91.

[0499] Figures 39A to 39B show modified examples of the manufacturing process for the interface semiconductor region 62. The interface semiconductor region 62 can also be formed by performing the steps in Figures 39A to 39B in order, instead of the steps in Figures 38B to 38C.

[0500] For example, referring to Figure 39A, after the formation of impurity regions such as the body region 22, the interface semiconductor region 62 is formed by ion implantation. More specifically, n-type impurity ions are implanted over the entire first main surface 3. In this configuration, the n-type impurity ions are implanted with an energy of 10 keV or less (for example, 0.1 keV to 10 keV). This ion implantation forms the interface semiconductor region 62 over the entire first main surface 3 (first wafer main surface 104).

[0501] Next, referring to Figure 39B, with the body region 22 (channel region 52) covered by the mask 112, a portion of the interface semiconductor region 62 is removed by etch-back. More specifically, the interface semiconductor region 62 that forms the surface drift region 51, the source region 33, and the contact region 34 is selectively removed. As a result, the interface semiconductor region 62 in the body region 22 (channel region 52) is selectively left intact.

[0502] As a result, a structure is formed that provides a profile PA having a maximum value M or inflection point IP in the range from the first main surface 3 (SiC surface 59) in the body region 22 to a depth of 20 nm in the direction toward the interior of the body region 22 (see Figures 30A and 30B). On the other hand, the surface semiconductor layer 111 is removed from the surface drift region 51, the source region 33, and the contact region 34. As a result, the first main surface 3 of the surface drift region 51, the source region 33, and the contact region 34 is formed with a structure that provides a profile PB that does not have any maximum value or inflection point in the depth direction from the first main surface 3.

[0503] (11) Vgs dependence of field-effect mobility (channel mobility) Next, the Vgs dependence of the field-effect mobility of semiconductor device 1E, which was described with reference to Figures 22 to 26, will be explained in detail.

[0504] The Vgs-dependent measurement samples are Sample 1 (see Figures 23 and 24), Sample 2 (see Figures 23 and 25), and Sample 4 (see Figure 26), which correspond to the concentration distribution measurement samples in Figures 22 to 26, as well as Sample 5 shown in Figure 40.

[0505] Figure 40 is a cross-sectional view showing the periphery of the channel region of semiconductor device 1F according to a reference example (sample 5). In Figure 40, the MIS transistor structure Tr portion of semiconductor device 1F is disclosed for the purpose of explaining the difference between semiconductor device 1E and semiconductor device 1F. In Figure 40, components that differ from those of semiconductor device 1E are given reference numerals, while components that are common to semiconductor device 1E are given the same reference numerals.

[0506] Referring to Figure 40, the semiconductor device 1F includes an n-type embedded channel layer 114 between the semiconductor region 61 (body region) and the insulating film 54. The thickness CT4 of the embedded channel layer 114 is, for example, greater than 50 nm and 300 nm, which is thicker than the interface semiconductor region 62.

[0507] Furthermore, the impurity concentration of the embedded channel layer 114 is, for example, 1 × 10⁻⁶. １５ cm －３ The above 1 x 10 １９ cm －３The following applies: The impurity concentration range is within the range of the maximum value M1 to M3 of semiconductor device 1E (see Figure 23, 1 × 10⁻¹⁰). １８ cm －３ The above 1 x 10 ２０ cm －３ This partially overlaps with the following. However, the embedded channel layer 114 is thicker than the interface semiconductor region 62 and does not have a maximum value of the impurity concentration range within a 20 nm depth range from the SiC interface 60. In this respect, the embedded channel layer 114 and the interface semiconductor region 62 have completely different configurations.

[0508] Figure 41 is a diagram illustrating the field-effect mobility of semiconductor devices 1E and 1F. Figure 41 shows the Vgs dependence of the field-effect mobility of semiconductor devices related to samples 1, 2, 4, and 5. The horizontal axis of Figure 41 shows the gate voltage (V) applied to the control electrode 58, and the vertical axis of Figure 41 shows the field-effect mobility (cm²). ２ This shows ( / Vs). The gate voltage (V) may be the voltage value relative to the semiconductor region 61, which is the ground voltage (source voltage).

[0509] In Figure 41, the thick solid line represents profile PM1 showing the field effect mobility of sample 1, the thick dashed line represents profile PM2 showing the field effect mobility of sample 2, the thick dashed line represents profile PM4 showing the field effect mobility of sample 4, and the thick double dashed line represents profile PM5 showing the field effect mobility of sample 5.

[0510] Referring to Figure 41, Profile PM1 and Profile PM2 have a high gate threshold voltage of approximately 4V, and reliable normally-off characteristics are achieved.

[0511] Furthermore, it can be seen that even when the channel region 50 is subjected to high electric field conditions by increasing the gate voltage, the mobility hardly decreases. More specifically, in profile PM1, the mobility on the higher voltage side of the peak Pk1 voltage value where the mobility is highest is maintained at more than 90% of the peak Pk1 mobility. For example, the peak Pk1 mobility at a gate voltage of 12.5V is approximately 27.5 cm². ２ / Vs. In profile PM1, at a gate voltage of around 20V, which is higher than the voltage value in question, approximately 27cm² is observed. ２ The mobility of / Vs (approximately 98% of the peak Pk1 mobility) is maintained. In addition, in profile PM1, the voltage width from the gate threshold voltage (turn-on voltage) to the peak Pk1 is approximately 8.5V, which is greater than 5V.

[0512] Furthermore, in profile PM2, the mobility at voltages higher than the peak Pk2 voltage value where mobility is highest is maintained at 90% or more of the peak Pk2 mobility. For example, the peak Pk2 mobility at a gate voltage of 13V is approximately 27cm². ２ / Vs. In profile PM2, at a gate voltage of around 20V, which is higher than the voltage value in question, approximately 26cm² is observed. ２ The mobility is maintained at a magnitude of / Vs (approximately 96% of the peak Pk2 mobility). In addition, in profile PM2, the voltage width from the gate threshold voltage (turn-on voltage) to peak Pk1 is approximately 9V, which is greater than 5V.

[0513] Thus, it can be seen that, for samples 1 and 2, high mobility can be maintained even at high voltages of 5V or more above the peak voltage values ​​of Pk1 and Pk2. More specifically, high mobility is maintained in the gate voltage range of 15V to 20V, and considering the slopes of profiles PM1 and PM2, it can be said that high mobility is exhibited even at gate voltages exceeding 20V and around 30V.

[0514] This is because, in samples 1 and 2, a concentration distribution of n-type impurities with maximum values ​​M1 to M3 or inflection points IP1 to IP2 is observed in the range from the SiC interface 60 to 20 nm in the channel region 50.

[0515] By forming an interfacial semiconductor region 62 having a maximum value M1 to M3 or inflection points IP1 to IP2 within this depth range, an inversion channel can be formed at a position slightly away from the SiC interface 60 in the depth direction. This is because, since the inversion channel is away from the SiC interface 60, it can be made less susceptible to the influence of the interface states at the SiC interface 60 (SiC / insulating film).

[0516] Furthermore, by keeping the maximum values ​​M1 to M3 or inflection points IP1 to IP2 within a range of 20 nm from the SiC interface 60, which is not too deep, the decrease in gate threshold voltage can be suppressed, and reliable normally-off characteristics can be achieved.

[0517] In contrast, in the profile PM4 of sample 4, where the interfacial semiconductor region 62 is not formed, the inversion channel is affected by the interfacial state at the SiC interface 60 (SiC / insulating film), and even the highest peak Pk4 is only about 10 cm². ２ The mobility remains at approximately / Vs.

[0518] Furthermore, in profile PM5 of sample 5, which has an embedded channel layer 114, approximately 30 cm² was observed when a gate voltage of approximately 2 V was applied. ２ While a high mobility of approximately / Vs (peak Pk5) is observed, an extreme drop in mobility is seen within the device's practical gate voltage driving range (e.g., 15V to 25V). Furthermore, the gate threshold voltage is nearly 0V, meaning that sufficient normally-off characteristics cannot be achieved.

[0519] (12) Capacitance Characteristics of the Device Next, the capacitance characteristics of the semiconductor device 1E described above will be explained in detail with reference to Figures 22 to 26. The capacitance characteristics of the semiconductor device 1E were determined by simulation comparing the conditions under which the interface semiconductor region 62 is formed (with the processing described in Figures 35C and 38B) with the conditions under which the said processing is not performed.

[0520] Figure 42 is a diagram illustrating the C-V characteristics of semiconductor device 1E. Figure 43 is an enlarged view of the area enclosed by XLIII in Figure 42. Figure 44 is an enlarged view of the area enclosed by XLIV in Figure 42.

[0521] The horizontal axis of Figure 42 shows the gate voltage (gate-source voltage (V)) applied to the control electrode 58, and the vertical axis of Figure 42 shows the capacitance (gate-source capacitance (pF / mm)) between the control electrode 58 and the semiconductor region 61 (body region). In Figure 42, the thick curve Sim1 represents the simulation result with the processing shown in Figures 35C and 38B, and the thin curve Sim2 represents the simulation result without the processing shown in Figures 35C and 38B.

[0522] Curve Sim1 may be divided into a storage voltage section 115, a depletion voltage section 116, and an inversion voltage section 117, as voltage sections corresponding to the magnitude of the gate-source voltage.

[0523] The accumulation voltage section 115 may be a state in which, for example, majority carriers (holes) in the p-type semiconductor region 61 are accumulated at the SiC interface 60 by electrostatic induction due to a negative potential applied to the control electrode 58 (gate electrode), thereby forming an accumulation layer.

[0524] The depletion voltage section 116 may be a state in which, for example, a positive potential applied to the control electrode 58 (gate electrode) causes holes near the SiC interface 60 to move in the depth direction, and a depletion layer is formed near the SiC interface 60.

[0525] The inversion voltage interval 117 may be a state in which, for example, the vicinity of the SiC interface 60 becomes n-type by increasing the potential applied to the control electrode 58 (gate electrode), and conduction electrons become majority carriers. In the inversion voltage interval 117, the curve Sim1 may be in a range where the change in capacitance value with respect to the change in gate-source voltage of 10V is 20% or less. Figures 42 and 43 show the inversion capacitance line 118, which indicates the capacitance value to which the curve Sim1 asymptotically approaches in the inversion voltage interval 117.

[0526] Curve Sim1 further includes a first change interval 119 and a second change interval 120. The first change interval 119 is the interval in which the slope changes from a steep first line 121 to a gentler second line 122 with respect to the horizontal axis of the graph.

[0527] Referring to Figure 43, the first line 121 may be, for example, a curved portion from which a tangent line 124 can be drawn that intersects the inversion capacitance line 118 at an angle θ1 of 60° or more and less than 90°. Multiple tangent lines 124 can be drawn to the first line 121. The section of the first change section 119 in which the first line 121 is located may be further defined as the first voltage section 125 (see Figure 42). In this embodiment, the voltage width of the first voltage section 125 may be greater than 0V and less than or equal to 2V.

[0528] Referring to Figure 43, the second line 122 may be, for example, a curved portion from which a tangent line 126 can be drawn that intersects the inversion capacitance line 118 at an angle θ2 of 5° or more and less than 60°. Multiple tangent lines 126 can be drawn to the second line 122. The tangent line 126 may have a slope of Cinv / 1000V or more and Cinv / 10V or less with respect to the capacitance value Cinv of the inversion capacitance line 118.

[0529] The section of the first change section 119 in which the second line 122 is located may be further defined as a second voltage section 127 (see Figure 42). In this configuration, the voltage width of the second voltage section 127 may be 3V or more and 10V or less. The voltage width of the second voltage section 127 may be wider than the voltage width of the depletion voltage section 116. For example, the voltage width of the depletion voltage section 116 may be 1V or more and 5V or less.

[0530] The first voltage section 125 and the second voltage section 127 are collectively referred to as the transition section 123 from the depletion voltage section 116 to the inversion voltage section 117. In the transition section 123, the curve Sim1 has a voltage width of 3V or more, preferably 3V to 10V, before asymptotically approaching the inversion capacitance line 118.

[0531] The second change interval 120 is the interval in which the slope of the horizontal axis of the graph changes from the steep third line 128 to the gentler fourth line 129, and is the transition interval from the accumulation voltage interval 115 to the depletion voltage interval 116.

[0532] Referring to Figure 43, the third line 128 may be, for example, a curved portion to which a tangent line 131 can be drawn that intersects the storage capacitance line 130 at an angle θ3 of 60° or more and less than 90°. In Figures 42 and 43, the storage capacitance line 130 is shown, which indicates the capacitance value to which the curve Sim1 asymptotically approaches in the storage voltage section 115. Multiple tangent lines 131 can be drawn to the third line 128.

[0533] Referring to Figure 43, the fourth line 129 may be, for example, a curved portion from which a tangent line 132 can be drawn that intersects the inversion capacitance line 118 at an angle θ2 of 5° or more and less than 60°. Multiple tangent lines 132 can be drawn to the fourth line 129.

[0534] Curve Sim2 may be divided into a storage voltage section 133, a depletion voltage section 134, and an inversion voltage section 135, as voltage sections corresponding to the magnitude of the gate-source voltage. Curve Sim2 further includes a first change section 136 and a second change section 137. The first change section 136 is the transition section from the depletion voltage section 134 to the inversion voltage section 135, and the second change section 137 is the transition section from the storage voltage section 133 to the depletion voltage section 134.

[0535] Comparing curve Sim1 and curve Sim2, the first change section 119 of curve Sim1 (depletion voltage section 116 → inversion voltage section 117) has a wider voltage range than the first change section 136 of curve Sim2 (depletion voltage section 134 → inversion voltage section 135). The difference in conditions between curve Sim1 and curve Sim2 is, as mentioned above, the presence or absence of the processing shown in Figures 35C and 38B. Therefore, it is considered that the mobility exhibited by a semiconductor device obtained by a process including the processing shown in Figures 35C and 38B (see Figure 41) can be achieved by a semiconductor device exhibiting curve Sim1.

[0536] (13) Characteristics of the semiconductor region 61 (body region) Figure 45 is a cross-sectional view showing the periphery of the channel region 50 of the semiconductor device 1G. Figure 45 discloses an MIS (Metal-Insulator-Semiconductor) transistor structure Tr to explain the concentration distribution of p-type impurities in the channel region 50 of the semiconductor device 1G. In Figure 45, a portion of the MIS transistor structure Tr of the semiconductor device 1G is disclosed for the purpose of explaining the difference between the semiconductor device 1E and the semiconductor device 1G. Also, in Figure 45, components that are different from those of the semiconductor device 1E are given reference numerals, and components that are common to the semiconductor device 1E are given the same reference numerals.

[0537] Referring to Figure 45, the semiconductor region 61 (body region) of semiconductor device 1G includes a base region 138 and a high-concentration region 139. In this respect, semiconductor device 1G differs from semiconductor device 1E. The base region 138 and the high-concentration region 139 may also be defined by the acceptor concentration distribution of the semiconductor region 61.

[0538] Figures 46A and 46B show the acceptor concentration profiles of the semiconductor region 61. The horizontal axis of Figures 46A and 46B represents the depth (nm) from the interface 63 between the semiconductor region 61 and the interfacial semiconductor region 62, and the vertical axis of Figures 46A and 46B represents the p-type impurity concentration. Each profile shown in Figures 46A and 46B is a graph where the depth from the interface 63 is the horizontal axis (x-axis) and the logarithmic value of the p-type impurity concentration is the vertical axis (y-axis).

[0539] There is a difference between Figure 46A and Figure 46B in the method of calculating the numerical values ​​that form the basis of the linear profiles showing the concentration distribution. As explained using Figures 23 to 26, the profile in Figure 46A shows the acceptor concentration distribution based on the capacitance-voltage characteristics (C-V characteristics) between the control electrode 58 and the semiconductor region 61. On the other hand, the profile in Figure 46B is created from a plot of acceptor concentrations based on the results of secondary ion mass spectrometry (SIMS).

[0540] Referring to Figure 46A, the profile PGA may be formed in a roughly mountain shape with a peak (maximum value M5) at a certain depth from the interface 63. The profile PGA may include a concentration transition section 140 containing the maximum value M5, an increasing section 141 on the interface 63 side of the concentration transition section 140, and a decreasing section 142 on the opposite side of the increasing section 141 from the concentration transition section 140.

[0541] The concentration transition section 140 is a convex portion that includes a series of concentration changes (inflection points) in which the acceptor concentration changes from increasing (increasing trend) to decreasing (decreasing trend) around the maximum value M5.

[0542] The maximum value M5 is 1 × 10⁻⁶ in this form. １８ cm －３ The above 1 x 10 ２０ cm －３ The following is preferable: The maximum value M5 is 1 × 10⁻⁶ １８ cm －３ The above 1 x 10 １９ cm －３ The following, and 1 x 10 １９ cm －３ The above 1 x 10 ２０ cm －３ It may have a value that falls within at least one of the following ranges.

[0543] In this embodiment, the maximum value M5 is preferably located in the range from the interface 63 to a depth of 20 nm. The maximum value M5 may also be located in the range from the interface 63 to a depth of 1 nm or more and 20 nm or less. The maximum value M5 may have a value that belongs to at least one of the following ranges from the interface 63 to a depth of 3 nm or more and 20 nm or less, 3 nm or more and 15 nm or less, 3 nm or more and 10 nm or less, 5 nm or more and 20 nm or less, 5 nm or more and 15 nm or less, and 5 nm or more and 10 nm or less. The concentration transition section 140 including the maximum value M5 may, for example, be in the range of 0.5 nm or more and 5 nm or less that straddles the maximum value M5 above and below in the depth direction.

[0544] The gradually increasing portion 141 may be in a range of 0.5 nm to 5 nm from the interface 63 in the depth direction. The range of donor concentrations in the gradually increasing portion 141 is smaller than the range of acceptor concentrations in the concentration transition portion 140.

[0545] Referring to Figure 46B, the profile PGB includes an upper curved section 143 and a lower curved section 144. The upper curved section 143 slopes downward from the high-concentration side to the low-concentration side. In this embodiment, the upper curved section 143 is formed as an upper convex section having a first curvatured section 145 that is convex toward the low-concentration side. The lower curved section 144 slopes downward from the high-concentration side to the low-concentration side in a deeper region than the upper curved section 143. In this embodiment, the lower curved section 144 is formed as a lower convex section having a second curvatured section 146 that is convex toward the high-concentration side.

[0546] The upper curved section 143 and the lower curved section 144 are continuous via an inflection point IP5. The inflection point IP5 may be the point where the curvature of the profile PGB changes from the first curvature section 145 to the second curvature section 146 (or, in other words, from the second curvature section 146 to the first curvature section 145).

[0547] The inflection point IP5 is located at approximately the same depth as the maximum value M5 in Figure 46A. In this configuration, the inflection point IP5 is 1 × 10 １８ cm －３ The above 1 x 10 ２０ cm －３ The following is preferable: The inflection point IP5 is 1 × 10 １８ cm －３ The above 1 x 10 １９ cm －３ The following, and 1 x 10 １９ cm －３ The above 1 x 10 ２０ cm －３ It may have a value that falls within at least one of the following ranges.

[0548] In this embodiment, the inflection point IP5 is preferably located in the range from the interface 63 to a depth of 20 nm. The inflection point IP5 may also be located in the range from the interface 63 to a depth of 1 nm or more and 20 nm or less. The inflection point IP5 may have a value that falls within at least one of the following ranges from the SiC interface 60 to a depth of 3 nm or more and 20 nm or less, 3 nm or more and 15 nm or less, 3 nm or more and 10 nm or less, 5 nm or more and 20 nm or less, 5 nm or more and 15 nm or less, and 5 nm or more and 10 nm or less.

[0549] Thus, in semiconductor device 1G, the maximum value M5 or inflection point IP5 is located in the range from interface 63 to a depth of 20 nm. As a result, a high density (for example, 1 × 10⁻¹⁶) is located from interface 63 to a depth of 20 nm. １８ cm －３ The region described above is defined as the high-concentration region 139, and the low-concentration region (for example, 1 × 10) is defined as the region deeper than 20 nm. １８ cm －３ The region less than may be defined as the base region 138.

[0550] The thickness CT5 of the base region 138 may be, for example, 50 nm or more and 500 nm or less. The thickness CT5 of the base region 138 may have a value that falls within at least one of the following ranges: 50 nm or more and 100 nm or less, 50 nm or more and 200 nm or less, 50 nm or more and 300 nm or less, 50 nm or more and 400 nm or less, and 50 nm or more and 500 nm or less.

[0551] The thickness CT6 of the high-concentration region 139 is thinner than that of the base region 138. The thickness CT6 of the high-concentration region 139 may be, for example, 5 nm or more and 50 nm or less. The thickness CT6 of the high-concentration region 139 may have a value that falls within at least one of the following ranges: 5 nm or more and 10 nm or less, 5 nm or more and 20 nm or less, 5 nm or more and 30 nm or less, 5 nm or more and 40 nm or less, and 5 nm or more and 50 nm or less.

[0552] By applying this semiconductor device 1G to various MISFETs such as the aforementioned semiconductor device 1A (see Figure 27) and semiconductor device 1C (Figure 29), the peak position (peak depth) of the acceptor concentration in the body region 22 can be adjusted. By adjusting the acceptor concentration, the magnitude of the gate threshold voltage can be appropriately adjusted.

[0553] Furthermore, by setting the peak position of the acceptor concentration in a relatively shallow region (for example, the range from the interface 63 to a depth of 20 nm), the body region 22 can be formed thinner. As a result, the cost of device fabrication can be reduced. In addition, thinning the body region 22 also contributes to reducing the JFET resistance.

[0554] (14) Regarding the characteristics of the source region 33, Figures 47 and 48 are cross-sectional views of the main part of the torrent gate structure. Figure 49 is a cross-sectional view of the main part of the planar gate structure. Figures 47 and 48 correspond to Figures 27 and 28, and Figure 49 corresponds to Figure 29.

[0555] Referring to Figures 47 to 49, the source region 33 may have a two-layer structure with different concentration ranges. More specifically, the source region 33 includes a base region 147 and a high-concentration region 148. The base region 147 is, for example, a region that occupies more than half of the thickness of the source region 33. The high-concentration region 148 is a contact region that is laminated on the base region 147 and connected to the source electrode 43.

[0556] Referring to Figure 47, in the trench gate structure, a base region 147 and a high-density region 148 are stacked in the thickness direction of the second semiconductor layer 7. In Figure 47, the area of ​​the high-density region 148 is indicated by dot hatching. The high-density region 148 is exposed from the top surface (first main surface 3) of the mesa portion 29. In this embodiment, the high-density region 148 may be formed over the entire width direction of the mesa portion 29, from the side surface 74 of one adjacent trench 26 to the side surface 74 of the other trench 26. As a result, the high-density region 148 is exposed from the side surface 74 of the trench 26. The high-density region 148 may be selectively formed only at the contact portion with the source electrode 43 at the top of the mesa portion 29.

[0557] Referring to Figure 48, in the planar gate structure, a base region 147 and a high-density region 148 are stacked in the thickness direction of the second semiconductor layer 7. In Figure 48, the area of ​​the high-density region 148 is indicated by dot hatching. The high-density region 148 is exposed from the first main surface 3. In this embodiment, the high-density region 148 may consist of an extension extending along the first main surface 3 from a protrusion 83 that constitutes the interface semiconductor region 62. The end of the high-density region 148 may be located at the boundary between the source region 33 and the contact region 34, or it may be located outside of that boundary.

[0558] The base region 147 and the high-concentration region 148 may be defined by the distribution of donor concentrations in the source region 33.

[0559] Figures 50A and 50B show the donor concentration profile in the depth direction at point A in Figures 47 and 49. Figure 51 shows the donor concentration profile in the depth direction at point B in Figures 48 and 49. In Figures 50A, 50B, and 51, the horizontal axis represents the depth (nm) from the first main surface 3, and the vertical axis represents the n-type impurity concentration. The profiles shown in Figures 50A, 50B, and 51 are graphs where the depth from the first main surface 3 is the horizontal axis (x-axis) and the logarithmic value of the n-type impurity concentration is the vertical axis (y-axis).

[0560] There is a difference between Figure 50A and Figure 50B in the method of calculating the numerical values ​​that form the basis of the linear profiles showing the concentration distribution. As explained using Figures 23 to 26, the profile in Figure 50A shows the distribution of donor concentrations based on the capacitance-voltage characteristics (C-V characteristics) between the control electrode 58 and the semiconductor region 61. On the other hand, the profile in Figure 50B is created from a plot of donor concentrations based on the results of secondary ion mass spectrometry (SIMS).

[0561] Referring to Figure 50A, the profile PSA may be formed in a roughly mountain shape with a peak (maximum value M6) at a certain depth position from the first main surface 3. The profile PSA may include a concentration transition section 149 containing the maximum value M6, an increasing section 150 on the first main surface 3 side of the concentration transition section 149, and a decreasing section 151 on the opposite side of the increasing section 150 from the concentration transition section 149.

[0562] The concentration transition section 149 is a convex portion that includes a series of concentration changes (inflection points) in which the donor concentration changes from increasing (increasing trend) to decreasing (decreasing trend) around the maximum value M6.

[0563] The maximum value M6 in this form is 1 × 10⁻⁶ １７ cm －３ The above 1 x 10 ２０ cm －３ The following is preferable: The maximum value M6 is 1 × 10⁻⁶ １７ cm －３ The above 1 x 10 １９ cm －３ The following, and 1 x 10１９ cm －３ The above 1 x 10 ２０ cm －３ It may have a value that falls within at least one of the following ranges.

[0564] In this embodiment, the maximum value M6 is preferably located in the range from the first main surface 3 to a depth of 20 nm. The maximum value M6 may also be located in the range from the first main surface 3 to a depth of 1 nm or more and 20 nm or less. The maximum value M6 may have a value that belongs to at least one of the following ranges from the first main surface 3 to a depth of 3 nm or more and 20 nm or less, 3 nm or more and 15 nm or less, 3 nm or more and 10 nm or less, 5 nm or more and 20 nm or less, 5 nm or more and 15 nm or less, and 5 nm or more and 10 nm or less. The concentration transition section 149 including the maximum value M6 may, for example, be in the range of 0.5 nm or more and 5 nm or less that straddles the maximum value M6 above and below in the depth direction.

[0565] The gradually increasing portion 150 may be in a range of 0.5 nm to 5 nm in the depth direction from the first main surface 3. The range of donor concentrations in the gradually increasing portion 150 is smaller than the range of donor concentrations in the concentration transition portion 149.

[0566] Referring to Figure 50B, the PSB profile includes an upper curved section 152 and a lower curved section 153. The upper curved section 152 slopes downward from the high-concentration side to the low-concentration side. In this embodiment, the upper curved section 152 is formed as an upper convex section having a first curvatured section 154 that is convex toward the low-concentration side. The lower curved section 153 slopes downward from the high-concentration side to the low-concentration side in a deeper region than the upper curved section 152. In this embodiment, the lower curved section 153 is formed as a lower convex section having a second curvatured section 155 that is convex toward the high-concentration side.

[0567] The upper curved section 152 and the lower curved section 153 are continuous via an inflection point IP6. The inflection point IP6 may be the point where the curvature of the profile PSB changes from the first curvature section 154 to the second curvature section 155 (or, in other words, from the second curvature section 155 to the first curvature section 154).

[0568] The inflection point IP6 is located at approximately the same depth as the maximum value M6 in Figure 50A. In this configuration, the inflection point IP6 is 1 × 10 １７ cm －３ The above 1 x 10 ２０ cm －３ The following is preferable: The inflection point IP6 is 1 × 10 １７ cm －３ The above 1 x 10 １９ cm －３ The following, and 1 x 10 １９ cm －３ The above 1 x 10 ２０ cm －３ It may have a value that falls within at least one of the following ranges.

[0569] In this embodiment, the inflection point IP6 is preferably located in the range from the first main surface 3 to a depth of 20 nm. The inflection point IP6 may also be located in the range from the first main surface 3 to a depth of 1 nm or more and 20 nm or less. The inflection point IP6 may have a value that falls within at least one of the following ranges from the SiC interface 60 to a depth of 3 nm or more and 20 nm or less, 3 nm or more and 15 nm or less, 3 nm or more and 10 nm or less, 5 nm or more and 20 nm or less, 5 nm or more and 15 nm or less, and 5 nm or more and 10 nm or less.

[0570] Thus, at point A, the maximum value M6 or inflection point IP6 is located in the range from the first main surface 3 to a depth of 20 nm. As a result, the high concentration (for example, 1 × 10⁻¹⁶) from the first main surface 3 to a depth of 20 nm is １７ cm －３ The region described above is defined as the high-concentration region 148, and the low-concentration region (for example, 1 × 10) is defined as the region deeper than 20 nm. １７ cm －３ The region less than may be defined as the base region 147.

[0571] The thickness CT7 of the base region 147 may be, for example, 20 nm or more and 300 nm or less. The thickness CT7 of the base region 147 may have a value that falls within at least one of the following ranges: 20 nm or more and 100 nm or less, 20 nm or more and 150 nm or less, 20 nm or more and 200 nm or less, 20 nm or more and 250 nm or less, and 20 nm or more and 300 nm or less.

[0572] The thickness CT8 of the high-concentration region 148 is thinner than that of the base region 147. The thickness CT8 of the high-concentration region 148 may be, for example, 5 nm or more and 50 nm or less. The thickness CT8 of the high-concentration region 148 may have a value that falls within at least one of the following ranges: 5 nm or more and 10 nm or less, 5 nm or more and 20 nm or less, 5 nm or more and 30 nm or less, 5 nm or more and 40 nm or less, and 5 nm or more and 50 nm or less.

[0573] In this way, by setting the peak position of the donor concentration in the source region 33 to a relatively shallow region (for example, a range from the first main surface 3 to a depth of 20 nm), the source region 33 can be made thin. As a result, the design freedom of the device can be improved. For example, in the trench gate structure shown in Figure 47, by making the source region 33 shallow, the trench 26 can also be made shallow. As a result, the body region 22 (channel region 24) and the well region 30 can be positioned at a shallow position from the first main surface 3.

[0574] On the other hand, as shown in Figure 51, at point B in Figures 48 and 49, a profile PC can be observed in the depth direction from the first main surface 3 that does not have any maximum values ​​or inflection points. This is because a localized high-concentration region is formed at point B, i.e., the contact region 34.

[0575] (15) Regarding the characteristics of the outer peripheral region 21, Figure 52 is an enlarged view of the main part of the outer peripheral region 21, which corresponds to the area enclosed by LII in Figure 6. Referring to Figure 52, the semiconductor device 1A may further include a second interface semiconductor region 156 formed in the outer peripheral region 21.

[0576] The second interface semiconductor region 156 is located between the drift region 64 and the main surface insulating film 38. In this embodiment, the second interface semiconductor region 156 may be exposed from the first main surface 3 (SiC surface 59) and form a SiC interface 157 between it and the main surface insulating film 38.

[0577] The thickness CT9 of the second interface semiconductor region 156 may be, for example, 0 nm to 50 nm from the SiC interface 157. The thickness CT9 of the second interface semiconductor region 156 may have a value that falls within at least one of the following ranges from 0 nm to 10 nm, 0 nm to 20 nm, 0 nm to 30 nm, and 0 nm to 40 nm from the SiC interface 157. Preferably, the thickness CT9 of the second interface semiconductor region 156 is 5 nm to 20 nm.

[0578] In this embodiment, the second interface semiconductor region 156 is formed on the surface of the drift region 64 and the multiple field regions 37. The second interface semiconductor region 156 is formed spanning the multiple field regions 37 and the portions of the drift region 64 between them, moving from the active region 20 side toward the first to fourth side surfaces 5A to 5D of the chip 2.

[0579] The second interface semiconductor region 156 may also be defined by the distribution of donor concentrations in the depth direction from the SiC interface 157.

[0580] Figures 53A and 53B show the donor concentration profile in the depth direction at point A in Figure 52. Figure 54 shows the donor concentration profile in the depth direction at point B in Figure 52. In Figures 53A, 53B, and 54, the horizontal axis represents the depth (nm) from the first main surface 3, and the vertical axis represents the n-type impurity concentration. The profiles shown in Figures 53A, 53B, and 54 are graphs where the depth from the first main surface 3 is the horizontal axis (x-axis) and the logarithmic value of the n-type impurity concentration is the vertical axis (y-axis).

[0581] There is a difference between Figure 53A and Figure 53B in the method of calculating the numerical values ​​that form the basis of the linear profiles showing the concentration distribution. As explained using Figures 23 to 26, the profile in Figure 53A shows the distribution of donor concentrations based on the results of capacitance-voltage characteristics (C-V characteristics). On the other hand, the profile in Figure 53B is created from a plot of donor concentrations based on the results of secondary ion mass spectrometry (SIMS).

[0582] Referring to Figure 53A, the profile POA may be formed in a roughly mountain shape with a peak (maximum value M7) at a certain depth position from the first main surface 3. The profile POA may include a concentration transition section 158 containing the maximum value M7, an increasing section 159 on the first main surface 3 side of the concentration transition section 158, and a decreasing section 160 on the opposite side of the increasing section 159 from the concentration transition section 158.

[0583] The concentration transition section 158 is a convex portion that includes a series of concentration changes (inflection points) where the donor concentration shifts from increasing (increasing trend) to decreasing (decreasing trend) around the maximum value M7.

[0584] The maximum value M7 in this form is 1 × 10⁻⁶ １８ cm －３ The above 1 x 10 ２０ cm －３ The following is preferable: The maximum value M7 is 1 × 10⁻⁶ １８ cm －３ The above 1 x 10 １９ cm －３ The following, and 1 x 10 １９ cm －３ The above 1 x 10 ２０ cm －３ It may have a value that falls within at least one of the following ranges.

[0585] In this embodiment, the maximum value M7 is preferably located in the range from the first main surface 3 to a depth of 20 nm. The maximum value M7 may also be located in the range from the first main surface 3 to a depth of 1 nm or more and 20 nm or less. The maximum value M7 may have a value that belongs to at least one of the following ranges from the first main surface 3 to a depth of 3 nm or more and 20 nm or less, 3 nm or more and 15 nm or less, 3 nm or more and 10 nm or less, 5 nm or more and 20 nm or less, 5 nm or more and 15 nm or less, and 5 nm or more and 10 nm or less. The concentration transition section 158 including the maximum value M7 may, for example, be in the range of 0.5 nm or more and 10 nm or less that straddles the maximum value M7 above and below in the depth direction.

[0586] The gradually increasing portion 159 may be in a range of 0.5 nm to 5 nm in the depth direction from the first main surface 3. The range of donor concentrations in the gradually increasing portion 159 is smaller than the range of donor concentrations in the concentration transition portion 158.

[0587] Referring to Figure 53B, the profile POB includes an upper curved section 161 and a lower curved section 162. The upper curved section 161 slopes downward from the high-concentration side to the low-concentration side. In this embodiment, the upper curved section 161 is formed as an upper convex section having a first curvatured section 163 that is convex toward the low-concentration side. The lower curved section 162 slopes downward from the high-concentration side to the low-concentration side in a deeper region than the upper curved section 161. In this embodiment, the lower curved section 162 is formed as a lower convex section having a second curvatured section 164 that is convex toward the high-concentration side.

[0588] The upper curved section 161 and the lower curved section 162 are continuous via an inflection point IP7. The inflection point IP7 may be the point where the curvature of the profile POB changes from the first curvature section 163 to the second curvature section 164 (or, in other words, from the second curvature section 164 to the first curvature section 163).

[0589] The inflection point IP7 is located at approximately the same depth as the maximum value M7 in Figure 53A. In this configuration, the inflection point IP7 is 1 × 10⁻⁶ １８ cm －３ The above 1 x 10 ２０ cm －３ The following is preferable: The inflection point IP7 is 1 × 10 １８ cm －３ The above 1 x 10 １９ cm －３ The following, and 1 x 10 １９ cm －３ The above 1 x 10 ２０ cm －３ It may have a value that falls within at least one of the following ranges.

[0590] In this embodiment, the inflection point IP7 is preferably located in the range from the first main surface 3 to a depth of 20 nm. The inflection point IP7 may also be located in the range from the first main surface 3 to a depth of 1 nm or more and 20 nm or less. The inflection point IP7 may have a value that falls within at least one of the following ranges from the SiC interface 60 to a depth of 3 nm or more and 20 nm or less, 3 nm or more and 15 nm or less, 3 nm or more and 10 nm or less, 5 nm or more and 20 nm or less, 5 nm or more and 15 nm or less, and 5 nm or more and 10 nm or less.

[0591] Thus, at point A, the maximum value M7 or inflection point IP7 is located in the range from the first main surface 3 to a depth of 20 nm. As a result, the high concentration (for example, 1 × 10⁻¹⁶) from the first main surface 3 to a depth of 20 nm is １８ cm －３ The region described above may be defined as the second interface semiconductor region 156.

[0592] In this way, by forming a second interface semiconductor region 156 in the outer peripheral region 21, the charge distribution near the SiC interface 157 can be adjusted. This makes it possible to suppress ion penetration into the SiC interface 157, for example, in a high-humidity environment, thereby suppressing device degradation.

[0593] On the other hand, as shown in Figure 54, at point B in Figure 52, a profile POC can be observed in the depth direction from the first main surface 3 that does not have any maximum values ​​or inflection points. This is because a second interface semiconductor region 156 is formed at point B, for example, in the outer well region 35. Note that a second interface semiconductor region 156 may also be formed in the outer well region 35.

[0594] While embodiments of this disclosure have been described, this disclosure can also be implemented in other forms.

[0595] Each of the above-described embodiments (including variations) can be implemented in other forms. The features of the above-described semiconductor devices 1A to 1G (including variations) can be combined as appropriate. Semiconductor devices 1A to 1G may simultaneously include two, three, four, five, or six of the features of the semiconductor devices 1A to 1G (including variations).

[0596] In each of the above-described embodiments, a structure may be adopted in which the conductivity type of the n-type semiconductor region is inverted to p-type, and the conductivity type of the p-type semiconductor region is inverted to n-type. In this case, the specific configuration can be obtained by replacing n-type with p-type and simultaneously replacing p-type with n-type, as shown in the above description and attached drawings.

[0597] In the embodiments described above, an n-type first semiconductor layer 6 was shown. However, the conductivity type of the first semiconductor layer 6 may be p-type. In this case, an IGBT (Insulated Gate Bipolar Transistor) structure is formed instead of the MISFET structure. In this case, as described above, the "source" of the MISFET structure is replaced by the "emitter" of the IGBT structure, and the "drain" of the MISFET structure is replaced by the "collector" of the IGBT structure.

[0598] The following are examples of features extracted from this specification and drawings. The alphanumeric characters in parentheses below represent the corresponding components of the aforementioned forms, but this is not intended to limit the scope of each item (Clause) to the aforementioned forms. The term "semiconductor device" in the following items may be replaced with "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "semiconductor rectifier," etc., as needed.

[0599] <Regarding the series described in Appendix 1> The embodiments described in Appendix 1-1 to Appendix 1-25 provide a semiconductor device that can improve the channel mobility of a SiC transistor and suppress the decrease in threshold.

[0600] [Appendix 1-1] A semiconductor device comprising: a SiC layer; a first semiconductor region of a first conductivity type formed within the SiC layer; a second semiconductor region of a second conductivity type in contact with the first semiconductor region within the SiC layer; a third semiconductor region of a first conductivity type in contact with the second semiconductor region within the SiC layer; an insulating film formed on the surface of the SiC layer so as to cover at least the second semiconductor region; and a control electrode to which a voltage is applied, facing the second semiconductor region via the insulating film and forming a channel of a first conductivity type that conducts the first semiconductor region and the third semiconductor region, wherein the first profile of the first conductivity type impurity in the depth direction from the SiC interface between the SiC layer and the insulating film toward the interior of the second semiconductor region has a maximum value or inflection point in the range from the SiC interface to a depth of 20 nm.

[0601] [Appendix 1-2] The semiconductor device according to Appendix 1-1, further comprising an interface semiconductor region formed near the SiC interface, where the maximum value or inflection point of the first profile is located.

[0602] [Appendix 1-3] The semiconductor device according to Appendix 1-2, wherein the interface semiconductor region includes a region where the width between two points enclosing the depth position of the maximum value or the inflection point is 0.5 nm or more and 10 nm or less.

[0603] [Appendix 1-4] The semiconductor device according to Appendix 1-2 or Appendix 1-3, wherein the interface semiconductor region includes an impurity region having a higher impurity concentration of a first conductivity type than the first semiconductor region.

[0604] [Appendix 1-5] The semiconductor device according to Appendix 1-2 or Appendix 1-3, wherein the interface semiconductor region includes an impurity layer having a higher concentration of first conductivity type impurities than the first semiconductor region.

[0605] [Appendix 1-6] The semiconductor device according to any one of Appendix 1-1 to 1-5, wherein the impurity concentration of the first conductivity type at the maximum value or inflection point of the first profile is higher than the impurity concentration of the second conductivity type in the second semiconductor region.

[0606] [Note 1-7] The impurity concentration of the first conductivity type at the maximum value or inflection point of the first profile is 1 × 10 １８ cm －３ The above 1 x 10 ２０ cm －３ The following applies, and the impurity concentration of the second conductivity type in the second semiconductor region is 1 × 10⁻⁶ １５ cm －３ The above 1 x 10 １８ cm －３ The following semiconductor device as described in any one of the appendices 1-1 to 1-6.

[0607] [Appendix 1-8] The semiconductor device according to any one of Appendix 1-1 to 1-7, wherein the impurity concentration of the first conductivity type at the maximum value or inflection point of the first profile is lower than the impurity concentration of the first conductivity type in the third semiconductor region.

[0608] [Appendix 1-9] The semiconductor device according to any one of Appendix 1-1 to 1-8, wherein the first profile includes a gradually increasing portion in the depth direction from the SiC interface where the impurity concentration of the first conductivity type gradually increases, a gradually decreasing portion in a region deeper than the gradually increasing portion where the impurity concentration of the first conductivity type gradually decreases, and a convex concentration transition portion in the region where the impurity concentration of the first conductivity type transitions from the gradually increasing portion to the gradually decreasing portion, and the first profile has a peak in the concentration transition portion as the maximum value.

[0609] [Appendix 1-10] The semiconductor device according to Appendix 1-9, wherein the first profile shows the impurity concentration of the first conductivity type obtained from the capacitance-voltage characteristics between the control electrode and the second semiconductor region.

[0610] [Appendix 1-11] The semiconductor device according to any one of Appendix 1-1 to 1-8, wherein the first profile includes an upper curved portion where the impurity concentration of the first conductivity type slopes downward from a high concentration side to a low concentration side, and a lower curved portion where the impurity concentration of the first conductivity type slopes downward from a high concentration side to a low concentration side in a region deeper than the upper curved portion, and the first profile has an inflection point where the curvature changes from the curvature of the upper curved portion to the curvature of the lower curved portion as the inflection point.

[0611] [Appendix 1-12] The semiconductor device according to Appendix 1-11, wherein the upper curved portion includes an upper convex portion having a first curvature portion that is convex toward the low concentration side, and the lower curved portion includes a lower convex portion having a second curvature portion that is convex toward the high concentration side.

[0612] [Appendix 1-13] The semiconductor device according to Appendix 1-11 or Appendix 1-12, wherein the first profile indicates the impurity concentration of the first conductivity type obtained from the results of secondary ion mass spectrometry (SIMS).

[0613] [Appendix 1-14] The semiconductor device according to any one of the appendices 1-1 to 1-13, wherein the first profile has the maximum value or the inflection point in a range of 3 nm to 10 nm in depth from the SiC interface.

[0614] [Appendix 1-15] The semiconductor device according to any one of Appendix 1-1 to 1-14, wherein the first conductivity type is n-type, the second conductivity type is p-type, and the first profile shows the concentration of at least one impurity from N, P, As, Sb, and S as the first conductivity type impurity.

[0615] [Note 1-16] The insulating film is SiO ２ A semiconductor device including a film, as described in any one of the appendices 1-1 to 1-15.

[0616] [Appendix 1-17] The semiconductor device according to Appendix 1-1, comprising a trench structure including a trench formed in the SiC layer, an insulating film formed on the inner surface of the trench, and a control electrode embedded in the trench via the insulating film, wherein the first semiconductor region, the second semiconductor region, and the third semiconductor region are arranged in this order from the bottom of the trench along the side surface of the trench, the SiC interface includes a side interface between the side surface of the trench and the insulating film, and a bottom interface between the bottom surface of the trench and the insulating film, and the first profile has the maximum value or the inflection point in the range from the side interface to a depth of 20 nm among the side interface and the bottom interface.

[0617] [Appendix 1-18] The semiconductor device according to Appendix 1-17, wherein the second profile of the first conductivity type impurity in the depth direction from the bottom interface toward the interior of the SiC layer does not have a maximum value or inflection point in the range from the bottom interface to a depth of 20 nm.

[0618] [Appendix 1-19] The semiconductor device according to Appendix 1-17 or Appendix 1-18, further comprising an interface semiconductor region formed near the lateral interface, where the maximum value or inflection point of the first profile is located.

[0619] [Appendix 1-20] The semiconductor device according to Appendix 1-19, wherein the interface semiconductor region spans the first semiconductor region, the second semiconductor region, and the third semiconductor region in the depth direction of the trench.

[0620] [Appendix 1-21] The semiconductor device according to Appendix 1-1, comprising a planar structure including the insulating film formed on the main surface of the SiC layer and the control electrode formed on the insulating film, wherein the first semiconductor region, the second semiconductor region and the third semiconductor region are arranged in this order along the main surface of the SiC layer, the SiC interface includes a first interface between the main surface and the insulating film in the first semiconductor region, a second interface between the main surface and the insulating film in the second semiconductor region, and a third interface between the main surface and the insulating film in the third semiconductor region, and the first profile has the maximum value or the inflection point in the range from the second interface to a depth of 20 nm among the first to third interfaces.

[0621] [Appendix 1-22] The semiconductor device according to Appendix 1-21, wherein the second profile of the first conductivity type impurity in the depth direction from the first interface toward the interior of the first semiconductor region does not have a maximum value or inflection point in the range from the first interface to a depth of 20 nm.

[0622] [Appendix 1-23] The semiconductor device according to Appendix 1-21 or Appendix 1-22, further comprising a fourth impurity region of a second conductivity type with a higher concentration than the second semiconductor region, formed on the main surface of the SiC layer and connected to the second semiconductor region, wherein the third profile of the first conductivity type impurity in the depth direction from the main surface of the SiC layer toward the interior of the fourth semiconductor region does not have a maximum value or inflection point in the range from the main surface to a depth of 20 nm.

[0623] [Appendix 1-24] The semiconductor device according to any one of Appendix 1-21 to 1-23, further comprising an interface semiconductor region selectively formed on the second semiconductor region among the first semiconductor region, the second semiconductor region and the third semiconductor region on the main surface of the SiC layer, where the maximum value or the inflection point of the first profile is located.

[0624] [Appendix 1-25] The semiconductor device according to Appendix 1-24, wherein the interface semiconductor region includes a convex portion that protrudes above the main surface of the first semiconductor region and the third semiconductor region.

[0625] <Regarding the Appendix 2 Series> The embodiments described in Appendix 2-1 to Appendix 2-16 provide a semiconductor device that can improve the channel mobility of a SiC transistor and suppress the decrease in threshold voltage.

[0626] [Appendix 2-1] A semiconductor device comprising: a SiC layer; a first semiconductor region of a first conductivity type formed within the SiC layer; a second semiconductor region of a second conductivity type in contact with the first semiconductor region within the SiC layer; an insulating film covering at least the second semiconductor region; and a control electrode facing the second semiconductor region via the insulating film, to which a voltage is applied to form a channel of the first conductivity type in the second semiconductor region, wherein the capacitance-voltage characteristic curve between the control electrode and the second semiconductor region has a change section in which the slope changes from a steep first line to a gentle second line with respect to the horizontal axis of the graph between a depletion voltage section in which the SiC interface between the second semiconductor region and the insulating film is in a depletion state and an inversion voltage section in which the SiC interface is in an inversion state.

[0627] [Note 2-2] The semiconductor device according to Note 2-1, wherein in the change interval, the voltage range from one end of the second line on the first line side to the other end of the inverting capacitance line side indicating the capacitance value in the inverting voltage interval is 3V or more and 10V or less.

[0628] [Appendix 2-3] The semiconductor device according to Appendix 2-1 or Appendix 2-2, wherein the second line is inclined with respect to the capacitance value Cinv of the inverting capacitance line at an angle of Cinv / 1000V or more and Cinv / 10V or less.

[0629] [Appendix 2-4] The semiconductor device according to any one of Appendix 2-1 to 2-3, wherein the change interval includes a first voltage interval on which the first line is located and a second voltage interval on which the second line is located, and the second voltage interval is wider than the depletion voltage interval.

[0630] [Appendix 2-5] The semiconductor device described in Appendix 2-4, wherein the voltage width of the second voltage section is 3V or more and 10V or less, and the voltage width of the depletion voltage section is 1V or more and 5V or less.

[0631] [Appendix 2-6] The semiconductor device according to any one of Appendix 2-1 to 2-5, wherein the capacitance-voltage characteristic curve further has a second change interval in which the slope of the horizontal axis of the graph changes from a steep third line to a gentler fourth line between the storage voltage interval in which the SiC interface is in a storage state and the depletion voltage interval.

[0632] [Appendix 2-7] A semiconductor device comprising: a SiC layer; a first semiconductor region of a first conductivity type formed within the SiC layer; a second semiconductor region of a second conductivity type in contact with the first semiconductor region within the SiC layer; an insulating film covering at least the second semiconductor region; and a control electrode facing the second semiconductor region via the insulating film, to which a voltage is applied to form a channel of the first conductivity type in the second semiconductor region, wherein the capacitance-voltage characteristic curve between the control electrode and the second semiconductor region has a transition voltage width of 3V or more in the transition section from a depletion voltage section where the SiC interface between the second semiconductor region and the insulating film is in a depleted state to an inversion voltage section where the SiC interface is in an inversion state, before asymptotically approaching an inversion capacitance line indicating the capacitance value in the inversion voltage section.

[0633] [Note 2-8] The semiconductor device described in Note 2-7, wherein the transition voltage range is 3V or more and 10V or less.

[0634] [Appendix 2-9] The semiconductor device according to any one of Appendix 2-2, Appendix 2-3, Appendix 2-7, and Appendix 2-8, wherein the inverting capacitance line is in the range where the change in capacitance value with respect to the change in voltage of 10V is 20% or less.

[0635] [Appendix 2-10] The semiconductor device according to any one of Appendix 2-1 to 2-9, wherein the first profile of the first conductivity type impurity in the depth direction from the SiC interface toward the interior of the second semiconductor region has a maximum value or inflection point in the range from the SiC interface to a depth of 20 nm, and further includes an interface semiconductor region formed near the SiC interface where the maximum value or inflection point of the first profile is located.

[0636] [Appendix 2-11] The semiconductor device according to Appendix 2-10, wherein the impurity concentration of the first conductivity type at the maximum value or inflection point of the first profile is higher than the impurity concentration of the second conductivity type in the second semiconductor region.

[0637] [Note 2-12] The impurity concentration o...

Claims

1. A semiconductor device comprising: a SiC layer; a first semiconductor region of a first conductivity type formed within the SiC layer; a second semiconductor region of a second conductivity type in contact with the first semiconductor region within the SiC layer; a third semiconductor region of a first conductivity type in contact with the second semiconductor region within the SiC layer; an insulating film formed on the surface of the SiC layer so as to cover at least the second semiconductor region; and a control electrode to which a voltage is applied, facing the second semiconductor region via the insulating film and forming a channel of a first conductivity type that conducts the first semiconductor region and the third semiconductor region, wherein the first profile of a first conductivity type impurity in the depth direction from the SiC interface between the SiC layer and the insulating film toward the interior of the second semiconductor region has a maximum value or inflection point in the range from the SiC interface to a depth of 20 nm.

2. The semiconductor device according to claim 1, further comprising an interface semiconductor region formed near the SiC interface, where the maximum value or inflection point of the first profile is located.

3. The semiconductor device according to claim 2, wherein the interface semiconductor region includes a region with a width of 0.5 nm or more and 10 nm or less between two points that straddle the depth position of the maximum value or the inflection point.

4. The semiconductor device according to claim 2 or 3, wherein the interface semiconductor region includes an impurity region having a higher impurity concentration of a first conductivity type than the first semiconductor region.

5. The semiconductor device according to claim 2 or 3, wherein the interface semiconductor region includes an impurity layer having a higher concentration of first conductivity type impurities than the first semiconductor region.

6. The semiconductor device according to any one of claims 1 to 5, wherein the impurity concentration of the first conductivity type at the maximum value or inflection point of the first profile is higher than the impurity concentration of the second conductivity type in the second semiconductor region.

7. The impurity concentration of the first conductivity type at the maximum value or inflection point of the first profile is 1 × 10⁻⁶ １８ cm －３ The above 1 x 10 ２０ cm －３ The following applies, and the impurity concentration of the second conductivity type in the second semiconductor region is 1 × 10⁻⁶ １５ cm －３ The above 1 x 10 １８ cm －３ The semiconductor device according to any one of claims 1 to 6, which is as follows:

8. The semiconductor device according to any one of claims 1 to 7, wherein the impurity concentration of the first conductivity type at the maximum value or inflection point of the first profile is lower than the impurity concentration of the first conductivity type in the third semiconductor region.

9. The semiconductor device according to any one of claims 1 to 8, wherein the first profile includes a gradually increasing portion in the depth direction from the SiC interface in which the impurity concentration of the first conductivity type gradually increases, a gradually decreasing portion in a region deeper than the gradually increasing portion in which the impurity concentration of the first conductivity type gradually decreases, and a convex concentration transition portion in the region where the impurity concentration of the first conductivity type transitions from the gradually increasing portion to the gradually decreasing portion, and the first profile has a peak in the concentration transition portion as the maximum value.

10. The semiconductor device according to claim 9, wherein the first profile shows the impurity concentration of the first conductivity type obtained from the capacitance-voltage characteristics between the control electrode and the second semiconductor region.

11. The semiconductor device according to any one of claims 1 to 8, wherein the first profile includes an upper curved portion in which the impurity concentration of the first conductivity type slopes downward from a high concentration side to a low concentration side, and a lower curved portion in which the impurity concentration of the first conductivity type slopes downward from a high concentration side to a low concentration side in a region deeper than the upper curved portion, and the first profile has an inflection point in which the curvature changes from the curvature of the upper curved portion to the curvature of the lower curved portion.

12. The semiconductor device according to claim 11, wherein the upper curved portion includes an upper convex portion having a first curvature portion that is convex toward the low concentration side, and the lower curved portion includes a lower convex portion having a second curvature portion that is convex toward the high concentration side.

13. The semiconductor device according to claim 11 or 12, wherein the first profile shows the impurity concentration of the first conductivity type obtained from the results of secondary ion mass spectrometry (SIMS).

14. The semiconductor device according to any one of claims 1 to 13, wherein the first profile has the maximum value or the inflection point in a range of 3 nm to 10 nm in depth from the SiC interface.

15. The semiconductor device according to any one of claims 1 to 14, wherein the first conductivity type is n-type, the second conductivity type is p-type, and the first profile shows the concentration of at least one impurity from N, P, As, Sb, and S as the first conductivity type impurity.

16. The insulating film is SiO ２ film, and the semiconductor device according to any one of claims 1 to 15.

17. A semiconductor device according to claim 1, comprising a trench structure including a trench formed in the SiC layer, an insulating film formed on the inner surface of the trench, and a control electrode embedded in the trench via the insulating film, wherein the first semiconductor region, the second semiconductor region, and the third semiconductor region are arranged in this order from the bottom of the trench along the side surface of the trench, the SiC interface includes a side interface between the side surface of the trench and the insulating film, and a bottom interface between the bottom surface of the trench and the insulating film, and the first profile has the maximum value or the inflection point in the range from the side interface to a depth of 20 nm among the side interface and the bottom interface.

18. The semiconductor device according to claim 17, wherein the second profile of the first conductivity type impurity in the depth direction from the bottom interface toward the interior of the SiC layer does not have a maximum value or inflection point in the range from the bottom interface to a depth of 20 nm.

19. The semiconductor device according to claim 17 or 18, further comprising an interface semiconductor region formed near the lateral interface, where the maximum value or inflection point of the first profile is located.

20. The semiconductor device according to claim 19, wherein the interface semiconductor region spans the first semiconductor region, the second semiconductor region and the third semiconductor region in the depth direction of the trench.

21. A semiconductor device according to claim 1, comprising a planar structure including the insulating film formed on the main surface of the SiC layer and the control electrode formed on the insulating film, wherein the first semiconductor region, the second semiconductor region and the third semiconductor region are arranged in this order along the main surface of the SiC layer, the SiC interface includes a first interface between the main surface and the insulating film in the first semiconductor region, a second interface between the main surface and the insulating film in the second semiconductor region, and a third interface between the main surface and the insulating film in the third semiconductor region, and the first profile has the maximum value or the inflection point in the range from the second interface to a depth of 20 nm among the first to third interfaces.

22. The semiconductor device according to claim 21, wherein the second profile of the first conductivity type impurity in the depth direction from the first interface toward the interior of the first semiconductor region does not have a maximum value or inflection point in the range from the first interface to a depth of 20 nm.

23. The semiconductor device according to claim 21 or 22, further comprising a fourth impurity region of a second conductivity type having a higher concentration than the second semiconductor region, formed on the main surface of the SiC layer and connected to the second semiconductor region, wherein the third profile of the first conductivity type impurity in the depth direction from the main surface of the SiC layer toward the interior of the fourth semiconductor region does not have a maximum value or inflection point in the range from the main surface to a depth of 20 nm.

24. The semiconductor device according to any one of claims 21 to 23, further comprising an interface semiconductor region selectively formed on the second semiconductor region among the first semiconductor region, the second semiconductor region and the third semiconductor region on the main surface of the SiC layer, where the maximum value or inflection point of the first profile is located.

25. The semiconductor device according to claim 24, wherein the interface semiconductor region includes a convex portion that protrudes above the main surface of the first semiconductor region and the third semiconductor region.

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