Processor with time tracking of cache events to reduce unnecessary pipeline flushing

Abstract

A processor includes a processing core including a control circuit. The control circuit is configured to: determine a first information associated with a fill time of a first cache line, wherein the fill time comprises a time when the cache line fills or enters an entry in a cache of the processing core; determine a first load operation that uses or accesses the first cache line; determine whether there has been a load-load memory ordering violation based on whether there is a younger load operation in the processing core that: is younger than the first load operation, completed before the first load operation was completed, and a cache line of the younger load operation was invalidated before the fill time of the first cache line; and if there has not been a load-load memory ordering violation, then cancel a flush of instruction processing pipeline for the processing core.

Description

Attorney Docket No. 0237-013 WO 1PROCESSOR WITH TIME TRACKING OF CACHE EVENTS TO REDUCE UNNECESSARY PIPELINE FLUSHINGCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. provisional patent application no. 63 / 698,873 filed on September 25, 2024, entitled “PROCESSOR WITH TIME TRACKING OF CACHE EVENTS TO REDUCE UNNECESSARY PIPELINE FLUSHING” the disclosure of which is hereby incorporated by reference in its entirety.TECHNICAL FIELD

[0002] This description relates to computer processing apparatuses, such as microprocessors, processors, central processing units, and the like. More specifically, this disclosure relates to computer processing apparatuses, and associated systems and methods for improving processing performance by cancelling of an unnecessary flushing of an instruction processing pipeline.BACKGROUND

[0003] Processors, such as processors implemented in computing systems, can include instruction processing pipelines (pipelines) for processing instructions, e.g., machine- readable instructions of a software program. For instance, processors, such as RISC-V®, processors, x86 processors, ARM® processors, Power® processors, etc., can include circuitry implementing one or more pipelines for processing instructions.

[0004] A program may include many instructions, and these instructions are provided in a program order. For example, instruction iO may be a first instruction, instruction il is the second instruction, instruction i2 is the third instruction, in the program order, . . . and instruction i455 is the last instruction in this program. Instruction iO is the oldest instruction in the program, and instruction i455 is the youngest (or most recent) instruction in this example program. Thus, instruction iO is older than instruction il because instruction iO occurs earlier in program order than instruction il. Likewise, instruction il is younger than instruction iO because instruction il occurs later (or more recently) in program order than instruction iO. Similarly, instruction iO is older than instruction i2, and instruction i2 is younger than instruction iO, in this example. Thus, in this example, an older instructionAttorney Docket No. 0237-013 WO 1 occurs earlier in the program order, and a younger instruction occurs later or more recently in program order.

[0005] An instruction processing pipeline may be, for example, a sequential, multistage instruction processing pipeline that includes a plurality of sequential stages for processing and / or executing instructions.

[0006] Some example instructions in a program may include load operations and store operations. Load operations are operations that cause a read of data from memory, e.g., into a processor register. Store operations are operations that cause a write of data into memory. Load operations may be performed out of order. However, in some situations, the out of order execution of load operations may cause a memory ordering violation. The memory ordering violation may cause the processor to flush (or delete one or more instructions from) the instruction processing pipeline, e.g., beginning with the instruction that caused the memory ordering violation. Such pipeline flushes can negatively impact execution performance of the program by the processor, as execution cycles used for processing instructions flushed from the pipeline are wasted, as those instructions do not complete processing in the pipeline, e.g., are flushed out of the pipeline at whatever pipeline stage they are currently at when the flush occurs. Therefore, a flush of an instruction processing pipeline should be avoided when possible because a flush may cause a significant hit to processor performance.SUMMARY

[0007] In a general aspect, a processor includes a processing core, the processing core including a control circuit configured to: determine a first information associated with a fill time of a first cache line, wherein the fill time comprises a time when the first cache line fills or enters an entry in a cache for the processing core; determine a first load operation that uses or accesses the first cache line; confirm that there is not a younger load operation in the processing core that: is younger than the first load operation, completed before the first load operation was completed, and a cache line of the younger load operation was invalidated before the fill time of the first cache line; and send a signal to cancel a flush of instruction processing pipeline of the processing core, or omit performing a flush of instruction processing pipeline of the processing core based on the confirming.

[0008] In another general aspect a processor includes a processing core including a control circuit, wherein the control circuit is configured to: determine a first informationAttorney Docket No. 0237-013 WO 1 associated with a fill time of a first cache line, wherein the fill time comprises a time when the cache line fills or enters an entry in a cache of the processing core; determine a first load operation that uses or accesses the first cache line; determine, based on at least the first information, whether there has been a load-load memory ordering violation based on whether there is a younger load operation in the processing core that: is younger than the first load operation, completed before the first load operation was completed, and a cache line of the younger load operation was invalidated before the fill time of the first cache line; and if there has not been a load-load memory ordering violation, then send a signal to a pipeline flush controller for the processing core to cancel a flush of instruction processing pipeline of the processing core, or omit performing the flush of instruction processing pipeline of the processing core.

[0009] In another general aspect a processor includes a processing core; the processing core comprising a control circuit configured to: determine a first load operation associated with a first cache line; with respect to performing or completing the first load operation, detect that the fill time of the first cache line into the core is older than all instructions in a re-order buffer (ROB) of the processing core, including older than all load operations in the ROB; and based on detecting that the first cache line being older than all instructions in the ROB, send a signal to cancel or omit performing a flush of instruction processing pipeline that may have been triggered based on the first load operation.

[0010] In another general aspect a processor includes a processing core comprising a control circuit configured to: determine a first load operation associated with a first cache line; upon detecting that a re-order buffer (ROB) retirement index value has wrapped once in the ROB of the processing core since the first cache line was filled into the processing core, set an old bit or old flag for the first cache line indicating that the first cache line stored in a cache of the processing core is older than all instructions in the ROB, and thus indicating that a fill time for the first cache line into a cache of the processing core occurred before any load operations in the ROB or processing core may have been invalidated; with respect to or during performing or completing the first load operation, detect that the old bit or old flag for the first cache line is set to indicate that the first cache line is older than all instructions in the ROB; and send a signal to cancel a flush of instruction processing pipeline of the processing core, or omit performing a flush of instruction processing pipeline of the processing core based on detecting that the old bit or old flag for the first cache line being set to indicate that the first cache line is older than all instructions in the ROB.Attorney Docket No. 0237-013 WO 1BRIEF DESCRIPTION OF THE DRAWINGS

[0011] FIG. l is a diagram illustrating a system including a multi-core processor according to an example embodiment.

[0012] FIG. 2A is a diagram illustrating a core (or processing core) of a multi-core processor, according to an example embodiment.

[0013] FIG. 2B is a diagram illustrating a core (or processing core) of a multi-core processor, according to another example embodiment.

[0014] FIG. 3 is a diagram illustrating an example in which there is not a load-load memory ordering violation based on relative timing of events of an older load operation and a younger load operation.

[0015] FIG. 4 is a diagram illustrating an example in which there is a load-load memory ordering violation based on relative timing of events of an older load operation and a younger load operation.

[0016] FIG. 5 is a diagram illustrating a system according to an example embodiment, including at least a portion of a core and a cache, according to the diagram of FIG. 2 A.

[0017] FIG. 6 is a diagram illustrating aspects of a cache time tracker according to an example embodiment.

[0018] FIG. 7 is a diagram illustrating an example architecture of a computing device, which can be used to implement aspects according to the present disclosure.

[0019] Like reference symbols in the various drawings indicate like and / or similar elements.DETAILED DESCRIPTION

[0020] This disclosure relates to computer processing apparatuses, such as processors, multi-core processors, microprocessors, central processing units, graphics processing units, tensor processing units, and accelerators, etc. (hereafter “processor(s)”), and related systems and methods, that can improve processor execution performance by reducing occurrence of instruction processing pipeline flushes.

[0021] Computing systems or processors (that include multiple processing cores or cores) may include one or more memory ordering requirements (or memory ordering restrictions). Memory ordering may be considered an agreement or contract between hardware and software on how loads and stores will interact with each other, generally in the context of multiple cores or multiple processors. Stronger memory ordering models allowAttorney Docket No. 0237-013 WO 1 less loads / stores to be re-ordered by hardware. Weaker memory ordering models (such as the weak memory ordering (WMO) model) allow hardware to squeeze out more performance by allowing loads and stores to be performed more out of order. Weaker memory ordering models allow more loads / stores to be re-ordered by hardware. Total Store Order (TSO) is an example of a stronger (or stricter) memory ordering model than WMO. Different processors or computing systems may include different memory ordering requirements. But most processors or computing systems will include at least some level of memory ordering requirements. The embodiments and techniques described herein are not limited to any particular memory ordering model (such as TSO), but may be applied to any memory ordering model.

[0022] As an example, TSO (Total Store Order) is a stronger memory ordering model than WMO (weak memory order). TSO, for example, may ensure that all stores are seen in the same order in memory as from each core. That is, stores are typically required to be performed in order. Also, in TSO, loads may be speculatively performed out of order. That is in TSO, loads can be speculatively reordered to improve performance. If a load-load reordering is seen by other cores, speculative loads must typically be squashed or deleted (flush of the instruction processing pipeline) and re-executed. Different processors or computing systems may have different memory ordering requirements. TSO is merely one illustrative example of memory ordering requirements.

[0023] A processor may include a plurality of processing cores (which may also be referred to as cores). Each processing core may include its own cache (e.g., data cache). In some cases, an out of order execution of load operations may cause a memory ordering violation, such as a load-load memory ordering violation, in which two out of order loads may cause (at least in some cases) a memory ordering violation. The memory ordering violation may typically cause a processor to flush the instruction processing pipeline. For example, at in least some processors, in order to maintain total store order (TSO), a memory ordering violation may be detected based on a younger load operation in the core, which is younger than a first (or older) load operation, which has completed before the first load operation in the core has completed, and the younger load operation’s cache line has been invalidated. However, as described in greater detail below, not all cases of this situation are actually a load-load memory ordering violation. Rather, in some cases, the timing of certain events (e.g., timing of certain cache events, or cache-related events) may indicate that this series of events is not actually a load-load memory ordering violation, and the flush of theAttorney Docket No. 0237-013 WO 1 instruction pipeline can (or should) be cancelled.

[0024] For example, techniques described herein may include a processing core (or core) that includes a control circuit that may track or determine one or more times (or information associated with times / timings) of events. The control circuit may be configured to determine whether there has been a load-load memory ordering violation based on whether there is a younger load operation in the core that: is younger than a first load operation (wherein the first load operation is associated with or has used or accessed the first cache line), completed before the first load operation was completed, and a cache line of the younger load operation was invalidated before the fill time of the first cache line. For example, there is a load-load memory ordering violation if the younger load operation (younger than the first load operation, and which completed before the first load operation) was invalidated before a fill time of the first cache line. If there has not been a load-load memory ordering violation, the control circuit may send a signal to cancel a flush of instruction processing pipeline, or omit performing the flush of instruction processing pipeline. Therefore, in order to determine whether there has been a load-load memory ordering violation, the control circuit may determine the relative timing or order (e.g., which of these events occurred first) of: 1) (tO) the fill time of the first cache line (which may be associated with the first load operation, e.g., the first cache line may be accessed by the first load operation or may have been filled based on the first load operation), and 2) (tl) the invalidation time of any younger load operation’s cache line within the core (which are younger than the first load operation, and were completed before the first load operation completed, and were invalidated).

[0025] Thus, in an illustrative example, the control circuit may track or determine two pieces (or types) of timing information for load operations, including: 1) a first information associated with a fill time (tO) of each cache line, e.g., where the fill time may include a time when the cache line fills or enters an entry in a cache of a processing core. The fill time may, for example, be a time when the cache line fills an entry of the cache based on a load operation, or based on another event or instruction. The first load operation may become associated with the cache line, e.g., by accessing or using the first cache line, or by causing the first cache line to be filled into the cache entry (by the first load operation). And, 2) a second information associated with an invalidation time (tl) for one or more load operations that have completed and had their cache lines invalidated or victimized from the core (e.g., either cache line was evicted from the cache, e.g., based on a least recently used (LRU)Attorney Docket No. 0237-013 WO 1 algorithm, or was snooped out of the cache by another processing core). The relative timing of these two events (or these two types of events) may be used by the control circuit to determine whether there has been a load-load memory ordering violation, based on the first load operation and the younger load operation. For example, the first information may be associated with or may indicate a fill time (tO) (e.g., which may be an actual fill time such as a time stamp, or information that may indicate relative time or relative timing, such as a retirement index value when the cache line was filled) of a cache line, or may be or may include an old bit or old flag of a cache line indicating whether the cache line is older than all instructions (including all load operations) in a re-order buffer (ROB) of the processing core. Also, for example, the second information may be associated with or may indicate an invalidation time (tl), which may be, e.g., an actual invalidation time such as a time stamp at the time of invalidation, or information indicating a relative time or relative timing of invalidation, such as a retirement index value when the load operation was invalidated or victimized.

[0026] In another example, a processor may include a control circuit configured to: with respect to or during performing or completing the first load operation, detect that an old bit or old flag for a first cache line is set to indicate that the first cache line is older than all instructions in the ROB (and thus, indicating that a fill time for the first cache line into a cache of the processing core occurred before any load operations in the ROB or processing core may have been invalidated); and send a signal to cancel a flush of instruction processing pipeline of the processing core, or omit performing a flush of instruction processing pipeline.

[0027] In some processor architectures, a MESI (modified, exclusive, shared, invalid) cache protocol (or simply the MESI protocol), or other protocol or approach may be used to track status of cache lines or maintain cache coherency among the local or LI data caches of each processing core (core) and the main memory. As used herein, the term cache, data cache, local cache, processing core’s data cache, LI cache, LI data cache, may refer to the local data cache used by or associated with each of the processing cores. The MESI cache protocol, as an illustrative example, may be an invalidate-based cache coherence protocol, and is one of the most common protocols that support write-back caches. The data caches (e.g., LI cache, data cache, local cache) associated with each processing core may be, e.g., provided to service memory data read and write requests originated as a result of code execution. Each cache line storage location within the core’s data cache can currently be in one of four possible states, for example, according to the MESI protocol: Modified (M): TheAttorney Docket No. 0237-013 WO 1 cache line is valid and is present only in the current cache (this core’s LI data cache) and is dirty, meaning that this cache line has been updated by this processing core since it was read into the core’s processing LI data cache, and no other core has a copy of the cache line in its cache; Exclusive (E): The cache line is valid present only in the current cache, and is clean (meaning that it matches what is in main memory); Shared state (S): The cache line is valid, still the same as main memory, and one or more other cores / processing cores (each having their own data cache) may have copies of the cache line; and, Invalid (I): indicates that this cache line is invalid (there is no valid line in the entry in the core’s cache). The MESI protocol is merely an example protocol that may be used, and other protocols, approaches or techniques may be used to keep track of cache lines or maintain cache coherency among multi-core or multi-processor architectures.

[0028] FIG. l is a diagram illustrating a system including a multi-core processor according to an example embodiment. Multi-core processor 108 may include multiple processing cores (multiple cores), including processing core 0 (shown as core 0) and processing core 1 (shown as core 1). Each processing core may have its own private data cache that is coupled to the processing core via a cache controller. Data cache 110 is provided for core 0, while data cache 112 is provided for core 1. Core 0 may store cache lines within data cache 110, while core 1 may store cache lines within data cache 112. The private data caches are connected to interconnection network 114 (or bus) via cache controllers. Each private data cache may store one or more cache lines, along with status tag bits, e.g., indicating the status of the cache line as either valid or invalid. The status tag bits may indicate one of the status or states for the cache line according to the MESI protocol, for example, where I refers to invalid (where the cache line is invalid or has been invalidated). Each cache line in a data cache may be in one of four states according to the MESI protocol. A main memory 118 is coupled to interconnection network 114 (or bus) via memory controller 116. Only some blocks or components of the system, and of the multi-core processor 108 are shown, and may include other components or blocks. This is merely an example processor architecture, and a processor having a different architecture may be used.

[0029] In order to ensure that all cores (processing cores) in the processor are dealing with the freshest copy of data, each core may always (or may typically) snoop memory bus transactions (e.g., memory reads or writes placed onto the interconnection network 114) from other cores. If a targeted or addressed cache line (memory location addressed by a load operation / memory read or a store operation / memory write) is present in the cache of a core,Attorney Docket No. 0237-013 WO 1 the core may indicate a snoop hit on the bus or interconnection network 114. In some cases, this may result in a cache line for the memory location or address being snooped out or invalidated. For example, a cache line for memory location B is stored in cache 110 of core 0. If core 1 performs a store (memory write) operation to the same memory location B, this can snoop out or invalidate the cache line of memory location B stored in cache 110 of core 0. Based on this store operation, for example, the cache 110 may then change the status of that cache line of memory location B in cache 110 to invalid (or invalidated).

[0030] FIG. 2A is a diagram illustrating a core (or processing core) of a multi-core processor, according to an example embodiment. Only some of the example components or blocks of a core are shown in FIG. 2A. The core may also have a different architecture.

[0031] With respect to FIG. 2A, core 0 may include an instruction processing pipeline 250, e.g., which may be a sequential multi-stage instruction processing pipeline that includes a plurality of sequential stages or units for processing and / or executing instructions. Some example stages of an instruction processing pipeline may include, for example, an instruction fetch unit to fetch instructions in program order, a re-order buffer (ROB) 210 to store instructions in program order, a dispatch unit to dispatch instructions for execution as data and execution resources become available, execution units (which may include load store units 220 to process or execute load and / or store operations) to execute instructions (e.g., where instructions may be executed out of order), and a retirement unit to retire instructions in program order which may include committing instruction execution results to the registers of the core. Instruction processing pipeline 250 may include different or additional stages, depending on the architecture.

[0032] Core 0 may include a re-order buffer (ROB) 210, which may also be referred to as an instruction pool. In some architectures, the ROB 210 may be considered part of the instruction processing pipeline 250. The ROB 210 is a first-in first-out FIFO circular buffer with a number of entries (e.g., 100 entries, to store 100 instructions, in program order). Instructions are placed in the entries of the ROB 210, in program order, as entries in the ROB 210 become available when other instructions are retired and deleted from the ROB 210. The ROB 210 maintains program order of all current instructions flowing through the core 0. The entry of ROB 210 an instruction is placed in has an index, which may be referred to as the ROB index.

[0033] As described herein, it may be useful for the core to be able to determine which load operations are younger than a specific load operation. Typically, a relative age ofAttorney Docket No. 0237-013 WO 1 two instructions (e.g., load operations) in the ROB 210 can be determined based on the ROB indexes for the instructions. The first instruction is placed into a ROB entry with ROB index 0; the second instruction will be placed into ROB index 1; the third instruction will be placed into ROB index 2, etc. Thus, older instructions will typically have a lower or smaller ROB index, and younger instructions will typically have a larger ROB index. Thus, typically, an instruction at ROB index 1 is younger than an instruction at ROB index 0. However, the opposite is true after the ROB has wrapped once.

[0034] Therefore, according to an example embodiment, each entry in ROB 210 may include a wrap bit or flag that indicates whether or not there has been at least one full wrap of the ROB, since or with respect to when an instruction was loaded into the ROB 210. For example, ROB indexes that are higher in number typically are younger instructions, but this is not necessarily the case after one wrap of the ROB has been performed as instructions are retired and new / younger instructions are added to the ROB 210.

[0035] Also, a ROB retirement index is provided in ROB 210 and indicates or points to the oldest instruction in ROB 210, which is the next instruction to be retired. Over time, as instructions are retired and deleted from ROB 210, the ROB retirement index will be incremented to the next ROB index.

[0036] According to an example embodiment, because the ROB retirement index changes over time, the ROB retirement index (as well as other retirement indexes, such as retirement indexes in a load queue 222 and store queue 224) may be used as a proxy or indication of relative time or timing. For example, initially, ROB retirement index may point to ROB index 35 as the oldest instruction in the ROB. Instructions 36-85 are in the ROB as well, but these are younger instructions. The instruction at ROB index 35 retires and is deleted from the ROB, and the ROB retirement index now points to ROB index 36 (the next oldest instruction in the ROB, which is the oldest instruction in the ROB or core 0 that is ready to retire). Instructions 37-85 may also be in the ROB, but these are younger instructions. Later, instruction at ROB index 36 retires and is deleted, and the ROB retirement index pointer is updated to point ROB index 37. Therefore, the ROB retirement index pointer, if recorded or stored, may be used to determine a relative time or timing between events, since the ROB retirement index changes over time, as instructions are retired and deleted from the ROB. Similarly, other timing indications (such as other retirement indexes) generated by the core 0 for an event that can be used to determine relative timing between events. For example, a load queue retirement index and a store queue retirementAttorney Docket No. 0237-013 WO 1 index may be used to determine relative time or relative timing between events for the core.

[0037] Load store units 220 may include a load queue 222 and a store queue 224 for managing and / or performing load operations and store operations, respectively. The store queue is also a FIFO structure that maintains memory ordering of all current store instructions / operations. The load queue is also a FIFO structure that maintains memory ordering of all load instructions / operations flowing through the core 0. While executing load instructions / operations, the core 0 will allow out-of-order execution of load operations. Because of the out of order execution of load operations, it is possible the execution of load operations may result in a memory ordering violation or violate total store order (TSO). The load queue 222 may keep track of the load operations and what happens to existing load operations and determine if any memory ordering violations have occurred. If a memory ordering violation has occurred for core 0, this will typically trigger or cause pipeline flush controller 240 to send a signal to instruction processing pipeline 250 to flush the instruction processing pipeline 250 for core 0 starting from the instruction that caused the memory ordering violation, and these instructions will be re-executed so that a correct memory ordering will be achieved for the second execution of this load operation (that previously caused the memory ordering violation).

[0038] According to an example embodiment, core 0 may include a cache time tracker 230, which may track or determine a fill time for each cache line. For example, the cache time tracker 230 may determine a first information associated with a fill time associated with the first cache line, wherein the fill time may include a time when the first cache line fills or enters an entry in a cache for the processing core. Load queue 222 (which may include a load queue control circuit) may determine a second information associated with an invalidation time for one or more load operation’s cache lines that were invalidated. For example, the load queue 222 (or load queue control circuit) may determine or store at least, for one or more load operations, a second information associated with an invalidation time of a cache line of a younger load operation that was completed and invalidated; and determine whether there has been a load-load memory ordering violation based on a comparison of at least the first information for the first cache line to the second information of the younger load operation that was completed and invalidated.

[0039] The load queue 222 (or load queue control circuit, or other circuit) may be configured to determine whether there has actually been a load-load memory ordering violation based on whether there is a younger load operation in the core that: is younger thanAttorney Docket No. 0237-013 WO 1 a first load operation (wherein the first load operation has used or accessed the first cache line or is associated with the first cache line, e.g., the first load operation may have caused the first cache line to be filled into the cache of the core), completed before the first load operation was completed, and a cache line of the younger load operation was invalidated before the fill time of the first cache line. If there has not been a load-load memory ordering violation, the load queue 222 (or load queue control circuit) may send a signal to the pipeline flush controller 240 to cancel a flush of instruction processing pipeline 250, or omit performing the flush of instruction processing pipeline 250. A control circuit 205 of processing core 0 may include cache time tracker 230 and load queue 222 (or load queue control circuit).

[0040] In this manner, the control circuit 205 of processing core 0 (e.g., which may include, e.g., in an illustrative example, cache time tracker 230, load queue 222) may reduce unnecessary pipeline flushes, and thereby improve processor performance, e.g., by sending a signal (e.g., to pipeline flush controller 240) to cancel a flush of instruction processing pipeline 250 if there actually is not a load-load memory ordering violation, based on the relative timing of the fill time (tO) of the first cache line associated with the first load operation and the invalidation time (tl) of a cache line of a younger load operation(s).

[0041] FIG. 2B is a diagram illustrating a core (or processing core) of a multi-core processor, according to another example embodiment. A control circuit 205 of processing core 0 in FIG. 2B may include fill time detection circuit 270, invalidation detection circuit 280 and / or memory ordering violation detection circuit 290.

[0042] The core shown in FIG. 2B is very similar to the core shown in FIG. 2A, with differences noted here. In general, the functions or operations of the cache time tracker 230 (FIG. 2A), including determining a fill time (tO) or determining a first information associated with a fill time (tO) of a first cache line, may be performed by fill time detection circuit (FIG. 2B). And, some of the operations of load queue 222 (or load queue control circuit) related to detecting or determining of an invalidation time (tl) of a load operation, or determining of a second information associated with an invalidation time, may be performed by an invalidation detection circuit 280, and operations related to detecting a memory ordering violation may be performed by a memory ordering violation detection circuit 290 of FIG. 2B.

[0043] Thus, FIG. 2B provides an alternative design or configuration for core 0. For example, fill time detection circuit 270 may determine or store at least the first information associated with a fill time of a first cache line, wherein the fill time includes a time when theAttorney Docket No. 0237-013 WO 1 first cache line fills or enters an entry in a cache of the processing core 0. The fill time detection circuit 270 may determine that the first cache line is associated with the first load operation (e.g., the load operation that uses or accesses the first cache line). Invalidation detection circuit 280 may determine or store at least, for one or more load operations, a second information associated with an invalidation time of a cache line of a younger load operation that was completed and invalidated. And, memory ordering violation detection circuit 290 may determine whether there has been a load-load memory ordering violation based on a comparison of at least the first information for the first cache line to the second information of the younger load operation that was completed and invalidated. Thus, for example, the memory ordering violation detection circuit 290 may determine, based on at least the first information, whether there has been a load-load memory ordering violation based on whether there is a younger load operation in the processing core that: is younger than the first load operation, completed before the first load operation was completed, and a cache line of the younger load operation was invalidated before the fill time of the first cache line. And, the memory ordering violation detection circuit 290 may also, if there has not been a load-load memory ordering violation, send a signal to a pipeline flush controller 240 for the processing core to cancel a flush of instruction processing pipeline of the processing core, or omit performing the flush of instruction processing pipeline of the processing core.

[0044] An example will be provided to explain how a memory ordering violation (e.g., a load-load memory ordering violation) might occur. For example, a processor, which may include multiple processing cores (or cores) implements total store order (TSO) memory ordering. This means in the code sequence below, if register xO receives new data, register xl must also receive new data. In this example, there are two processing cores for this processor, including core 0 and core 1. Core 0 receives instructions iO and il to execute, while core 1 receives instructions i2 and i3, from the same program.

[0045] The interleaving between the cores may happen in any sequence. For example, in order to be TSO (total store order) compliant, the case of xl=OLD, x0=NEW would create a memory ordering violation, in the example below.

[0046] Initial values:[A] = OLD[B] = OLD

[0047] Instructions of the program, executed by different cores:Attorney Docket No. 0237-013 WO 1Core 0 Core 110 LD xO [A] i2 ST NEW [B]11 LD xl [B] i3 ST NEW [A]10 LD xO [A] - is a load (memory read) operation (the oldest instruction and the oldest load operation in this series of instructions) which reads data from memory location A and stores it in register xO. Execution of this load operation (iO) may cause the data (as a first cache line) from memory location A to fill or enter an entry in a cache 110 of core 0. Also, this first cache line (for memory location A) may have already been filled or entered into an entry of cache 110 of core 0, e.g., via a pre-fetch operation, by a store operation, or other operation, and if so, this load operation (iO) would access or use this first cache line of memory location A. Thus, in this manner (either way), it may be said that this old load operation (iO) is associated with the first cache line in cache 110 of core 0, e.g., based on the load operation’s (iO) using of or accessing (e.g., reading or writing) this first cache line, or this first cache line of memory location A is a cache line of the old load operation (iO).11 LD xl [B] - is a load operation which reads data from memory location B and stores it in register xl. Instruction iO is older than instruction il. Thus, as between iO and il, instruction iO may be considered an old (or older) instruction, while instruction il may be considered a young (or younger) instruction.12 ST NEW [B] - is a store (memory write) operation that writes or stores NEW data to memory location B.13 ST NEW [A] - is a store operation that writes or stores NEW data to memory location A.

[0048] Because a processor may execute loads out of order, the order of instruction execution of this program may be in the following order, for example:11 LD xl [B] - this younger load operation is executed first by core 0, and causes the data at memory location B to be read from memory and stored in register xl.12 ST NEW [B] - this instruction causes xl [B] cache line (the cache line of memory location B) to be snooped out of core 0, thereby invalidating this cache line within core 0.Attorney Docket No. 0237-013 WO 1 i3 ST NEW [A] - this instruction causes xO [A] (the cache line of memory location A) to be snooped out of core 0, thereby invalidating this cache line within core 0. iO LD xO [A] - this older load operation is executed last by core 0, among these instructions.This is an example of a memory ordering violation that can occur. Core 0 will flush (delete) LD xl [B] and re-execute it after LD xO [A],

[0049] The typical operation of a core: For example, core 0 will typically keep track of the cache lines for this core (core 0), e.g., core 0 will keep track of the status (whether the cache lines is invalid, or not) of the cache lines for iO and il. Instruction i2, from core 1, attempts to obtain data from memory location B, which snoops out (and invalidates) the cache line of memory location B for instruction il. Core 0 will mark this cache line for instruction il as invalid (invalidated) or victimized, based on the snoop due to instruction i2 by core 1. Subsequently, when instruction iO completes (or is attempting to complete), core 0 will check (e.g., CAM - perform a content addressable memory lookup in the load queue 222 storing the cache lines and status of each of the cache lines in core 0 for load operations) all the load queue entries in core 0, and will find a younger load operation / instruction (il) (which is younger than load instruction iO) that completed before instruction iO was completed (since instruction iO is not yet completed, and is now attempting to complete), and load operation il was invalidated or victimized (the victimized / invalidated bit in the load queue for the first cache line of memory location B of load operation il was marked by the load queue 222 as invalid / victimized when it was invalidated). When core 0 detects this younger completed load operation (il) that completed before the older load operation (iO) and the younger load operation (il) was invalidated / victimized (based on the load queue reading or detecting that the victimized / invalidated bit for this cache line of load operation il is set), load queue 222 or core 0 may typically determine or consider this as a memory ordering violation, and would then typically execute a flush of instructions from instruction il (which caused the memory ordering violation) and on / younger (instructions within core 1 are not flushed or affected). Thus, in this example, instructions in a re-order buffer (ROB) of core 0 would be flushed, beginning with instruction il.

[0050] However, depending on the timing of certain events with respect to the older load operation (iO) and the younger load operation (il), this may or may not actually be aAttorney Docket No. 0237-013 WO 1 load-load memory ordering violation (a memory ordering violation caused by two load operations that were performed out of order). Presently, processors do not consider the time or timing (or relative timing) of either 1) the fill time of the first cache line associated with the older load operation (iO), nor 2) the timing or time (or relative timing or time) when the younger load operation’s (il) cache line was invalidated. The older load operation (iO) may be considered associated with the first cache line (e.g., of memory location A) (or the first cache line of memory location A may be a cache line of the older load operation iO) based on, e.g., the older load operation (iO) used or accessed the first cache line, and / or the older load operation (iO) during execution caused the first cache line (the cache line for memory location A) to be filled or entered into an entry in the cache 110 of core 0. Thus, for example, it may be said that the first cache line (of memory location A) is a cache line of or associated with the old instruction iO.

[0051] Specifically, if an older load’s cache line (iO LD xO[A]) (or a cache line associated with or of the older load operation iO), which is referred to above as the first cache line, enters the core (e.g., enters or fills an entry of cache 110 of core 0) before any / all younger load's cache line (such as il LD xl [B]) was invalidated (e.g., evicted or snooped out of core 0), there is no TSO memory ordering violation present. This is because in TSO, the only invalid case of two loads in sequence is new data followed by old. The control circuit 205 of the processing core, and various techniques described herein, may be used to detect whether this relative timing condition (an older load’s cache line enters or fills a cache of the core at time tO before any younger load’s cache line is invalidated at time tl) is met, and if so, the control circuit 205 may send a signal (e.g., to pipeline flush controller 240) to cancel a flush of instruction processing pipeline 250, or omit performing a flush of instruction processing pipeline 240 based on this relative timing condition being met or present.

[0052] FIG. 3 is a diagram illustrating an example in which there is not a load-load memory ordering violation based on relative timing of events of an older load operation and a younger load operation. At 310, [B] cache line for younger load operation (il) enters core 0, e.g., this cache line may enter or fill a cache entry of cache 110 of core 0 (either via the older load operation il LD xl [B], via pre-fetch, a store operation, etc.). This is the fill time for the cache line [B] of younger load operation il LD xl [B], At 312, the younger load operation il LD xl [B] completes or is executed, which may be at the same time as operation 310 (if the younger load (il) caused the cache line to fill an entry of cache 110) or slightly after operation 310. At 314, at time tO, [A] cache line for older load (iO) enters core 0, e.g., entersAttorney Docket No. 0237-013 WO 1 or fills a cache entry of core 0 (either via iO LD xO [A] load operation, via pre-fetch, a store operation, etc.). This is the fill time (tO) for the cache line [A] of older load operation iO LD xO [A] (cache line [A] is also referred to as the first cache line of older load). In an example, the performing or operation of the older load operation (iO) may cause the first cache line of memory location [A] to fill an entry of cache 110. Thus, this first cache line [A] is of the older load operation (iO) or associated with the older load operation (iO). The time that the cache line [A] (e.g., which may be referred to herein as the first cache line) of (or associated with) older load operation iO LD xO [A] fills an entry of cache 110 (e.g., at 314 in this example) is referred to as time tO. At 316, at time tl, [B] cache line leaves core 0 (capacity eviction or snooped out of the cache 110), thereby invalidating [B] cache line. The time when [B] cache line of younger load operation il LD xl [B] is invalidated (e.g., at 316 in this example) is referred to as time tl. At 318, the older load operation iO LD xO [A] is completed.

[0053] With reference to FIG. 3, during completion of older load operation iO, the load queue 222 may typically check all younger load operations, including younger load operation il, and will determine that there is a younger load operation (il) that completed before the older load operation (iO) completed, and the cache line [B] of the younger load operation 1 was invalidated (the cache line [B] of the younger load operation il was invalidated at time tl, at 316). At 318, the older load operation iO, or during execution of the older load operation iO, core 0 will check the status bit(s) of the cache line [B] of the younger load operation il that completed before the older load operation, and will determine that, based on the status bit, the cache line [B] of the younger load operation il is invalid or invalidated (e.g., based on that cache line [B] being evicted from the cache based on LRU, or based on that cache line [B] being snooped out). Presently, processors do not store or even consider fill times (time tO) of a cache line or invalidation times (time tl) of cache lines, nor the relative timing between these events or times (fill time (tO) and invalidation time (tl)). Rather, in this example shown in FIG. 3, most processors would simply declare a memory ordering violation and would cause a flush of the pipeline because the younger load operation il completed before the older load operation iO was completed, and the younger load operation’s cache line [B] was invalidated. Current processors simply do not determine nor even consider the relative timing between times tO and time tl.

[0054] However, with reference to FIG. 3, in this case, no actual load-load memory ordering violation occurred. Cache line [B] received old data, but cache line [A] must have also received old data because cache line [A] has lived (or was first entered or filled intoAttorney Docket No. 0237-013 WO 1 cache 110) in cache 110 in core 0 since before cache line [B] was updated. Therefore, in this example, based on the timing of the events here, e.g., specifically because the time tO at 314 when cache line [A] entered or filled the cache 110 of core 0 is before the time tl at 316 when cache line [B] is invalidated (for any or all younger load operations, including younger load operation il in core 0 that completed before iO and were invalidated), there is no loadload memory ordering violation. The control circuit of the processing core 0 may track or determine the times tO (fill time of cache line of or associated with the older load operation iO) and tl (the invalidation time of the younger load operation il), and may determine that because the fill time (tO) of cache line [A] of the older load operation iO is or occurred before the invalidation time (tl) of a cache line of any or all younger load operations in the core 0 (e.g., including the invalidation time of cache line [B] of younger load operation il), there is no load-load memory order violation, and the cache time tracker sends a signal to the pipeline flush controller 240 to cancel the flush of the instruction processing pipeline 250.

[0055] FIG. 4 is a diagram illustrating an example in which there is a load-load memory ordering violation based on relative timing of events of an older load operation and a younger load operation. In FIG. 4, operations 310, 312 and 318 are the same as in FIG. 3. However, in FIG. 4, the operations 314 and 316 are in reverse order, and are shown as operations 314A and 316A, respectively, in FIG. 4. As shown in FIG. 4, at operation 316A, at time tl, [B] cache line of younger load operation ilis invalidated. Later, at 314A, at time tO, [A] cache line of older load (or associated with older load) iO enters or fills an entry of cache 110 of core 0 (or enters core 0). Therefore, it can be seen that in FIG. 4, the cache line [B] of younger load operation il is invalidated at time tl before the cache line [A] of older load operation iO is filled or enters the cache 110 at time tO. Based on the relative timing of these two events (and times tO and tl) in FIG. 4, cache time tracker 230 (FIGs. 2A and 2B) may determine that, because the fill time (tO) of cache line [A] of the older load operation iO occurs after the invalidation time (tl) of cache line [B] of younger load operation il), there is a load-load memory ordering violation, and the control circuit 205 will not send (or will omit sending) a signal to the pipeline flush controller 240 to cancel the flush of the instruction processing pipeline 250, or the cache time tracker 230 will allow the flush of the instruction processing pipeline 250 to be performed.

[0056] FIG. 5 is a diagram illustrating a system according to an example embodiment, including at least a portion of a core and a cache, according to the diagram of FIG. 2 A. As noted, with reference to FIGs. 2A and 5, the control circuit 205 of processing core 0 (FIG.Attorney Docket No. 0237-013 WO 12 A) may include a cache time tracker 230 to determine the first information associated with the fill time (tO) of the first cache line, wherein the fill time comprises the time when the first cache line fills or enters an entry in a cache for the processing core. Also, the cache time tracker 230 may determine a load operation (e.g., first load operation) that uses or accesses the first cache line (e.g., determines that the first load operation is associated with the first cache line). Load queue 222 may confirm that there is not a younger load operation in the processing core that: is younger than the first load operation, completed before the first load operation was completed, and a cache line of the younger load operation was invalidated before the fill time of the first cache line; and send a signal to pipeline flush controller 240 to cancel a flush of instruction processing pipeline 250 of the processing core 0, or omit performing a flush of instruction processing pipeline of the processing core based on the confirming.

[0057] System 510 may include cache time tracker (CTT) 230 that may store a set way location information for the location of the cache line and old bit, and a fill time (tO) (or first information associated with a fill time) of the cache line for one or more load operations (e.g., for load operations iO, il,...). System 510 may include a cache 110 that stores, for each of one or more cache lines, data (the cache line), a cache line tag bits or status indicating a status of the cache line (CL status bits), e.g., based on the MESI protocol or other status indication approach, and an old bit that indicates whether or not the cache line is older (and thus, fill time of the cache line is older) than all instructions (and hence older than all load operations) in the ROB 210 or core 0.

[0058] With respect to FIG. 5, when a cache line of a load operation (e.g., cache line [A] of load operation iO, and cache line [B] of load operation il) is filled or enters cache 110, cache time tracker 230 may store the cache line of the load operation and the fill time (time tO) for one or more of the cache lines or for all of the cache lines. The cache time tracker 230 keeps track of the fill time of cache lines, and other information. Load operations (or the core) may access the fill time (tO) for one or more cache lines. The fill time (tO) may be provided or stored as, e.g., a time stamp, or a retirement index (e.g., ROB retirement index), or other time or timing information, at the time the cache line is filled. The ROB retirement index may be a proxy or indication of time or relative timing because the ROB retirement index will change over time as instructions are retired from the ROB 210.

[0059] Load queue 222 stores cache lines of load operations, a status bit indicating whether or not the cache line is invalid, and an invalidation time (time tl) if the cache line ofAttorney Docket No. 0237-013 WO 1 the load operation is invalid. Thus, load queue 222 may monitor the snoop / eviction of cache lines, and if a cache line is invalidated or victimized (e.g., evicted or snooped out), the load queue 222 sets the invalid bit of every load operation in the load queue 222 (LDQ) that uses the invalidated cache line. Also, the load queue 222 may, for example, store or record the invalidation time (tl) indicating the time or relative timing of when the cache line was invalidated. The invalidation time (tl) may be stored, e.g., as a time stamp or a retirement index (e.g., ROB retirement index) at the time the cache line is invalidated or other time or timing related information. Thus, in this example, load queue 222 may store the ROB retirement index value as time tl (indicating the invalidation time for the cache line) when a cache line is invalidated.

[0060] When a cache line associated with a load operation is filled in cache 110, the cache line will be stored in a set way in the cache 110. Cache time tracker 230 also stores in a cache time tracker entry for the cache line: the set way information for that cache line (indicating where this cache line and its old bit or flag is stored in the cache 110), and the fill time (tO) or the first information associated with a fill time (tO) for the cache line. In this example, the fill time (tO), or first information associated with the fill time, includes or is stored as the ROB retirement index value when the cache line was filled in the cache 110.

[0061] Each cache line has an old bit that may be cleared (e.g., a value of 0 indicating that the ROB retirement index within ROB 210 has not wrapped once) or set (e.g., set to a value of 1 to indicate that the ROB retirement index within ROB 210 has wrapped once). Cache time tracker 230 may keep track of ROB retirement index with respect to fills coming into the cache 110 of core 0. If the ROB retirement index wraps once with respect to the fill time (tO) of a cache line, cache time tracker 230 will set the old bit for that cache line for the corresponding entry in the cache time tracker 230. Setting the old bit for the cache line indicates that the cache line is older than all instructions (and thus all load operations) in the ROB 210, and thus, indicating that a fill time (time tO) for this cache line into a cache of the processing core occurred before any existing load operations appeared in or were loaded into the ROB 210.

[0062] After the cache time tracker 230 detects or determines that a ROB retirement index has wrapped once in the ROB 210 since a cache line was filled (e.g., if ROB retirement index is used to compare relative timing of events), fill time (tO) may be compared against the current ROB retirement index to detect if a wrap of the ROB has occurred (i.e., every entry of the ROB has been used at least once), the cache time tracker entry (including cache lineAttorney Docket No. 0237-013 WO 1 associated with the load operation, set way information for the cache line and the fill time (time tO) for the cache line, are deleted from the cache time tracker 230, and the old bit (in the cache 110) for this cache line is set to indicate that this cache line is older than all instructions in the ROB 210 (or older than all instructions in core 0). When the old bit is set, after the ROB retirement index has wrapped once in the ROB after a cache line is filled, this means that the cache line is older than all instructions (including all load operations) in the ROB 210. Thus, after an old bit is set for a cache line, the control circuit 205 no longer needs to compare relative times tO (for the cache line), to tl (for younger cache lines that were invalidated). If the old bit for the older (first) cache line is set, then the control circuit 205 can cancel a flush of instruction processing pipeline. Thus, there is no need to continue storing the entry in cache time tracker 230 for this first cache line (including set way information for the cache line and fill time tO), and this entry in cache time tracker 230 may be deleted for this cache line. Thus, in general, if a first cache line of a first load operation becomes old, the old bit is set for this first cache line, and the entry for this first cache line in the cache time tracker 230 may be deleted, since there is no need to compare the fill time (tO) of this first cache line to invalidation times (tl) of younger load operations (the old bit being set indicates that this first cache line is older than all (other) load operations in the ROB 210), thus indicating that the control circuit 205 may cancel a flush of the instruction pipeline that may have occurred based on this first load operation associated with the first cache line.

[0063] Load queue 222, after a load operation uses or becomes associated with a first cache line, may monitor the set way location for the first cache line. If the set way location for this first cache line is snooped or evicted (invalidated), then the load queue 222 sets the invalidated / victimized bit for the first load operation associated with this first cache line, and sets the invalidation time (tl) of the first load operation to the current value of the ROB retirement pointer (the ROB retirement index value when the first cache line associated with the first load operation is invalidated or victimized).

[0064] An example will now be described.

[0065] 1) A first cache line is filled into cache 110, and the fill time (tO) is stored in the cache time tracker 230 for this first cache line. A first load operation (an older load operation) becomes associated with the first cache line, e.g., by first cache line being accessed or used by the first load operation.

[0066] 2) A younger load operation is performed or completed (or load queue 222 tries to perform or complete a younger load operation), and stores the set way information.Attorney Docket No. 0237-013 WO 1

[0067] 3) The cache line of or associated with this younger load operation is invalidated or victimized. Load queue sets the invalidated bit and stores the invalidation time (tl) for this load operation within load queue 222.

[0068] 4) The first load (or older load) operation is received (e.g., via LD completion(x3) lines in FIG. 5), and the load queue 222 attempts to complete or perform this first load operation, accesses its data or cache line in cache 110, and accesses old bit. If old bit = 1 for the first cache line, this means that the first cache line is older than all load operations in the ROB, so the control circuit sends a signal to cancel a flush of instruction processing pipeline, and there is no need to compare tO of the first cache line to tl of cache lines of any other load operations. In this example it shall be assumed that old bit = 0 for the first cache line, so this means this first cache line is not old, so need to compare tO for this first cache line to tl of younger load operation that have completed and are invalidated. Load queue 222 is tracking invalidation times (tl) for load operations, and cache time tracker 230 is tracking or storing fill time (tO) for load operations including this first load operation. Load queue 222 will check every younger load operation in load queue to determine if there are any younger load operations that have completed, are younger than the first load operation (this can be determined based on location within load queue of the load operations), and the cache line of the younger load operation was invalidated (tl) before the first cache line fill time (tO). Thus, for example, the load queue or the control circuit 205 may determine whether there has been a load-load memory ordering violation based on whether there is a younger load operation in the processing core that: is younger than the first load operation, completed before the first load operation was completed, and a cache line of the younger load operation was invalidated before the fill time of the first cache line. If there has not been a load-load memory ordering violation, then send a signal to a pipeline flush controller for the processing core to cancel a flush of instruction processing pipeline of the processing core, or omit performing the flush of instruction processing pipeline of the processing core. If there has been a load-load memory ordering violation (based on fill time (tO) of first cache line occurring after invalidation time (tl) of a younger load operation(s). In such case, there will be a flush of instruction processing pipeline from the oldest younger load that is invalidated and tO is younger than tl (tl / invalidation time occurred before tO / fill time).

[0069] In terms of comparing tO and tl (comparing the ROB retirement indexes of tO for the first cache line associated with the first load operation to the tl / invalidation time of cache line of the younger load operation), normally an older cache line will have a smallerAttorney Docket No. 0237-013 WO 1ROB retirement index value. However, after the ROB retirement index in ROB 210 wraps once for one of the load operations (either the younger load operation or the first load operation), the opposite condition is true (that is, an older cache line will have a larger ROB retirement index value).

[0070] For example, if the ROB retirement index has wrapped once after a ROB index for a load operation, the wrap bit for that ROB index is set to 1. Otherwise, the wrap bit is 0. If the wrap bits for both load operations are the same value (e.g., both 0), then the normal comparison is performed, where an older cache line will have a smaller ROB retirement index value. On the other hand, if the wrap bits for the two load operations (first load operation and younger load operation) are different, then the opposite comparison is performed, where an older cache line will have a larger ROB retirement index value. This is an example technique that may be used to handle the limited ROB size and if there is a wrapping once of the ROB retirement index value.

[0071] FIG. 6 is a diagram illustrating aspects of a cache time tracker according to an example embodiment. Cache time tracker (CTT) 230 may store a set way location information for the location of the cache line and old bit, and a fill time (tO) (or first information associated with a fill time) of the cache line for one or more load operations. At fill time of a cache line, if a CTT entry is available (either a CTT entry that is empty, or a CTT entry for which its valid bit is 0 meaning that this entry is invalid and may be re-used), information of the cache line will be written to an entry in the CTT 230, including: a valid bit (set to 1 indicating that this cache line or this CTT entry is valid), the cache line set way information in the cache, the old bit is initialized to 0 (zero) (indicating that the cache line is not old), and the fill time (tO) for this cache line is set to the current ROB retirement index value. If the cache line is snooped out or invalidated, the entry for this cache line in the CTT 230 will be invalidated, e.g., by camming the set way of the invalidated / snooped out cache line with all the set way information saved in the CTT entries of CTT 230. In this manner, the processing core compares the snooped out / invalidated cache line set way with the saved set way information of all CTT entries, and any CTT entries that match will have their cache lines invalidated (valid bit is cleared to 0 indicating that this CTT entry or cache line is invalid). The load operation (or the processing core for the load operation) may obtain the old bit value and / or the fill time tO for its cache line in one of multiple ways (this information may be obtained from the CTT 230 or the cache): 1) the load operation may obtain the value of the old bit from the CTT entry for its cache line by camming its own set way informationAttorney Docket No. 0237-013 WO 1 against the set way information of all CTT entries in CTT 230, and there is a match (this will provide the old bit and / or the fill time (tO) for the CTT entry that matched its set way information);(note that if the old bit is set to indicate that this cache line is old, then the fill time (tO) does not matter and will not be compared); or, 2) if the operation of 1) (obtaining value of old bit and / or fill time (tO) based on camming CTT entries) does not result in a match, then the load operation may read its old bit value for this cache line from the cache (load operation reads the old bit added for each cache line in the cache for this purpose).

[0072] As noted above, if the ROB retirement index wraps once with respect to the fill time (tO) of a cache line, cache time tracker 230 will set the old bit for that cache line for the corresponding entry in the cache time tracker 230. Thus, for example, based on the fill time (tO) and the current value of the ROB retirement index (e.g., by comparing the fill time (tO) to the current value of the ROB retirement index), the core may determine that the cache line has wrapped fully in the ROB, and will set the old bit in the CTT entry (to indicate that this cache line is old) for that cache line. Then the core will drain the old bit held in the cache using the set way information held in the CTT entry for that cache line. For every CTT entry for which an old bit is set (indicating that the cache line is old), the CTT 230 will use the set way information in the CTT to set the old bit in the cache to 1 for this cache line, and will also set the valid bit for this CTT entry to 0, to allow this CTT entry to be re-used. Thus, there may be two old bits for a cache line, including an old bit in the CTT entry for a cache line (see FIG. 6), and an old bit in the cache for each cache line (see FIG. 5 old bit for each cache line).

[0073] In some cases, a grouping ROB may be used in which there are multiple instructions per ROB entry, in which all of the instructions (of that group) will be retired together or not retired, since all the instructions of a group share the same ROB retirement index.

[0074] A load queue may be used to keep track of memory ordering violations for load operations. Either an in order load queue or an out-of-order (OOO) load queue may be used. In order load queues generally keep track of load operations for memory ordering violations, whereas, OOO load queues keep track of cache lines for memory ordering violations. Either approach may be used.

[0075] In some cases, all CTT entries of CTT 230 may be occupied, and a fill time and other information for a cache line of a load operation may not be tracked, but this will not cause any errors or problems with the operation of the core or processor. In the event that theAttorney Docket No. 0237-013 WO 1CTT 230 is full (no CTT entries available), the core will still behave correctly, and potential performance gains using these techniques will not be achieved if an unnecessary flush of the instruction pipeline processing is performed.

[0076] Some examples will be described.

[0077] Example 1. A processor including: a processing core; the processing core comprising a control circuit configured to: determine a first information associated with a fill time of a first cache line, wherein the fill time comprises a time when the first cache line fills or enters an entry in a cache for the processing core; determine a first load operation that uses or accesses the first cache line; confirm that there is not a younger load operation in the processing core that: is younger than the first load operation, completed before the first load operation was completed, and a cache line of the younger load operation was invalidated before the fill time of the first cache line; and send a signal to cancel a flush of instruction processing pipeline of the processing core, or omit performing a flush of instruction processing pipeline of the processing core based on the confirming.

[0078] Example 2. The processor of example 1, wherein the control circuit configured to send comprises the control circuit configured to: send a signal to the processing core to cancel a load-load memory ordering violation flush of instruction processing pipeline of the processing core, or omit performing a load-load memory ordering violation flush of instruction processing pipeline based on the confirming.

[0079] Example 3. The processor of any of examples 1-2, wherein the first load operation causes the first cache line to be filled in the cache of the processing core.

[0080] Example 4. The processor of any of examples 1-3, wherein the cache line of the younger load operation being invalidated comprises the cache line of the younger load being evicted from the cache or being snooped out by another processing core of the processor.

[0081] Example 5. The processor of any of examples 1-4, wherein the control circuit is further configured to: determine a second information associated with an invalidation time or victimization time of a cache line of a younger load operation, wherein the younger load operation is younger than the first load operation and the younger load operation was completed and invalidated.

[0082] Example 6. The processor of example 5, wherein the control circuit configured to determine the second information comprises: a load queue, a load queue control circuit or an invalidation detection circuit configured to determine and / or store the second informationAttorney Docket No. 0237-013 WO 1 associated with an invalidation time of a cache line for each of a plurality of load operations.

[0083] Example 7. The processor of any of examples 1-6, wherein the control circuit comprises: a cache time tracker configured to determine the first information associated with the fill time of the first cache line, wherein the fill time comprises the time when the first cache line fills or enters an entry in a cache for the processing core; and the cache time tracker configured to determine the first load operation that uses or accesses the first cache line; a load queue or a load queue control circuit configured to: confirm that there is not a younger load operation in the processing core that: is younger than the first load operation, completed before the first load operation was completed, and a cache line of the younger load operation was invalidated before the fill time of the first cache line; and send the signal to cancel the flush of instruction processing pipeline of the processing core, or omit performing a flush of instruction processing pipeline of the processing core based on the confirming.

[0084] Example 8. The processor of example 1, wherein the control circuit comprises: a fill time detection circuit configured to determine the first information associated with the fill time of the first cache line, wherein the fill time comprises the time when the first cache line fills or enters an entry in a cache for the processing core; wherein the fill time detection circuit is configured to determine that the first load operation uses or accesses the first cache line; a memory ordering violation detection circuit configured to confirm that there is not a younger load operation in the processing core that: is younger than the first load operation, completed before the first load operation was completed, and a cache line of the younger load operation was invalidated before the fill time of the first cache line; and the memory ordering violation detection circuit configured to send the signal to cancel the flush of instruction processing pipeline of the processing core, or omit performing a flush of instruction processing pipeline of the processing core based on the confirming.

[0085] Example 9. A processor including: a processing core including a control circuit, wherein the control circuit is configured to: determine a first information associated with a fill time of a first cache line, wherein the fill time comprises a time when the cache line fills or enters an entry in a cache of the processing core; determine a first load operation that uses or accesses the first cache line; determine, based on at least the first information, whether there has been a load-load memory ordering violation based on whether there is a younger load operation in the processing core that: is younger than the first load operation, completed before the first load operation was completed, and a cache line of the younger load operation was invalidated before the fill time of the first cache line; and if there has not beenAttorney Docket No. 0237-013 WO 1 a load-load memory ordering violation, then send a signal to a pipeline flush controller for the processing core to cancel a flush of instruction processing pipeline of the processing core, or omit performing the flush of instruction processing pipeline of the processing core.

[0086] Example 10. The processor of example 9, wherein the control circuit is further configured to: if there has been a load-load memory ordering violation, then perform at least one of the following: perform, or allow the processing core to perform, or omit canceling, the flush of instruction processing pipeline of the processing core; or send a signal to the processing core, or indicate to the processing core, that there has been a load-load memory ordering violation of the processing core.

[0087] Example 11. The processor of any of examples 9-10, wherein the first information associated with the fill time of the first cache line comprises at least one of the following: a time stamp indicating or associated with a time when the first cache line filled or entered an entry of the cache of the processing core; a retirement index value at a time when the first cache line filled or entered an entry of the cache of the processing core; a re-order buffer (ROB) retirement index value at a time when the first cache line filled or entered an entry of the cache of the processing core, wherein the ROB retirement index value indicates or points to an oldest instruction in the ROB; a load queue retirement index value at a time when the first cache line filled or entered an entry of the cache of the processing core, wherein the load queue retirement index value indicates or points to an oldest load operation in the load queue; or a store queue retirement index value at a time when the first cache line filled or entered an entry of the cache of the processing core, wherein the store queue retirement index value indicates or points to an oldest store operation in the load queue; a timing indication generated by the processing core for an event that can be used to determine relative timing between events within the processing core; or an Old bit or flag that indicates whether or not the first cache line is older than all instructions in the ROB.

[0088] Example 12. The processor of any of examples 9-11, wherein the control circuit comprises: a cache time tracker that stores at least the first information for the first cache line; a load queue or load queue control circuit configured to: determine or store at least, for one or more load operations, a second information associated with an invalidation time of a cache line of a younger load operation that was completed and invalidated; and determine whether there has been a load-load memory ordering violation based on a comparison of at least the first information for the first cache line to the second information of the younger load operation that was completed and invalidated.Attorney Docket No. 0237-013 WO 1

[0089] Example 13. The processor of any of examples 9-11, wherein the control circuit comprises: a fill time detection circuit configured to determine or store at least the first information for the first cache line; an invalidation detection circuit configured to determine or store at least, for one or more load operations, a second information associated with an invalidation time of a cache line of a younger load operation that was completed and invalidated; and a memory ordering violation detection circuit configured to determine whether there has been a load-load memory ordering violation based on a comparison of at least the first information for the first cache line to the second information of the younger load operation that was completed and invalidated.

[0090] Example 14. The processor of example 13, wherein the memory ordering violation detection circuit, in performing the comparison, also considers a value of a wrap bit or wrap flag for each of the first load operation and the younger load operation, wherein the wrap bit or wrap flag indicates whether or not there has been at least one full wrap of the ROB.

[0091] Example 15. The processor of any of examples 13-14, wherein the second information associated with an invalidation time of a cache line of a younger load operation that was completed and invalidated comprises at least one of the following: a time stamp indicating or associated with a time when the cache line of the younger load operation was invalidated; a retirement index value at a time when the cache line of the younger load operation was invalidated; a re-order buffer (ROB) retirement index value at a time when the cache line of the younger load operation was invalidated, wherein the ROB retirement index value indicates or points to an oldest instruction in the ROB; a load queue retirement index value at a time when the cache line of the younger load operation was invalidated, wherein the load queue retirement index value indicates or points to an oldest load operation in the load queue; a store queue retirement index value at a time when the cache line of the younger load operation was invalidated, wherein the store queue retirement index value indicates or points to an oldest store operation in the load queue; a timing indication generated by the processing core for an event that can be used to determine relative timing between events within the processing core.

[0092] Example 16. The processor of any of examples 13-15, wherein: the first information comprises a first retirement index value at a time when the first cache line was filled or entered an entry of the cache of the processing core; and the second information for the younger load operation comprises a second retirement index value at a time when theAttorney Docket No. 0237-013 WO 1 cache line of the younger load operation was invalidated.

[0093] Example 17. The processor of example 16, wherein the first retirement index value comprises at least one of: a retirement index value at a time when the first cache line filled or entered an entry of the cache of the processing core; a re-order buffer (ROB) retirement index value at a time when the first cache line filled or entered an entry of the cache of the processing core, wherein the ROB retirement index value indicates or points to an oldest instruction in the ROB; a load queue retirement index value at a time when the first cache line filled or entered an entry of the cache of the processing core, wherein the load queue retirement index value indicates or points to an oldest load operation in the load queue; or a store queue retirement index value at a time when the first cache line filled or entered an entry of the cache of the processing core, wherein the store queue retirement index value indicates or points to an oldest store operation in the load queue.

[0094] Example 18. The processor of any of examples 16-17, wherein the second retirement index value comprises at least one of: a retirement index value at a time when the cache line of the younger load operation was invalidated; a re-order buffer (ROB) retirement index value at a time when the cache line of the younger load operation was invalidated, wherein the ROB retirement index value indicates or points to an oldest instruction in the ROB; a load queue retirement index value at a time when the cache line of the younger load operation was invalidated, wherein the load queue retirement index value indicates or points to an oldest load operation in the load queue; or a store queue retirement index value at a time when a cache line of the younger load operation was invalidated, wherein the store queue retirement index value indicates or points to an oldest store operation in the load queue.

[0095] Example 19. The processor of any of examples 9-18, wherein the control circuit is configured to: upon detecting that a re-order buffer (ROB) retirement index value has wrapped once in the ROB since the fill time of the first cache line, set an old bit in the cache for the first cache line indicating that the first cache line is older than all instructions in the ROB, and thus indicating that the fill time for the first cache line occurred before any load operations in the processing core may have been invalidated.

[0096] Example 20. The processor of any of examples 9-19, wherein the control circuit is configured to: upon detecting that a re-order buffer (ROB) retirement index value has wrapped once in the ROB since the fill time of the first cache line, delete an entry for the first cache line in a cache time tracker or in a fill time detection circuit, including deleting the first information for the first cache line, and set an old bit in the cache for the first cache lineAttorney Docket No. 0237-013 WO 1 indicating that the first cache line is older than all instructions in the ROB.

[0097] Example 21. The processor of example 9, wherein the control circuit configured to determine, based on at least the first information, whether there has been a load-load memory ordering violation comprises a load queue control circuit or a memory ordering violation detection circuit configured to: based on reading data from the cache for the first cache line as part of processing the first load operation, read the first information associated with the fill time of the first cache line, wherein the first information is stored in a cache time tracker or a fill time detection circuit; and determine, based at least on the first information, whether there has been a load-load memory ordering violation.

[0098] Example 22. The processor of example 9, wherein the control circuit comprises: a fill time detection circuit configured to determine the first information associated with the fill time of the first cache line, wherein the fill time comprises a time when the cache line fills or enters an entry in the cache of the processing core; the fill time detection circuit configured to determine the first load operation that uses or accesses the first cache line; a memory ordering violation detection circuit configured to determine, based on at least the first information, whether there has been a load-load memory ordering violation based on whether there is a younger load operation in the processing core that: is younger than the first load operation, completed before the first load operation was completed, and a cache line of the younger load operation was invalidated before the fill time of the first cache line; and the memory ordering violation detection circuit configured to, if there has not been a load-load memory ordering violation, send a signal to the pipeline flush controller for the processing core to cancel a flush of instruction processing pipeline of the processing core, or omit performing the flush of instruction processing pipeline of the processing core.

[0099] Example 23. A processor comprising: a processing core; the processing core comprising a control circuit configured to: determine a first load operation associated with a first cache line; with respect to performing or completing the first load operation, detect that the fill time of the first cache line into the core is older than all instructions in the ROB of the processing core, including older than all load operations in the ROB; and based on detecting that the first cache line being older than all instructions in the ROB, send a signal to cancel or omit performing a flush of instruction processing pipeline that may have been triggered based on the first load operation.

[0100] Example 24. The processor of example 23, wherein the control circuit is configured to: with respect to performing or completion of the first load operation, detect thatAttorney Docket No. 0237-013 WO 1 an old bit or old flag for the first cache line is set to indicate that the first cache line is older than all instructions in the ROB, including all load operations in the ROB.

[0101] Example 25. A processor comprising: a processing core; the processing core comprising a control circuit configured to: determine a first load operation associated with a first cache line; upon detecting that a re-order buffer (ROB) retirement index value has wrapped once in the ROB of the processing core since the first cache line was filled into the processing core, set an old bit or old flag for the first cache line indicating that the first cache line stored in a cache of the processing core is older than all instructions in the ROB, and thus indicating that a fill time for the first cache line into a cache of the processing core occurred before any load operations in the ROB or processing core may have been invalidated; with respect to or during performing or completing the first load operation, detect that the old bit or old flag for the first cache line is set to indicate that the first cache line is older than all instructions in the ROB; and send a signal to cancel a flush of instruction processing pipeline of the processing core, or omit performing a flush of instruction processing pipeline of the processing core based on detecting that the old bit or old flag for the first cache line being set to indicate that the first cache line is older than all instructions in the ROB.

[0102] Example 26. The processor of example 25, wherein the control circuit comprises: a cache time tracker or other circuit configured to, upon detecting that a re-order buffer (ROB) retirement index value has wrapped once in the ROB of the processing core since the first cache line was filled into the processing core, set the old bit in the cache for the first cache line indicating that the first cache line is older than all instructions in the ROB; and a load queue, load queue control circuit or a memory ordering violation detection circuit configured to: during or with respect to performing or completion of the first load operation, detect that the old bit for the first cache line is set to indicate that the first cache line is older than all instructions in the ROB; and send a signal to a pipeline flush controller to cancel a flush of instruction processing pipeline of the processing core, or omit performing a flush of instruction processing pipeline of the processing core based on detecting that the old bit for the first cache line being set to indicate that the first cache line is older than all instructions in the ROB.

[0103] FIG. 7 illustrates an example architecture of a computing device 750 that can be used to implement aspects of the present disclosure, including any of the plurality of computing devices described herein, such as a computing device including a processor, such as multi-core processor 108 and / or processing core(s), or any other computing devices thatAttorney Docket No. 0237-013 WO 1 may be utilized in the various possible embodiments. The computing device illustrated in FIG. 7 can be used to execute and operating system, application programs and software modules, such as described herein.

[0104] The computing device 750 includes, in some embodiments, at least one processing device 760, such as a central processing unit (CPU). A variety of processing devices are available from a variety of manufacturers, for example, Intel or Advanced Micro Devices. In this example, the computing device 750 also includes a system memory 762, and a system bus 764 that couples various system components including the system memory 762 to the processing device 760. The system bus 764 is one of any number of types of bus structures including a memory bus, or memory controller; a peripheral bus; and a local bus using any of a variety of bus architectures.

[0105] Examples of computing devices suitable for the computing device 750 include a server computer, an edge computer, a desktop computer, a laptop computer, a tablet computer, a mobile computing device (such as a smart phone, an iPod® or iPad® mobile digital device, or other mobile devices), or other devices configured to process digital instructions.

[0106] The system memory 762 includes read only memory 766 and random access memory 768. A basic input / output system 770 containing the basic routines that act to transfer information within computing device 750, such as during start up, is typically stored in the read only memory 766.

[0107] The computing device 750 also includes a secondary storage device 772 in some embodiments, such as a hard disk drive, for storing digital data. The secondary storage device 772 is connected to the system bus 764 by a secondary storage interface 774. The secondary storage device 772 and its associated computer readable media can provide nonvolatile storage of computer readable instructions (including application programs and program modules), data structures, and other data for the computing device 750.

[0108] Although the example environment described herein employs a hard disk drive as a secondary storage device, other types of computer readable storage media are used in other embodiments. Examples of these other types of computer readable storage media include magnetic cassettes, flash memory cards, digital video disks, Bernoulli cartridges, compact disc read only memories, digital versatile disk read only memories, random access memories, or read only memories. Some embodiments include non-transitory Computer-Attorney Docket No. 0237-013 WO 1 readable media. Additionally, such computer readable storage media can include local storage or cloud-based storage.

[0109] A number of program modules can be stored in secondary storage device 772 or system memory 762, including an operating system 776, one or more application programs 778, other program modules 780 (such as the software engines described herein), and program data 782. The computing device 750 can utilize any suitable operating system, such as Microsoft Windows™, Google Chrome™ OS or Android, Apple OS, Unix, or Linux and variants and any other operating system suitable for a computing device. Other examples can include Microsoft, Google, or Apple operating systems, or any other suitable operating system used in tablet computing devices.

[0110] In some embodiments, a user provides inputs to the computing device 750 through one or more input devices 784. Examples of input devices 784 include a keyboard 786, mouse 788, microphone 790, and touch sensor 792 (such as a touchpad or touch sensitive display). Other embodiments include other input devices 784. The input devices are often connected to the processing device 760 through an input / output interface 794 that is coupled to the system bus 764. These input devices 784 can be connected by any number of input / output interfaces, such as a parallel port, serial port, game port, or a universal serial bus. Wireless communication between input devices and the input / output interface 794 is possible as well, and includes infrared, BLUETOOTH® wireless technology, 802.1 la / b / g / n, cellular, ultra-wideband (UWB), ZigBee, or other radio frequency communication systems in some possible embodiments.

[0111] In this example embodiment, a display device 796, such as a monitor, liquid crystal display device, projector, or touch sensitive display device, is also connected to the system bus 764 via an interface, such as a video adapter 798. In addition to the display device 796, the computing device 750 can include various other peripheral devices (not shown), such as speakers or a printer.

[0112] When used in a local area networking environment or a wide area networking environment (such as the Internet), the computing device 750 is typically connected to the network through a network interface 1000, such as an Ethernet interface or WiFi interface. Other possible embodiments use other communication devices. For example, some embodiments of the computing device 750 include a modem for communicating across the network.Attorney Docket No. 0237-013 WO 1

[0113] The computing device 750 typically includes at least some form of computer readable media. Computer readable media includes any available media that can be accessed by the computing device 750. By way of example, computer readable media include computer readable storage media and computer readable communication media.

[0114] Computer readable storage media includes volatile and nonvolatile, removable and non-removable media implemented in any device configured to store information such as computer readable instructions, data structures, program modules or other data. Computer readable storage media includes, but is not limited to, random access memory, read only memory, electrically erasable programmable read only memory, flash memory or other memory technology, compact disc read only memory, digital versatile disks or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and that can be accessed by the computing device 750.

[0115] Computer readable communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media. The term “modulated data signal” refers to a signal that has one or more of its characteristics set or changed in such a manner as to encode information in the signal. By way of example, computer readable communication media includes wired media such as a wired network or direct-wired connection, and wireless media such as acoustic, radio frequency, infrared, and other wireless media. Combinations of any of the above are also included within the scope of computer readable media.

[0116] The computing device illustrated in FIG. 7 is also an example of programmable electronics, which may include one or more such computing devices, and when multiple computing devices are included, such computing devices can be coupled together with a suitable data communication network so as to collectively perform the various functions, methods, or operations disclosed herein.

Claims

Attorney Docket No. 0237-013 WO 1CLAIMSWhat is claimed is:

1. A processor comprising: a processing core; the processing core comprising a control circuit configured to: determine a first information associated with a fill time of a first cache line, wherein the fill time comprises a time when the first cache line fills or enters an entry in a cache for the processing core; determine a first load operation that uses or accesses the first cache line; confirm that there is not a younger load operation in the processing core that: is younger than the first load operation, completed before the first load operation was completed, and a cache line of the younger load operation was invalidated before the fill time of the first cache line; and send a signal to cancel a flush of instruction processing pipeline of the processing core, or omit performing a flush of instruction processing pipeline of the processing core based on the confirming.

2. The processor of claim 1, wherein the control circuit configured to send comprises the control circuit configured to: send a signal to the processing core to cancel a load-load memory ordering violation flush of instruction processing pipeline of the processing core, or omit performing a load-load memory ordering violation flush of instruction processing pipeline based on the confirming.

3. The processor of any of claims 1-2, wherein the first load operation causes the first cache line to be filled in the cache of the processing core.

4. The processor of any of claims 1-3, wherein the cache line of the younger load operation being invalidated comprises the cache line of the younger load being evicted from the cache or being snooped out by another processing core of the processor.

5. The processor of any of claims 1-4, wherein the control circuit is further configured to:Attorney Docket No. 0237-013 WO 1 determine a second information associated with an invalidation time or victimization time of a cache line of a younger load operation, wherein the younger load operation is younger than the first load operation and the younger load operation was completed and invalidated.

6. The processor of claim 5, wherein the control circuit configured to determine the second information comprises: a load queue, a load queue control circuit or an invalidation detection circuit configured to determine and / or store the second information associated with an invalidation time of a cache line for each of a plurality of load operations.

7. The processor of any of claims 1-6, wherein the control circuit comprises: a cache time tracker configured to determine the first information associated with the fill time of the first cache line, wherein the fill time comprises the time when the first cache line fills or enters an entry in a cache for the processing core; and the cache time tracker configured to determine the first load operation that uses or accesses the first cache line; a load queue or a load queue control circuit configured to: confirm that there is not a younger load operation in the processing core that: is younger than the first load operation, completed before the first load operation was completed, and a cache line of the younger load operation was invalidated before the fill time of the first cache line; and send the signal to cancel the flush of instruction processing pipeline of the processing core, or omit performing a flush of instruction processing pipeline of the processing core based on the confirming.

8. The processor of any of claims 1-7, wherein the control circuit comprises: a fill time detection circuit configured to determine the first information associated with the fill time of the first cache line, wherein the fill time comprises the time when the first cache line fills or enters an entry in a cache for the processing core; wherein the fill time detection circuit is configured to determine that the first load operation uses or accesses the first cache line;Attorney Docket No. 0237-013 WO 1 a memory ordering violation detection circuit configured to confirm that there is not a younger load operation in the processing core that: is younger than the first load operation, completed before the first load operation was completed, and a cache line of the younger load operation was invalidated before the fill time of the first cache line; and the memory ordering violation detection circuit configured to send the signal to cancel the flush of instruction processing pipeline of the processing core, or omit performing a flush of instruction processing pipeline of the processing core based on the confirming.

9. A processor comprising: a processing core including a control circuit, wherein the control circuit is configured to: determine a first information associated with a fill time of a first cache line, wherein the fill time comprises a time when the cache line fills or enters an entry in a cache of the processing core; determine a first load operation that uses or accesses the first cache line; determine, based on at least the first information, whether there has been a load-load memory ordering violation based on whether there is a younger load operation in the processing core that: is younger than the first load operation, completed before the first load operation was completed, and a cache line of the younger load operation was invalidated before the fill time of the first cache line; and if there has not been a load-load memory ordering violation, then send a signal to a pipeline flush controller for the processing core to cancel a flush of instruction processing pipeline of the processing core, or omit performing the flush of instruction processing pipeline of the processing core.

10. The processor of claim 9, wherein the control circuit is further configured to: if there has been a load-load memory ordering violation, then perform at least one of the following: perform, or allow the processing core to perform, or omit canceling, the flush of instruction processing pipeline of the processing core; or send a signal to the processing core, or indicate to the processing core, that there has been a load-load memory ordering violation of the processing core.Attorney Docket No. 0237-013 WO 111. The processor of any of claims 9-10, wherein the first information associated with the fill time of the first cache line comprises at least one of the following: a time stamp indicating or associated with a time when the first cache line filled or entered an entry of the cache of the processing core; a retirement index value at a time when the first cache line filled or entered an entry of the cache of the processing core; a re-order buffer (ROB) retirement index value at a time when the first cache line filled or entered an entry of the cache of the processing core, wherein the ROB retirement index value indicates or points to an oldest instruction in the ROB; a load queue retirement index value at a time when the first cache line filled or entered an entry of the cache of the processing core, wherein the load queue retirement index value indicates or points to an oldest load operation in the load queue; or a store queue retirement index value at a time when the first cache line filled or entered an entry of the cache of the processing core, wherein the store queue retirement index value indicates or points to an oldest store operation in the load queue; a timing indication generated by the processing core for an event that can be used to determine relative timing between events within the processing core; or an old bit or flag that indicates whether or not the first cache line is older than all instructions in the ROB.

12. The processor of any of claims 9-11, wherein the control circuit comprises: a cache time tracker that stores at least the first information for the first cache line; a load queue or load queue control circuit configured to: determine or store at least, for one or more load operations, a second information associated with an invalidation time of a cache line of a younger load operation that was completed and invalidated; and determine whether there has been a load-load memory ordering violation based on a comparison of at least the first information for the first cache line to the second information of the younger load operation that was completed and invalidated.

13. The processor of any of claims 9-11, wherein the control circuit comprises: a fill time detection circuit configured to determine or store at least the first information for the first cache line;Attorney Docket No. 0237-013 WO 1 an invalidation detection circuit configured to determine or store at least, for one or more load operations, a second information associated with an invalidation time of a cache line of a younger load operation that was completed and invalidated; and a memory ordering violation detection circuit configured to determine whether there has been a load-load memory ordering violation based on a comparison of at least the first information for the first cache line to the second information of the younger load operation that was completed and invalidated.

14. The processor of claim 13, wherein the memory ordering violation detection circuit, in performing the comparison, also considers a value of a wrap bit or wrap flag for each of the first load operation and the younger load operation, wherein the wrap bit or wrap flag indicates whether or not there has been at least one full wrap of the ROB.

15. The processor of any of claims 13-14, wherein the second information associated with an invalidation time of a cache line of a younger load operation that was completed and invalidated comprises at least one of the following: a time stamp indicating or associated with a time when the cache line of the younger load operation was invalidated; a retirement index value at a time when the cache line of the younger load operation was invalidated; a re-order buffer (ROB) retirement index value at a time when the cache line of the younger load operation was invalidated, wherein the ROB retirement index value indicates or points to an oldest instruction in the ROB; a load queue retirement index value at a time when the cache line of the younger load operation was invalidated, wherein the load queue retirement index value indicates or points to an oldest load operation in the load queue; a store queue retirement index value at a time when the cache line of the younger load operation was invalidated, wherein the store queue retirement index value indicates or points to an oldest store operation in the load queue; a timing indication generated by the processing core for an event that can be used to determine relative timing between events within the processing core.

16. The processor of any of claims 13-15, wherein:Attorney Docket No. 0237-013 WO 1 the first information comprises a first retirement index value at a time when the first cache line was filled or entered an entry of the cache of the processing core; and the second information for the younger load operation comprises a second retirement index value at a time when the cache line of the younger load operation was invalidated.

17. The processor of claim 16, wherein the first retirement index value comprises at least one of a retirement index value at a time when the first cache line filled or entered an entry of the cache of the processing core; a re-order buffer (ROB) retirement index value at a time when the first cache line filled or entered an entry of the cache of the processing core, wherein the ROB retirement index value indicates or points to an oldest instruction in the ROB; a load queue retirement index value at a time when the first cache line filled or entered an entry of the cache of the processing core, wherein the load queue retirement index value indicates or points to an oldest load operation in the load queue; or a store queue retirement index value at a time when the first cache line filled or entered an entry of the cache of the processing core, wherein the store queue retirement index value indicates or points to an oldest store operation in the load queue.

18. The processor of any of claims 16-17, wherein the second retirement index value comprises at least one of a retirement index value at a time when the cache line of the younger load operation was invalidated; a re-order buffer (ROB) retirement index value at a time when the cache line of the younger load operation was invalidated, wherein the ROB retirement index value indicates or points to an oldest instruction in the ROB; a load queue retirement index value at a time when the cache line of the younger load operation was invalidated, wherein the load queue retirement index value indicates or points to an oldest load operation in the load queue; or a store queue retirement index value at a time when a cache line of the younger load operation was invalidated, wherein the store queue retirement index value indicates or points to an oldest store operation in the load queue.Attorney Docket No. 0237-013 WO 119. The processor of any of claims 9-18, wherein the control circuit is configured to: upon detecting that a re-order buffer (ROB) retirement index value has wrapped once in the ROB since the fill time of the first cache line, set an old bit in the cache for the first cache line indicating that the first cache line is older than all instructions in the ROB, and thus indicating that the fill time for the first cache line occurred before any load operations in the processing core may have been invalidated.

20. The processor of any of claims 9-19, wherein the control circuit is configured to: upon detecting that a re-order buffer (ROB) retirement index value has wrapped once in the ROB since the fill time of the first cache line, delete an entry for the first cache line in a cache time tracker or in a fill time detection circuit, including deleting the first information for the first cache line, and set an old bit in the cache for the first cache line indicating that the first cache line is older than all instructions in the ROB.

21. The processor of any of claims 9-20, wherein the control circuit configured to determine, based on at least the first information, whether there has been a load-load memory ordering violation comprises a load queue control circuit or a memory ordering violation detection circuit configured to: based on reading data from the cache for the first cache line as part of processing the first load operation, read the first information associated with the fill time of the first cache line, wherein the first information is stored in a cache time tracker or a fill time detection circuit; and determine, based at least on the first information, whether there has been a load-load memory ordering violation.

22. The processor of any of claims 9-21, wherein the control circuit comprises: a fill time detection circuit configured to determine the first information associated with the fill time of the first cache line, wherein the fill time comprises a time when the cache line fills or enters an entry in the cache of the processing core; the fill time detection circuit configured to determine the first load operation that uses or accesses the first cache line; a memory ordering violation detection circuit configured to determine, based on at least the first information, whether there has been a load-load memory ordering violationAttorney Docket No. 0237-013 WO 1 based on whether there is a younger load operation in the processing core that: is younger than the first load operation, completed before the first load operation was completed, and a cache line of the younger load operation was invalidated before the fill time of the first cache line; and the memory ordering violation detection circuit configured to, if there has not been a load-load memory ordering violation, send a signal to the pipeline flush controller for the processing core to cancel a flush of instruction processing pipeline of the processing core, or omit performing the flush of instruction processing pipeline of the processing core.

23. A processor comprising: a processing core; the processing core comprising a control circuit configured to: determine a first load operation associated with a first cache line; with respect to performing or completing the first load operation, detect that a fill time of the first cache line into the core is older than all instructions in a re-order buffer (ROB) of the processing core, including older than all load operations in the ROB; and based on detecting that the first cache line being older than all instructions in the ROB, send a signal to cancel or omit performing a flush of instruction processing pipeline that may have been triggered based on the first load operation.

24. The processor of claim 23, wherein the control circuit is configured to: with respect to performing or completion of the first load operation, detect that an old bit or old flag for the first cache line is set to indicate that the first cache line is older than all instructions in the ROB, including all load operations in the ROB.

25. A processor comprising: a processing core; the processing core comprising a control circuit configured to: determine a first load operation associated with a first cache line; upon detecting that a re-order buffer (ROB) retirement index value has wrapped once in the ROB of the processing core since the first cache line was filled into the processing core, set an old bit or old flag for the first cache line indicating that the first cache line stored in a cache of the processing core is older than all instructions in the ROB, and thus indicatingAttorney Docket No. 0237-013 WO 1 that a fill time for the first cache line into a cache of the processing core occurred before any load operations in the ROB or processing core may have been invalidated; with respect to or during performing or completing the first load operation, detect that the old bit or old flag for the first cache line is set to indicate that the first cache line is older than all instructions in the ROB; and send a signal to cancel a flush of instruction processing pipeline of the processing core, or omit performing a flush of instruction processing pipeline of the processing core based on detecting that the old bit or old flag for the first cache line being set to indicate that the first cache line is older than all instructions in the ROB.

26. The processor of claim 25, wherein the control circuit comprises: a cache time tracker or other circuit configured to, upon detecting that a re-order buffer (ROB) retirement index value has wrapped once in the ROB of the processing core since the first cache line was filled into the processing core, set the old bit in the cache for the first cache line indicating that the first cache line is older than all instructions in the ROB; and a load queue, load queue control circuit or a memory ordering violation detection circuit configured to: during or with respect to performing or completion of the first load operation, detect that the old bit for the first cache line is set to indicate that the first cache line is older than all instructions in the ROB; and send a signal to a pipeline flush controller to cancel a flush of instruction processing pipeline of the processing core, or omit performing a flush of instruction processing pipeline of the processing core based on detecting that the old bit for the first cache line being set to indicate that the first cache line is older than all instructions in the ROB.

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