Serial memory buffer for serial attached memory module

Abstract

A buffer device for a serial attached memory system interfaces between a host device and one or more memory devices. The buffer device receives packetized commands from the host device for performing memory operations and facilitates transfer of read and write data between the host device and the one or more memory devices. The host device controls scheduling of the packetized commands. The serial buffer device generates memory device commands based on the packetized commands and sequences the commands to control command timing in a manner that meets timing specifications of the memory device. The memory buffer device may optionally perform memory media ECC computations to generate ECC bits for write data being written to the one or more memory devices and to verify ECC bits of read data being read from the one or more memory devices.

Description

SERIAL MEMORY BUFFER FOR SERIAL ATTACHED MEMORY MODULEBACKGROUND

[0001] In a serial attached memory module, a serial interface provides a link between the memory module and a host device. Serial attached memory modules can provide more spaceefficient designs and reduced packaging costs relative to traditional parallel interfaces.BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The teachings of the embodiments herein can be readily understood by considering the following detailed description in conjunction with the accompanying drawings.

[0003] FIG. l is a block diagram illustrating an example embodiment of a serial attached memory system including a buffer device for interfacing between a host device and one or more memory devices.

[0004] FIG. 2 is a flowchart illustrating an example embodiment of a process for processing a write command in a memory system in which memory media error correction code (ECC) computations are performed in a serial buffer device.

[0005] FIG. 3 is a flowchart illustrating an example embodiment of a process for processing a write command in a memory system in which memory media ECC computations are performed in a host device.

[0006] FIG. 4 is a flowchart illustrating an example embodiment of a process for processing a read command in a memory system in which memory media ECC computations are performed in a serial buffer device.

[0007] FIG. 5 is a flowchart illustrating an example embodiment of a process for processing a read command in a memory system in which memory media ECC computations are performed in a host device.

[0008] FIG. 6 is an example embodiment of a memory module of a serial attached memory system.

[0009] FIG. 7 is an example embodiment of a memory system in which multiple host devices interoperate with one or more memory modules.DETAILED DESCRIPTION

[0010] A buffer device for a serial attached memory system interfaces between a host device and one or more memory devices. The buffer device receives packetized commands from the hostdevice for performing memory operations in the one or more memory devices and facilitate transfer of read and write data between the host device and the one or more memory devices. The host device controls scheduling of the packetized commands, which may be optimized based on arbitration schemes, quality of service (QoS) schemes, hazard mitigation schemes, maintenance planning, or other scheduling factors. The serial buffer device generates and sequences memory device commands to one or more memory devices based on the packetized commands to carry out the memory operations in the order received. The packetized commands may be received with timing independent of the specific timing constraints of the memory device, and the memory buffer device may control timing of issuing the memory device commands to meet these timing constraints. For example, the memory buffer device may enforce minimum timing delays between consecutive memory device commands even when packetized commands are received without adequate timing delays. For read and write commands depending on the context, the buffer device may generate multiple commands (such as an activate command, a read / write command, and a precharge command) from a single packetized read or write command, and may control timing of the individual memory device commands to meet the timing specifications of the memory device. The specific sequence of commands may be context-dependent and dependent on the memory device specifications. For example, for multiple column accesses to the same row, the row may remain active and the buffer device 150 may sequence the column accesses without activating and precharging the row for each access. Optionally, the memory buffer device may perform memory media ECC computations associated with the data at rest in the memory device (which may be independent from ECC computations associated with data in transport under the packetized protocol). For example, the memory buffer device may generate ECC bits for write data being written to the one or more memory devices and to verify ECC bits of read data being read from the one or more memory devices.

[0011] FIG. 1 is an example embodiment of a serial attached memory system 100. The serial attached memory system 100 includes at least one host device 110 and at least one memory module 130 coupled by a serial communication link 180. In the illustrated example, a single host device 110 and single memory module 130 are shown. In various applications, the serial attached memory system 100 can include any number of memory modules 130 coupled to the same host device 110 (via different serial communication links 180 or via a shared link), and / or the serial attached memory system 100 can include multiple host devices 110 accessing the same memory module 130 (e.g., as shown in the configuration of FIG. 7 described below).

[0012] The communication link 180 may comprise a network-based communication link or a direct serial communication link. Communications between the host device 110 and the memorymodule 130 may conform to a packetized serial communication protocol at the physical and data link layers such as a coherent accelerator processor interface (e.g., OpenCAPI) protocol, a compute express link (CXL) protocol, a peripheral component interconnect express (PCI-e) protocol or other serial communication protocol suitable for communicating packetized commands and data in a serial attached memory system 100. The communication link 180 may implement a link-based ECC protocol associated with the in-transit packetized data or commands, which is independent of the memory media ECC computations associated with memory read and write operations.

[0013] The memory module 130 includes at least one buffer device 150 and at least one memory device 170. The memory device 170 may comprise a dynamic random-access memory (DRAM) device having an array of memory cells. The array of memory cells may be organized into one or more bank groups that each comprise a set of memory banks. Each memory bank comprises a set of memory cells arranged in rows and columns. A memory address of an individual memory cell may also be characterized by a package and / or chip identifier that identifies the memory device 170, a bank group, a bank address, a row address, and a column address.

[0014] The memory device 170 may operate with various timing constraints associated with different types of memory operations or sequences of operations. For example, a read / write timing constraint may enforce a minimum time between a row of the memory device 170 being activated and the memory device 170 performing a read or write operation associated with that row. Furthermore, the memory device 170 may be constrained to having a single row per bank activated at a given time. In another example, a timing constraint may enforce a minimum time between the memory device 170 writing data to a memory location and the memory device 170 reading the data from that memory location. Other timing requirements may be imposed based on the specifications of the memory device 170.

[0015] The buffer device 150 operates to translate and buffer commands and data communicated between the host device 110 and the memory device 170. Communications between the buffer device 150 and the host device 110 may conform to a packetized communication protocol compatible with the communication link 180. Communications between the buffer device 150 and the memory device 170 may conform to a standard memory device protocol (e.g., using communications over a command / address link, data link, and other memory device links).

[0016] In operation, the buffer device 150 receives packetized commands from the host device 110 and issues memory device commands to the memory device 170 to control its operation.The buffer device 150 may furthermore facilitate communication of data between the host device 110 and the memory device 170 by translating between packetized data communicated via the communication link 180 and the memory device data format used by the memory device 170.The buffer device 150 may communicate with the host device 110 according to a different command list and protocol than the command list and protocol used for communications between the buffer device 150 the memory devices 170. For read and write commands, the buffer device 150 may execute a sequence of memory operation commands from a single packetized read or write command. For example, in response to a packetized read or write command, the buffer device 150 may issue memory device commands for activating a row, performing the read or write, and subsequently precharging the row. The buffer device 150 may communicate with the host device 110 with command timing that is independent of timing constraints of the memory device 170. The buffer device 150 preserves the command order of the packetized commands received from the host device 110 (e.g., by issuing the commands in order of receipt), but controls relative timing between memory device commands to meet the timing constraints of the memory device 170.

[0017] In an example operation, the host device 110 may send a packetized write command and packetized write data to a buffer device 150. The buffer device 150 receives the packetized write command and the packetized write data, issues an activate command to a row of the memory device 170 (if not already active) specified in the packetized write command, and subsequently issues a write command and the write data to the memory device 170 in accordance with the timing constraints of the memory device 170 (e.g., enforcing a minimum and / or maximum time delay). Similarly, for a memory read, the host device 110 may send a packetized read command to the buffer device 150. The buffer device 150 issues an activate command to a row of the memory device 170 (if not already active), issues a read command to read the data from the memory device 170 according to a specific time delay, and then generates and sends packetized read data to the host device 110. When appropriate under the memory device specifications, the buffer device 150 may furthermore issue a precharge command following read or write operations with timing meeting the specifications of the memory device 170. The buffer device 150 may furthermore control timing of other types of commands from the host device 110 associated with maintenance (e.g., memory-specific commands such as explicit activate or precharge commands or buffer-specific maintenance commands), training (memory-specific or buffer-specific), or other operations such refresh operations, mode register read and write operations, and other memory operations. For sequences of packetized commands, the buffer device 150 preserves the ordering of the commands from the host device 110.

[0018] In an example implementation, the host device 110 includes a memory controller hub 112, one or more memory media controller front ends 114, and one or more host-side packetized serial interfaces 116. Other components of the host device 110 unrelated to the memory management functions described herein are omitted from FIG. 1. For example, a typical hostdevice 110 may include other computer elements (not shown) such as one or more processors, local storage, network interface modules, etc.

[0019] The memory controller hub 112 manages one or more memory media controller front ends 114. The memory controller hub 112 manages and coordinates memory operations for the host device 110. The memory controller hub 112 may perform functions such as generating memory commands to support processes executing on the host device 110, sending commands to appropriate memory media controller front ends 114, and managing data flow between processes of the host device 110 and the memory media controller front ends 114. The memory controller hub 112 may also perform address translations between a physical address used by the host device 110 and a row / column address used by the memory device 170. In some embodiments, the memory controller hub 112 may interoperate with multiple memory media controller front ends 114 that may be configured for interacting with different types of memory such as DRAM, FLASH, or hybrid memories.

[0020] The memory media controller front end 114 comprises an intermediate interface between the memory controller hub 112 and the host-side packetized serial interfaces 116. The memory media controller front end 114 may generate packetized memory commands that facilitate packetized data transfers to and from the buffer device 150 of the memory module 130. The memory media controller front ends 114 may furthermore perform functions such as command and data translation (e.g., to convert commands to formats specific to a memory type), local management and control functions, buffer and flow control, etc. The memory media controller front end 114 may also perform address translations (instead of or in addition to the memory controller hub 112) between a physical address used by the host device 110 and a row / column address used by the memory device 170.

[0021] In an example implementation, the memory media controller front end 114 may include scheduling logic 118, arbitration logic 122, Quality of Service (QoS) logic 120, hazard mitigation logic 124, maintenance logic 126, and optional memory media ECC logic 128. The scheduling logic 118 controls ordering of the packetized read and write commands for sending over the hostside packetized serial interface 116. For example, the scheduling logic 118 may optimize scheduling based on factors such as data availability and latency minimization. The scheduling logic 118 may issue the packetized commands and / or data according to timing consistent with the communication protocol of the communication link 180, but does not directly control the specific timing of when the commands are issued to the memory devices 170. Thus, the scheduling logic 118 may issue the packetized commands and / or data faster than minimum timing requirements of the memory devices 170 for receiving commands and / or data. The scheduling logic 118 may furthermore facilitate scheduling of other types of commands such as refresh commands, explicitactivate or precharge commands, or other commands associated with maintenance, training, and configuration.

[0022] Scheduling by the scheduling logic may be further supported by scheduling parameters generated by the arbitration logic 122, QoS logic 120, and / or hazard mitigation logic 124. The arbitration logic 122 facilitates prioritization between memory requests originating from different processes executing on the host device 110. The arbitration logic 122 may optimize for memory efficiency or other performance goals depending on the configuration. The QoS logic 120 identifies high priority memory commands and establishes appropriate priority levels for scheduling the commands. For example, QoS logic 120 may operate to prioritize command and / or data associated with certain types of streaming media commands or other data where low latency is prioritized. The hazard mitigation logic 124 detects and resolves potential conflicts or hazards that may arise from concurrent memory operations and which may impact scheduling. The maintenance logic 126 may function to control memory maintenance tasks such as refresh operations and error handling to ensure the reliability of memory components.

[0023] The memory media controller front end 114 may optionally include memory media ECC logic 128 for performing error correction detection and / or correction associated with write and read operations. For example, in a write operation, the memory media ECC logic 128 may generate ECC bits based on the write data for transmitting together with the write data in conjunction with packetized write commands. Similarly, for read operations, the memory media ECC logic 128 may obtain ECC bits received in conjunction with read data, and perform error detection and / or correction.

[0024] In an embodiment, the memory media controller front end 114 may operate independently of the specific command and data transfer protocol of a memory device 170 and without tracking an operational state of the memory device 170. In another embodiment, the memory media controller front end 114 may receive limited feedback from the memory device 170 (via the buffer device 150 and communication link 180) indicative of its specifications and / or operational state. For example, the memory media controller front end 114 may receive information from the memory devices 170 that may be used to further optimize command scheduling. In a further embodiment, the memory media controller front end 114 may send control information to the buffer device 150 to configure timing constraints of the memory device 170 that are implemented by the buffer device 150. In a further embodiment, the memory media controller front end 114 may send timing information together with individual commands to enable the sequencer 158 of the media controller back end 154 to operate with simplified logic to control sequencing.

[0025] In another implementation, the media controller front end 114 may include logic thatduplicates some or all of the sequencer 158 such that timing of data transmitted on the communication link 180 is regulated in a manner that avoids overflowing the buffer device 150. In this implementation, the sequencer 158 in the memory media controller backend 154 remains responsible for command sequencing to the memory device 170, but the duplicated logic (or portion thereof) may be used in the scheduling logic 118 to aid in scheduling decisions.

[0026] The memory media controller front end 114 couples with the communication link 180 via a host-side packetized serial interface 116. The host-side packetized serial interface 116 may conform to any serial communication protocol at the physical and data link layers such as OpenCAPI, CXL, PCIe or other serial protocols as described above.

[0027] In an embodiment, the memory controller hub 112 may couple to multiple memory media controller front ends 114, which in turn couple to respective host-side packetized serial interfaces 116. Each host-side packetized serial interface 116 may communicate over a channel of the communication link 180. Different communication channels may correspond to links between the host device 110 and different buffer devices 150 of the same memory module 130 or buffer devices 150 on two or more different memory modules 130. Furthermore, data may be communicated over multiple channels between a buffer device 150 and a multi-channel memory device 170. In an embodiment the memory media controller front end 114 may multiplex commands and data for multiple channels over a single serial communication link 180.

[0028] The buffer device 150 includes a buffer-side packetized serial interface 152, a memory media controller back end 154, and one or more memory device interfaces 156. The buffer-side packetized serial interface 152 may conform to any serial communication protocol compatible at the physical and data link layers with the communication link 180 (such as OpenCAPI, CXL, or other serial protocols) to enable communication with the host device 110 via packetized commands and data. The buffer-side packetized serial interface 152 may couple to one or multiple memory media control back ends 154 which each couple to one or more memory devices 170 via a respective memory device interface 156. The buffer devices 150 may facilitate communications over multiple channels of a memory module 130 (e.g., as shown in FIG. 7, described in further detail below).

[0029] The memory media controller back end 154 receives the packetized commands via the buffer-side packetized serial interface 152 and translates the packetized commands into memory operation commands for issuing to the memory device 170 via the memory device interface 156. In an embodiment, the memory media controller back end 154 may deserialize commands from one or more memory media controller front ends 114 over one or more channels. For write commands, the memory media controller back end 154 furthermore receives packetized write data, depacketizes the write data, and writes the write data to the memory device 170 inconjunction with a write operation. For read commands, the memory media controller back end154 reads data from the memory device 170, packetizes the read data, and sends the packetized read data to the host device 110 via the communication link 180.

[0030] The memory media controller back end 154 includes a sequencer 158 and memory media ECC logic 160. The sequencer 158 receives the packetized commands and data in the order scheduled by the memory media controller front end 114, translates the packetized commands into memory operation commands, and issues memory commands to the memory device 170 that conform to the timing constraints of the memory device 170. Translating the commands may include generating two or more memory operation commands from a single packetized command depending on the context and configuration of the memory device 170. For example, in response to a packetized write command or read command, the sequencer 158 may first generate an activate command followed by the write or read command in accordance with timing constraints of the memory device 170. The sequencer 158 may furthermore initiate precharge commands with appropriate timing after read and write operations. In other instances, the sequencer may issue multiple consecutive read or write accesses to the same row without separate activate and write commands for each access, as per the memory device specifications. The sequencer 158 may furthermore control timing of memory operations based on other constraints of the memory device 170, such as enforcing minimum timing between write operations to the same bank, or enforcing minimum timing for a read operation following a write to the same memory address.

[0031] The memory media ECC logic 160 facilitates error detection and / or correction relating to data transmitted between the buffer device 150 and the memory device 170. Thus, in a write operation, the memory media ECC logic 160 receives write data, performs an ECC computation to generate ECC bits associated with the write data, and writes the ECC bits to the memory device 170 in conjunction with the write operation. In a read operation, the memory media ECC logic 160 receives read data together with its ECC bits and performs an ECC computation to detect and / or correct errors in the read data before sending packetized read data to the host device 110.

[0032] In an alternative embodiment, the memory media ECC logic 160 may be omitted from the memory media controller back end 154 and may instead be implemented in the memory media controller front end 114 as described above.

[0033] Regardless of whether the memory media ECC logic 128, 160 is implemented in the buffer device 150 or the memory media controller front end 114 (or both), an independent ECC protocol may furthermore be employed to ensure integrity of packets in transit communication over the communication link 180. This packetized data ECC logic may be implemented via the respective packetized serial interfaces 116, 152.

[0034] FIG. 2 illustrates an example embodiment of a process implemented by the memory system 100 in association with a write command, where memory media ECC calculations are performed by the buffer device 150. The host device 110 sends 202 a packetized write command and write data to the buffer device 150 over the communication link 180. The buffer device 150 receives 204 the packetized write command and write data. The buffer device 150 issues an activate command to activate 206 a row of a memory device 170 (based on a memory address in the packetized write command). The buffer device 150 also performs 208 a memory media ECC calculation to generate ECC bits associated with the write data. The memory media ECC calculation may be performed before, after, or in parallel with activating 206 the row. The buffer device 150 writes 210 the write data and the ECC bits to the memory device 170 by issuing a write command (e.g., a column operation). The buffer device 150 may control the timing of sending the write command and the write data (with ECC bits) to the memory device 170 following the activate command to meet timing specifications of the memory device 170.Following the write operation, the buffer device 150 may issue a precharge command to precharge 212 the row associated with the write operation. The buffer device 150 may likewise control timing of the precharge command to meet timing specifications of the memory device 170.

[0035] FIG. 3 illustrates an example embodiment of a process implemented by the memory system 100 in association with a write command where the memory media ECC calculation is instead performed by the host device 110. The host device 110 performs 302 the memory media ECC calculation and sends 304 a packetized write command and write data including the calculated ECC bits to the buffer device 150 over the communication link 180. The serial buffer receives 306 the packetized write command and the write data including the ECC bits. The buffer device 150 issues an activate command to activate 308 a row of a memory device 170 (based on a memory address in the packetized write command). The buffer device 150 writes 310 the write data and the ECC bits to the memory device 170 by issuing a write command and then issues a precharge command to precharge 312 the row. The buffer device 150 may control the timing of issuing the activate command, write command, sending the write data, and issuing the precharge command based to meet the timing constraints of the memory device 170 as described above.

[0036] FIG. 4 illustrates an example embodiment of a process implemented by the memory system 100 in association with a read command, where memory media ECC calculations are performed by the buffer device 150. The host device 110 sends 402 a packetized read command to the buffer device 150 over the communication link 180. The buffer device 150 receives 404 the packetized read command. The buffer device 150 issues an activate command to activate 406a row of a memory device 170 (based on a memory address in the packetized read command). The buffer device 150 issues 408 a read command to read from the memory device and obtain read data, which includes ECC bits. The buffer device 150 performs 410 ECC verification and / or correction of the read data based on the ECC bits. The buffer device 150 then generates and sends 412 packetized read data to the host device 110. The packetized read data is received 414 by the host device 110 over the communication link 180. The buffer device 150 may furthermore issue a precharge command to precharge 416 the row associated with the read operation. The precharge command may be issued before, after, or in parallel with the steps of verifying 410 the read data and sending 412 the packetized read data to the host device 110.

[0037] FIG. 5 illustrates an example embodiment of a process implemented by the memory system 100 in association with a read command, where memory media ECC calculations are performed by the host device 110. The host device 110 sends 502 a packetized read command to the buffer device 150 over the communication link 180. The serial buffer receives 504 the packetized read command. The buffer device 150 issues an activate command to activate 506 a row of a memory device 170 (based on a memory address in the packetized read command). The buffer device 150 issues a read command to read from the memory device 508 and obtain read data, which includes the ECC bits. The buffer device 150 then generates and sends 512 packetized read data to the host device 110 including the ECC bits. The packetized read data is received 514 by the host device 110 over the communication link 180. The host device 110 may then perform 518 a memory media ECC calculation to verify and / or correct the read data based on the ECC bits. The buffer device 150 may furthermore issue a precharge command to precharge 516 the row associated with the read operation before, after, or in parallel with sending 512 the packetized read data to the host device 110.

[0038] In each of FIGs. 2-5, the buffer device 150 may control timing of activating the row, issuing the read or write commands and associated data, and precharging the row independently of information in the packetized commands. The buffer device 150 may also control timing of initiating the memory operations associated with a sequence of packetized commands in the order received but with timing independent of the timing of receipt of those commands. For example, the buffer device 150 may buffer packetized commands and / or data and initiate the memory operations with timing that meets timing constraints of the memory device 170.

[0039] While FIGs. 2-5 show example processes for situations where memory command sequences include both activate and precharge commands, in other situations, the activate and / or precharge commands are not necessarily issued dependent on the configuration and state of the memory device 170. The buffer device 150 may monitor the configuration and state of the relevant memory device 170 to control and issue the appropriate command sequence, which mayor may not include the activate and / or precharge commands. For example, an activate and precharge command may not be necessary when multiple consecutive read or write commands are issued to the same row.

[0040] FIG. 6 illustrates an embodiment of memory module 600 that includes two or more buffer devices 150, a plurality of memory devices 170 and supporting hardware including one or more serial link interfaces 606, a power control interface 602, and a power management and serial presence detect integrated circuit 604 (PMIC & SPD). The buffer devices 150 may operate in conjunction with a host device 110 and the memory devices 170 according to the operating principles described herein. The serial link interfaces 606 comprise pins and / or relevant logic for communicating with the host device 110 via the communication link 180. The power control interface 602 includes pins for delivering power and related control signals to the memory module 170. The PMIC & SPD may perform power management functions, presence detection functions, and / or other control and configuration functions associated with operation of the memory module 600.

[0041] In this example architecture, the memory module 600 may operate with two independent channels 610 (e.g., Channel A 610-A and Channel B 610-B) of the communication link 180. Each channel 610 is supported by a respective serial link interface 606 and buffer device 150. The buffer device 150 for each channel 610 may control a plurality of memory devices 170 (e.g., five memory devices 170 per channel). The power control module 602 and PMIC & SPD may be shared between the channels 610.

[0042] In other embodiments, the memory module 600 may support a different number of channels 610 and / or may have a different number of memory devices 170 per channel. For example, a four channel memory module 130 could include four buffer devices 150 and associated serial link interfaces 606, with each channel having any number of memory devices 170. In other embodiments, a four channel module 130 may operate with two buffer devices 150 or a single buffer device 150. In further embodiments, a memory device 170 may have two or more independent (or partially independent) channels and a buffer device 150 may facilitate communication to multiple channels of the memory device 170.

[0043] FIG. 7 illustrates another example of a memory system 700 that includes a pooled memory architecture. Here, one or more host devices 110 are coupled to one or more pooled memory modules 130 via a switch 770. In this configuration, available memory of the memory modules 130 may be shared between two or more host devices 110. The fabric manager 780 operates to coordinate between the multiple host devices 110 and facilitate memory allocation of available memory to different host devices 110. For example, the fabric manager 780 may dynamically allocate memory to different host devices 110 depending on memory requirementsof the different devices 110. In another embodiment, a switch 770 may be incorporated into one or more individual memory modules 130 and operates to switch multiple host devices 110 with one or more buffer devices 150 of the individual memory module 130.

[0044] Upon reading this disclosure, those of ordinary skill in the art will appreciate still alternative structural and functional designs and processes for the described embodiments, through the disclosed principles of the present disclosure. Thus, while particular embodiments and applications of the present disclosure have been illustrated and described, it is to be understood that the disclosure is not limited to the precise construction and components disclosed herein. Various modifications, changes and variations which will be apparent to those skilled in the art may be made in the arrangement, operation and details of the method and apparatus of the present disclosure herein without departing from the scope of the disclosure as defined in the appended claims.

Claims

WHAT IS CLAIMED IS:

1. A memory buffer device comprising: a packetized serial interface to communicate with a host device via a serial communication link to facilitate receipt of packetized commands from the host device in a command order, and to facilitate sending and receiving of data to and from the host device relating to the packetized commands; a memory device interface coupled to one or more memory devices; and a memory media controller to receive the packetized commands from the packetized serial interface in the command order, to generate memory device commands for one or more memory devices that preserve the command order of the packetized commands, to sequence the memory device commands over the memory device interface in accordance with timing specifications of the one or more memory devices, and to facilitate sending and received of data between the packetized serial interface and the memory device interface relating to the memory device commands.

2. The memory buffer device of claim 1, wherein the packetized commands include a packetized write command specifying a write address and is sent in association with write data for writing to the write address, and wherein in response to the packetized write command, the memory media controller generates and sequences an activate command to activate for a row of the one or more memory devices specified in the write address, a memory device write command to write the write data to the write address, and a precharge command to precharge the row following the write command, wherein the memory media controller controls relative timing of the activate command, the write command, and the precharge command.

3. The memory buffer device of claim 1, wherein the packetized commands include a packetized read command specifying a read address, and wherein in response to the packetized read command, the memory media controller generates and sequences an activate command to activate for a row of the one or more memory devices specified in the read address, a memory device read command to read from the read address, and a precharge command to precharge the row following the read command, wherein the memory media controller controls relative timing of the activate command, the read command, and the precharge command.

4. The memory buffer device of claim 1, wherein the packetized serial interface communicates with the host device over multiple channels, and wherein the memory media controller preserves the command order within each of the multiple channels.

5. The memory buffer device of claim 1, wherein the memory media controller is further configured to compute error correction code bits in association with write data received from the host device in association with packetized write commands, and to write the error correction code bits to the one or more memory devices together with the write data, and wherein the memory media controller is further configured to verify or correct error correction code bits read from the one or more memory devices prior to sending read data to the host device.

6. The memory buffer device of claim 1, wherein write data received from the host device in association with packetized write commands includes error correction code bits computed by the host device, and wherein read data sent to the host device in response to packetized read commands includes error correction code bits for verifying by the host device.

7. The memory buffer device of claim 1, wherein the packetized commands include at least one of a packetized write command, a packetized read command, a maintenance command, and training command.

8. The memory buffer device of claim 1, wherein the packetized serial interface and the memory device interface operate with independent command timing when receiving packetized commands from the host device and when sending memory device commands to the one or more memory devices.

9. The memory buffer device of claim 1, wherein the memory media controller receives packetized configuration commands from the host device indicative of the timing specifications of the one or more memory devices, and wherein the memory media controller sets internal configuration parameters for sequencing the memory device commands based on the timing specifications.

10. A memory module comprising: one or more memory devices; and a memory buffer device comprising: a packetized serial interface to communicate with a host device via a serial communication link to facilitate receipt of packetized commands from the host device in a command order, and to facilitate sending and receiving of data to and from the host device relating to the packetized commands;a memory device interface coupled to the one or more memory devices; and a memory media controller to receive the packetized commands from the packetized serial interface in the command order, to generate memory device commands for one or more memory devices that preserve the command order of the packetized commands, to sequence the memory device commands over the memory device interface in accordance with timing specifications of the one or more memory devices, and to facilitate sending and received of data between the packetized serial interface and the memory device interface relating to the memory device commands.

11. The memory module of claim 10, wherein the packetized commands include a packetized write command specifying a write address and is sent in association with write data for writing to the write address, and wherein in response to the packetized write command, the memory media controller generates and sequences an activate command to activate for a row of the one or more memory devices specified in the write address, a memory device write command to write the write data to the write address, and a precharge command to precharge the row following the write command, wherein the memory media controller controls relative timing of the activate command, the write command, and the precharge command.

12. The memory module of claim 10, wherein the packetized commands include a packetized read command specifying a read address, and wherein in response to the packetized read command, the memory media controller generates and sequences an activate command to activate for a row of the one or more memory devices specified in the read address, a memory device read command to read from the read address, and a precharge command to precharge the row following the read command, wherein the memory media controller controls relative timing of the activate command, the read command, and the precharge command.

13. The memory module of claim 10, wherein the packetized serial interface communicates with the host device over multiple channels, and wherein the memory media controller preserves the command order within each of the multiple channels.

14. The memory module of claim 10, wherein the memory media controller is further configured to compute error correction code bits in association with write data received from the host device in association with packetized write commands, and to write the error correction code bits to the one or more memory devices together with the write data, and wherein the memory media controller is further configured to verify or correct error correctioncode bits read from the one or more memory devices prior to sending read data to the host device.

15. The memory module of claim 10, wherein write data received from the host device in association with packetized write commands includes error correction code bits computed by the host device, and wherein read data sent to the host device in response to packetized read commands includes error correction code bits for verifying by the host device.

16. The memory module of claim 10, wherein the packetized commands include at least one of a packetized write command, a packetized read command, a maintenance command, and training command.

17. The memory module of claim 10, wherein the packetized serial interface and the memory device interface operate with independent command timing when receiving packetized commands from the host device and when sending memory device commands to the one or more memory devices.

18. The memory module of claim 10, wherein the memory media controller receives packetized configuration commands from the host device indicative of the timing specifications of the one or more memory devices, and wherein the memory media controller sets internal configuration parameters for sequencing the memory device commands based on the timing specifications.

19. A method for operating a buffer device of a memory module, the method comprising: receiving, packetized commands from a host device at a packetized serial interface in a command order set by the host device; based on the packetized commands, generating memory device commands for one or more memory devices that preserve the command order of the packetized commands; and sequencing the memory device commands over a memory device interface to issue the memory device commands in accordance with timing specifications of the one or more memory devices to facilitate one or more memory operations.

20. The method of claim 19, wherein sequencing the memory device commands comprises sequencing at least an activate command, a read or write command, and a precharge command in response to a packetized read or write command.

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