System and method for generation of a configurable module for elements in a network-on-chip (NOC)

Abstract

System and methods are implemented by a tool used in generation and synthesis of networks, such as a network-on-chip (NoC) having network interface units (NIUs). The tool includes a template tile or module tile with translation tables that can be adapted to represent many instances of elements, including the NIUs, for the NoC. The tool allows a designer or user to verify the performance of the element represented by the tile using a more precise and error-free verification based on verification of the module tile or template tile.

Description

Attorney Docket No. ART-149PCT PCT Application Serial No.: TBDTITLE

[0001] SYSTEM AND METHOD FOR GENERATION OF A CONFIGURABLE MODULE FOR ELEMENTS IN A NETWORK-ON-CHIP (NoC).CROSS-REFERENCE

[0002] This application claims priority to US Provisional Application Serial No. 63 / 701 ,572 titled SYSTEM AND METHOD FOR USING TILES TO IMPLEMENT ELEMENTS OF A NETWORK-ON-CHIP (NoC) by Xavier VAN RUYMBEKE, et al. filed on September 30, 2024 and claims priority to US Provisional Application Serial No. 63 / 721 ,40 titled SYSTEM AND METHOD FOR GENERATION OF ELEMENTS USING A GENERIC REPLICATABLE ELEMENT STRUCTURE by Xavier VAN RUYMBEKE, et al. filed on November 15, 2024, the entire disclosures of which are incorporated herein by reference.TECHNICAL FIELD

[0003] The present technology is in the field of system design and, more specifically, related to topology generation of networks-on-chip (NoC) using .BACKGROUND

[0004] Multiprocessor systems have been implemented in systems-on-chips (SoCs) that communicate through network-on-chips (NoCs). The SoCs include instances of source (initiator) intellectual property (IP) blocks and destination (target) IP blocks. Transactions, in the form of packets, are sent from an initiator to one or more target using industry-standard protocols. Targets and initiators are connected to the NoC through network interface units (NIUs). The initiator sends one or more request transactions to a target, using an address to select the target through an initiator NIU. The target is connected to the NoC through a target NIU. The NoC decodes the address and transports the request from the initiator to the target. The target handles the request. The target sends, as needed, a response transaction back to the initiator, which is transported by the NoC. Therefore, what is needed is design tool with the ability to generate a module, forAttorney Docket No. ART-149PCT PCT Application Serial No.: TBD example a Verilog module, that can be used to represent multiple elements, such as NIUs, based on a static configuration input.SUMMARY

[0005] In accordance with various embodiments and aspects of the invention, systems and methods are disclosed, which are executed by a tool, that allows for generation or creation of a Verilog module or tile that is used to represent multiple NIUs based on a static configuration input. The design and configuration of a NoC is very complicated. Further, the configuration of the NoC elements add complication to the design and generation process. The NoC includes the NIUs, which can be represented by similar configurations that are different instances and the similarity provides the ability to generate a single Verilog module to represent the various configurations and instances of the NIU. The NIUs use a translation table to handle the transactions. These translation tables are populated and prepared post-processing, which complicates design verification because it is done after the generation and synthesis of the NoC. These translation table are critical to the performance of the NoC given the role that the NIUs play in handling transactions. Typically, a representation of the NIU is included with an empty translation table. Then the translation table is filled (or populated) post-processing. This means that a design of the exact NIU in the NoC will not be verified because the translation tables of the final NIU is empty; the translation table of NIU is filled in post-processing.

[0006] For a given set of performance requirements, such as connectivity and latency between source and destination, frequency of the various elements, maximum area available for the NoC logic, minimum throughput between sources and destinations, position on the floorplan of elements attached to the NoC, it is a complex task to create an optimal NoC that fulfills all the requirements with a minimum amount of logic and wires. This is typically the job of the chip architect or chip designer to create this optimal NoC, and this is a difficult and time-consuming task. In addition to this being a difficult task, the design of the NoC is revised every time one of the requirement changes, such as modifications of the chip floorplan or modification of the expected performance. As a result, this task needs to be redone frequently over the design time of the chip. This process is time consuming, which results in production delays.

[0007] A NoC is an example for designing scalable communication architecture for SoCs. It is currently known to route messages through an array of data processing nodesAttorney Docket No. ART-149PCT PCT Application Serial No.: TBD to facilitate a plurality of paths directed to a destination. The paths through the NoC include many Network Interface Units (NIUs). Customers often create multiple instances of NIUs, which have an almost identical configuration; the difference between each NIU is a different translation table. The translation tables are the lookup tables that identify where to send information. The different translation tables are due to the fact that the NIUs (for example an initiator NIU) are configured to talk to different NIUs (for example different target NIUs). The problem is that these differences in translation tables means that the tool has to generate a different Verilog module for each one. Further problem is that the user or designer will have to independently verify and simulate each individual NIU module that is created. This is especially cumbersome for safety applications (e.g. automotive). The tile includes a translation table that contains all possible combinations for each possible configuration of an NIU. The inputs of the tile will be driven with a constant signal to specify the translation table that is to be used or selected for the specific instance of the tile.

[0008] An advantage of the invention is simplification of the design process and the work of the chip architect or designer. A NoC generation or synthesis method having representation of various NIUs using an adaptable and repeatable Verilog module tile significantly simplifies and expedites the design process and generation of the NoC.BRIEF DESCRIPTION OF THE DRAWINGS

[0009] FIG. 1 A illustrates a logic view of a network-on-chip (NoC) that includes various elements that create the NoC.

[0010] FIG. 1 B illustrates a NoC with elements placed on a floorplan of a network.

[0011] FIG. 2A illustrates a method for generating a NoC description based on a set of constraints in accordance with various aspects and embodiments of the invention.

[0012] FIG. 2B illustrates a block diagram of a NoC synthesis tool in accordance with various aspects and embodiments of the invention.

[0013] FIG. 3 illustrates a process for generation of a NoC using tiling in accordance with the various aspects and embodiments of the invention.

[0014] FIG. 4 illustrates a process for generation of a NoC using tiling in accordance with the various aspects and embodiments of the invention.

[0015] FIG. 5 illustrates a process for generation of a NoC using tiling in accordance with the various aspects and embodiments of the invention.Attorney Docket No. ART-149PCT PCT Application Serial No.: TBD

[0016] FIG. 6 illustrates a process for generation of a NoC using tiling in accordance with the various aspects and embodiments of the invention.

[0017] FIG. 7 illustrates a process for generation of a NoC using tiling in accordance with the various aspects and embodiments of the invention.

[0018] FIG. 8 illustrates a tile table of a template or module tile in accordance with the various aspects and embodiments of the invention.

[0019] FIG. 9 illustrates an instance table in accordance with the various aspects and embodiments of the invention.

[0020] FIG. 10 illustrates a unique instances for a tile in accordance with the various aspects and embodiments of the invention.

[0021] FIG. 11 illustrates a method for NoC topology synthesis processing in accordance with the various aspects and embodiments of the invention.

[0022] FIG. 12 illustrates a process of NoC synthesis based on a mesh custom subnetwork description in accordance with the various aspects and embodiments of the invention.DETAILED DESCRIPTION

[0023] The following describes various examples of the present technology that illustrate various aspects and embodiments of the invention. Generally, examples can use the described aspects in any combination. All statements herein reciting principles, aspects, and embodiments as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents and equivalents developed in the future, i.e., any elements developed that perform the same function, regardless of structure.

[0024] It is noted that, as used herein, the singular forms “a,” “an” and “the” include plural referents unless the context clearly dictates otherwise. Reference throughout this specification to “one aspect,” “an aspect,” “certain aspects,” “various aspects,” or similar language means that a particular aspect, feature, structure, or characteristic described in connection with any embodiment is included in at least one embodiment.

[0025] Thus, appearances of the phrases “in one embodiment,” “in at least one embodiment,” “in an embodiment,” "in certain embodiments," and similar language throughout this specification may, but do not necessarily, all refer to the sameAttorney Docket No. ART-149PCT PCT Application Serial No.: TBD embodiment or similar embodiments. Furthermore, aspects and embodiments described herein are merely exemplary, and should not be construed as limiting of the scope or spirit of the invention as appreciated by those of ordinary skill in the art. All statements herein reciting principles, aspects, and embodiments are intended to encompass both structural and functional equivalents thereof. It is intended that such equivalents include both currently known equivalents and equivalents developed in the future. Furthermore, to the extent that the terms "including", "includes”, “having", "has", "with", or variants thereof are used in either the detailed description and the claims, such terms are intended to be inclusive in a similar manner to the term "comprising."

[0026] As used herein, a “source” and a “initiator” refer to similar intellectual property (IP) modules or units and the terms are used interchangeably within the scope and embodiments of the invention. As used herein, a “destination” and a “target” refer to similar IP modules or units and the terms are used interchangeably within the scope and embodiments of the invention. As used herein, a transaction may be a request transaction or a response transaction. Examples of request transactions include write request and read request.

[0027] As used herein, a node is defined as a distribution point and / or a communication endpoint that is capable of creating, receiving, and / or transmitting information over a communication path or channel. A node may refer to any one of the following: switches, splitters, mergers, buffers, and adapters. As used herein, splitters and mergers are switches; not all switches are splitters or mergers. As used herein and in accordance with the various aspects and embodiments of the invention, the term “splitter” describes a switch that has a single ingress port and multiple egress ports. As used herein and in accordance with the various aspects and embodiments of the invention, the term “merger” describes a switch that has a single egress port and multiple ingress ports.

[0028] Reference is made to FIG. 1A, which illustrates a simple example of an SoC 100 including a plurality of initiators 110 and targets 120. Examples of the initiators 110 include central processing units (CPUs), graphics processing units (GPUs), video cards, accelerators, and direct memory access (DMA) controllers. Examples of the targets 120 include volatile memory, persistent memory, and peripherals.

[0029] The SoC 100 further includes a NoC 130. The NoC 130 sends request transactions from an initiator 110 to one or more targets 120 using industry-standard protocols. A request transaction includes an address of the target 120. The NoC 130Attorney Docket No. ART-149PCT PCT Application Serial No.: TBD decodes the address and transports the request transaction. The target 120 handles the request transaction and may send a response transaction, which is transported back to the initiator 110 via the NoC 130.

[0030] The NoC 130 includes a plurality of network interface units (NIUs) 140 and 150 and a transport interconnect 160. Each initiator 110 is coupled to the transport interconnect 160 via a corresponding initiator NIU 140. Each target 120 is coupled to the transport interconnect 160 via a corresponding target NIU 150.

[0031] Each NIU 140 and 150 is configured to convert the protocol used by its corresponding core into a transport protocol used inside the NoC 130. The transport protocol is typically based on the transmission of packets.

[0032] The transport interconnect 160 transports packets between the initiator NIUs 140 and the target NIUs 150. The transport interconnect 160 includes switches, adapters, and buffers. Switches may be used to route flows of traffic between sources and destinations. Adapters may be used to deal with various conversions between data width, clock domains, and power domains. Buffers may be used to insert pipelining elements to span long distances, or to store packets to deal with rate adaptation between fast senders and slow receivers or vice-versa.

[0033] In general, the NoC 130 is highly configurable. Certain components such as the NIUs 140 and 150 and switches have many different possible configurations. Other components such as buffers have relatively fewer possible configurations. Values of these component parameters can be varied to optimize the cost, performance, and power consumption of each element.

[0034] Referring now to FIG. 1 B, a NoC 130 is shown with various elements, such as NIUs, switches, and blockage areas in the floorplan. The NoC 130 includes various connectivity elements through various switches. In accordance with one aspect of the invention, a set of constraints are used as input to the tool, which is discussed in greater detail below. In accordance with some aspects of the invention, the tool executes a set of sub-steps and produces the description (synthesis) of a resulting NoC, such as the NoC 130, with its configured elements and the position of each element on the floorplan. The generated description is used to actually implement the NoC hardware, using the physical information produced to provide guidance to the back-end implementation flow.

[0035] Referring now to FIG. 2A, in accordance with some aspects of the invention, a set of constraints (210, 212, 214, 216, and Scenarios) are provided to a synthesis tool 220. In accordance with some embodiments and aspects of the invention, theAttorney Docket No. ART-149PCT PCT Application Serial No.: TBD performance and function of the tool 220 may include third-party ASIC implementation tools such as logic synthesis, place and route back end tools, and so on. A designer or user builds the set of constraints that are provide to the tool 220. The constraints are captured in machine-readable form, such as computer files using a defined format to capture information, that is understood and processed by the tool. In accordance with one aspect of the invention the format is XML. In accordance with another aspect of the invention the format is JSON. The scope of the invention is not limited by the specific format used.

[0036] Referring now to FIG. 2B, the tool reads the files containing the description of the constraints and executes the synthesis process. In accordance with some aspects of the invention, the synthesis process is broken down into multiple steps. A sequencer 250 is responsible for executing each step of the process. In accordance with some aspects of the invention, a set of steps are executed by the sequencer 250 of the tool 220 in light of the constraints set forth by the user / designer. The scope of the invention is not limited by the number and kind of steps the sequencer 250 may call and execute.

[0037] Referring again to FIG. 2A along with FIG. 2B, in accordance with the various aspects of the invention, the designer of the network provided and defines a set of constraints, such as constraints 210, 212, 214, and 216. A sequencer 250 receives various inputs, including: input 251 that includes global consolidation roadmaps with connectivity between initiators and targets including roadmap creation and information between each initiator and target; input 252 that includes traffic classification and main switch creation; input 254 that includes main switch decomposition into mergers and splitters; input 258 that includes information about physical distribution of splitters and mergers in the roadmap; input 259 that includes information about edge clustering; and input 260 that includes information about performance aware node clustering. In accordance with one aspect of the invention, the sequencer 250 also receives input 262 that includes information about optimization and network restructuring. In accordance with one aspect of the invention, the sequencer 250 receives 264 that includes information about routing and legalization. In accordance with various aspects and embodiments of the invention, the sequencer 250 uses all the inputs 251-264 to generate the network. In accordance with various aspects and embodiments of the invention, the sequencer 250 uses a combination of the inputs 251-264 to generate the network.

[0038] In accordance with the various aspects of the invention, input 251 includes input about the global consolidation roadmap. The global consolidation roadmap includesAttorney Docket No. ART-149PCT PCT Application Serial No.: TBD a consolidation model that captures the global physical view of the connectivity of the floorplan’s free space, as well as the connectivity across / between the initiators and targets. The global consolidation roadmap is modeled by a graph of physical nodes and canonical segments that are used to position the nodes, (splitters, mergers, switches, adapters) of the network under construction. The global consolidation roadmap is used to fasten computation. In accordance with various aspects of the invention, the global consolidation roadmap is persistent, which means that it is data the system exports and re-consumes in incremental synthesis and subsequent runs.

[0039] In accordance some aspects of the invention, input 259 incudes information about edge clustering. Edge clustering aims to minimize resources and enhancing performance goals through proper algorithms and techniques. In accordance with some aspects of the invention, edge clustering is applied in conjunction and in cooperation with input 260, node clustering. Edge clustering and node clustering can be used in combination by mixing, by being applied concurrently, or by being applied in sequence. The advantage and goal is to expand the spectrum of synthesis and span a larger solution space for the network.

[0040] In accordance with various aspects of the invention, input 262 includes information about re-structuring. Re-structuring includes a variety of transformations and capabilities. In accordance with some aspects of the invention, the transformations are logical in that there is a change in structure of the network. In accordance with some aspects of the invention, the transformation are physical because there is a physical change in the network, such as moving a node to a new location. Other examples of re- structing include: breaking a node into smaller nodes; reparenting between nodes; network sub-part duplication to avoid deadlocks and to deal with congestion; and physically re-routing links to avoid congestion areas or to meet timing constraints.

[0041] In accordance with various embodiments and aspects of the invention, the tool includes safety features related to memory protection that can classify faults, for example and limited to: malfunctions in the design, corruption of the circuit, changes in state of the NoC). The tool detects and classifies failures. The tool can solve the failure identified. The tool can mask the failure and provide solutions. In accordance with various embodiments and aspects of the invention, the tool allows the designer or user to take corrective action. In accordance with various embodiments and aspects of the invention, the tool reports information to the use and possible hardware configuration solutions, especially in a highly developed network (NoC) throughout the design stages.Attorney Docket No. ART-149PCT PCT Application Serial No.: TBD

[0042] In accordance with various embodiments and aspects of the invention, the tool also includes memory protection algorithm that saves bits. The tool detects can determine, when there is memory access and a fault, the cause of the fault. For a non-limiting example, faults can be caused by control logic handling the write-read process or faults can be caused by corrupted data cell location. In one example, the correct address is used, but the data stored at the address is corrupted. In the other example, there is a problem with the logic when the data is sent because the address is corrupted.

[0043] In accordance with various embodiments and aspects of the invention, the tool can determine the cause of the fault regardless of the type of scheme used to detect and correct error, including but not limited to full error protection schemes, such as priority error detection, double error protection. The tool’s algorithm saves bit and thereby creates memory protection using the algorithm.

[0044] In accordance with various embodiments and aspects of the invention, the tool classifies fault detection on the data. In accordance with various embodiments and aspects of the invention, the tool classifies fault when associated with fault in the control logic, such as when a given address to write in memory and or read from the memory was corrupted by the control logic. Thus, the tool can classify and protect memory using an algorithm where the data is corrupted due to error. In accordance with various embodiments and aspects of the invention, the tool can notify that there is a fault, for example on the control side the write operation has failed because the address is corrupted. In accordance with various embodiments and aspects of the invention, the tool includes an algorithm that makes it efficient in identifying how the data was corrupted, thereby creating flexibility and allowing control of problems.

[0045] In accordance with various embodiments and aspects of the invention, the tool also include a display feature that uses an algorithm to generate a butterfly view of the NoC for editing and manipulation by a designer / user to provide the advantage of improvement in speed for solving problem and updating the topology of the NoC to efficiently generate the NoC design.

[0046] In accordance with the various aspects of the invention, another constraint includes extension of the clock domain and power domain 212 can also be provided. The domain 212 includes areas of the chip where logic belonging to a particular domain is allowed to be placed.Attorney Docket No. ART-149PCT PCT Application Serial No.: TBD

[0047] In accordance with the various aspects of the invention, capabilities of the logic library, which will be used to implement the NoC, are provided. The information includes the size of a reference logic gate, and the time it takes for a signal to cover a 1 mm distance.

[0048] Referring again to FIG. 2A, in accordance with the various aspects of the invention, a SoC includes multiple clocks domains and multiple power domains. A clock domain is defined by all the logic fed by a given clock input. The clock input is characterized by the frequency of the clock, which is its most important parameters. A power domain is defined by all the logic getting power supply from the same power source. In accordance with the various aspects of the invention, the power source is gated, thus, the power domain can be on or off or isolated from other power domains. As such, the designer provides the set of clock domain and power domain constraints 212 as part of the initial design.

[0049] In accordance with the various aspects of the invention, initiators and targets are communicatively connected to the NoC. An initiator is a unit that send requests, typically read and write commands. A target is a unit that serves or responds to requests, typically read and writes commands. Each initiator is attached to or connected to the NoC through a NIU. The NIU that is attached to an initiator is called an initiator network interface unit (INIU). Further, each target is attached to the NoC through an NIU. The NIU that is attached to a target is called a target network interface unit (TNIU). The primary functionality of the NoC is to carry each request from an initiator to the desired destination target, and if the request demands or needs a response, then the NoC carries each target’s response to the corresponding requesting initiator. Initiators and targets have many different parameters that characterize them. In accordance with the various aspects of the invention, for each initiator and target, the clock domain and power domain they belong to are defined. The width of the data bus they use to send write and receive reads payloads is a number of bits. In accordance with the various aspects of the invention, the width of the data bus for the connection (the communication path to / from a target) used to send write requests and receive write responses are also defined. Furthermore, the clock and power domain definition are a reference to the previously described clock and power domains existing in the SoC, as described herein.

[0050] In accordance with the various aspects and embodiments of the invention, the tool generates a template or a Verilog module tile, which can be used to represent multiple NIUs based on a static configuration input that changes the template’s behavior. The NIUs that can be represented by a template or a module tile are similar and differ inAttorney Docket No. ART-149PCT PCT Application Serial No.: TBD translation table. In accordance with the various aspects and embodiments of the invention, the module tile contains all possible combinations of translation tables for each NIU that the module tile can represent. At least one input of the inputs of the module tile will be driven with a control signal or constant signal. The information presented by the control signal determines the instance or configuration of the tile. In accordance with the various aspects and embodiments of the invention, a control signal is used to specify a specific translation table content that will be used for a specific instance or representation of a network element, such as a NIU. In accordance with the various aspects and embodiments of the invention, as the control signal is changed, then the configuration table of the module tile is altered for the new instance of representing the NIU.

[0051] In accordance with the various aspects and embodiments of the invention, a configurable modular tile can be used to represent many different instances of N I Us (or any other element that can be replicated with minor changes from one instance to another) along with a control signal. This allows for configuration of the modular tile that have been verified one time. Thus, the user is able to verify the exact configuration of the modular tile (through representation in the table) that will be embedded into the interconnect or implemented in the design of the device without having to verify every instance. One advantage is that there is less error given that there is no need to verify each instance of the design post-processing and generate a new Verilog because the single representation of the modular tile is replicating an element and that modular tile or template tile was verified.

[0052] Referring now to FIG. 3, a process is show for generation of a replicated element or structure, such as a modular tile for a NIU, in accordance with the various aspects and embodiments of the invention. In accordance with various aspects and embodiments of the invention, the replicated tile (template tile) is the reference tile or the template tile. The process is performed by the design tool to generate the tile. The tool identifies a node or the user selects a node. The tool then determines in the node has children. If the node does not have children, then the tool generates the RTL for the object (node representation). If the node has a child, then for each child, the tool determines an object representation. If the object is a tile, then the tool determines if the object has already been generated. If an RTL or an object has already been generated for this tile, then the tool goes to the next node. If an RTL or the object has not been generated for this tile, then the tool generates the RTL for the object.Attorney Docket No. ART-149PCT PCT Application Serial No.: TBD

[0053] Referring now to FIG. 4, a process is shown that is executed by a design tool for generation of a NoC using tiles, in accordance with the various aspects and embodiments of the invention. The process starts by loading a project for the design tool. The tool then adds a root node to the stack. The tool, using the process, determines if the all the nodes have been added to the stack. If all nodes are added, then the load is finished. If the stack is not empty, then the tool retrieves the first node. The tool then determines if the node is a reference node. If the node is not a reference node, the tool generates the program object for the node and adds the children for the node to the stack. If the node is a reference node, then the tool retrieves (from memory) and loads information for the reference node (external file). The tool adds a listener for file changes. The tool then tags (adds notes to) the stack for the reference node as read-only value being set to true. Then the tool continues to check the stack to determine if the stack is empty.

[0054] Referring now to FIG. 5, a process is shown for top-down processing by the tool to generate a tile that is replicated for a project in accordance with the various aspects and embodiments of the invention. The tool creates various constraints as placeholders for the various instances that are represented by the tile. The tool determine if all the constraints have been added. If all constraints are added, then the tool adds the unit and determines if all the units or instances are added to the replicate tile or modular tile. If the units or instances of the specific tile are added to the general modular tile, then the tool configures the units using the constraints. The tool then checks all the units or instances of the modular tile. If the modular tile does not pass the checks, then the tool continues to configure the units and run the checks again. If the tile configurations pass the checks, then the tool generates a specification, reference tiles (the modular tile), the numbers of instance for the reference tile, and then the NoC is configured automatically and generated using the modular tile for the replicatable elements or tiles. Then the tool perform system level checks based on the generated configuration. If the configuration passes the checks, then the tool exports and RTL of the configuration. IF the configuration does not pass the checks, then the tool re-performs the configuration and makes changes as needed.

[0055] Referring now to FIG. 6, a process is shown for bottom-up processing by the tool to generate a tile that is replicatable and used to generate a NoC for a project in accordance with the various aspects and embodiments of the invention. The tool receives a specification or generates a specification based on parameters or constraints providedAttorney Docket No. ART-149PCT PCT Application Serial No.: TBD as an input to the tool. The adds units and configures the units. The tool then performs system level checks on the design and if the configuration does not pass the test, the tool then proceeds to reconfigure the units until the configuration passes the system level checks. If the configuration passes the system level checks, the tool then process to define the replicatable unit or tile and performs equivalence checks that include the defined or designed configuration of the tile and all the instances for the tile. IF the design passes the checks, then the tool exports the RTL configuration, which was created using the tile and the various instances of the time. When the tile is generated and all the instances are loaded in the tile design to the table for the tile, then any instance or configuration of tile will also pass the checks. If the tool checks the design and the design does not pass the configuration, then the tool re-configures the tile or unit design until the tile passes the system level checks and the tile equivalence checks.

[0056] Referring now to FIG. 7, a process is shown for the tool to update the unit or tile changes (reference file changes) of a tile that is replicatable in accordance with the various aspects and embodiments of the invention. The tool identifies or receives input of a reference tile or unit change. The tool can then notify the user and load the changes for the unit or object file into memory for the specific tile configuration. The tool then removes the old object file for the tile or unit. The tool also performs in-place imports for the new or changed reference file.

[0057] Referring now to FIG. 8 and FIG. 9, a tile table 400 is shown with parameters for configuration of the tile that can represent multiple configurations or instance of NIUs. Any tile can be specified in the tool in a dedicated table, such as tile table 400. The module of the tile contains parameters for the number of instances the user would like to create that can be represent by the modular tile, and a prefix and / or suffix to attach to instanced NoC element. The prefix / suffix can contain a “%d” that will be replaced with the instance index. In tile table 400, any NoC element (e.g. a socket) can be added to the tile module. The normal parameters for the added element may be displayed in the tile table 400. In accordance with some aspects and embodiments of the invention, in table 500 the tool displays the instances of the tiled elements as if they had been created manually. In accordance with some aspects of the invention, the instances (of a tile) may be marked as read-only, to indicate to the user that they are part of a single representation of the tile.

[0058] Referring now to FIG. 10, in accordance with some aspects and embodiments of the invention, a table 610 is shown wherein any change to the tile socket (or the tileAttorney Docket No. ART-149PCT PCT Application Serial No.: TBD template or tile module) is propagated automatically to any of the instances associated with the tile socket. In accordance with some aspects of the invention, some parameters may need to be unique for the instance. In accordance with some aspects of the invention, the parameter that are unique to one instance are overridden for the other instances.

[0059] A scenario can be represented as 2 matrices, one defining read throughputs and one defining write throughputs. In accordance with the various aspects of the invention, read throughput requirements will be used to size the response network, which handles data returning from targets back to initiator. Write throughput requirements will be used to size the request network, which is data going from initiator to target, in accordance with the various aspects of the invention. An example, in accordance with the various aspects of the invention, of the throughput requirements for the various scenarios can be represented in a table. The actual format used to represent a scenario can be different, as long as each pair of (initiator, target) has a precise definition of its minimum required throughput for read and for write. For example, in a table, read transaction from an initiator (M1) to a target (S1 ) has a minimum performance throughput of 100MB / S. In accordance with some aspects of the invention, in the table, a write transaction from M1 to S1 has a minimum throughput of 50 MB / s. In accordance with some aspects of the invention, scenarios are not defined for the tool, in which case the tool optimizes the NoC synthesis process for physical cost, such as lowest gate cost and / or lowest wire cost.

[0060] An initial network is created in accordance with the various aspects of the invention. The network implements the connectivity matrix with the following defined parameter or components:• one network interface unit per initiator,• one network interface unit per target,• one switch is created per defined traffic class, called the main switch of the class,• one switch after each initiator / initiator NIU that split traffic to the different main switches that this initiator needs to reach,• one switch before each target / target NIU that merges traffic from the different main switches that are sending traffic to that target

[0061] The data width of each switch, and the clock domain it belongs to, is computed using the data width of each attached interface, and their clock domain, as inputs to the tool. In accordance with the various aspects of the invention, each step that transformsAttorney Docket No. ART-149PCT PCT Application Serial No.: TBD the network, which is part of the NoC, also perform the computation of the data width and the clock domain of the newly created network elements.

[0062] Referring again to FIG. 2B, the network is shown wherein the tool’s process transforms of the network in accordance with the various aspects of the invention. The sequencer 250 has an input 254 representing the main switch decomposition into mergers and splitters. The tool decomposes each main switch of the network into its equivalent implementation with splitters and mergers. In accordance with the various aspects of the invention, some switches have a single ingress port and multiple egress ports. In accordance with the various aspects of the invention, some switches that have multiple ingress ports and a single egress port. Each main switch ingress port is connected to a splitter, each main switch egress ports is connected to a merger. For a main switch, splitters and mergers are connected together according to the connectivity table.

[0063] In accordance with the various aspects of the invention, the tool transforms the network in order to reduce the number of wires used between switches achievable, while keeping the performances as defined in the scenarios, which are a set of required minimum throughput between initiator and target. In accordance with the various aspects of the invention switches are clustered for performance aware switching, mergers and splitters that have been distributed on the roadmaps are treated like ordinary switches.

[0064] In accordance with an aspect of the invention, the tool uses a process that is iterative and will merge switches under the condition that performances are still met, until no further switch merge can occur. The tool uses a process that is described as follows, while no more switch fusion is possible, do the following:

[0065] a) Select a candidate switch for fusion with one of its neighbors. The selection process ensures all switches in the network are eventually candidates.

[0066] b) When a candidate is selected, search for a neighbor to fusion with. The neighboring criteria is based on evaluation of a cost function. The cost function shall return a switch that is “best suited” to fusion with the candidate. The definition of “best suited” is implementation dependent, but the cost functions shall be such that the potential fusion of the two switches maximizes the gain in term of at least one metric including: wire length; logic area; power; and performances, etc.

[0067] c) Test if, in case the fusion happens, that the performance scenarios will still all meet the minimum throughput requirements. If not, then theseAttorney Docket No. ART-149PCT PCT Application Serial No.: TBD two switches cannot be merged. The process executed by the tool searches for another neighbor until either no more neighbors can be found, in which case all switches are left intact, or one neighbor is found that can be merged with the candidate without violating the minimum throughput requirements of all scenarios, in which case the network is modified by merging the candidate switch with the neighbor.

[0068] In accordance with various aspects of the invention, it is possible for the process to ensure the switches do not grow above a certain size (maximum number of ingress ports, maximum number of egress ports). If a combined switch is above the set threshold, then the merge is prevented.

[0069] Referring again to FIG. 2B, an input 262 to the sequencer 250 includes various optimizations can be performed to further reduce the number of wires used by the network, the area of the network elements, and the power consumed by network elements. Examples of such optimization include: detection of links that can be removed because they are not used, or their traffic can be re-routed; reducing the width of a link if the link is wider than required by the scenarios; and performing wire length optimization through finding an optimal placement of all the switch elements that minimizes the total wire length of the network, wherein the total wire length of the network is the sum of the distance spanned by each connection between network elements times the width of that connection.

[0070] In accordance with various embodiments and aspects of the invention, the tool includes reliability, availability and serviceability (RAS) features as applied to configurable NoC designs.

[0071] Continuing with FIG. 2B, an input 264 to the sequencer 250 includes producing a legal NoC by modifying the location of the network elements so that the network elements fit in the allocated free space and do not overlap, and they exist in the corresponding clock and power domain limits. In accordance with various aspects of the invention, the area occupied on the die by each network element is computed using the information provided regarding the capabilities of the technology, such as the area of a reference logic gate. Then each element is tested for correctness of its placement (enough free space exists for the element, no other element overlaps). If the test fails, the element is moved until a suitable location is found where the test passes.

[0072] In accordance with one aspect and embodiment of the invention, the system performs the generation and synthesis process and all existing network routes areAttorney Docket No. ART-149PCT PCT Application Serial No.: TBD translated into segments and turns. In an embodiment, the whole NoC is described as a set of at least one segment as defined by the physical path existing between two nodes (S,D) for example. In accordance with the various aspects and embodiments of the invention, if the network is not deadlock-free, the system provides a “fail” notice and returns to the user, as the network or NoC must be initially deadlock-free in accordance with one or more aspects of the invention. The system also extract the set of connections that do not have defined routes and / or connections that need to be synthesized. Sort the extracted set of connections given a heuristic. In accordance with the various aspects and embodiments of the invention, for each connection Source “S” to Destination “D”, the single connection synthesis process involves using a configuration explorer, a configuration filtering module, a configuration selection module, splitting, creating, and route computing. Configuring, by assigning a clock domain and a data width setting, each of the newly created components, switches and links, such that the bandwidth requirements are fulfilled.

[0073] Referring now to FIG. 11 , a process 1500 used by a design tool is shown for a NoC generator using topology synthesis processing. Input 1503A to be synthesized may be new connection 1501 and / or input 1503B may be an existing segment 1502. New connection 1501 includes of creating new components, such as switches and / or links, defining a network route from “S” to “D”. Existing segment 1502 may be re-expressed as at least one segment and / or a pair of segments having at least one turn. An existing network has a set of turns that cannot be changed. When new segments are added, turns associated with the newly added segments are added as well to complete a route from “S” to “D”. The added turns do not generate cycles and / or deadlocks with existing turns.

[0074] Configuration explorer 1504 receives input 1503A being new connection 1501 and input 1503B being existing segment 1502. Since there are a plurality of ways to connect to a segment “S” to “D”, configuration explorer 1504 influences the best configuration based on each segment being assigned communication policy 1506. Configuration explorer 1504 explores different ways to connect “S” to “D” using exploration of legal configurations 1505. Legal configurations 1505 are a list of described parameters. Configuration explorer 1504 is configured to explore and / or review and analyze at least one configuration of possibilities indicating a location, traversing the segment, to split a segment from a list of meaningful configurations stored in memory. Configuration explorer 1504 may have a configuration with a new entry segment for connecting “S” to some segment of the NoC. If “S” is already connected, it already hasAttorney Docket No. ART-149PCT PCT Application Serial No.: TBD an entry segment. Configuration explorer 1504 may have a configuration with a new exit segment for connecting.

[0075] The cost of a given path is updated at each step according to communication policy 1506. In an example, moving within an existing segment away from the destination may have more or less cost than creating a new segment that directly reaches the destination depending on whether communication policy 1506 favors wire length and / or latency. It is within the scope of this invention for a well-established, shortest path algorithm to explore both concrete segments and identify potential future segments, using the cost updates as a way to effectively implement several communication policies.

[0076] The main configuration exploration process 1504 may be designed as specialized version of a common shortest-path algorithm including, but not limited to, A* and / or Dijkstra. A given step in the shortest path algorithm considers the different points that can be reached from the current point. The current point is at least one point along the physical path of an existing segment. The path from the current point in the current segment to a subsequent point is subject to considerations.

[0077] In an embodiment, the path may advance one step along the current segment’s path. In an embodiment, if the end of the segment’s path has been reached, the path may advance to the first point in the path of any of the next segments, such as segments that are directly connected to the current segment, and which the current segment is capable to “turn” to.

[0078] In an embodiment, if the destination is not connected, such as if no exit segment exists, the path may jump directly to the destination point. This corresponds to creating a new exit segment. The new and / or future exit segment is then added to the configuration.

[0079] In yet another embodiment, the path may jump to any point of any segment, as long as no cyclic-dependencies are created, the two segments have compatible communication policies, and the communication policy allows merging. This corresponds to creating a new internal segment, which is added to the configuration.

[0080] Referring again to FIG. 11 , configuration filtering module 1507 has a predetermined listing containing data including, but not limited to, which configurations are legal, which configurations result in deadlocks, which configurations are not optimal. Configuration filtering module 1507 filters configurations given multiple criteria including, but not limited to, communication policy 1506 based criteria and / or any custom criteria and only keeps a sub-set. In an example of custom criteria, a user such, as a programmer,Attorney Docket No. ART-149PCT PCT Application Serial No.: TBD may base the parameters on low latency defined by a shorter length between the route from “S” to “D”. The user may define a maximum length of a path. Configuration filtering module 1507 of communication policy 1506 will remove a route if the length of the path exceeds the user defined threshold. In another example, the parameters may be based on the use of a minimum number of extra wires. In another example, a parameter may be based on a cost function that favors a route from “S” to “D” having the lowest cost. Configuration filtering module 1507 is customizable to user predefined parameters. A user may set their own filters and discard certain types of configurations.

[0081] The first criteria is communication policy 1506 based criteria. A user may control the way in which new segments are created. Communication policy 1506 is a set of parameters that may be associated with any given connection in the network. The system may have a plurality of communication policies defined and each connection may be associated with one communication policy 1506. Communication policy 1506 has parameters and flags. In an example of a flag, low latency is when a connection should be implemented in a way that minimizes the total path length from source to destination. In another example of a flag, enable serialization is when the links involved in the path from source to destination are allowed to employ serialization to save wire. Some configurations for a given connection may not be legal with respect to communication policy 1506 governing the connection. Eligible configurations 1508 are a filtered version of legal configurations. In an example, if connection “S” to “D” is set to have a low latency communication policy, then a limit on the total length of the route and the number of hops or traversed components must be applied and configuration candidates that do not fall within these limits are discarded.

[0082] Referring again to FIG. 11 , after filtering, configuration filtering module 1507 outputs eligible configurations 1508. It is desirable to select one eligible configuration performed by configuration selection module 1509. Selecting the best configuration is achieved using configuration selection module 1509, which retains only one final configuration to be implemented as the final synthesis of connection “S” to “D”. The metric used to select a best configuration is configurable and may take several parameters into account, based on community policy 1506. In an embodiment, a communication policy parameter is total additional wire-length The length of extra created segments creates wire needed to traverse a route. There are costs associated with wire. It would be more desirable for a parameter to be aimed at minimizing the total wire length to reduce the cost of topology. In an embodiment, a communication policy parameter is total routeAttorney Docket No. ART-149PCT PCT Application Serial No.: TBD length. The total length of the route is the combination of the total of existing segments plus the newly added segments. This parameter is focused on minimizing the latency. In another embodiment, a communication policy parameter is based on bandwidth distribution. This parameter optimizes performance by focusing on traffic distribution and the associated level of congestion on the segments.

[0083] Once best configuration 1510 is selected, the system will implement 1511 best configuration 1510 by splitting the segments involved and creating 1512 new segments and turns and apply it to the network. It is within the scope of this invention for the best configuration to be the final configuration. When a segment is split, it is split at all the existing segments that need to be connected to new segments at the points dictated by the chosen configuration. In regards to optimization, if the splitting point is within a certain distance from one of the segment’s endpoints, and the endpoint is a switch, then the endpoint shall be reused for the connection instead of creating a new switch. This can reduce the number of created switches. Creating 1512 the required new segments dictated by the chosen configuration and activate the corresponding turns. The newly created 1512 segments and turns in combination with existing 1502 segments and turns are input into routing tool 1513 that generates final route 1514. The route is computed from “S” to “D” given the newly created segments. The route is stored in memory. Routing tool 1513 is routing connections on the geographical floorplan because the segment is defined in terms of its geographical path following the floorplan.

[0084] In an embodiment, the system may pre-set a number of common communication policies to make the choice easier for a user. It is more desirable for a user to pick from a list of presets instead of requiring a user to create a communication policy. Connections that are associated with different communication policies will have synthesized routes that are physically separated. During synthesis, configuration filtering module 1507 (FIG. 11 ) and configuration selection module 1509 (FIG. 11 ) rely on communication policy 1506 (FIG. 11 ) to output best configuration 1510 for implementing 1511 a route.

[0085] The basic method for incrementally synthesizing new connections while reusing existing segments is disclosed in accordance with the various aspects and embodiments of the invention, which includes spitting existing segments into new segments. At the end of the process, only the newly created components are configured such as, a clock and / or data width, and the existing components are left unaltered. Referring again to FIG. 11 , existing segments and turns 1502 are altered by user control at incrementality levels. AAttorney Docket No. ART-149PCT PCT Application Serial No.: TBD user utilizes communication policy 1506 to control the creation and selection of not only the new segments in a network, but also to modify the existing topology or segments. In an example, reusing an existing segment in new routes may not be desirable due to performance considerations or to previous optimizations that a user may have implemented and that depend upon the segment remaining unaltered. When a segment is split, a hop may be added to traverse a plurality of routes, which may not be the desired outcome. As a result, the system defines a number of incrementality levels, or modes, that are based on physical mutability of segments, physical mutability of switches, and logical mutability of network elements. It is more desirable to capture a user’s intent when synthesizing a set of new connections in the presence of an existing NoC topology.

[0086] In an alternate embodiment, incremental synthesis modes allow a user to customize how the existing topology is altered.

[0087] In regards to physical mutability of segments, a segment is mutable by default. The segment may be split to fork-out a new segment. A user may make a segment immutable if, for example, it is not desired to have a switch added to an existing route.

[0088] Referring to physical mutability of switches, a new segment may be connected to an existing endpoint of an immutable segment if the endpoint is a switch. If it is not desired to modify the physical size of the switch, then the switch may be immutable so that no new segments can be connected to the immutable switch.

[0089] Referring now to logical mutability of network elements, as a default, existing network elements including, but not limited to, data width and / or an assigned clock, are not reconfigured by the incremental synthesis process. Only newly created switches and adapters are configured. This may lead to inefficient configurations such as insufficient bandwidth and / or too many clock domain crossings. Any component may be marked as logically mutable to allow existing components to be reconfigured given new resulting topology. In an example of how preset incremental synthesis modes can be defined in the system based on the aforementioned concepts, three preset modes are discussed.

[0090] Referring not to FIG. 12, a process of NoC synthesis is illustrated based on a mesh custom subnetwork description. First, mesh segments are generated and physically placed optimally on the requested space. Second, the new mesh segments, now considered as pre-existing segments by the incremental synthesis process are used opportunistically when appropriate to generate the final routes. The result is a topology mixing an automatically generated regular mesh topology with new optimally synthesized segments. In a fully connected system NoC 1900 has each node 1901 connecting toAttorney Docket No. ART-149PCT PCT Application Serial No.: TBD every other node. Region 1902 is specified for a 3x3 mesh using an XY routing algorithm. As a result of the synthesis process 1903, NoC 1905 uses requested mesh segments and newly synthesized segments. Automatically synthesized local trees 1904 are shown. Mesh is generated and optimally placed within specified region 1906.

[0091] In accordance with other aspects of the invention, extension of clock and power domains on the floorplan are provided and each element is tested to ensure it is located within the bounds of the specified clock and power domain. If the test fails, the element is moved until a suitable location is found where the test is passing. Once a suitable placement has been found for each element, a routing is done of each connection between element. The routing process will find a suitable path for the set of wires making the connections between elements. After routing is done, distance-spanning pipeline elements are inserted on the links if required, using the information provided regarding the capabilities of the technology, based on how long it takes for a signal to cover a 1 mm distance.

[0092] In accordance with some aspects and embodiments of the invention, the tool generates one or more computer files describing the generated NoC that includes:

[0093] The list of network elements with their configuration: data width, clock domain.

[0094] The position of each generated network element on the floorplan.

[0095] The set of routes through the network elements implementing the connectivity.

[0096] In accordance with the aspects of the invention, a route is an ordered list of network elements, one for each pair of (initiator, target) and one for each pair of (target, initiator). The route represents how traffic between the pairs will flow and through which elements.

[0097] In accordance with various aspects of the invention, the tool is used to generate metrics about the generated NoC, such as: histograms of wire length distribution, number of switches, histogram of switch by size.

[0098] In accordance with another aspect of the invention, the tool automatically inserts in the network various adapters and buffers. The tool inserts the adapters based on the adaptation required between two elements that have different data width, different clock and power domains. The tool inserts the buffers based on the scenarios and the detected rate mismatch.Attorney Docket No. ART-149PCT PCT Application Serial No.: TBD

[0099] In accordance with some aspects and embodiments, the tool can be used to ensure multiple iterations of the synthesis are done for incremental optimization of the NoC, which includes a situation when one constraint provided to the tool is information about the previous run.

[0100] After execution of the synthesis process by the software, the results are produced in a machine-readable form, such as computer files using a well-defined format to capture information. An example of such a format is XML, another example of such a format is JSON. The scope of the invention is not limited by the specific format.

[0101] Some aspects of the invention employ an incremental approach to network synthesis. This incremental approach is useful in numerous contexts. For instance, in some embodiments, the incremental process begins from a specification and a clean floorplan. In these and other embodiments, some of which were discussed above,

[0102] In accordance with some aspects and embodiments, connections can have a communication policy, which specifies, for example, a connection’s sensitivity to latency.

[0103] Certain methods according to the various aspects of the invention may be performed by instructions that are stored upon a non-transitory computer readable medium. The non-transitory computer readable medium stores code including instructions that, if executed by one or more processors, would cause a system or computer to perform steps of the method described herein. The non-transitory computer readable medium includes: a rotating magnetic disk, a rotating optical disk, a flash random access memory (RAM) chip, and other mechanically moving or solid-state storage media. Any type of computer-readable medium is appropriate for storing code including instructions according to various example.

[0104] Certain examples have been described herein and it will be noted that different combinations of different components from different examples may be possible. Salient features are presented to better explain examples; however, it is clear that certain features may be added, modified and / or omitted without modifying the functional aspects of these examples as described.

[0105] Various examples are methods that use the behavior of either or a combination of machines. Method examples are complete wherever in the world most constituent steps occur. For example, and in accordance with the various aspects and embodiments of the invention, IP elements or units include: processors (e.g., CPUs or GPUs), randomaccess memory (RAM - e.g., off-chip dynamic RAM or DRAM), a network interface for wired or wireless connections such as ethernet, WIFI, 3G, 4G long-term evolution (LTE),Attorney Docket No. ART-149PCT PCT Application Serial No.: TBD5G, and other wireless interface standard radios. The IP may also include various I / O interface devices, as needed for different peripheral devices such as touch screen sensors, geolocation receivers, microphones, speakers, Bluetooth peripherals, and USB devices, such as keyboards and mice, among others. By executing instructions stored in RAM devices processors perform steps of methods as described herein.

[0106] Some examples are one or more non-transitory computer readable media arranged to store such instructions for methods described herein. Whatever machine holds non-transitory computer readable media including any of the necessary code may implement an example. Some examples may be implemented as: physical devices such as semiconductor chips; hardware description language representations of the logical or functional behavior of such devices; and one or more non-transitory computer readable media arranged to store such hardware description language representations. Descriptions herein reciting principles, aspects, and embodiments encompass both structural and functional equivalents thereof. Elements described herein as coupled have an effectual relationship realizable by a direct connection or indirectly with one or more other intervening elements.

[0107] Practitioners skilled in the art will recognize many modifications and variations. The modifications and variations include any relevant combination of the disclosed features. Descriptions herein reciting principles, aspects, and embodiments encompass both structural and functional equivalents thereof. Elements described herein as “coupled” or “communicatively coupled” have an effectual relationship realizable by a direct connection or indirect connection, which uses one or more other intervening elements. Embodiments described herein as “communicating” or “in communication with” another device, module, or elements include any form of communication or link and include an effectual relationship. For example, a communication link may be established using a wired connection, wireless protocols, near-filed protocols, or RFID.

[0108] To the extent that the terms "including", "includes”, “having", "has", "with", or variants thereof are used in either the detailed description and the claims, such terms are intended to be inclusive in a similar manner to the term "comprising."

[0109] The scope of the invention, therefore, is not intended to be limited to the exemplary embodiments shown and described herein. Rather, the scope and spirit of present invention is embodied by the appended claims.

Claims

Attorney Docket No. ART-149PCT PCT Application Serial No.: TBDCLAIMSWhat is claimed is:1 . A tool comprising a processor and non-transitory computer readable medium for storing code, wherein when the processor executes the code, the tool is caused to: analyze an input topology of a network-on-chip (NoC) along with constraints and performance parameters; and generate a tile including a connectivity table, wherein the tile represents a plurality of instances and each instance of the plurality of instances is selectable using a control signal provided as input to the tile in order to identify one instance of the plurality of instances an instance for the tile.

2. The tool of claim 1 , wherein to generate includes adding parameters to the tile for each instance of the plurality of instances and configuring at least one instance based on at least one constraint.

3. The tool of claim 1 is further caused to add at least one new instance to the tile and update the connectivity table.

4. The tool of claim 1 is further caused to test the tile to determine if the tile representing the plurality of instances passes performance parameters and meets the constraints for each instance.

5. The tool of claim 1 is further caused to export a Verilog for the tile.

6. A template tile representation a plurality of elements, the template tile comprising: a plurality of constraints; a plurality of instances, any one of which is selectable to allow the template tile to implement each of the plurality of elements, wherein each instance represents one configuration of the template tile corresponding to one element selected from the plurality of element and is configured using one or more of the plurality of constraints; and an input for receiving a control signal, wherein the control signal identifies one specific instance selected from the plurality of instances to be implement by the template tile.

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