Method for integration through crystallographic growth and release from inorganic light absorber

Abstract

Methods and corresponding structures for fabricating an integrated electronics structure are provided. A temporary stack is provided that includes a carrier body, a bonding layer, and an electronics structure base that is crystallographically grown on the bonding layer. An electronics structure is built on the electronics structure base, defining an integrated electronics structure that includes the electronics structure base and the electronics structure. A pulse of light is used to weaken the bonding layer, and the integrated electronics structure is separated from the carrier body.

Description

3530742.000901METHOD FOR INTEGRATION THROUGH CRYSTALLOGRAPHIC GROWTH AND RELEASE FROM INORGANIC LIGHT ABSORBERCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of United States Provisional Application No. 63 / 703,008, filed October 3, 2024, which is hereby incorporated herein by reference in its entirety.FIELD

[0002] The present disclosure generally relates to electronics device manufacturing, and more particularly equipment and methods that involve temporarily bonding an electronics structure to a carrier for building free-standing heterogeneous microelectronics structures.BACKGROUND

[0003] The present disclosure is directed to equipment and methods for debonding electronics structures built on temporary carrier structures. The methods provided herein can be employed to build fragile, thin electronics structures on rigid, maneuverable carriers with a releasable bonding layer that facilitates the fabrication of multi-layer, heterogeneous microelectronics structures such as microelectronic or MEMS devices, power devices, memory, photovoltaic devices, optical devices, interposers, and other structures comprising semiconductor base materials (e.g., Si) or alternative semiconductor base materials (e.g., GaN, GaAs, Ge, SiC, two-dimensional materials, etc.).SUMMARY

[0004] In one aspect, a method for fabricating an integrated electronics structure includes providing a temporary stack comprising a carrier body, a bonding layer, and an electronics structure base. The electronics structure base is crystallographically grown on the bonding layer. The bonding layer creates a bond between the carrier body and the electronics structure base. The method further includes building an electronics structure on the electronics structure base to define an integrated electronics structure that includes the electronics structure and the electronics structure base. The method further includes providing a pulse of debonding light to debond the integrated electronics structure from the carrier body. The bonding layer comprises a light-absorbing material configured to weaken the bond1CORE / 3530742.000901 / 232182323.13530742.000901 between the carrier body and the electronics structure base upon exposure to the pulse of debonding light.

[0005] In another aspect, a method for fabricating an integrated electronics structure includes applying an adhesive material on a surface of a rigid carrier body. The method further includes growing an electronics structure base on the adhesive material. The method further includes building an electronics structure on the electronics structure base to define an integrated electronics structure that comprises the electronics structure and the electronics structure base. The adhesive material allows the electronics structure base to extend from the adhesive material in a controlled crystal orientation. The carrier body is substantially transparent to light in a debonding light wavelength range, and the adhesive material is substantially absorptive of light in the debonding light wavelength range.

[0006] Other objects and features will be in part apparent and in part pointed out hereinafter.2CORE / 3530742.000901 / 232182323.13530742.000901BRIEF DESCRIPTION OF THE DRAWINGS

[0007] FIG. 1 A is a diagram of a carrier-electronics structure stack in accordance with an example method for electronics structure integration;

[0008] FIG. IB is a diagram of the stack wherein the electronics structure is subjected to surface patterning;

[0009] FIG. 1C is a diagram of the stack wherein a first interconnect is built on the electronics structure;

[0010] FIG. ID is a diagram of the stack wherein a second electronics structure and a second interconnect are built on the first interconnect;

[0011] FIG. IE is a diagram of the stack of FIG. ID subjected to a debonding light pulse

[0012] FIG. IF is a diagram of the electronics structure and carrier after debonding;

[0013] FIG. 2A is a diagram of the first carrier-electronics structure stack and a second carrier-electronics structure stack to be bonded together in accordance with another example method for electronics structure integration;

[0014] FIG. 2B is a diagram of the first stack and the bonded stack bonded together to form an integrated electronics structure, wherein the second stack is subjected to a debonding light pulse;

[0015] FIG. 2C is a diagram of the integrated electronics structure of FIG. 2B after debonding of the second stack;

[0016] FIG. 2D is a diagram of the integrated electronics structure wherein the exposed integrated electronics structure is subjected to surface patterning for subsequent integration;

[0017] FIG. 3 A is a diagram of a first carrier-electronics stack in accordance with another example method for electronics structure integration;

[0018] FIG. 3B is a diagram of the first stack and a second carrier-electronics structure stack bonded together to form an integrated electronics structure, wherein the second stack is subjected to a debonding light pulse;

[0019] FIG. 3C is a diagram of the integrated electronics structure of FIG. 3B after debonding of the second stack; and

[0020] FIG. 4 is a diagram of a stack in accordance with an alternative example.

[0021] Corresponding reference characters indicate corresponding parts throughout the drawings.3CORE / 3530742.000901 / 232182323.13530742.000901DETAILED DESCRIPTION

[0022] The present disclosure relates to the fabrication of integrated electronics structures using varieties of temporary carriers (broadly, "carrier structures") used in TBDB. In various methods, layers of materials can be added to a carrier structure to form a stack that broadly includes a carrier structure (e.g., a carrier body), a temporary bonding layer (or foundation layer) for electronics structures, and one or more electronics structures deposited on the bonding layer comprising semiconductor materials with crystallographic oriented pathways. When carried by the carrier structure, the one or more electronics structures can be subjected to processing operations (e.g., substrate thinning, redistribution layer (RDL) buildup, deep reactive ion etching (DRIE), photolithography, sputtering, via formation, plating, building of additional device layers, and other suitable operations). Additionally, multiple stacks can be joined and bonded together to form an integrated electronics structure (e.g., a heterogeneous integrated microelectronics device). After the desired processing has been completed, the processed electronics structure can be debonded from the carrier using a light source to weaken the temporary bonding layer. In photonic debonding, a flashlamp is used to provide one or more pulses of intense, incoherent light (broadly, debonding light) that is absorbed by the temporary bonding layer, e.g., to generate heat. In laser debonding, a laser is used to generate intense light (broadly, debonding light) that is absorbed by the temporary bonding layer. The process can be scaled for full-wafer-size release or for singulated devices (e.g., chips).

[0023] Referring to FIGS. 1 A-1F, an example of an integrated electronics structure fabrication process using a temporary carrier structure is shown. A temporary stack suitable for debonding using a debonding light is shown generally as reference number 100 in FIG. 1 A. The stack 100 includes a carrier body 102, a bonding layer 104 deposited on a carrying surface of the carrier body, and a first electronics structure base 106 deposited on the bonding layer opposite the carrier body. The carrier body 102 is a rigid substrate and can comprise a material that is substantially light-transmissive in a debonding light spectrum (e.g., NIR, visible light, and / or UV) such as glass or sapphire. The bonding layer 104 includes an inorganic adhesive material that is configured to absorb a substantial amount of debonding light transmitted through the carrier body 102 to provide sufficient energy for debonding (see, e.g., FIG. IE). The adhesive material is configured to weaken (e.g., decompose) during debonding but is thermally resistant with respect to other processing operations like processing at an elevated steady-state temperature that is lower than a critical threshold debonding temperature for the adhesive material. The adhesive material may be capable of4CORE / 3530742.000901 / 232182323.13530742.000901 generating gas in a controlled manner during debonding, though the adhesive material may be configured generally not to outgas in a vacuum. Additionally, the adhesive material of bonding layer 104 has a crystallographic structure that enables substrate growth that extends from the bonding layer in a controlled crystal orientation (or potentially multiple controlled crystal orientations in various regions). It is contemplated that the crystallographic structure of the adhesive material promotes epitaxial substrate growth, as opposed to amorphous substrate growth.

[0024] The adhesive material of the bonding layer 104 can take several forms. As a first non-limiting example, the adhesive material can comprise a ceramic or semiconductor compound, such as TiN, Si2Ns, GaN, GaAs, AgNCh, AgO, phosphors, silicon oxides, hafnium oxides, or zirconium oxides. As a second non-limiting example, the adhesive material can comprise a phase-changing compound that undergoes a phase transition (e.g., gasifies) upon exposure to light and / or heat, which can result in a change in density (e.g., an increase or decrease in density) that disrupts or cleaves the adhesive bond, such as Sn-Zn alloys, Cu-Ti alloys, and / or salt hydrates. As a third non-limiting example, as is further described in greater detail below in connection with FIG. 4, the bonding layer 104 can comprise two layers of different materials (e.g., layers 404, 405) which chemically react to produce a gaseous byproduct when heated during debonding. For example, a pairing of Al and Si sub-layers or of Ga and P sub-layers can be used in accordance with the third example.

[0025] Referring now to FIG. IB, the first electronics structure base 106 can be built (e.g., processed, patterned, etc.) while carried on the carrier body 102, effectively causing the temporary stack 100 to grow. For example, the first electronics structure base 106 can be a crystalline substrate matched with the bonding layer 104. Matching the first electronics structure base 106 with the bonding layer 104 preferably results in a grain size that is larger than the substrate to minimize defects (e.g., fewer than 109defects per cm2for suitable fabrication conditions). After the building stage, the first electronics structure base 106 defines a contact surface 108. As is generally shown in the examples provided herein, a variety of additional electronic structures can be built on the contact surface 108. For example, in FIG. 1C, a first interconnect structure 110 is built on the contact surface 108. The temporary stack 100 can be grown by placing additional electronics structures above the first interconnect structure 110, e.g., by building structures directly on the first interconnect structure or by bonding already-built structures thereto. For example, as seen in FIG. ID, a second electronics structure base 112 and a second interconnect structure 114 are built above the first interconnect structure 110 to define an integrated electronics structure 120 (e.g., a5CORE / 3530742.000901 / 232182323.13530742.000901 device) that is carried on the carrier body 102 and supported by the bonding layer 104. Optionally, the bonding layer 104 can comprise a material that is substantially transmissive (e.g. around 50% or greater) to light in a processing light wavelength range (e.g., NIR and / or IR light wavelengths), allowing for use processing equipment that emits light in the processing light wavelength range that is directed through the carrier body, which is also substantially transmissive to light in the processing light wavelength range, as well as the bonding layer 104. The processing light is absorbed by one or more of the electronics structures beyond the bonding layer 104 to facilitate processing of one or more of the electronics structures supported by the bonding layer. As an example for purposes of illustration, NIR or IR processing equipment can be used to generate heat in the second interconnect 114 in a situation where the integrated electronics structure 120 is bonded (e.g., by thermocompression bonding or hybrid bonding) to another electronics structure, similar to the formation of integrated electronics device 240 described in greater detail below in connection with FIG. 2B.

[0026] Referring now to FIGS. IE and IF, after completion of work on the integrated electronics structure 120, the integrated electronics structure can be debonded from the carrier body 102 by exposing the bonding layer 104 to a debonding light emitted by a light source 150 and transmitted through the carrier body 102. In FIG. IE, the light source 150 is a xenon flashlamp, which is a pulsed light source configured to emit one or more intense pulses of incoherent light in at least the visible spectrum of light (e.g., a broadband spectrum). It is contemplated that other kinds of light sources can be used without departing from the scope of the present disclosure. A substantial amount (e.g., at least 50%) of the debonding light is absorbed by the bonding layer 104, which causes the bonding layer to weaken so the integrated electronics structure 120 can be separated from the carrier body 102. For example, adhesion in the bonding layer 104 can be reduced as a result of crystallographic phase change within the bonding layer, chemical dissociation, or one or more chemical reactions in the bonding layer. It will be appreciated that some residual portions of the bonding layer 104 and / or byproducts from the debonding process may remain on the carrier body 102 and the integrated electronics structure 120 and can be cleaned by chemical or mechanical means. During the debonding described herein in connection with FIG. IE, it is contemplated that the non-carrier side of the integrated electronics structure 120 may be supported or handled by a supportive force provided by a distributed pressure apparatus and / or a weak adhesive such as a tape frame (not shown), though other suitable structures or equipment can be used without departing from the scope of the present disclosure.6CORE / 3530742.000901 / 232182323.13530742.000901

[0027] In the above example, when the bonding layer 104 is transmissive to light in a processing light wavelength range, it will be appreciated that a debonding light wavelength range of the light source 150 and the processing light wavelength range are different. For example, the light source 250 may generally be configured to emit debonding light in a broadband debonding light wavelength range that can include NIR, visible, and UV light range, whereas the bonding layer 104 is configured to transmit light of a narrower band (e.g., IR) as the processing light wavelength range. In certain situations, there may be an overlap (e.g., a partial overlap) between the debonding light wavelength range and the processing light wavelength range, e.g., where the light source 150 emits broadband light that includes some amount of NIR light in the processing light wavelength range. In this instance, it will be appreciated that the bonding layer 104 can be transmissive of light in the NIR wavelength spectrum while also being substantially absorptive of light in the broadband debonding light spectrum without departing from the scope of the disclosure. For example, the bonding layer 104 can be substantially absorptive of light in other significant portions of the debonding light wavelength range, such as UV light and visible light.

[0028] It will be appreciated that two temporary stacks comprising complementary electronics structures can be bonded face-to-face to form some or all of an integrated electronics structure as an alternative to the vertical building processes generally described above in connection with FIGS. 1 A-1F. Referring to FIGS. 2A-2D, an additional example of an integrated electronics structure fabrication process using temporary carrier structures is shown. A first temporary stack suitable for debonding using a debonding light is shown generally as reference number 200 in FIG. 2A. The first stack 200 includes a respective carrier body 202, a respective bonding layer 204 deposited on a carrying surface of the carrier body, a respective first electronics structure base 206 deposited on the bonding layer opposite the carrier body, and a respective first interconnect structure 210 built on the first electronics substrate. The exposed side of the first interconnect structure 210 defines a contact surface 212 which is configured to be directly or indirectly coupled to a surface of another electronics structure as described in greater detail below. It will be appreciated that the various structures of the first stack 200 are generally similar to the features of the carrier body 102, bonding layer 104, first electronics structure base 106, and first interconnect structure 110 described above in connection with FIGS 1 A-1C and can be formed in substantially the same way using the same or similar materials. Accordingly, the above-described principles of crystallographic growth apply when using the bonding layer 204 to build the first electronics structure base 206 in an effective manner with minimal structural defects.7CORE / 3530742.000901 / 232182323.13530742.000901

[0029] Referring still to FIG. 2A, a second temporary stack suitable for debonding using a debonding light is shown generally as reference number 230. The second stack 230 includes a respective carrier body 232, a respective bonding layer 234, and a respective electronics structure base 236. The exposed side of the electronics structure base 236 defines a contact surface 238 which is configured to be directly or indirectly coupled to a surface of another electronics structure, such as the contact surface 212, as described in greater detail below. The carrier body 232, bonding layer 234, and second electronics structure base 236 generally have characteristics similar to the carrier body 102, bonding layer 104, and first electronics structure base 106 described above in connection with FIGS. 1 A-1B and can be formed in the same or a similar way using the same or similar materials. Moreover, it is contemplated that the respective material of each bonding layer 204, 234 may be the same or may be different, for example, for effectiveness with respective materials of the respective electronics structure base 206, 236 built on each respective bonding layer. However, it will be appreciated that the underlying principle of crystallographic growth for structured building is generally consistent regardless of the material that is used.

[0030] Referring now to FIG. 2B, the first stack 200 and the second stack 230 are bonded to form an integrated electronics structure 240. For example, hybrid bonding, diffusion bonding, and / or thermocompression bonding techniques can be used. As discussed above in connection with the bonding layer 104, it is contemplated that one or both of the respective bonding layers 204, 234 can be substantially transmissive to light in a processing wavelength range (e.g., NIR or IR light) to facilitate the heating of material for hybrid or thermocompression bonding or other forms of processing. After the integrated electronics structure 240 is formed, the carrier body 232 of the second stack 230 may be selectively debonded from the electronics structure base 236 using a light source 250. It will be appreciated that the debonding light wavelength, intensity, duration, and other parameters associated with the light source 250 may be different from the operating conditions for the light source 150 described above in connection with FIG. IE, e.g., depending on the physical, thermal, and / or chemical properties of the bonding layer 234 relative to bonding layer 104.

[0031] As can be seen in FIG. 2C, when the integrated electronics structure 240 is released from the carrier body 232 and after any residual portions of bonding layer 234 have been removed therefrom, the exposed side of the integrated electronics structure can be processed (e.g., by thinning, via formation, surface smoothing, etc.) to provide a foundation for further building of layers as generally described above in connection with FIGS. 1C-1D and / or additional cycles of being bonded with electronics structures carried on other stacks as8CORE / 3530742.000901 / 232182323.13530742.000901 generally described above in connection with FIGS. 2A-2B. For example, in FIG. 2D, the electronics structure base 236 is shown with patterns formed on an exposed side of the integrated electronics structure 240 to define a contact surface 242. Additional electronic materials can be deposited or bonded at contact surface 242 to form a larger integrated electronics structure, e.g., by building a structure like the first interconnect structure 110 as shown in FIG. 1C or by bonding a structure the stack 200 as shown in FIG. 2B. It will be appreciated that other kinds of electronics structures can be built on or bonded to the integrated electronics structure without departing from the scope of the disclosure. After all desired electronics structures are integrated, the carrier body 202 can be debonded from the first electronics structure base 206 using a light source such as flashlamp 250 configured to emit incoherent broadband light, resulting in a debonded integrated electronics structure that can be placed in larger devices, such as panels, boards, or films. It will be appreciated that different debonding parameters (debonding light wavelength, pulse duration, intensity, etc.) may vary from those of light source 250 depending on the physical, thermal, and / or chemical properties of the bonding layer 204.

[0032] Referring now to FIGS. 3A-3C, a further example of an integrated electronics structure fabrication process using temporary carrier structures is shown. A first temporary stack suitable for debonding using a debonding light is shown generally as reference number 300 in FIG. 3 A. The first stack 300 includes a respective carrier body 302, a respective bonding layer 304 deposited on a carrying surface of the carrier body, a respective first electronics structure base 306 deposited on the bonding layer opposite the carrier body, a structured electronics substrate 308 deposited on the first electronics structure base 306, and one or more contacts 310 located on portions of the structured electronics substrate. It will be appreciated that wells or trenches 312 can be formed in the structured electronics substrate 308 (e.g., by etching) before or after the contacts 310 are deposited to provide open space which can be used in resulting electronics devices, e.g., for microfluidics channels or wave blockers for a photonics system. A contact surface 314 is formed on each of the contacts 310. In some embodiments, multiple contact surfaces 314 (e.g., all of the contact surfaces) can be substantially coplanar, which may facilitate bonding with other electronics structures. The structures of the first stack 300 can comprise materials like those described above in connection with the stack 100 of FIG. IB. Accordingly, the above-described principles of crystallographic growth apply when using the bonding layer 304 to build the first electronics structure base 306 in an effective manner with minimal structural defects. The structured9CORE / 3530742.000901 / 232182323.13530742.000901 electronics substrate 308 can comprise a physically stable material that is conductive, semiconductive, or configured to accommodate electrical conduits such as vias.

[0033] Referring now to FIG. 3B, the first stack 300 is bonded to a second temporary stack 320 suitable for debonding using a debonding light. The second stack 320 includes a respective carrier body 322, a respective bonding layer 324, a respective electronics structure base 326, and an interconnect structure 328 having generally similar characteristics to corresponding elements in the stack 200 described above in connection with FIG. 2A and promoting the principles of crystallographic growth in electronics structure base 326 as described above. Optionally, one or both of the respective bonding layers 304, 324 comprises material that is at least partially transmissive to light in a processing light wavelength range as described above in connection with the bonding layer 104. When one or both of the respective bonding layers 304, 324 are at least partially transmissive to light in the processing light wavelength range (e.g., NIR or IR), the bonding of the first stack 300 and second stack 320 can be facilitated by using a processing light source that emits light in the processing light wavelength range to heat the interconnect structure 328 and / or the structured electronics substrate 308. When the first stack 300 is bonded to the second stack, an integrated electronics structure 340 is formed.

[0034] Referring now to FIGS. 3B and 3C, the carrier body 322 is debonded from the integrated electronics structure 340 by exposing the bonding layer 324 to a debonding light (e.g., incoherent light in a broadband debonding light wavelength range) emitted by a light source 350 and transmitted through the carrier body 322. A contact surface 342 is exposed on a non-carrier side of the integrated electronics structure 340, and additional processing, building, and / or bonding can occur on the contact surface 342 in accordance with the principles described above in connection with FIGS. ID and 2A-2B, as non-limiting examples. It will be appreciated that other varieties of integrated electronics structures can be formed through other combinations of the structures and steps described herein without departing from the scope of the present disclosure.

[0035] It will be appreciated that the bonding layers described herein (e.g., in connection with reference numbers 104, 204, 234, 304, 324) can comprise a single material or can comprise multiple materials and / or multiple sub-layers. Referring to FIG. 4, an example of a temporary stack that includes a bonding layer comprising multiple sub-layers is shown generally in connection with reference number 400. The stack 400 comprises a carrier body 402, a first bonding sub-layer 104 deposited on a carrying surface of the carrier body, a second bonding sub-layer deposited on the first bonding sub-layer, and a first electronics10CORE / 3530742.000901 / 232182323.13530742.000901 structure base 106 deposited on the second bonding sub-layer opposite the carrier body. The elements of the stack 400 are generally consistent with the elements of stack 100 described above in connection with FIG. 1 A and in particular the previously discussed example in which the bonding layer 104 can comprise two layers of different materials which chemically react to yield a gaseous byproduct when heated during debonding. As a non-limiting example, the carrier body 402 can comprise a rigid glass substrate or sapphire, the first bonding sub-layer 404 can comprise an electrically conductive film (e.g., comprising one or more metals like Al, Ga, Cu, and / or Ti), and the second bonding sub-layer 405 can comprise a nonmetal substrate (e.g., Si, P) which provides a foundation for crystallographic growth of the electronics structure base 406. It will be appreciated that the bonding sub-layers 404, 405 as described herein can generally be used interchangeably with the bonding layers 104, 204, 234, 304, 324 discussed above.

[0036] When introducing elements of the present disclosure or the preferred embodiments(s) thereof, the articles "a", "an", "the" and "said" are intended to mean that there are one or more of the elements. The terms "comprising", "including" and "having" are intended to be inclusive and mean that there may be additional elements other than the listed elements.

[0037] In view of the above, it will be seen that the several objects of the present disclosure are achieved and other advantageous results attained.

[0038] As various changes could be made in the above constructions and methods without departing from the scope of the present disclosure, it is intended that all matter contained in the above description and shown in the accompanying drawings shall be interpreted as illustrative and not in a limiting sense. Although several examples of reusable carrier structures and features thereof are described above in connection with certain embodiments, it will be appreciated that numerous additions, combinations, and other modifications to the features described herein can be carried out without departing from the scope of the present disclosure11CORE / 3530742.000901 / 232182323.1

Claims

3530742.000901WHAT IS CLAIMED IS:

1. A method for fabricating an integrated electronics structure comprising: providing a temporary stack comprising a carrier body, a bonding layer, and an electronics structure base crystallographically grown on the bonding layer, the bonding layer creating a bond between the carrier body and the electronics structure base; building an electronics structure on the electronics structure base to define an integrated electronics structure that comprises the electronics structure and the electronics structure base; and providing a pulse of incoherent debonding light to debond the integrated electronics structure from the carrier body; wherein the bonding layer comprises a light-absorbing material configured to weaken the bond between the carrier body and the electronics structure base upon exposure to the pulse of incoherent debonding light.

2. The method of claim 1, wherein the step of providing the temporary stack comprises: providing the carrier body with the bonding layer deposited on a carrying surface of the carrier body; and depositing an electronics structure material on the bonding layer to form the electronics structure base.

3. The method of claim 2, wherein the step of building the electronics structure on the electronics structure base comprises depositing an electronics structure material on the electronics structure base.

4. The method of claim 2, wherein the step of building the electronics structure on the electronics structure base comprises bonding the electronics structure to the electronics structure base.

5. The method of claim 4, wherein bonding the electronics structure to the electronics structure base comprises hybrid bonding.

6. The method of claim 4:12CORE / 3530742.000901 / 232182323.13530742.000901 wherein the step of building the electronics structure on the electronics structure base comprises providing a second temporary stack comprising a second carrier body, a second bonding layer, a second electronics structure base crystallographically grown on the second bonding layer, and the electronics structure; and wherein the electronics structure is carried by the second electronics structure base.

7. The method of claim 6: wherein the second bonding layer creates a bond between the second carrier body and the second electronics structure base; and wherein the bonding layer of the second stack comprises a light-absorbing material configured to weaken the bond between the carrier body and the electronics structure base upon exposure to the pulse of incoherent debonding light; the method further comprising providing a pulse of incoherent debonding light to debond the integrated electronics structure from the second carrier body.

7. The method of claim 1, wherein the pulse of incoherent debonding light is provided by a flashlamp.

8. The method of claim 1, wherein the carrier body comprises one of a glass substrate or a sapphire substrate.

9. The method of claim 1, wherein the electronics structure base comprises a ceramic compound.

10. The method of claim 1, wherein the electronics structure base comprises at least one of TiN, Si2Ns, GaN, GaAs, AgNCh, AgO, or a phosphor.

11. The method of claim 1, wherein the electronics structure base comprises at least one of a silicon oxide, a hafnium oxide, or a zirconium oxide.

12. The method of claim 1, wherein the electronics structure base comprises a phase-changing compound configured to undergo a phase transition upon exposure to the pulse of incoherent debonding light.13CORE / 3530742.000901 / 232182323.13530742.00090113. The method of claim 1, wherein the electronics structure base comprises at least one of a Sn-Zn alloy, a Cu-Ti alloy, or a salt hydrate.

14. The method of claim 1, wherein the electronics structure base comprises a first sub-layer and a second sub-layer that chemically react upon exposure to the pulse of incoherent debonding light.

15. The method of claim 14, wherein the first sub-layer comprises a metal.

16. The method of claim 14, wherein the first sub-layer comprises at least one ofAl, Ga, Cu, or Ti.

17. The method of claim 14, wherein the second sub-layer comprises a nonmetal.

18. The method of claim 14, wherein the second sub-layer comprises one of Si orP.

19. The method of claim 1, wherein weakening the bond between the carrier structure and the electronics structure base comprises a crystallographic phase change of material in the bonding layer.

20. The method of claim 1, wherein weakening the bond between the carrier structure and the electronics structure base comprises chemical dissociation of the bonding layer.

21. The method of claim 1, wherein weakening the bond between the carrier structure and the electronics structure base comprises a chemical reaction of two or more materials in the bonding layer upon exposure to the pulse of incoherent debonding light.

22. A method for fabricating an integrated electronics structure comprising: applying an inorganic adhesive material on a surface of a rigid carrier body; growing an electronics structure base on the adhesive material; and14CORE / 3530742.000901 / 232182323.13530742.000901 building an electronics structure on the electronics structure base to define an integrated electronics structure that comprises the electronics structure and the electronics structure base; wherein the adhesive material allows the electronics structure base to extend from the adhesive material in a controlled crystal orientation; wherein the carrier body is substantially transparent to light in a broadband debonding light wavelength range; and wherein the adhesive material is substantially absorptive of light in the broadband debonding light wavelength range.

23. The method of claim 22, further comprising: using a pulsed light source to emit a pulse of light in the broadband debonding light wavelength range to weaken the adhesive material; and separating the integrated electronics structure from the carrier body.

24. The method of claim 23, wherein the pulse of light in the broadband debonding light wavelength range is transmitted through the carrier body.

25. The method of claim 22, wherein the adhesive material is substantially transmissive of light in a processing light wavelength range which is different from the broadband debonding light wavelength range.

26. The method of claim 25, wherein the processing light wavelength range comprises at least one of NIR or IR light.

27. The method of claim 26, wherein the broadband debonding light wavelength range comprises visible light.15CORE / 3530742.000901 / 232182323.1

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