Data transmission method and apparatus, and electronic device, readable storage medium and program

Abstract

Provided in the embodiments of the present application are a data transmission method and apparatus, and an electronic device, a computer-readable storage medium and a computer program. The method comprises: a data receiving program receiving first data from a hardware end, and writing the first data into a shared memory when a data processing program is idle; the data processing program acquiring the first data from the shared memory, executing a data processing task on the basis of the first data, so as to obtain first result data, and writing the first result data into the shared memory when a data sending program is idle; and the data sending program acquiring the first result data from the shared memory, and sending the first result data to the hardware end. The embodiments of the present invention realize data interaction between a software end and a hardware end, such that the data transmission efficiency is improved, thereby facilitating a reduction in the transmission delay between the software end and the hardware end, and improving the overall performance of a software and hardware system.

Description

Data transmission methods, apparatus, electronic devices, readable storage media and programs

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411441833.1, filed on October 15, 2024, entitled "A data transmission method, apparatus, electronic device and readable storage medium", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of computer technology, and in particular to a data transmission method, apparatus, electronic device, computer-readable storage medium, and computer program. Background Technology

[0004] Hardware-software collaboration is an important means of improving system performance. Using FPGA and software to work together is a common practice in the industry. When FPGA and software work together, because the software speed is much slower than the hardware, when the hardware needs to wait for the software to execute data, the software is blocked by communication with the FPGA and cannot perform data transmission and data processing at the same time. The system performance bottleneck is often constrained by the software. Summary of the Invention

[0005] This application provides a data transmission method, apparatus, electronic device, computer-readable storage medium, and computer program to solve problems in related technologies.

[0006] In a first aspect, embodiments of this application disclose a data transmission method applied to a software terminal, wherein the software terminal is used to collaboratively execute data processing tasks with a hardware terminal; the software terminal includes a data receiving program, a data sending program, and a data processing program; the method includes:

[0007] The data receiving program receives first data from the hardware terminal and writes the first data into shared memory when the data processing program is idle.

[0008] The data processing program retrieves the first data from the shared memory, performs a data processing task based on the first data, obtains the first result data, and writes the first result data into the shared memory when the data sending program is idle.

[0009] The data sending program retrieves the first result data from the shared memory and sends the first result data to the hardware.

[0010] Secondly, embodiments of this application disclose a data transmission device applied to a software terminal, wherein the software terminal is used to collaboratively execute data processing tasks with a hardware terminal; the device includes:

[0011] A data receiving module is used to receive first data from the hardware terminal and write the first data into shared memory when the data processing program is idle.

[0012] The data processing module is used to obtain the first data from the shared memory, perform data processing tasks based on the first data to obtain the first result data, and write the first result data into the shared memory when the data sending program is idle.

[0013] The data transmission module is used to obtain the first result data from the shared memory and send the first result data to the hardware terminal.

[0014] Thirdly, embodiments of this application also provide an electronic device, including a processor;

[0015] Memory used to store the processor's executable instructions;

[0016] The processor is configured to execute the instructions to implement the method.

[0017] Fourthly, embodiments of this application also provide a computer-readable storage medium that, when the instructions in the computer-readable storage medium are executed by a processor of an electronic device, enables the electronic device to perform the method of the first aspect.

[0018] Fifthly, embodiments of this application provide a computer program including computer-readable code, which, when run on a computing processing device, causes the computing processing device to perform the method described thereon.

[0019] This application provides a data transmission method that divides the software into three independent programs: a data receiving program, a data processing program, and a data sending program. The data receiving program receives first data from the hardware and writes the first data to shared memory when the data processing program is idle. The data processing program retrieves the first data from the shared memory and performs data processing tasks based on the first data to obtain first result data. When the data sending program is idle, it writes the first result data to the shared memory. The data sending program retrieves the first result data from the shared memory and sends the first result data to the hardware. This application implements data interaction between the software and hardware through the data receiving and sending programs, and data transmission between the data receiving, data processing, and data sending programs is achieved through shared memory. Furthermore, the data processing program can work simultaneously with the data receiving and sending programs, performing data processing and data transmission respectively. While ensuring exclusive access to shared memory by the programs, this improves data transmission efficiency, thereby reducing transmission latency between the software and hardware and improving the overall performance of the software and hardware system.

[0020] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 is a flowchart of the steps of an embodiment of a data transmission method according to this application;

[0023] Figure 2 is a structural block diagram of a data transmission device according to this application;

[0024] Figure 3 is a structural block diagram of an electronic device for accessing memory provided in this application example. Specific Implementation

[0025] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and are not limited in number; for example, a first object can be one or more. Furthermore, the term "and / or" in the specification and claims is used to describe the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. In the embodiments of this application, the term "multiple" refers to two or more, and other quantifiers are similar.

[0027] Referring to Figure 1, a flowchart of an embodiment of a data transmission method according to this application is shown. The method may specifically include the following steps:

[0028] Step 101: The data receiving program receives the first data from the hardware terminal and writes the first data into shared memory when the data processing program is idle.

[0029] Step 102: The data processing program retrieves the first data from the shared memory, performs a data processing task based on the first data, obtains the first result data, and writes the first result data into the shared memory when the data sending program is idle.

[0030] Step 103: The data sending program retrieves the first result data from the shared memory and sends the first result data to the hardware.

[0031] The data transmission method provided in this application embodiment can be applied to a software side, which is used to cooperate with the hardware side to perform data processing tasks; the software side includes a data receiving program, a data sending program, and a data processing program.

[0032] In one possible application scenario of this application, collaborative verification of the Design Under Test (DUT) is performed through both software and hardware. Specifically, the DUT and its corresponding reference model can be deployed on the hardware side. For example, the DUT can be deployed in the programmable logic (PL) area of ​​a Field Programmable Gate Array (FPGA), and the reference model can be deployed on the FPGA's processing system. The DUT and the reference model are run synchronously on the FPGA to perform functional verification. When the running state of the DUT is inconsistent with that of the reference model, it is determined that the DUT is malfunctioning. At this point, a snapshot of the overall state information of the FPGA can be saved using hardware snapshot technology. Then, the saved snapshot information is transmitted to the software side, where simulation software is run to perform fine-grained debugging and repair of the DUT. Collaborative verification of the DUT based on both hardware and software can improve verification efficiency while enabling fine-grained debugging and repair of the DUT.

[0033] Since the operating speed of the hardware is far greater than that of the software, another application scenario of this application allows for collaborative computation between the software and hardware. For example, in the field of image processing, neural network models are typically used for image processing, such as image recognition, image classification, image enhancement (e.g., removing occlusions, watermarks, background blurring, image fusion, etc.), and AI drawing. However, the computational speed of the software is also limited. Therefore, the neural network model can be hardware-reconstructed on an FPGA, enabling on-chip image processing. For instance, the software interacts with the user to obtain user requirements and the image to be processed, parses the image, and transmits the parsed image data to the FPGA. The FPGA then processes the image data based on the user's requirements and feeds the processing results back to the software. The software then parses the received processing results, generates the processed target image, and displays it to the user.

[0034] It's important to note that an FPGA is a reconfigurable integrated circuit chip with a wide range of applications. Unlike traditional fixed-function integrated circuits (ASICs), FPGAs can be flexibly reprogrammed and reconfigured to adapt to different applications and functions according to user needs. An FPGA consists of a large number of programmable logic blocks and programmable interconnect resources. Programmable logic blocks typically consist of look-up tables (LUTs), registers, and other logic elements, capable of performing various logical functions. Programmable interconnect resources are used to connect the logic blocks to form the desired circuit structure. Using FPGAs, design engineers can describe the required circuit functions using hardware description languages ​​and translate them into a bitstream compatible with the FPGA chip using programming tools. The bitstream contains information for programming and configuring the FPGA's internal logic and interconnect resources. One of the main advantages of FPGAs is their programmability and flexibility. It allows design engineers to implement custom functions and algorithms at the hardware level without the need for traditional custom integrated circuit design and manufacturing processes. This makes FPGAs play a crucial role in prototyping and rapid design iteration.

[0035] The hardware in this application embodiment can be an FPGA, or other hardware devices or modules, such as GPU, DSA, ASIC, etc.

[0036] Software and hardware need to communicate through a defined interaction structure, achieving decoupling between them through interfaces. For example, for a CPU, the interface between software and hardware is the Instruction Set Architecture (ISA). The processor below the ISA is the hardware, while the various programs, datasets, files, etc., above the instruction set are the software.

[0037] In this application embodiment, the software refers to a program on top of an instruction set. The software can be installed on a personal computer (PC) or on other electronic devices with an operating system that can run software.

[0038] In this embodiment, the software can be divided into three independent programs according to their functions: a data receiving program, a data processing program, and a data sending program. The data receiving program receives data from the hardware; the data processing program parses and processes the received data; and the data sending program sends the processing results from the data processing program to the hardware.

[0039] The data receiving program, data processing program, and data sending program transmit data through shared memory. Specifically, after receiving the first data from the hardware, the data receiving program writes the first data into shared memory when the data processing program is idle. The data processing program retrieves the first data from shared memory, performs data processing tasks based on the first data, obtains the first result data, and then writes the first result data into shared memory when the data sending program is idle. The data sending program retrieves the first result data from shared memory and then sends the first result data to the hardware.

[0040] It is understood that, in this embodiment, only one of the data receiving program and the data processing program can perform write operations on the shared memory at any given time. In other words, the data receiving program and the data processing program cannot perform write operations on the shared memory simultaneously to avoid data errors caused by both programs writing data to the shared memory at the same time (for example, if the data receiving program and the data processing program simultaneously modify the same memory space in the shared memory, it will lead to data errors). The data receiving program receives the first data from the hardware and packages it. When the data processing program is idle, it writes the accumulated first data to the shared memory and transmits it to the data processing program. It should be noted that while the data processing program is reading the first data from the shared memory and performing data processing tasks, the data receiving program can continue to receive data from the hardware, but it will not write the data to the shared memory temporarily. Instead, it will accumulate the data locally and write the accumulated data to the shared memory when the data processing program is idle.

[0041] Only one program, either the data processing program or the data sending program, can perform read or write operations on shared memory at any given time. In other words, when the data processing program writes data to shared memory, the data sending program cannot read data from shared memory. This is to avoid errors caused by differences in data order between the two programs (e.g., one program writes data sequentially while the other reads it in reverse order) or differences in instantaneous data rates (e.g., the data processing program writes data at a frequency of 200MHz while the data sending program reads data at a frequency of 50MHz), which could lead to errors in the data read by the data sending program. The data processing program executes its data processing task to obtain the first result data and waits for the data sending program to become idle before writing the first result data to shared memory. It should be noted that while the data sending program is reading the first result data from shared memory, the data processing program can continue executing the next data processing task, but it will not write the result data to shared memory immediately. Instead, it will accumulate the data locally and write the accumulated result data to shared memory when the data sending program becomes idle.

[0042] For example, suppose data is first transmitted from the hardware to the software; that is, the receiving program first receives the first data from the hardware. At this time, both the data processing program and the sending program are in their initial state, i.e., idle state. The receiving program can directly write the first data into shared memory. The data processing program reads the first data from shared memory and performs data processing tasks based on the read first data until it obtains the first result data. At this time, the sending program is in an idle state, and the data processing program can write the first result data into shared memory. After writing, the data processing program is in an idle state. The sending program reads the first result data from shared memory and sends the first result data to the hardware. While the data processing program is in an idle state, the receiving program continues to write new first data received from the hardware into shared memory.

[0043] Furthermore, the hardware in this embodiment can be an FPGA, and PCIE-XDMA can be used as the communication protocol between the software and hardware. PCIE (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard, primarily used to expand the data throughput of computer system buses and improve device communication. XDMA is an official PCIE "advanced" IP included in Xilinx FPGAs. Its operation is mainly at the "application layer." Simply put, after the FPGA is instantiated and configured, the FPGA basically does not need to perform many operations at the logic level. The software can interact with the FPGA via DMA by calling library functions. All DMA operations are implemented by the host machine corresponding to the software through PCIE configuration of the XDMA registers.

[0044] Optionally, the software is mounted on an electronic device, which further includes a communication driver; the data receiving program receives first data from the hardware, including:

[0045] Step S11: The data receiving program receives first data from the hardware terminal through the communication driver;

[0046] The data sending program retrieves the first result data from the shared memory and sends the first result data to the hardware, including:

[0047] Step S12: The data sending program obtains the first result data from the shared memory and sends the first result data to the hardware terminal through the communication driver.

[0048] The communication driver may include a software driver library (e.g., an XDMA driver function library) and a hardware driver configuration, such as PCIE-XDMA.

[0049] For example, the hardware (i.e., the FPGA board) is connected to the PCIe slot of an electronic device (i.e., a PC) with software. The hardware sends data to the software using the AXI-STREAM protocol interface. The receiving program can interact with the hardware through the XDMA driver function library to receive the first data from the hardware. The first result data from the software is returned to the hardware by the sending program via PCIe-XDMA. After being parsed by the hardware's parsing module, the data is written to the FIFO or passed to the hardware for processing. FIFO stands for "First In, First Out," a common queue data structure management method. In FIFO, the first element to enter the queue is taken out first, and the last element to enter the queue is taken out last, just like the person at the front of the queue leaves first. This data structure can be used to simulate various real-world scenarios, such as queuing and request processing. FIFO queues are commonly used for managing shared resources, processing tasks, and cache management.

[0050] Optionally, the first data includes simulator stimulus data; the data processing program retrieves the first data from the shared memory, performs a data processing task based on the first data to obtain first result data, and writes the first result data into the shared memory when the data sending program is idle, including:

[0051] Step S21: The data processing program obtains the simulator stimulus data from the shared memory;

[0052] Step S22: The data processing program parses the simulator excitation data to obtain simulation input information;

[0053] Step S23: The data processing program drives the simulation software to perform simulation processing on the simulation input information to obtain simulation results;

[0054] Step S24: When the data processing program is idle, the simulation results are written to the shared memory.

[0055] In one optional embodiment of this application, verification can be performed using a simulator through a combination of hardware and software. The simulator is used to simulate processor behavior. For example, during the processor design process, a simulator can be used to simulate processor behavior, and by verifying the simulator, the processor design logic can be verified and tested.

[0056] Specifically, on the hardware side, stimulus data is input to the simulator to trigger its operation and obtain the simulator's running results. The hardware side transmits the simulator stimulus data to the software side, where a data receiving program receives the data and writes it to shared memory when the data processing program is idle. The data processing program retrieves the simulator stimulus data from shared memory and parses it to obtain simulation input information. The data processing program inputs this simulation input information into the simulation software for simulation processing to obtain simulation results. When the data sending program is idle, it writes the simulation results to shared memory. The data sending program then sends the simulation results to the hardware side, which compares the simulation results with the simulator's running results to determine if the simulator has encountered any errors.

[0057] In another possible application scenario of this application, the hardware can also send the simulator's running results to the software, which then compares the simulator's running results with the simulation results of the simulation software and sends the comparison results to the hardware. The hardware can then directly determine whether the simulator has run into an error based on the comparison results.

[0058] In one optional embodiment of this application, the shared memory includes at least two memory partitions; the data receiving program receives first data from the hardware terminal, and writes the first data into the shared memory when the data processing program is idle, including:

[0059] Step S31: The data receiving program receives first data from the hardware terminal, and when the data processing program is idle, writes the first data into the first memory partition; the first memory partition is any free memory partition in the shared memory.

[0060] The data processing program retrieves the first data from the shared memory, performs a data processing task based on the first data to obtain first result data, and writes the first result data into the shared memory when the data sending program is idle, including:

[0061] Step S32: The data processing program obtains the first data from the first memory partition, performs a data processing task based on the first data, obtains the first result data, and writes the first result data to the second memory partition when the data sending program is idle; the second memory partition is any free memory partition in the shared memory.

[0062] In this embodiment, the shared memory can be divided into multiple memory partitions, and the data receiving program, data processing program, and data sending program can take turns using the shared memory in a ping-pong operation.

[0063] Specifically, assuming data is first transmitted from the hardware to the software, meaning the receiving program first receives the first data from the hardware, the receiving program, data processing program, and sending program are all in their initial, idle states. After receiving the first data D1 from the hardware, the receiving program, while the data processing program is idle, writes the first data D1 to the first memory partition R1. The data processing program retrieves the first data D1 from the first memory partition R1, executes the data processing task corresponding to the first data D1, and obtains the first result data S1. At this time, the sending program is idle, and the data processing program writes the first result data S1 to the second memory partition R2. The sending program retrieves the first result data S1 from the second memory partition R2 and sends the first result data S1 to the hardware.

[0064] It is understandable that when the data processing program writes the first result data S1 to the second memory partition R2, the data processing program is in an idle state for the first memory partition R1. Therefore, the data receiving program can continue to write new first data D2 to the first memory partition R1.

[0065] Through this ping-pong operation, the data receiving program and the data processing program can simultaneously write data to the shared memory (to different memory partitions), saving program waiting time and improving data transmission efficiency.

[0066] It should be noted that once all the data in a memory partition has been read, that memory partition can be cleared so that new data can be written.

[0067] Furthermore, in this embodiment, semaphores can be used to control access to shared memory by the data receiving program, data processing program, and data sending program. A semaphore is a synchronization mechanism in an operating system used to control access to shared resources by multiple processes. In this embodiment, semaphores can be used to determine the occupancy status of shared memory and control the execution logic between multiple programs.

[0068] Optionally, the method further includes:

[0069] Step S41: When the data processing program executes the data processing task, it sets the value of the first semaphore to a first value; the first value is used to indicate that the data processing program is in a non-idle state.

[0070] Step S42: After the data processing program writes the first result data into the shared memory, it sets the value of the first semaphore to a second value; the first value is used to indicate that the data processing program is in an idle state.

[0071] Step S43: The data receiving program monitors the first semaphore in real time, and determines that the data processing program is idle when the value of the first semaphore is the second value.

[0072] Step S44: After the data sending program reads the first result data from the shared memory, it sets the value of the second semaphore to a third value; the third value is used to indicate that the data receiving program is in a non-idle state.

[0073] Step S45: After the data sending program sends the first result data to the hardware terminal, it sets the value of the second semaphore to a fourth value; the fourth value is used to indicate that the data receiving program is in an idle state.

[0074] Step S46: The data processing program monitors the second semaphore in real time, and determines that the data transmission program is idle when the value of the second semaphore is the fourth value.

[0075] In this embodiment, the data receiving program, data processing program, and data sending program can be initialized first, and the initial state of these three programs is an idle state.

[0076] In one possible application scenario of this application, the data receiving program waits for the hardware to send the first data. After the first data is received, it waits for a first semaphore indicating that the data processing program is idle to be set (valid). It can be understood that if the first semaphore is set or valid, for example, if the value of the first semaphore is a second value, such as "1", it indicates that the data processing program is in an idle state; if the first semaphore is not set or invalid, for example, if the value of the first semaphore is a first value, such as "0", it indicates that the data processing program is in a non-idle state.

[0077] If new first data is sent while the receiving program is waiting for the first semaphore to be set, the receiving program will append the new data to the data that has not yet been written to the shared memory.

[0078] After the first semaphore is valid, the data receiving program writes the first received data into the shared memory and continues to wait for data from the hardware or for the data processing program to become idle.

[0079] When the data processing program is processing data, it updates the value of the first semaphore to a first value, indicating that the data processing program is in a non-idle state. After execution is complete, the semaphore indicating that valid data processing is complete waits for the data sending program to become idle before writing the first result data into shared memory. After the first result data is written, the semaphore indicating that invalid data processing is complete updates the value of the first semaphore to a second value, indicating that the data processing program is in an idle state.

[0080] After receiving the first result data to be sent, the data transmitting program sets the value of the second semaphore to a third value, such as "1", indicating that the data receiving program is in a non-idle state. Only after the first result data is sent to the hardware does the value of the second semaphore change to a fourth value, such as "0", indicating that the data transmitting program is in an idle state.

[0081] In summary, this application provides a data transmission method that divides the software into three independent programs: a data receiving program, a data processing program, and a data sending program. The data receiving program receives first data from the hardware and writes it to shared memory when the data processing program is idle. The data processing program retrieves the first data from the shared memory, performs data processing tasks based on the first data to obtain first result data, and writes the first result data to shared memory when the data sending program is idle. The data sending program retrieves the first result data from shared memory and sends it to the hardware. In this application embodiment, only one of the data receiving program and the data processing program can perform write operations on the shared memory at any given time. However, while the data processing program is performing data processing tasks, the data receiving program can continue to receive data from the hardware, but it will not write the data to the shared memory until the data processing program becomes idle. Similarly, while the data sending program is reading the first result data from the shared memory, the data processing program can continue to execute the next data processing task, but it will not write the result data to the shared memory until the data sending program becomes idle. This application embodiment realizes data interaction between the software and hardware through a data receiving program and a data sending program. Data transmission between the data receiving program, the data processing program, and the data sending program is realized through shared memory. Furthermore, the data processing program can work simultaneously with the data receiving and sending programs, performing data processing and data transmission respectively. While ensuring exclusive access of the program to the shared memory, the data transmission efficiency is improved, thereby helping to reduce the transmission latency between the software and hardware and improve the overall performance of the software and hardware system.

[0082] It should be noted that, for the sake of simplicity, the method embodiments are all described as a series of actions. However, those skilled in the art should understand that the embodiments of this application are not limited to the described order of actions, because according to the embodiments of this application, some steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also understand that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily necessary for the embodiments of this application.

[0083] Device Examples

[0084] Referring to Figure 2, a structural block diagram of a data transmission device according to this application is shown. The device is applied to a software side, which is used to cooperate with the hardware side to perform data processing tasks. Specifically, the device may include:

[0085] The data receiving module 201 is used to receive first data from the hardware terminal and write the first data into shared memory when the data processing program is idle.

[0086] Data processing module 202 is used to obtain the first data from the shared memory, perform data processing tasks based on the first data to obtain the first result data, and write the first result data into the shared memory when the data sending program is idle.

[0087] The data transmission module 203 is used to obtain the first result data from the shared memory and send the first result data to the hardware terminal.

[0088] Optionally, the shared memory includes at least two memory partitions; the data receiving module includes:

[0089] The first data receiving submodule is used to receive first data from the hardware terminal and, when the data processing program is idle, write the first data into a first memory partition; the first memory partition is any free memory partition in the shared memory.

[0090] The data processing module includes:

[0091] The first processing submodule is used to obtain the first data from the first memory partition, and perform a data processing task based on the first data to obtain the first result data. When the data sending program is idle, the first result data is written to the second memory partition; the second memory partition is any free memory partition in the shared memory.

[0092] Optionally, the device further includes:

[0093] The first setting module is used to set the value of the first semaphore to a first value when performing a data processing task; the first value is used to indicate that the data processing program is in a non-idle state.

[0094] The second setting module is used to set the value of the first semaphore to a second value after writing the first result data into the shared memory; the first value is used to indicate that the data processing program is in an idle state.

[0095] The first determining module is used to monitor the first semaphore in real time, and determine that the data processing program is idle when the value of the first semaphore is the second value.

[0096] Optionally, the device further includes:

[0097] The third setting module is used to set the value of the second semaphore to a third value after reading the first result data from the shared memory; the third value is used to indicate that the data receiving program is in a non-idle state.

[0098] The fourth setting module is used to set the value of the second semaphore to a fourth value after sending the first result data to the hardware terminal; the fourth value is used to indicate that the data receiving program is in an idle state.

[0099] The second determining module is used to monitor the second semaphore in real time, and determine that the data transmission program is idle when the value of the second semaphore is the fourth value.

[0100] Optionally, the software is mounted on an electronic device, which also includes a communication driver;

[0101] The data receiving module includes:

[0102] The first receiving submodule is used to receive first data from the hardware terminal through the communication driver;

[0103] The data transmission module includes:

[0104] The first sending submodule is used to obtain the first result data from the shared memory and send the first result data to the hardware terminal through the communication driver.

[0105] Optionally, the first data includes simulator stimulus data; the data processing module includes:

[0106] The stimulus acquisition submodule is used to acquire the simulator stimulus data from the shared memory;

[0107] The data parsing submodule is used to parse the simulator excitation data to obtain simulation input information;

[0108] The simulation driver submodule is used to drive the simulation software to perform simulation processing on the simulation input information and obtain simulation results.

[0109] The result writing submodule is used to write the simulation results into the shared memory when the data sending program is idle.

[0110] Optionally, the device further includes:

[0111] The clear module is used to clear the memory partition after all the data in one of the at least two memory partitions has been read, so that new data can be written.

[0112] Optionally, the first value is 0 and the second value is 1.

[0113] Optionally, the third value is 1 and the fourth value is 0.

[0114] Optionally, only one of the data receiving program and the data processing program can perform write operations on the shared memory at any given time.

[0115] Optionally, only one of the data processing program and the data sending program can perform read or write operations on the shared memory at any given time.

[0116] Optionally, the hardware includes one or more of FPGA, GPU, DSA, and ASIC.

[0117] As the device embodiment is basically similar to the method embodiment, the description is relatively simple, and relevant parts can be found in the description of the method embodiment.

[0118] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0119] Regarding the processor in the above embodiments, the specific manner in which each module performs operations has been described in detail in the embodiments related to the method, and will not be elaborated here.

[0120] Referring to Figure 3, a structural block diagram of an electronic device for verification provided in an embodiment of this application is shown. As shown in Figure 3, the electronic device includes: a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface communicate with each other through the communication bus. The memory is used to store executable instructions, which cause the processor to execute the data transmission method of the aforementioned embodiment.

[0121] The processor can be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable devices, transistor logic devices, hardware components, or any combination thereof. The processor can also be a combination that implements computational functions, such as a combination of one or more microprocessors, or a combination of a DSP and a microprocessor.

[0122] The communication bus may include a path for transmitting information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The communication bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one line is used in Figure 3, but this does not indicate that there is only one bus or one type of bus.

[0123] The memory may be ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or it may be EEPROM (Electrically Erasable Programmable Read Only Memory), CD-ROM (Compact Disc Read Only Memory), magnetic tape, floppy disk, and optical data storage devices, etc.

[0124] This application also provides a non-transitory computer-readable storage medium, which, when the instructions in the storage medium are executed by the processor of an electronic device (server or terminal), enables the processor to execute the data transmission method shown in FIG1.

[0125] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the methods described in the above embodiments.

[0126] The terms "an embodiment," "embodiment," or "one or more embodiments" as used herein mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of this application. Furthermore, please note that the examples of the phrase "in one embodiment" do not necessarily all refer to the same embodiment.

[0127] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this application may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0128] In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. This application can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.

[0129] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

[0130] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0131] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

[0132] The above are merely preferred embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0133] The present application provides a detailed description of a data transmission method, apparatus, electronic device, computer-readable storage medium, and computer program. Specific examples have been used to illustrate the principles and implementation methods of the present application. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present application. At the same time, those skilled in the art will recognize that there will be changes in the specific implementation methods and application scope based on the ideas of the present application. Therefore, the content of this specification should not be construed as a limitation of the present application.

Claims

1. A data transmission method, wherein, It is applied to the software side, which is used to work with the hardware side to perform data processing tasks. The software includes a data receiving program, a data sending program, and a data processing program; the method includes: The data receiving program receives first data from the hardware terminal and writes the first data into shared memory when the data processing program is idle. The data processing program retrieves the first data from the shared memory, performs a data processing task based on the first data, obtains the first result data, and writes the first result data into the shared memory when the data sending program is idle. The data sending program retrieves the first result data from the shared memory and sends the first result data to the hardware.

2. The method of claim 1, wherein, The shared memory includes at least two memory partitions; the data receiving program receives first data from the hardware and writes the first data into the shared memory when the data processing program is idle, including: The data receiving program receives first data from the hardware terminal, and when the data processing program is idle, writes the first data into a first memory partition; the first memory partition is any free memory partition in the shared memory.

3. The method of claim 2, wherein, The data processing program retrieves the first data from the shared memory, performs a data processing task based on the first data to obtain first result data, and writes the first result data into the shared memory when the data sending program is idle, including: The data processing program obtains the first data from the first memory partition and performs a data processing task based on the first data to obtain the first result data. When the data sending program is idle, it writes the first result data into the second memory partition; the second memory partition is any free memory partition in the shared memory.

4. The method of claim 1, wherein, The method further includes: When the data processing program performs a data processing task, it sets the value of the first semaphore to a first value; the first value is used to indicate that the data processing program is in a non-idle state. After writing the first result data into the shared memory, the data processing program sets the value of the first semaphore to a second value; the first value is used to indicate that the data processing program is in an idle state. The data receiving program monitors the first semaphore in real time, and determines that the data processing program is idle when the value of the first semaphore is the second value.

5. The method of claim 1, wherein, The method further includes: After the data sending program reads the first result data from the shared memory, it sets the value of the second semaphore to the third value; the third value is used to indicate that the data receiving program is in a non-idle state. After the data sending program sends the first result data to the hardware, it sets the value of the second semaphore to a fourth value; the fourth value is used to indicate that the data receiving program is in an idle state. The data processing program monitors the second semaphore in real time, and determines that the data transmission program is idle when the value of the second semaphore is the fourth value.

6. The method of claim 1, wherein, The software is mounted on an electronic device, which also includes a communication driver.

7. The method of claim 6, wherein, The data receiving program receives first data from the hardware, including: The data receiving program receives first data from the hardware terminal through the communication driver.

8. The method of claim 7, wherein, The data sending program retrieves the first result data from the shared memory and sends the first result data to the hardware, including: The data sending program retrieves the first result data from the shared memory and sends the first result data to the hardware terminal through the communication driver.

9. The method of claim 1, wherein, The first data includes simulator stimulus data; the data processing program retrieves the first data from the shared memory, performs a data processing task based on the first data to obtain first result data, and writes the first result data into the shared memory when the data sending program is idle, including: The data processing program obtains the simulator stimulus data from the shared memory; The data processing program parses the simulator excitation data to obtain simulation input information; The data processing program drives the simulation software to perform simulation processing on the simulation input information and obtain simulation results; When the data processing program is idle, the data processing program writes the simulation results into the shared memory.

10. The method of claim 2, wherein, The method further includes: After all the data in one of the at least two memory partitions has been read, the memory partition is cleared in order to write new data.

11. The method of claim 4, wherein, The first value is 0, and the second value is 1.

12. The method of claim 5, wherein, The third value is 1, and the fourth value is 0.

13. The method of claim 1, wherein, Only one of the data receiving program and the data processing program can perform write operations on the shared memory at any given time.

14. The method of claim 1, wherein, Only one of the data processing program and the data sending program can perform read or write operations on the shared memory at any given time.

15. The method of claim 1, wherein, The hardware includes one or more of FPGA, GPU, DSA, and ASIC.

16. A data transmission apparatus, wherein, The device is applied to a software component, which is used to collaboratively execute data processing tasks with the hardware component; the device includes: A data receiving module is used to receive first data from the hardware terminal and write the first data into shared memory when the data processing program is idle. The data processing module is used to obtain the first data from the shared memory, perform data processing tasks based on the first data to obtain the first result data, and write the first result data into the shared memory when the data sending program is idle. The data transmission module is used to obtain the first result data from the shared memory and send the first result data to the hardware terminal.

17. The apparatus of claim 16, wherein, The shared memory includes at least two memory partitions; The data receiving module includes: The first data receiving submodule is used to receive first data from the hardware terminal and, when the data processing program is idle, write the first data into a first memory partition; the first memory partition is any free memory partition in the shared memory. The data processing module includes: The first processing submodule is used to obtain the first data from the first memory partition, and perform a data processing task based on the first data to obtain the first result data. When the data sending program is idle, the first result data is written to the second memory partition; the second memory partition is any free memory partition in the shared memory.

18. An electronic device, comprising: The electronic device includes a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface communicate with each other through the communication bus. The memory is used to store executable instructions, which cause the processor to execute the data transmission method as described in any one of claims 1 to 15.

19. A readable storage medium, wherein, When the instructions in the readable storage medium are executed by the processor of the electronic device, the processor is enabled to perform the data transmission method as described in any one of claims 1 to 15.

20. A computer program comprising computer-readable code that, when executed on a computing processing device, causes the computing processing device to perform the method according to any one of claims 1 to 15.

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