Managing memory refresh operations in dynamic random access memory

Abstract

In some examples, provided is a method for managing memory refresh operations in a dynamic random access memory, DRAM, bank, the method comprising measuring a leakage current of an electronic device within a DRAM bank, generating, based on the measured leakage current, an oscillating signal using an oscillator, counting a number of cycles of the oscillating signal, comparing the number of cycles of the oscillating signal to a pre-defined threshold value, and, in response to determining that the number of cycles of the oscillating signal exceeds the pre-defined threshold value, refreshing the DRAM bank.

Description

[0001] MANAGING MEMORY REFRESH OPERATIONS IN DYNAMIC RANDOM ACCESS MEMORY

[0002] TECHNICAL FIELD

[0003] The present disclosure relates, in general, to managing memory operations in a dynamic random-access memory (DRAM) bank. Aspects of the disclosure relate to determining a refresh interval per each DRAM bank.

[0004] BACKGROUND

[0005] Dynamic random-access memory (DRAM) is a widely used type of memory that retains data as electrical charge stored on the gate of a metal-oxide-semiconductor (MOS) transistor. One inherent characteristic of DRAM is that reading the data from the memory cells is destructive, requiring a write-back operation to restore the same data to its original address after each read. Additionally, the charge stored in the memory cells gradually dissipates over time due to leakage currents, resulting in potential data loss unless the cells are periodically refreshed. This refresh interval is temperature-dependent, as higher temperatures increase leakage rates.

[0006] To preserve data integrity, DRAM cells must undergo periodic refresh cycles, where each memory cell is read and rewritten. These refresh operations occur in the background when the DRAM bank is not being accessed. However, this process consumes power and introduces system overhead, reducing overall efficiency. Therefore, it is important to minimise the number of refresh operations by maximising the time between refreshes while still ensuring data integrity.

[0007] In existing systems, the refresh rate is typically calculated based on the temperature of the DRAM. This is achieved through the use of large and complex analogue temperature sensors that monitor the temperature of the entire DRAM die. However, there are several drawbacks associated with this approach. Firstly, the use of analogue temperature sensors adds considerable complexity to the system design, increasing both cost and power consumption. Secondly, this method results in a single, worstcase refresh interval being applied across the entire DRAM die, regardless of localised temperature variations. Consequently, conservative refresh rates are applied to account for the worst-case scenario, leading to excessive refresh cycles.

[0008] Moreover, significant margins must be assumed to accommodate potential temperature fluctuations, which further shortens the refresh intervals unnecessarily, particularly at lower temperatures. This not only results in inefficiencies but also increases power consumption, as more refresh operations are performed than required. Accordingly, there is a need for an improved mechanism that optimises the refresh process and reduces the associated overhead.

[0009] SUMMARY

[0010] An objective of the present disclosure is to reduce a power consumption of a DRAM bank by refreshing the DRAM bank based on measured leakage current.

[0011] The foregoing and other objectives are achieved by the features of the independent claims.

[0012] Further implementation forms are apparent from the dependent claims, the description and the Figures.

[0013] A first aspect of the present disclosure provides a method for managing memory refresh operations in a dynamic random access memory, DRAM, bank, the method comprising measuring a leakage current of an electronic device within a DRAM bank, generating, based on the measured leakage current, an oscillating signal using an oscillator, counting a number of cycles of the oscillating signal, comparing the number of cycles of the oscillating signal to a pre-defined threshold value, and, in response to determining that the number of cycles of the oscillating signal exceeds the pre-defined threshold value, refreshing the DRAM bank.

[0014] Accordingly, DRAM power consumption can be reduced by generating a maximal yet safe refresh interval for each DRAM bank. By utilizing leakage to model the specific leakage characteristics of the DRAM, the system can effectively minimise margins and power usage. The implementation of an innovative one-stage oscillator structure contributes to a smaller area requirement and reduces hardware complexity. Additionally, several leaky devices per bank can be employed, allowing for further reductions in margins and power consumption, ensuring that refresh operations are optimised while maintaining data integrity across the memory banks. This comprehensive approach leads to a more efficient and effective DRAM design.

[0015] The electronic device may comprise a transistor.

[0016] The oscillator may comprise a ring oscillator.

[0017] The DRAM bank may comprise multiple electronic devices and multiple oscillators, wherein each of the multiple electronic devices may be associated with a distinct oscillator of the multiple oscillators.

[0018] Measuring the leakage current of the electronic device may comprise measuring respective leakage currents of the multiple electronic devices, wherein generating, based on the measured leakage current, the oscillating signal using the oscillator may comprise generating, based on the respective leakage currents, respective oscillating signals of the multiple oscillators, wherein counting the number of cycles of the oscillating signal may comprise counting the number of cycles of the respective oscillating signals, wherein comparing the number of cycles of the oscillating signal to the pre-defined value may comprise selecting a number of cycles of the respective oscillating signals and comparing the selected number of cycles to the pre-defined threshold value, wherein refreshing the DRAM bank may comprise refreshing the DRAM bank in response to determining that the selected number of cycles exceeds the pre-defined threshold value.

[0019] The number of cycles of the respective oscillating signals may comprise selecting the number of cycles comprising the largest number of cycles.

[0020] A second aspect of the present disclosure provides a dynamic random-access memory, DRAM, assembly comprising a DRAM die comprising multiple DRAM banks, wherein each DRAM bank of the multiple DRAM banks comprises an electronic device, wherein the electronic device is arranged to emit a leakage current, a logic die, connected to the DRAM die, wherein the logic die comprises a logic circuit arranged to measure the leakage current and an oscillator arranged to generate an oscillating signal based on the measured leakage current, wherein the logic circuit is further arranged to count a number of cycles of the oscillating signal generated by the oscillator and to compare the number of cycles of the oscillating signal to a pre-defined threshold value, and, in response to determining that the number of cycles of the oscillating signal exceeds the pre-defined threshold value, refresh the DRAM bank.

[0021] The electronic device may comprise a transistor.

[0022] The oscillator may comprise a ring oscillator.

[0023] The logic die may be connected to the DRAM die using a through-silicon via (TSV).

[0024] The logic circuit may comprise an inverter and multiple logic gates.

[0025] Each DRAM bank may comprise multiple electronic devices arranged to emit respective leakage currents, wherein the logic die may comprise multiple oscillators arranged to generate respective oscillating signals based on the respective leakage currents, wherein the logic circuit may be arranged to count the number of cycles of the respective oscillating signals, wherein the logic circuit may be further arranged to select a number of cycles of the respective oscillating signals and compare the selected number of cycles to the pre-defined threshold value and refresh the DRAM bank in response to determining that the selected number of cycles exceeds the pre-defined threshold value.

[0026] The logic circuit may be arranged to select the number of cycles of the respective oscillating signals comprising the largest number of cycles.

[0027] The electronic device may be arranged in a peripheral area of the DRAM bank, wherein the peripheral area may comprise an area surrounding a memory array of the DRAM bank.

[0028] A third aspect of the present invention provides a computer program stored on a non-transitory medium and including code instructions, which, when executed on more or more processors, cause the one or more processors to execute the method described herein.

[0029] These and other aspects of the invention will be apparent from the embodiments) described below.

[0030] BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order that the present invention may be more readily understood, embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings, in which:

[0032] Figure 1 is a flow chart of a method for managing memory refresh operations in a dynamic random-access memory (DRAM) bank according to an example.

[0033] Figure 2 is a schematic representation of a DRAM assembly according to an example;

[0034] Figure 3 is a schematic representation of a DRAM die according to an example; and

[0035] Figure 4 is a schematic representation of a DRAM bank according to an example;

[0036] DETAILED DESCRIPTION

[0037] Example embodiments are described below in sufficient detail to enable those of ordinary skill in the art to embody and implement the systems and processes herein described. It is important to understand that embodiments can be provided in many alternate forms and should not be construed as limited to the examples set forth herein.

[0038] Accordingly, while embodiments can be modified in various ways and take on various alternative forms, specific embodiments thereof are shown in the drawings and described in detail below as examples. There is no intent to limit to the particular forms disclosed. On the contrary, all modifications, equivalents, and alternatives falling within the scope of the appended claims should be included. Elements of the example embodiments are consistently denoted by the same reference numerals throughout the drawings and detailed description where appropriate.

[0039] The terminology used herein to describe embodiments is not intended to limit the scope. The articles “a,” “an,” and “the” are singular in that they have a single referent, however the use of the singular form in the present document should not preclude the presence of more than one referent. In other words, elements referred to in the singular can number one or more, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and / or “including,” when used herein, specify the presence of stated features, items, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, items, steps, operations, elements, components, and / or groups thereof. Unless otherwise defined, all terms (including technical and scientific terms) used herein are to be interpreted as is customary in the art. It will be further understood that terms in common usage should also be interpreted as is customary in the relevant art and not in an idealized or overly formal sense unless expressly so defined herein.

[0040] Currently, the refresh rate in DRAM is determined based on temperature, which plays a critical role in the rate at which data stored in the memory cells deteriorates due to leakage currents. To manage this, a temperature measurement is taken from a sensor located on the DRAM die itself, and the refresh rate is calculated accordingly. However, this method introduces several challenges due to the inherent temperature variations across different regions of the DRAM die.

[0041] One significant issue with this approach is that temperature is not uniform across the die. Individual memory banks within the DRAM may operate at different temperatures due to factors such as varying workload distribution, localised heating, and thermal dissipation characteristics. However, in prior art, the refresh rate is calculated based on a single temperature measurement taken from a specific point on the die, which may not accurately reflect the temperatures of all regions. As a result, additional safety margins must be introduced to ensure that the refresh rate is sufficient to cover potential temperature differences between the sensor location and hotter areas of the die, particularly those where data leakage occurs at a faster rate.

[0042] Furthermore, within-die variations in the characteristics of DRAM cells exacerbate the problem. Some regions of the die may have cells that exhibit faster leakage than others due to manufacturing variability, even at the same temperature. These "leakier" regions require more frequent refreshing to maintain data integrity. Since the temperature measurement is taken from a single point, the refresh rate is set conservatively to accommodate the worst-case scenario, where both temperature and leakage rates are highest. This conservative approach results in refresh cycles being applied more frequently than necessary in cooler or less leaky areas of the die, leading to inefficiencies.

[0043] Prior art typically employs large and complex analogue temperature sensors to perform the temperature measurement. These sensors introduce additional complexity, size, and power consumption into the overall system design. Despite their sophistication, these sensors still yield a single refresh interval for the entire DRAM die, which must account for worst-case temperature and leakage conditions across all regions of the die. This results in significant margins being added to the refresh rate calculation, as the system must assume that any portion of the die could be experiencing the worst-case conditions. Consequently, the use of a single temperature measurement, combined with the necessity to accommodate within-die variations, leads to overly conservative refresh intervals. These conservative intervals result in unnecessary refresh cycles, increasing power consumption and reducing the overall efficiency of the DRAM.

[0044] According to an example, there is provided a mechanism to reduce DRAM power consumption by generating an optimal yet safe refresh interval for each DRAM bank. More specifically, aspects relate to modelling leakage at multiple locations within each DRAM bank using N-type transistors. These transistors are strategically placed in boundary regions, ensuring no additional area cost. In an example, the leakage model allows for more precise refresh timing by directly correlating the refresh cycle with the actual leakage characteristics of the bank. This reduces the conservative margins typically required in prior art, thereby lowering power consumption. Additionally, the use of an innovative one-stage oscillator structure minimises both area and hardware complexity. By employing multiple leaky devices per bank, this mechanism further reduces power overhead and unnecessary refresh cycles while ensuring the integrity of the stored data.

[0045] Examples in the present disclosure can be provided as methods, systems or machine-readable instructions, such as any combination of software, hardware, firmware or the like. Such machine-readable instructions may be included on a computer readable storage medium (including but not limited to disc storage, CD-ROM, optical storage, etc.) having computer readable program codes therein or thereon. The present disclosure is described with reference to flow charts and / or block diagrams of the method, devices and systems according to examples of the present disclosure. Although the flow diagrams described above show a specific order of execution, the order of execution may differ from that which is depicted. Blocks described in relation to one flow chart may be combined with those of another flow chart. In some examples, some blocks of the flow diagrams may not be necessary and / or additional blocks may be added. It shall be understood that each flow and / or block in the flow charts and / or block diagrams, as well as combinations of the flows and / or diagrams in the flow charts and / or block diagrams can be realized by machine readable instructions.

[0046] The machine-readable instructions may, for example, be executed by a machine such as a general-purpose computer, user equipment such as a smart device, e.g., a smart phone, a special purpose computer, an embedded processor or processors of other programmable data processing devices to realize the functions described in the description and diagrams. In particular, a processor or processing apparatus may execute the machine-readable instructions. Thus, modules of apparatus (for example, a module implementing a comparator unit, or a firewall structure and so on) may be implemented by a processor executing machine readable instructions stored in a memory, or a processor operating in accordance with instructions embedded in logic circuitry. The term 'processor' is to be interpreted broadly to include a CPU, processing unit, ASIC, logic unit, or programmable gate set etc. The methods and modules may all be performed by a single processor or divided amongst several processors.

[0047] Such machine-readable instructions may also be stored in a computer readable storage that can guide the computer or other programmable data processing devices to operate in a specific mode. For example, the instructions may be provided on a non- transitory computer readable storage medium encoded with instructions, executable by a processor.

[0048] Figure 1 is a flow chart of a method for managing memory refresh operations in a dynamic random-access memory (DRAM) bank according to an example. The method comprises, in block 101, measuring a leakage current of an electronic device within a DRAM bank. The electronic device may comprise an electronic device configured to emit a leakage current, for example, a transistor. In a specific example, the electronic device comprises an N-type transistor. The individual leakage current of multiple electronic devices within the DRAM bank may be measured.

[0049] In block 102, the method comprises generating, based on the measured leakage current, an oscillating signal using an oscillator. The oscillator may comprise a ring oscillator. The ring oscillator may comprise a series of inverters connected in a loop, where the output of the last inverter is fed back into the first. The ring oscillator may generate an oscillating signal based on the propagation delay through the inverters. It may operate without requiring an external clock signal, as the feedback loop causes the signal to oscillate. Multiple ring oscillators may be present; for example, each of the electronic devices may be connected to an individual oscillator.

[0050] The method comprises, in block 103, counting a number of cycles of the oscillating signal. As the leakage current of the electronic device(s) is used to run the oscillators), each cycle of the oscillating signal may signify a certain amount of leakage current. By counting the number of cycles of the oscillating signal, the method may accumulate the leakage current over time. Each cycle of the oscillating signal may represent a discrete quantity of leakage current, as the oscillation is driven by the leakage current of the electronic device(s). As the cycles are counted, the total number of cycles may correspond to the cumulative leakage current over a given period.

[0051] In this context, integrating the leakage current may mean summing or aggregating the leakage current contributions over time. By continuously counting the cycles, the method may effectively provide a measurement of the total or average leakage current across the measurement period, thereby capturing any variations in leakage over time. The cycle count may thus serve as an indication of the overall charge lost due to leakage, which can be useful for power management or reliability assessments. In block 104, the method comprises comparing the number of cycles of the oscillating signal to a pre-defmed threshold value. This threshold value may be configured based on the amount of leakage current that has been integrated. Since each cycle of the RO represents a specific amount of leakage current, the comparison may determine whether the leakage has accumulated to a level that requires attention. The pre-defined threshold may be set to correspond to the point where the leakage current has reached a level that could impact the performance or reliability of the DRAM bank.

[0052] In block 105, the method comprises, in response to determining that the number of cycles of the oscillating signal exceeds the pre-defined threshold value, refreshing the DRAM bank. That is, instead of refreshing the DRAM on a fixed schedule, the system refreshes the DRAM based on the actual amount of leakage that has occurred. The refresh may be triggered to ensure that the integrity of the stored data is maintained, compensating for the charge loss due to leakage.

[0053] As mentioned above, respectively leakage currents of multiple electronic devices may be measured, whereby to generate respective oscillating signals using distinct oscillators. The number of cycles of each respective oscillating signal may be counted and compared to the pre-defmed threshold value. The signal from the oscillator having the largest number of cycles may be selected, and the system may perform the DRAM bank refresh based thereon. That is, the method may use the fastest oscillating signal, which corresponds to the worst-case leakage scenario, for each individual DRAM bank. The DRAM bank with the highest leakage may be identified, as its ring oscillator will complete its cycles the quickest, indicating that it has reached the threshold first. The refresh cycle may then be triggered for that specific DRAM bank (or the entire DRAM die).

[0054] Figure 2 is a schematic representation of a DRAM assembly according to an example. The DRAM assembly 200 may comprise a DRAM die 210, as well as at least one logic die 220. In the example of Figure 2, the DRAM assembly 200 comprises multiple DRAM dies 210 and one logic die 220, but the invention is not limited thereto.

[0055] The DRAM die 210 will be described shortly in relation to Figure 3. The logic die 220 is connected to the at least one DRAM die 210. The logic die 220 may be connected to the at least one DRAM die 210 using through-silicon vias (TSVs). TSVs are vertical electrical connections that pass through the silicon substrate of the die, enabling high-density and high-speed communication between stacked dies in a 3D integrated circuit. By utilising TSVs, the connection between the logic die and DRAM die may allow for a compact and efficient system, as it minimises the physical distance between the components and provides a high-bandwidth, low-latency communication path.

[0056] The logic die 220 may serve as a control or processing layer, responsible for managing the operation of the DRAM die 210, including tasks such as monitoring leakage current, controlling refresh cycles, and handling data requests. The logic die 220 comprises a logic circuit (not shown) arranged to measure a leakage current emitted by an electronic device of the DRAM die 210. The logic die 220 also comprises an oscillator (not shown) arranged to generate an oscillating signal based on the measured leakage current. The logic circuit of the logic die 220 is arranged to count a number of cycles of the oscillating signal generated by the oscillator and to compare the number of cycles of the oscillating signal to a pre-defined threshold value, and, in response to determining that the number of cycles of the oscillating signal exceeds the pre-defmed threshold value, refresh the DRAM bank. That is, the logic circuit is arranged to perform the applicable steps of the method described above in relation to Figure 1.

[0057] Figure 3 is a schematic representation of a DRAM die according to an example. The DRAM die 300 comprises multiple DRAM banks 301. Figure 4 is a schematic representation of a DRAM bank according to an example. The DRAM bank 400 may comprise an area 410, comprising an active cell and circuits. At a boundary region 420 of the DRAM bank 400, the DRAM bank 400 comprises an electronic device 401, wherein the electronic device 401 is arranged to emit a leakage current. In the example of Figure 4, multiple electronic devices 401 are shown. In order to measure the leakage current from the electronic device 401, a circuit may be implemented within the DRAM bank 400. The circuit may include a larger, leaky device, connected to a shared leakage net that aggregates leakage current from various sources, including the electronic device 401. The circuit may also include logic gates and signal processing components that process the input signal and account for the leakage current introduced by the electronic device.

[0058] The input signal may be fed into the circuit and may pass through a series of logic elements, including nodes that are sensitive to the leakage current. These nodes may experience delays in signal propagation due to the accumulated leakage current on the shared leakage net. For example, as the leakage current from the electronic device 401 flows through the circuit, it may affect the timing of the signal at key points within the circuit, introducing delays at nodes where the signal is processed.

[0059] As the leakage current increases, the delay will become shorter, allowing the circuit to effectively measure the amount of leakage by counting the cycles of the delayed signal. The accumulated leakage current over time may correspond to the number of cycles counted, providing an integrated measure of leakage.

[0060] This circuit may also serve as part of a larger system that monitors leakage and triggers further actions. For example, based on the total number of signal cycles, the system may initiate a refresh cycle for the DRAM bank 400 once the leakage current exceeds a predefined threshold. This allows the system to account for leakage in real time and ensure the stability and reliability of the DRAM bank by refreshing it when necessary . In some implementations, the circuit may be used to trigger further actions, such as initiating a refresh cycle in the DRAM bank 400, based on the total number of cycles counted in response to the integrated leakage current.

[0061] According to an example, machine-readable instructions can be loaded onto a computer or other programmable data processing devices, so that the computer or other programmable data processing devices perform a series of operations to produce computer-implemented processing, thus the instructions executed on the computer or other programmable devices provide an operation for realizing functions specified by flow(s) in the flow charts and / or block(s) in the block diagrams.

[0062] Further, the teachings herein may be implemented in the form of a computer or software product, such as a non-transitory machine-readable storage medium, the computer software or product being stored in a storage medium and comprising a plurality of instructions, e.g., machine readable instructions, for making a computer device implement the methods recited in the examples of the present disclosure.

[0063] In some examples, some methods can be performed in a cloud-computing or network-based environment. Cloud-computing environments may provide various services and applications via the Internet. These cloud-based services (e.g., software as a service, platform as a service, infrastructure as a service, etc.) may be accessible through a web browser or other remote interface of the user equipment for example. Various functions described herein may be provided through a remote desktop environment or any other cloud-based computing environment.

[0064] While various embodiments have been described and / or illustrated herein in the context of fully functional computing systems, one or more of these exemplary embodiments may be distributed as a program product in a variety of forms, regardless of the particular type of computer-readable-storage media used to actually carry out the distribution. The embodiments disclosed herein may also be implemented using software modules that perform certain tasks. These software modules may include script, batch, or other executable files that may be stored on a computer-readable storage medium or in a computing system. In some embodiments, these software modules may configure a computing system to perform one or more of the exemplary embodiments disclosed herein. In addition, one or more of the modules described herein may transform data, physical devices, and / or representations of physical devices from one form to another. The preceding description has been provided to enable others skilled in the art to best utilize various aspects of the exemplary embodiments disclosed herein. This exemplary description is not intended to be exhaustive or to be limited to any precise form disclosed. Many modifications and variations are possible without departing from the spirit and scope of the instant disclosure. The embodiments disclosed herein should be considered in all respects illustrative and not restrictive. Reference should be made to the appended claims and their equivalents in determining the scope of the instant disclosure.

Claims

CLAIMS1. A method for managing memory refresh operations in a dynamic random access memory, DRAM, bank, the method comprising: measuring a leakage current of an electronic device within a DRAM bank (101); generating, based on the measured leakage current, an oscillating signal using an oscillator (102); counting a number of cycles of the oscillating signal (103); comparing the number of cycles of the oscillating signal to a pre-defmed threshold value (104); and in response to determining that the number of cycles of the oscillating signal exceeds the pre-defined threshold value, refreshing the DRAM bank (105).

2. The method of claim 1 , wherein the electronic device comprises a transistor.

3. The method of claim 1 or 2, wherein the oscillator comprises a ring oscillator.

4. The method of claim 1, 2 or 3, wherein the DRAM bank comprises multiple electronic devices and multiple oscillators, wherein each of the multiple electronic devices is associated with a distinct oscillator of the multiple oscillators.

5. The method of claim 4, wherein measuring the leakage current of the electronic device (101) comprises measuring respective leakage currents of the multiple electronic devices, wherein generating, based on the measured leakage current, the oscillating signal using the oscillator (102) comprises generating, based on the respective leakage currents, respective oscillating signals of the multiple oscillators, wherein counting the number of cycles of the oscillating signal (103) comprises counting the number of cycles of the respective oscillating signals; wherein comparing the number of cycles of the oscillating signal to the pre-defined value (104) comprises selecting a number of cycles of the respective oscillating signals and comparing the selected number of cycles to the pre-defined threshold value, wherein refreshing the DRAM bank (105) comprises refreshing the DRAM bank in response to determining that the selected number of cycles exceeds the pre-defined threshold value.

6. The method of claim 5, wherein selecting the number of cycles of the respective oscillating signals comprises selecting the number of cycles comprising the largest number of cycles.

7. A dynamic random-access memory, DRAM, assembly (200) comprising:9a DRAM die (210) comprising multiple DRAM banks (301), wherein each DRAM bank of the multiple DRAM banks comprises an electronic device, wherein the electronic device is arranged to emit a leakage current; a logic die (220), connected to the DRAM die (210), wherein the logic die (220) comprises a logic circuit arranged to measure the leakage current and an oscillator arranged to generate an oscillating signal based on the measured leakage current, wherein the logic circuit is further arranged to count a number of cycles of the oscillating signal generated by the oscillator and to compare the number of cycles of the oscillating signal to a pre-defined threshold value, and, in response to determining that the number of cycles of the oscillating signal exceeds the pre-defined threshold value, refresh the DRAM bank.

8. The DRAM assembly (200) of claim 7, wherein the electronic device comprises a transistor.

9. The DRAM assembly (200) of claim 7 or 8, wherein the oscillator comprises a ring oscillator.

10. The DRAM assembly (200) of claim 7, 8 or 9, wherein the logic die (220) is connected to the DRAM die (210) using a through-silicon via, TSV.

11. The DRAM assembly (200) of any one of claims 7 to 10, wherein the logic circuit comprises an inverter and multiple logic gates.

12. The DRAM assembly (200) of any one of claims 7 to 11, wherein each DRAM bank (301) comprises multiple electronic devices arranged to emit respective leakage currents, wherein the logic die (220) comprises multiple oscillators arranged to generate respective oscillating signals based on the respective leakage currents, wherein the logic circuit is arranged to count the number of cycles of the respective oscillating signals, wherein the logic circuit is further arranged to select a number of cycles of the respective oscillating signals and compare the selected number of cycles to the pre-defined threshold value and refresh the DRAM bank (301) in response to determining that the selected number of cycles exceeds the pre-defined threshold value.

13. The DRAM assembly (200) of claim 12, wherein the logic circuit is arranged to select the number of cycles of the respective oscillating signals comprising the largest number of cycles.

14. The DRAM assembly (200) of any one of claims 7 to 13, wherein the electronic device is arranged in a peripheral area (420) of the DRAM bank (301), wherein the peripheral area (420) comprises an area (410) surrounding a memory array of the DRAM bank.

15. A computer program stored on a non-transitory medium and including code instructions, which, when executed on more or more processors, cause the one or more processors to execute the method of any of claims 1 to 6.

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