Managing voltage supply between multiple memory dice within an integrated circuit

Abstract

In some examples, provided is a method for managing voltage supply between multiple memory dice within an integrated circuit, the method comprising, in response to determining that memory operations within a memory die of the multiple memory dice have been completed, generating, by a processor, at least one first signal, wherein the first signal comprises a signal indicating that memory operations within the memory die of the multiple memory dice have been completed, generating, by the processor, based on the generated at least one first signal, a second signal, wherein a timing of the second signal is adjusted using a delay path, comparing, using a phase detector, the second signal and a third signal, wherein the third signal comprises at least one signal indicating that non-memory operations within the memory die of the multiple memory dice have been completed, and adjusting the voltage supply of at least one memory die of the multiple memory dice based on a result of the comparison.

Description

[0001] MANAGING VOLTAGE SUPPLY BETWEEN MULTIPLE MEMORY DICE WITHIN AN INTEGRATED

[0002] CIRCUIT

[0003] TECHNICAL FIELD

[0004] The present disclosure relates, in general, to managing voltage supply between multiple memory dice within an integrated circuit. Aspects of the disclosure relate to maximising performance of a system-on-chip (SOC) by controlling the voltage supply.

[0005] BACKGROUND

[0006] The increasing complexity and performance demands of modem electronic devices have necessitated advancements in semiconductor technology, particularly in system-on-chip (SoC) design. A die, which is a small block of semiconducting material on which a functional circuit is fabricated, plays a critical role in these systems. SoCs often integrate multiple components, such as processors, memory, and input / output interfaces, onto a single die to enhance functionality and reduce physical size.

[0007] In current SoC implementations, the supply of the two dice - each corresponding to different functional components - has been arbitrarily set to be equal. This uniformity leads to significant design challenges, primarily due to the inability to accommodate varying silicon speeds and optimally regulate performance. Such limitations can result in a signoff process that is more intricate and resource-intensive than necessary. As a consequence, this inflexible approach necessitates increased chip area and power consumption, while simultaneously limiting overall performance.

[0008] Moreover, the design and implementation of dual supply voltage systems are often fraught with complications, making it challenging to achieve the desired balance between performance and efficiency. This situation highlights a pressing need for more innovative design methodologies that can reduce overall design effort, minimise chip area, and lower power consumption. Furthermore, there is an imperative to maximise performance through the optimal control of disparate supply voltages associated with different components on the die. Addressing these issues could pave the way for enhanced SoC designs that meet the evolving demands of the technology landscape.

[0009] SUMMARY

[0010] An objective of the present disclosure is to optimally control two different supply voltages in order to maximise performance of a system-on-chip.

[0011] The foregoing and other objectives are achieved by the features of the independent claims.

[0012] Further implementation forms are apparent from the dependent claims, the description and the Figures.

[0013] The first aspect of the present disclosure provides a method for managing voltage supply between multiple memory dice within an integrated circuit, the method comprising, in response to determining that memory operations within a memory die of the multiple memory dice have been completed, generating, by a processor, at least one first signal, wherein the first signal comprises a signal indicating that memory operations within the memory die of the multiple memory dice have been completed, generating, by the processor, based on the generated at least one first signal, a second signal, wherein a timing of the second signal is adjusted using a delay path, comparing, using a phase detector, the second signal and a third signal, wherein the third signal comprises at least one signal indicating that non-memory operations within the memory die of the multiple memory dice have been completed, and adjusting the voltage supply of at least one memory die of the multiple memory dice based on a result of the comparison. Accordingly, design effort, chip area, and power consumption can be reduced while maximising the performance of a system- on-chip through the optimal control of two different supply voltages. By effectively managing CPU power, the system can utilise a memory completion signal along with a complementary delay path in the CPU die, ensuring protection against slow memory data without jeopardising system integrity. The inclusion of a phase detector serves to signal when the memory path delay is dominant, allowing for timely adjustments. This strategic control also extends to memory power, enabling the system to operate efficiently and maintain high performance while minimising resource usage.

[0014] The second signal may be generated by performing a logic operation on the at least one first signal.

[0015] The third signal may be generated by performing a logic operation on the at least one signal indicating that non-memory operations within the memory die of the multiple memory dice have been completed.

[0016] The memory operations within the memory die may comprise reading data stored in one or more memory arrays within the memory die of the multiple memory dice.

[0017] Adjusting the voltage supply of the at least one dice of the multiple memory dice based on the result of the comparison may comprise altering the voltage supply of the at least one dice of the multiple memory dice in response to determining that a phase difference between the second signal and the third signal exceeds a pre-defined threshold.

[0018] The timing of the second signal may be adjusted using a tunable delay path, wherein the method may further comprise tuning the delay path.

[0019] The processor may comprise a tunable replica circuit (TRC) clock generator.

[0020] A second aspect of the present disclosure provides an apparatus comprising multiple memory dice, a processor arranged to, in response to determining that memory operations within a memory die of the multiple memory dice have been completed, generate at least one first signal, wherein the first signal comprises a signal indicating that memory operations within the memory die of the multiple memory dice have been completed, generate, based on the generated at least one first signal, a second signal, wherein a timing of the second signal is adjusted using a delay path, a phase detector arranged to compare the second signal and a third signal, wherein the third signal comprises at least one signal indicating that non-memory operations within the memory die of the multiple memory dice have been completed, wherein the processor is further arranged to adjust the voltage supply of at least one memory die of the multiple memory dice based on a result of the comparison.

[0021] The processor may be arranged to generate the second signal by performing a logic operation on the at least one first signal.

[0022] The processor may be arranged to generate the third signal by performing a logic operation on the at least one signal indicating that non-memory operations within the memory die of the multiple memory dice have been completed.

[0023] The memory operations within the memory die may comprise reading data stored in one or more memory arrays within the memory die of the multiple memory dice.

[0024] To adjust the voltage supply of the at least one memory die of the multiple memory dice based on the result of the comparison, the processor may be arranged to alter the voltage supply of the at least one dice of the multiple memory dice in response to determining that a phase difference between the second signal and the third signal exceeds a pre-defined threshold.

[0025] The delay path may comprise a tunable delay path. The processor may comprise a tunable replica circuit (TRC) clock generator.

[0026] A third aspect of the present disclosure provides a computer program stored on a non-transitory medium and including code instructions, which, when executed on more or more processors, cause the one or more processors to execute the method described herein.

[0027] These and other aspects of the invention will be apparent from the embodiments) described below.

[0028] BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order that the present invention may be more readily understood, embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings, in which:

[0030] Figure 1 is a flow chart of a method for managing voltage supply between multiple memory dice within an integrated circuit according to an example;

[0031] Figure 2 is a schematic representation of delay paths according to an example; and

[0032] Figure 3 is a schematic representation of an apparatus according to an example.

[0033] DETAILED DESCRIPTION

[0034] Example embodiments are described below in sufficient detail to enable those of ordinary skill in the art to embody and implement the systems and processes herein described. It is important to understand that embodiments can be provided in many alternate forms and should not be construed as limited to the examples set forth herein.

[0035] Accordingly, while embodiments can be modified in various ways and take on various alternative forms, specific embodiments thereof are shown in the drawings and described in detail below as examples. There is no intent to limit to the particular forms disclosed. On the contrary, all modifications, equivalents, and alternatives falling within the scope of the appended claims should be included. Elements of the example embodiments are consistently denoted by the same reference numerals throughout the drawings and detailed description where appropriate.

[0036] The terminology used herein to describe embodiments is not intended to limit the scope. The articles “a,” “an,” and ‘The” are singular in that they have a single referent, however the use of the singular form in the present document should not preclude the presence of more than one referent. In other words, elements referred to in the singular can number one or more, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and / or “including,” when used herein, specify the presence of stated features, items, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, items, steps, operations, elements, components, and / or groups thereof.

[0037] Unless otherwise defined, all terms (including technical and scientific terms) used herein are to be interpreted as is customary in the art. It will be further understood that terms in common usage should also be interpreted as is customary in the relevant art and not in an idealized or overly formal sense unless expressly so defined herein.

[0038] The management of voltage supply between multiple memory dice within an integrated circuit is a critical aspect of SoC design. In the current state of the art, the voltage supply for two separate dice is set to be equal by default. This arbitrary uniformity introduces substantial design challenges, primarily stemming from the inherent differences in silicon processing speeds between the two dice. These variations often lead to suboptimal performance, as the fixed voltage supply fails to accommodate the distinct operational characteristics of each die.

[0039] One significant disadvantage of this prior art approach is the complexity it adds to the signoff and design processes. The need to maintain equal voltage supply constrains the ability to fine-tune the performance of individual components, making it increasingly difficult to achieve the desired performance levels across the entire SoC. As a result, designers are forced to expend greater resources, both in terms of chip area and power consumption. The higher power requirements associated with this rigid voltage supply system lead to reduced overall performance efficiency, further exacerbating the issues faced during the design cycle.

[0040] Moreover, the inability to dynamically adjust the voltage supply according to the specific needs of each die complicates the implementation of power management strategies. This inflexibility not only increases the design effort but also limits the potential for optimising power efficiency within the integrated circuit.

[0041] The present disclosure introduces a novel approach to optimising the performance of a system-on-chip while simultaneously reducing design effort, chip area, and power consumption. This is achieved through the independent control of two different supply voltages allocated to distinct components within the SoC. By allowing each component to operate at its optimal voltage, the performance of the entire system can be significantly enhanced.

[0042] According to an example embodiment, the mechanism facilitates effective power management for the CPU, enabling it to dynamically adjust its power consumption based on real-time workload demands. This adaptive control mechanism allows the CPU to operate at lower power levels during periods of reduced activity, thereby conserving energy without compromising performance during peak demands.

[0043] Furthermore, this approach incorporates a safety mechanism, which protects against instances where memory data retrieval may be slower than required. The mechanism ensures that data integrity is maintained, preventing potential performance bottlenecks that could arise from delayed memory access. By prioritising the timely delivery of critical data, the mechanism enables a smooth and efficient operation of the SoC, safeguarding against disruptions in processing.

[0044] In addition to CPU power management, this methodology also extends to effective control over memory power consumption. By independently regulating the supply voltage to memory components, it is possible to optimise their power usage in line with operational requirements. This targeted voltage control not only reduces overall power consumption but also enhances the performance capabilities of the memory subsystems, contributing to the overall efficiency of the SoC.

[0045] Overall, the proposed method for managing supply voltages in an SoC environment provides significant advantages in performance optimisation, resource efficiency, and power management, ultimately leading to improved system functionality while minimising the associated design complexities.

[0046] Examples in the present disclosure can be provided as methods, systems or machine-readable instructions, such as any combination of software, hardware, firmware or the like. Such machine-readable instructions may be included on a computer readable storage medium (including but not limited to disc storage, CD-ROM, optical storage, etc.) having computer readable program codes therein or thereon.

[0047] The present disclosure is described with reference to flow charts and / or block diagrams of the method, devices and systems according to examples of the present disclosure. Although the flow diagrams described above show a specific order of execution, the order of execution may differ from that which is depicted. Blocks described in relation to one flow chart may be combined with those of another flow chart. In some examples, some blocks of the flow diagrams may not be necessary and / or additional blocks may be added. It shall be understood that each flow and / or block in the flow charts and / or block diagrams, as well as combinations of the flows and / or diagrams in the flow charts and / or block diagrams can be realized by machine readable instructions.

[0048] The machine-readable instructions may, for example, be executed by a machine such as a general-purpose computer, user equipment such as a smart device, e.g., a smart phone, a special purpose computer, an embedded processor or processors of other programmable data processing devices to realize the functions described in the description and diagrams. In particular, a processor or processing apparatus may execute the machine-readable instructions. Thus, modules of apparatus (for example, a module implementing a comparator unit, or a firewall structure and so on) may be implemented by a processor executing machine readable instructions stored in a memory, or a processor operating in accordance with instructions embedded in logic circuitry. The term 'processor' is to be interpreted broadly to include a CPU, processing unit, ASIC, logic unit, or programmable gate set etc. The methods and modules may all be performed by a single processor or divided amongst several processors.

[0049] Such machine-readable instructions may also be stored in a computer readable storage that can guide the computer or other programmable data processing devices to operate in a specific mode. For example, the instructions may be provided on a non- transitory computer readable storage medium encoded with instructions, executable by a processor.

[0050] Figure 1 is a flow chart of a method for managing voltage supply between multiple memory dice within an integrated circuit. The method comprises, in block 101, in response to determining that memory operations within a memory die of the multiple memory dice have been completed, generating, by a processor, at least one first signal. The method may also comprise, prior to block 101, determining whether the memory operations within the memory die of the multiple memory dice have been completed.

[0051] The first signal comprises a signal indicating that the memory operations within the memory die of the multiple memory dice have been completed. These memory operations may include tasks such as reading data from one or more memory arrays, refreshing stored data, or updating memory cells. The first signal may specifically comprise a memory read completion signal, which is arranged to indicate whether the reading of data from one or more memory arrays within the memory die of the multiple memory dice has been completed.

[0052] In this context, the first signal (i.e., memory read completion signal) may not function as a clock signal, but instead may serve to indicate the validity of the output data. When the signal indicates that the reading is completed, it may signify that the data retrieved from the memory arrays is now valid — meaning that the data is fully available and ready for use by the system. Conversely, if the signal indicates that the reading is still in progress, the output data may be considered invalid, meaning that the data is incomplete or not yet ready, and thus cannot be used by the system until the reading operation is fully finished.

[0053] In block 102, the method comprises generating, by the processor, based on the at least one generated first signal, a second signal, where the timing of the second signal is adjusted using a delay path. The second signal may comprise a "memory path completion signal" and may be generated by performing a logic operation on at least one first signal. Specifically, the logic operation may involve ANDing the memory completion signals from the multiple memory dice. This means that the memory path completion signal may be generated when at least one memory completion signal from at least one memory die is valid, though it may also incorporate multiple signals from several dice.

[0054] The second signal may be used to control the clock generator, which waits for the memory completion signals to arrive before initiating the next clock pulse. The clock generator may comprise a tunable replica circuit (TRC) clock generator. This mechanism may ensure that the clock signal is aligned with the memory operations, allowing the clock to rise or fall only when all memory completion signals have been confirmed, indicating that the memory output is available. The clock may effectively "wait" for the data to propagate correctly through the memory path, ensuring synchronisation between the memory operations and the clock signal.

[0055] The timing of the second signal may be adjusted using a delay path. The delay may be introduced after the ANDing operation to generate the final second signal. Advantageously, the delay path can enable precise control over the timing of the second signal to reflect the delays traversed by the memory operations. The delay path may involve not only applying a delay to account for memory data propagation time, but also subtracting the delays introduced by various memory operations.

[0056] The delay path may comprise a tunable delay path, and the method may further comprise tuning the delay path. Tuning the delay path may involve adjusting parameters such as resistors, capacitors, or programmable logic elements to match the timing of the memory data propagation. By properly tuning the delay path, the system can ensure that the clock signal is triggered only after the memory data is fully propagated and ready for use, thereby optimising system performance.

[0057] In block 103, the method comprises comparing, using a phase detector, the second signal with a third signal. The third signal may comprise at least one signal indicating that non-memory operations within the CPU die of the multiple memory dice have been completed. Non-memory operations refer to activities that differ from the memory read or write processes previously discussed. These may include tasks such as data processing, error correction, address decoding, or control logic operations that occur within the CPU die but are not directly related to the retrieval or storage of data in memory arrays. These operations ensure that the system is prepared for subsequent steps, such as managing data flow or handling interrupts.

[0058] The third signal may be generated by performing a logic operation on at least one signal that indicates the completion of these non-memory operations. Similar to the generation of the second signal, this logic operation may involve ANDing multiple signals from different non-memory completion paths across the multiple CPU dice. This means that the third signal may be formed by combining signals that individually indicate the completion of various non-memory tasks, ensuring that the third signal is generated only when all necessary non-memory operations have concluded across the relevant dice.

[0059] The second signal (indicating memory operation completion) is then compared with the third signal (indicating non-memory operation completion) using a phase detector. The phase detector is responsible for determining the relative timing or alignment between these two signals. This comparison allows the system to identify any discrepancies in timing between the completion of memory and non-memory tasks.

[0060] The outcome of this comparison may help determine whether the memory supply voltage needs to be adjusted. Specifically, if the second signal and the third signal are not properly aligned, it may indicate that the memory operations are lagging behind the non-memory operations or vice versa. In such cases, the system may increase or decrease the memory supply voltage as necessary to optimise performance. For instance, if the memory operations are slower than non-memory operations, the memory supply voltage may be increased to speed up the memory processes. Conversely, if the memory operations are completing faster than required, the memory supply voltage may be decreased to save power while maintaining system integrity and synchronisation.

[0061] The method comprises, in block 104, adjusting the voltage supply of the at least one memory die of the multiple memory dice based on the result of a comparison between the second signal and the third signal. This comparison may be conducted using a phase detector, which compares the timing of memory completion signals (represented by the second signal) with non- memory operations (represented by the third signal). If a phase difference between the second signal and the third signal exceeds a predefined threshold, it indicates a timing mismatch. The control signal generated by the phase detector may either be sent directly to the memory power supply regulator or pass through a power management unit (PMU). In either case, the result is an adjustment to the memory voltage supply to resolve the imbalance and ensure proper timing alignment.

[0062] For instance, the phase detector may identify if the memory completion signal rises later than the non-memory signals, meaning that memory operations are slower than other parts of the system and are dictating the overall cycle time of the clock. In such a scenario, the memory’s delayed readiness could delay the system from advancing to the next clock cycle efficiently. To counter this, the system may respond by increasing the voltage supply to the memory die, thereby speeding up the memory operations until the phase difference falls within the predefined acceptable range and the memory is no longer delaying the clock cycle.

[0063] Furthermore, the method may involve using the phase detector to continuously monitor and detect when the memory path completion signal becomes dominant - specifically, when it delays the clock cycle relative to non-memory operations. After properly calibrating the delay paths in the clock generation circuitry, the control circuit may signal to the power management unit (PMU) or directly to an integrated voltage regulator (IVR) that an adjustment in the voltage supply is necessary. In particular, the phase detector may indicate whether the memory system is operating fast enough to avoid delaying the CPU. The supply voltage for the CPU may be managed by counting CPU cycles within a reference clock time window. If the count is below a certain threshold, it indicates that the CPU is operating too slowly and its supply voltage needs to be increased. However, this method is effective only if the memory system is not causing delays for the CPU. The phase detector and the memory voltage adjustment loop can help in ensuring that the memory system’s speed does not become a bottleneck for CPU performance.

[0064] In this manner, the method ensures that the voltage supply is dynamically adjusted based on real-time performance comparisons, allowing the system to optimise both the CPU and memory speeds, reducing delays, and improving overall system efficiency. By carefully tuning the memory and CPU voltage supplies, the method helps balance power consumption and performance while maintaining synchronisation between memory and non-memory operations within the SoC. In turn, this can help reduce design effort, chip area and power consumption, while maximising the performance of the SoC through optimally controlling two different supply voltages.

[0065] Figure 2 is a schematic representation of delay paths according to an example. The system depicted in the figure may provide an optimised mechanism for adjusting the power supply and managing the timing of both memory and CPU operations. The system may incorporate configurable memory delay paths 202 and configurable cycle delay paths 204 to account for the timing differences between memory operations and CPU processes. These delay paths may be employed to ensure synchronisation between the memory and CPU, such that neither component becomes a limiting factor for overall system performance.

[0066] The system may include configurable memory delay paths 202, which are responsible for managing signals associated with memory operations. These delay paths may process memory completion signals 201 from multiple memory dice, indicating whether memory read or write operations have been completed. If memory operations are found to be slower than expected, the delay path may introduce a tunable delay to synchronise the memory operations with the CPU clock. The system may generate a memory path completion signal by performing a logic operation on the memory completion signals, such as an ANDing operation. This means that the memory path completion signal may only be generated when at least one memory completion signal 201 is valid, or it may require multiple signals from various memory dice. The timing of this signal may be adjusted using a tunable delay to ensure that the clock signal is gated until memory read completion is confirmed.

[0067] The phase detector 203 within the system may compare the timing of memory operations with CPU logic paths. This comparison may be crucial for determining which component is dictating the system’s clock cycle. If the memory is slower than the CPU logic, the phase detector may signal that the memory supply needs to be increased, thereby improving memory speed to match the CPU’s timing. Conversely, if memory is not delaying the clock cycle, the phase detector may signal that the memory voltage supply does not need further adjustment, allowing the CPU to proceed without being bottlenecked by memory operations.

[0068] In addition to the memory delay paths, the system may also feature configurable cycle delay paths 204, which may manage the overall system clock cycle to ensure that the clock does not advance before CPU are ready. The cycle delay may be tuned to match the speed of memory operations, thereby preventing the CPU clock from proceeding prematurely. This is ensured by an AND gate at the input of block 206 (not shown), which verifies that the memory data has been properly processed and is ready for use by the CPU, thereby synchronizing the two components.

[0069] The system may further include configurable phase paths 205, 207, which may work in conjunction with the cycle delay path 204 and the phase detector 203 to ensure that the phase relationship between the memory completion signals and CPU logic remains aligned. The configurable phase path may control the gating of the clock signal with greater specificity. Phase path 207 may indicate when it is time to de-assert the clock signal, ensuring that the clock goes low before it can rise again. Phase path 205, in conjunction with the cycle path 204 and the combined memory paths 202, may then gate the next clock rise. This coordinated process can ensure that both memory and CPU operations are properly synchronised, optimising system performance by avoiding unnecessary delays in the clock cycle.

[0070] The configurable delay paths may be tuned. In particular, when the memory supply is high and the memory delay is minimal, the configurable delay paths 205 and 207 may be tuned to enable proper CPU functionality. These paths may then be slightly sped up to intentionally cause a failure, after which the configurable cycle delay path 204 may be adjusted to set the correct CPU speed at the given power supply level. If a faster CPU operation is desired, the CPU power may be increased accordingly. Once the CPU speed is set, the memory supply may be gradually reduced until the system begins to fail. At this point, the configurable memory delay path 202 may be tuned by incrementally increasing its delay to ensure the clock signal gated by path 202 slows down, allowing the memory operations to complete and restoring system functionality. After tuning, if the phase detector 203 signals that memory is now slowing the system, the memory supply may be increased slightly. Following this process, the system may be efficiently tuned for optimal performance.

[0071] The system may also incorporate a set-reset (SR) latch 206, which functions as the clock itself. The output of this SR latch, denoted as Q, is the clock signal. It ensures that the system’s timing adjustments remain consistent even as operations vary between memory and CPU.

[0072] The operational flow of the system may involve several stages. In one scenario, the system evaluates CPU performance by determining whether the clock circuit generates enough clock pulses within a given reference window. If the CPU is underperforming, the system may increase CPU power to boost its speed. The memory system, on the other hand, must adjust to the CPU's performance, as indicated by the phase detector. If the memory is not keeping up with the CPU, the system may increase the memory voltage to ensure it conforms to the CPU's timing, rather than adjusting the CPU power based on memory performance.

[0073] Figure 3 is a schematic representation of an apparatus according to an example. The apparatus 300 may be arranged to perform the method described above in relation to Figure 1. The apparatus 300 comprises multiple memory dice 310 and a processor 320. The processor 320 operates independently and its supply is governed by meeting specific performance goals. The memory dice 310, as dependent subsystems, each have specific delay paths and converge into the main system (the processor 320). In response to determining that memory operations within a memory die of the multiple memory dice 310 have been completed, the apparatus generates at least one first signal. This first signal indicates the completion of memory operations. The processor 320 is further arranged to generate, based on the at least one first signal, a second signal, wherein the timing of the second signal is adjusted using a delay path. This method efficiently governs and controls the speed (or supply) of the dependent memory subsystems, taking into account their intrinsic delays as well as the delay their signals undergo within the main system. In other words, the processor 320 may be arranged to perform the blocks 101 and 102 described above in relation to Figure 1.

[0074] The apparatus 300 further comprises a phase detector 330 arranged to compare the second signal and a third signal, wherein the third signal comprises at least one signal indicating that non-memory operations within the memory die of the multiple memory dice have been completed. In other words, the phase detector 330 is arranged to perform the block 103 described above in relation to Figure 1. The processor 320 is further arranged to adjust the voltage supply of at least one memory die of the multiple memory dice based on a result of the comparison. The processor 320 may comprise a tunable replica circuit (TRC) clock generator.

[0075] According to an example, machine-readable instructions can be loaded onto a computer or other programmable data processing devices, so that the computer or other programmable data processing devices perform a series of operations to produce computer-implemented processing, thus the instructions executed on the computer or other programmable devices provide an operation for realizing functions specified by flow(s) in the flow charts and / or block(s) in the block diagrams.

[0076] Further, the teachings herein may be implemented in the form of a computer or software product, such as a non-transitory machine-readable storage medium, the computer software or product being stored in a storage medium and comprising a plurality of instructions, e.g., machine readable instructions, for making a computer device implement the methods recited in the examples of the present disclosure.

[0077] In some examples, some methods can be performed in a cloud-computing or network-based environment. Cloud-computing environments may provide various services and applications via the Internet. These cloud-based services (e.g., software as a service, platform as a service, infrastructure as a service, etc.) may be accessible through a web browser or other remote interface of the user equipment for example. Various functions described herein may be provided through a remote desktop environment or any other cloud-based computing environment.

[0078] While various embodiments have been described and / or illustrated herein in the context of fully functional computing systems, one or more of these exemplary embodiments may be distributed as a program product in a variety of forms, regardless of the particular type of computer-readable-storage media used to actually carry out the distribution. The embodiments disclosed herein may also be implemented using software modules that perform certain tasks. These software modules may include script, batch, or other executable files that may be stored on a computer-readable storage medium or in a computing system. In some embodiments, these software modules may configure a computing system to perform one or more of the exemplary embodiments disclosed herein. In addition, one or more of the modules described herein may transform data, physical devices, and / or representations of physical devices from one form to another.

[0079] The preceding description has been provided to enable others skilled in the art to best utilize various aspects of the exemplary embodiments disclosed herein. This exemplary description is not intended to be exhaustive or to be limited to any precise form disclosed. Many modifications and variations are possible without departing from the spirit and scope of the instant disclosure. The embodiments disclosed herein should be considered in all respects illustrative and not restrictive. Reference should be made to the appended claims and their equivalents in determining the scope of the instant disclosure.

Claims

CLAIMS1. A method for managing voltage supply between multiple memory dice within an integrated circuit, the method comprising: in response to determining that memory operations within a memory die of the multiple memory dice have been completed, generating, by a processor, at least one first signal, wherein the first signal comprises a signal indicating that memory operations within the memory die of the multiple memory dice have been completed (101); generating, by the processor, based on the generated at least one first signal, a second signal, wherein a timing of the second signal is adjusted using a delay path (102); comparing, using a phase detector, the second signal and a third signal, wherein the third signal comprises at least one signal indicating that non-memory operations within the memory die of the multiple memory dice have been completed(103); and adjusting the voltage supply of at least one memory die of the multiple memory dice based on a result of the comparison(104).

2. The method of claim 1 , wherein the second signal is generated by performing a logic operation on the at least one first signal.

3. The method of claim 1 or 2, wherein the third signal is generated by performing a logic operation on the at least one signal indicating that non-memory operations within the memory die of the multiple memory dice have been completed.

4. The method of claim 1 , 2 or 3, wherein the memory operations within the memory die comprise reading data stored in one or more memory arrays within the memory die of the multiple memory dice.

5. The method of any one of claims 1 to 4, wherein adjusting the voltage supply of the at least one dice of the multiple memory dice based on the result of the comparison (104) comprises altering the voltage supply of the at least one dice of the multiple memory dice in response to determining that a phase difference between the second signal and the third signal exceeds a pre-defined threshold.

6. The method of any one of claims 1 to 5, wherein the timing of the second signal is adjusted using a tunable delay path, the method further comprising: tuning the delay path.

7. The method of any one of claims 1 to 6, wherein the processor comprises a tunable replica circuit, TRC, clock generator.

8. An apparatus (300) comprising: multiple memory dice (310); a processor (320) arranged to, in response to determining that memory operations within a memory die of the multiple memory dice (310) have been completed, generate at least one first signal, wherein the first signal comprises a signal indicating that memory operations within the memory die of the multiple memory dice (310) have been completed, and generate, based on the generated at least one first signal, a second signal, wherein a timing of the second signal is adjusted using a delay path; a phase detector (330) arranged to compare the second signal and a third signal, wherein the third signal comprises at least one signal indicating that non-memory operations within the memory die of the multiple memory dice (310) have been completed,wherein the processor (320) is further arranged to adjust the voltage supply of at least one memory die of the multiple memory dice (310) based on a result of the comparison.

9. The apparatus of claim 8, wherein the processor (320) is arranged to generate the second signal by performing a logic operation on the at least one first signal.

10. The apparatus of claim 8 or 9, wherein the processor (320) is arranged to generate the third signal by performing a logic operation on the at least one signal indicating that non-memory operations within the memory die of the multiple memory dice (310) have been completed.

11. The apparatus of claim 8, 9 or 10, wherein the memory operations within the memory die comprise reading data stored in one or more memory arrays within the memory die of the multiple memory dice (310).

12. The apparatus of any one of claims 8 to 11, wherein, to adjust the voltage supply of the at least one memory die of the multiple memory dice (310) based on the result of the comparison, the processor (320) is arranged to alter the voltage supply of the at least one dice of the multiple memory dice (310) in response to determining that a phase difference between the second signal and the third signal exceeds a pre-defined threshold.

13. The apparatus of any one of claims 8 to 12, wherein the delay path comprises a tunable delay path.

14. The apparatus of any one of claims 8 to 13, wherein the processor (320) comprises a tunable replica circuit, TRC, clock generator.

15. A computer program stored on a non-transitory medium and including code instructions, which, when executed on more or more processors, cause the one or more processors to execute the method of any of claims 1 to 7.

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