Method for transferring electronic elements and array of electronic elements

Abstract

The invention concerns a method for transferring electronic elements from a carrier substrate to a target substrate comprising the steps of : Providing a plurality of electronic elements arranged in an array- like pattern on the carrier substrate; Transferring at least a portion of the plurality of electronic elements from the carrier substrate to an interposer layer comprising a plurality of through contacts, such that at least one of the plurality of through contacts is electrically coupled to one of the plurality of electronic elements, respectively; Processing a side of the at least portion of the plurality of electronic elements opposite the interposer layer to provide an outcoupling structure and / or outcoupling element and / or electric contact on a side of each of the electronic elements opposite the interposer layer; And arranging the interposer layer on the target substrate comprising an integrated circuit and a plurality of contact pads, such that at least one of the plurality of through contacts is electrically coupled to one of the plurality of contact pads, respectively.

Description

[0001] 2024PF00575

[0002] METHOD FOR TRANSFERRING ELECTRONIC ELEMENTS AND ARRAY OF ELECTRONIC

[0003] ELEMENTS

[0004] The present application claims priority from German patent application DE 10 2024 130 248 . 8 filed on October 17 , 2024 , the disclosure of which 5 is incorporated by way for reference in its entirety .

[0005] The present invention concerns a method for transferring electronic and in particular optoelectronic elements . The present invention also concerns an array of such electronic and in particular optoelectronic elements arranged on an interposer layer .

[0006] BACKGROUND pLEDs are optoelectronic elements / components that comprise a lateral dimension in the range from a few hundred nm to about 10pm or 40 pm . Such elements provide a variety of different applications , including but not limited to displays and applications like AR / VR . Instead of such small discrete elements it is also possible to use larger LEDs which however are pixelized to such an extent that the smallest light emitting pixel ( separated or still connected together ) of such a larger LED can be in the range from a few hundred nm to about 10pm or 40 pm . In terms of the present invention an optoelectronic element can thus be regarded to as a separate element with aforementioned dimensions or can be regarded to as a sub element / portion of a larger LED which comprises several light emitting pixels as an array, wherein the light emitting pixels comprise aforementioned dimensions . The light emitting pixels can thereby be separated but embedded in a common material or still be connected by a common material layer ( for example EPI layer ) .

[0007] Such optoelectronic elements are usually processed in arrays of several thousands of optoelectronic elements , and subsequently transferred from their growth substrate or an intermediate carrier to a target substrate ( e . g . display backplane / driver chip ) . After being transferred to the target substrate the optoelectronic elements are then attached / electrically connected to it by for example reflow soldering , glueing or Si direct bonding . Such a bonding process typically takes 2024PF00575 places before the top Remitting side ) of the optoelectronic elements has been processed . Increased light outcoupling can be achieved by for example roughening the optoelectronic elements ' top surfaces , or adding specific outcoupling structures . Lenses and other micro optical structures can for example be added for beam shaping . This requires several process steps that the optoelectronic elements need to undergo once they are arranged on the target substrate , and may include high temperature steps , aggressive chemistries and / or mechanical stresses that are compatible with the material of the optoelectronic elements , but might affect the quality of the target substrate .

[0008] It is therefore an obj ect of the proposed principle to specify a method that overcomes at least partially the above-mentioned disadvantages .

[0009] SUMMARY OF THE INVENTION

[0010] This and other obj ects are addressed by the subj ect matter of the independent claims . Features and further aspects of the proposed principles are outlined in the dependent claims .

[0011] The inventors propose to use an interposer layer between optoelectronic elements and a target substrate to which they are to be transferred . By this a side of the optoelectronic elements opposite the target substrate can be further processed before they are actually transferred to the target substrate as such a further processing may be limited in the choice of processes due to the target substrate being too sensitive for some of such steps . The interposer layer thereby serves as stabilization layer during such further processing for example holding the optoelectronic elements together and allowing a further processing of an emission side of the optoelectronic elements and allows the optoelectronic elements to be transferred to the target substrate arranged in arrays afterwards . At the same time the interposer layer comprises electrical through contacts to allow the optoelectronic elements to be electrically connected with the target substrate such that the interposer layer can remain in the final product between the optoelectronic elements and the target substrate . This allows a greater flexibility in the selection of emission side processes of the 2024PF00575 optoelectronic elements and coming with it allows a greater potential for increased light outcoupling and / or beam shaping of light being emitted from the optoelectronic elements .

[0012] According to a first aspect , a transfer method for transferring electronic elements from a carrier substrate to a target substrate comprises the steps of :

[0013] Providing a plurality of electronic elements arranged in an arraylike pattern, for example in rows and columns or a hexagonal pattern, on the carrier substrate ;

[0014] Transferring at least a portion of the plurality of electronic elements from the carrier substrate to an interposer layer comprising a plurality of through contacts , such that at least one of the plurality of through contacts is electrically coupled to one of the plurality of electronic elements , respectively;

[0015] Processing a side of the at least portion of the plurality of electronic elements opposite the interposer layer to provide an outcoupling structure and / or outcoupling element and / or electric contact on a side of each of the electronic elements opposite the interposer layer ; and

[0016] Arranging the interposer layer on the target substrate comprising an integrated circuit and a plurality of contact pads , such that at least one of the plurality of through contacts is electrically coupled to one of the plurality of contact pads , respectively .

[0017] The electronic elements can be formed in particular by optoelectronic elements such as discrete pLEDs or light emitting pixels of a larger pixelized LEDs . The electronic elements can thus be elements which are designed to emit light of a desired wavelength and which have particularly small dimensions . For example , the electronic elements can have edge lengths of less than 40pm, less than 10pm or less than 1pm. However, the electronic elements can also be formed by other electronic elements such as integrated circuits ( ICs ) or microintegrated circuits ( pICs ) . The electronic elements can for example be formed by separate elements with aforementioned dimensions or can be sub element ( s ) / portion ( s ) of a larger element which comprises several of the smaller electronic elements as an array, wherein the sub 2024PF00575 elements / portions comprise aforementioned dimensions . The sub elements / portions can thereby be separated but embedded in a common material or still be connected by a common material layer ( for example EPI layer ) .

[0018] According to some aspects , the step of processing a side of the at least portion of the plurality of electronic elements comprises an at least partial removal of the carrier substrate . In particular the carrier substrate can serve as stabilization layer for the electronic elements until arranging them in the interposer layer which then can serve as stabilization layer for the electronic elements so that the carrier substrate can at least partly be removed without damaging the stability of the whole structure . Hence a further processing of the side of the electronic elements opposite the interpose layer is then possible with the electronic elements staying in place .

[0019] According to some aspects , the plurality of electronic elements is grown on the carrier substrate . Accordingly, the carrier substrate may be the growth substrate of the plurality of electronic elements , for example in the form of a wafer . The electronic elements are arranged on the carrier substrate in an array like pattern, for example in rows and columns . In particular , the electronic elements are arranged on the carrier substrate in a manner that is most suitable for manufacturing the electronic elements on the carrier substrate . For example , the electronic elements on the carrier substrate can be laterally separated from each other or pixelized by a mesa etching process . However , it is also conceivable that the carrier substrate is a substrate onto which the electronic elements have been rebonded during their manufacture .

[0020] According to some aspects , the step of processing a side of the at least portion of the plurality of electronic elements opposite the interposer layer comprises to provide an outcoupling structure and / or outcoupling element of the carrier substrate . In particular portions of the carrier substrate can be used to form an outcoupling structure and / or outcoupling element above each of the electronic , in particular optoelectronic elements . For example , a surface structuring can be formed above the electronic, in particular optoelectronic elements or 2024PF00575 lenses / plenses can be formed above the electronic , in particular optoelectronic elements . Such an outcoupling structure and / or outcoupling element can however also be formed at least partly of a different material applied to the electronic elements and does not have to be ( only) of the material of the carrier substrate .

[0021] According to some aspects , the target substrate is a CMOS wafer . In particular , the target substrate can be an intelligent substrate to which the electronic elements are to be transferred such as a backplane . The target substrate can in particular serve to control the electronic elements and can in particular be sensitive (mechanically and / or thermally and / or chemically) to processes for further processing an ( emission) side of the electronic elements opposite the target substrate . Therefore , the use of such an interposer layer is particularly useful as any steps to which the target substrate may be sensitive to can be done on the interposer layer and before arranging the electronic elements on the target substrate .

[0022] According to some aspects , the step of processing a side of the at least portion of the plurality of electronic elements opposite the interposer layer comprises to provide a common electric contact for the electronic elements on a side of the electronic elements opposite the interposer layer . In case of optoelectronic elements such a common electric contact can in particular be of a transparent material such as a TCO material . Such a common contact can for example be provided only or together with an outcoupling structure and / or outcoupling element above the electronic elements . In case of the latter the common electric contact can be arranged between an outcoupling structure and / or outcoupling element and the electronic elements or on top of it .

[0023] According to some aspects , interposer layer is of silicon, or the interposer layer may comprise a glass or be formed by a glass , such as quartz glass . Alternatively or additionally, the interposer layer may comprise or be formed by sapphire . For example , the interposer layer can be a silicon wafer with through contacts , possibly also with wiring layers consisting of metals and dielectrics . Instead of being made of 2024PF00575 silicon, the interposer layer can also be based on glass or ceramic . For example , the interposer layer can also be formed of a foil comprising electrical through contact through the foil .

[0024] According to some aspects , the interposer layer can serve for one or more several tas ks , namely as a redistribution layer and / or forming (backside ) reflector for the electronic elements ( in case of optoelectronic elements ) . Therefore , the interposer layer can besides the electrical through contacts comprises a reflective material ( for example a metal ) forming a (backside ) reflector for the electronic elements . The interposer layer can for example also form / be a DBR- layer forming a (backside ) reflector for the electronic elements .

[0025] According to some aspects , the step of transferring at least a portion of the plurality of electronic elements from the carrier substrate to the interposer layer comprises bonding the electronic elements on the carrier substrate to the interposer layer and in particular its electrical contacts to the trough contacts though the interposer layer . According to some aspects , the step of arranging the interposer layer on the target substrate comprises bonding the interposer layer on the target substrate and in particular its electrical trough contacts though the interposer layer with the contact pads on the target substrate .

[0026] According to some aspects , the electronic elements transferred to the target substrate have a different pitch on the target substrate than the electronic elements arranged on the carrier substrate / its growth substrate . The spacing on the target substrate may, for example , correspond to a desired pixel pitch on the target substrate , whereas the spacing of the electronic elements on the carrier substrate may correspond to a very small spacing from one another , in particular a spacing with which the electronic elements on the carrier substrate have been produced relative to one another . The spacing of the electronic elements on the target substrate can be greater , and in particular many times greater , than the spacing of the electronic elements on the carrier substrate . 2024PF00575

[0027] According to some aspects , not all but only some of the electronic elements arranged on the carrier substrate are transf erred / bonded to the interposer layer, for example only every second, third, fourth or fifth electronic element , such that the pitch of the electronic elements on the interposer layer is different to the pitch of the electronic elements on the carrier substrate .

[0028] According to some aspects , different electronic elements from different carrier substrates are transf erred / bonded to the interposer layer before the side of the electronic elements opposite the interposer layer is further processed . By this for example RGB-pixels can be formed on the interposer layer before the side of the optoelectronic elements opposite the interposer layer is further processed .

[0029] According to some aspects , the interposer layer or at least portions of the interposer layer not covered by electronic elements is more resistant to chemical etching processes than the target substrate . In particular portions of the interposer layer surrounding the electrical through contacts can be more resistant to chemical etching processes than the through contacts and the target substrate . By this , such processes to for example form an outcoupling structure and / or outcoupling element and / or electric contact may not harm the elements being in contact with it .

[0030] According to some aspects , the interposer layer is thinned before being arranged on the target substrate . The interposer layer can at maximum be thinned to such an extent that it j ust holds the electronic elements together . However, if a stable structure of electric contact and / or outcoupling elements is formed on the side of the electronic elements opposite the interposer layer holding the electronic elements together the interposer layer can in theory be thinned even more until it almost no longer exists .

[0031] According to some aspects the electronic elements are tested and / or sampled and / or evaluated on the interposer layer . Further the electronic elements can be separated from one another and / or sorted on the interposer layer before they are transfer to the target substrate . 2024PF00575

[0032] According to a further aspect , an electronic device comprises a plurality of electronic elements arranged in an array-like pattern, for example in rows and columns or a hexagonal pattern, on an interposer layer comprising a plurality of through contacts . At least one of the plurality of through contacts is thereby electrically coupled to one of the plurality of electronic elements , respectively . The device further comprises an outcoupling structure and / or outcoupling element and / or electric contact on a side of each of the electronic elements opposite the interposer layer and a target substrate comprising an integrated circuit and a plurality of contact pads . The interposer layer is arranged between the target substrate and the electronic elements and at least one of the plurality of through contacts is electrically coupled to one of the plurality of contact pads , respectively .

[0033] The electronic device can, for example , be a product of the method according to the invention, namely a device comprising the interposer layer, the target substrate , optionally portions of the carrier substrate , and the electronic elements arranged on the target substrate after these have been further processed on the interposer layer and before these are transferred to the target substrate .

[0034] According to some aspects , the target substrate is a CMOS wafer . In particular , the target substrate can be an intelligent substrate to which the electronic elements are to be transferred such as a backplane . The target substrate can in particular serve to control the electronic elements and can in particular be sensitive (mechanically and / or thermally and / or chemically) to processes for further processing an ( emission) side of the electronic elements opposite the target substrate .

[0035] According to some aspects , the device comprises a common electric contact for the electronic elements on a side of the electronic elements opposite the interposer layer . In case of optoelectronic elements such a common electric contact can in particular be of a transparent material such as a TCO material . Such a common contact can for example be provided only or together with an outcoupling structure and / or 2024PF00575 outcouplmg element above the electronic elements . In case of the latter the common electric contact can be arranged between an outcoupling structure and / or outcoupling element and the electronic elements or on top of it .

[0036] According to some aspects , interposer layer is of silicon, or the interposer layer may comprise a glass or be formed by a glass , such as quartz glass . Alternatively or additionally, the interposer layer may comprise or be formed by sapphire . For example , the interposer layer can be a silicon wafer with through contacts , possibly also with wiring layers consisting of metals and dielectrics . Instead of being made of silicon, the interposer layer can also be based on glass or ceramic . For example , the interposer layer can also be formed of a foil comprising electrical through contact through the foil .

[0037] According to some aspects , the interposer layer comprises a minimal thickness such that the material is self-supporting . For example , this could be 100]im for glass . The interposer layer can also initially be relatively thick ( e . g . up to 1 . 5mm) and then be thinned to 100-300]im before transferred to the target substrate .

[0038] According to some aspects , the interposer layer can serve for one or more several tas ks , namely as a redistribution layer and / or forming (backside ) reflector for the electronic elements ( in case of optoelectronic elements ) . Therefore , the interposer layer can besides the electrical through contacts comprises a reflective material ( for example a metal ) forming a (backside ) reflector for the electronic elements . The interposer layer can for example also form / be a DBR- layer forming a (backside ) reflector for the electronic elements .

[0039] SHORT DESCRIPTION OF THE DRAWINGS

[0040] Further aspects and embodiments in accordance with the proposed principle will become apparent in relation to the various embodiments and examples described in detail in connection with the accompanying drawings in which 2024PF00575

[0041] Figures 1A and IB show steps of a method for transferring optoelectronic elements from a carrier substrate to a target substrate directly;

[0042] Figures 2A to 2D show steps of a method for transferring electronic elements from a carrier substrate to a target substrate using an interposer layer in accordance with some aspects of the proposed principle ; and

[0043] Figures 3A and 3B show steps of a further method for transferring optoelectronic elements from a carrier substrate to a target substrate using an interposer layer in accordance with some aspects of the proposed principle .

[0044] DETAILED DESCRIPTION

[0045] The following embodiments and examples disclose various aspects and their combinations according to the proposed principle . The embodiments and examples are not always to scale . Likewise , different elements can be displayed enlarged or reduced in size to emphasize individual aspects . It goes without saying that the individual aspects of the embodiments and examples shown in the figures can be combined with each other without further ado , without this contradicting the principle according to the invention . Some aspects show a regular structure or form . It should be noted that in practice slight differences and deviations from the ideal form may occur without , however , contradicting the inventive idea .

[0046] In addition, the individual figures and aspects are not necessarily shown in the correct size , nor do the proportions between individual elements have to be essentially correct . Some aspects are highlighted by showing them enlarged . However , terms such as "above" , "over" , "below" , "under" "larger" , "smaller" and the like are correctly represented with regard to the elements in the figures . So it is possible to deduce such relations between the elements based on the figures . 2024PF00575

[0047] Figures 1A and IB show steps of a method for transferring optoelectronic elements 2 from a carrier substrate 3 to a target substrate 4 directly . The optoelectronic elements 2 are thereby arranged on / off the carrier substrate 3 arranged in an array-like pattern and are bonded to contact pads 8 on the target substrate 4 directly with the carrier substrate 3 holding the optoelectronic elements 2 together . The carrier substrate 3 comprises a semiconductor layer stack 9 from which the optoelectronic elements 2 are formed, wherein the optoelectronic elements 2 are separated by mesa trenches into the semiconductor layer stack 9 . A common layer of the semiconductor layer stack 9 holds the optoelectronic elements 2 together and a dielectric passivation layer 10 covers the optoelectronic elements 2 and extends into the trenches . Once the optoelectronic elements 2 are bonded to the target substrate 4 , the side of the optoelectronic elements 2 opposite the target substrate 4 can be further processed to provide an outcoupling structure / outcoupling elements / electric contact ( s ) for the optoelectronic elements 2 . In case of the target substrate 4 being an intelligent substrate , for example a CMOS chip, the choice of processes for further processing the side of the optoelectronic elements 2 opposite the target substrate 4 is very limited as the target substrate may in particular be sensitive to most of the processes known for providing an efficient outcoupling structure / outcoupling elements / electric contact ( s ) .

[0048] To counteract this problem, the invention proposes a method for transferring electronic elements 2 from a carrier substrate 3 to a target substrate 4 using an interposer layer 5 as shown in Fig . 2A to 2D . The idea is to add an additional wafer ( interposer layer 5 ) , e . g . a Si wafer with electrical feedthroughs or vias 6 between the CMOS wafer ( target substrate 4 ) and the optoelectronic elements 2 . The carrier substrate 3 with the optoelectronic elements 2 ist first be bonded onto the interposer wafer 5 . It is then possible to do the emission side processing of the optoelectronic elements 2 on the interposer wafer 5 which is less sensitive than the CMOS wafer 4 , thus allowing for more freedom in the selection of processes for e . g . increasing light outcoupling from the optoelectronic elements 2 . After further processing the optoelectronic elements 2 on the interposer 2024PF00575 layer 5 can be bonded to the target substrate 4 without exposing the target substrate to any aggressive chemistry and / or high temperatures for example .

[0049] Hence the proposed method allows more flexibility / less restrictions in the selection of emission side processes , which in turn increases the potential for increased light outcoupling and / or beam shaping of light generated in the optoelectronic elements 2 .

[0050] The interposer layer 5 can be a Si wafer with Au vias 6 . The carrier substrate 3 with the optoelectronic elements 2 is for example bonded onto the interposer layer 5 , emission side processing of the optoelectronic elements 2 is done , and the interposer layer 5 with the optoelectronic elements 2 on it is then for example bonded to the target substrate 4 . The interposer layer 5 can also be a Si wafer with blind holes filled with an electrically conductive material , e . g . Au on which the optoelectronic elements 2 are then bonded . This avoids exposure of the electrically conductive material / metal to aggressive chemistry .

[0051] In more detail , in a first step, as shown in Fig . 2A, a carrier substrate 3 with a plurality of electronic elements 2 arranged in rows and columns is provided . The electronic elements may in particular be pLEDs that have been produced on the carrier substrate 3 . The carrier substrate 3 can, for example , be the growth substrate / manuf acturing wafer of the electronic elements 2 . The electronic elements are arranged in rows and columns on the carrier substrate 3 . In particular , the electronic elements 2 are arranged on the carrier substrate 3 in such a way as may result from manufacturing the electronic elements 2 on the charrier substrate 3 . The carrier substrate 3 comprises a semiconductor layer stack 9 from which the optoelectronic elements 2 are formed, wherein the optoelectronic elements 2 are separated by etching mesa trenches into the semiconductor layer stack 9 . A common layer of the semiconductor layer stack 9 holds the optoelectronic elements 2 together and a dielectric passivation layer 10 covers the optoelectronic elements 2 and extends into the trenches . 2024PF00575

[0052] Further an interposer layer 5 is provided comprising a plurality of through contacts 6 . The number of through contacts 6 can thereby in particular relate to the number of electronic elements 2 to be transferred from the carrier substrate 3 to a target substrate 4 . In addition, the target substrate 4 is provided . The target substrate comprises a plurality of contact pads 8 on / in a tops surface of the target substrate 4 . The number of contact pads 8 can thereby in particular relate to the number of electronic elements 2 to be transferred from the carrier substrate 3 to the target substrate 4 . The target substrate 4 is in particular an intelligent substrate for driving the electronic elements 2 and in particular comprises or is an integrated circuit .

[0053] The electronic elements 2 are then bonded to the interposer layer 5 as shown in Fig . 2B such that the electronic elements 2 are in electrical contact with each one of the through contacts 6 . The interposer layer 5 is thereby conf igured / f ormed to hold the electronic elements 2 together and serve as a new "carrier" substrate when at least partially removing the carrier substrate 3 .

[0054] As shown in Fig . 2C, the side of the electronic elements 2 opposite the interposer layer 5 is then further processed forming outcoupling elements 7 in form of plenses above each one of the electronic elements 2 . The outcoupling elements 7 are formed in the particular case out of the carrier substrate 3 and in particular out of the common semiconductor layer of the semiconductor layer stack 9 . Hence by forming the outcoupling elements 7 the carrier substrate 3 holding the electronic elements 2 is disassembled so that the interposer layer is needed to hold the electronic elements 2 in place as the electronic elements 2 are separated from each other each forming a discrete pLED .

[0055] The outcoupling elements 7 as shown are thereby to be understood exemplary and any other type of outcoupling structure / outcoupling elements / electric contact ( s ) on a side of the electronic elements 2 opposite the interposer layer 5 can be provided . 2024PF00575 14

[0056] The processed electronic elements 2 on the interposer layer 5 are then bonded to the target substrate 4 and in particular on the contact pads 8 of the target substrate 4 such that the electronic elements 2 via the through contacts 6 are in electrical contact with each one of the contact pads 8 . The resulting product according to Fig . 2D corresponds to an electronic device 1 according to some aspects of the proposed principle . The electronic device 1 can for example be used in a display or VR / AR application for pro j ecting / imaging an image into a human' s eye .

[0057] Figures 3A and 3B show steps of a further method for transferring optoelectronic elements from a carrier substrate to a target substrate using an interposer layer in accordance with some aspects of the proposed principle . In particular the steps shown in Figures 3A and 3B can follow the steps shown in Figures 2A and 2B and can replace the steps shown in Figures 2C and 2D .

[0058] As shown in Figures 3A and 3B the further processing of the electronic elements 2 opposite the interposer layer 5 forming outcoupling elements 7 in form of plenses above each one of the electronic elements 2 does not separate the electronic elements 2 from each other but the electronic elements 2 are still connected by the common semiconductor layer of the semiconductor layer stack 9 . The electronic elements 2 are thus formed by each a light emitting pixel of a larger pixelized component / LED .

[0059] The processed electronic elements 2 on the interposer layer 5 in form of an array are then bonded to the target substrate 4 and in particular on the contact pads 8 of the target substrate 4 such that the electronic elements 2 via the through contacts 6 are in electrical contact with each one of the contact pads 8 . The resulting product according to Fig . 3B corresponds to an electronic device 1 according to some aspects of the proposed principle . The electronic device 1 can for example be used in a display or VR / AR application for pro j ecting / imaging an image into a human' s eye . 2024PF00575 15

[0060] LIST OF REFERENCES

[0061] 1 electronic device

[0062] 2 electronic element

[0063] 5 3 carrier substrate

[0064] 4 target substrate

[0065] 5 interposer layer

[0066] 6 trough contact

[0067] 7 outcoupling element0 8 contact pad

[0068] 9 semiconductor layer stack

[0069] 10 dielectric material

Claims

2024PF00575CLAIMS1. A method for transferring electronic elements (2) from a carrier substrate (3) to a target substrate (4) comprising the steps of:Providing a plurality of electronic elements (2) arranged in an array-like pattern on the carrier substrate ( ) ;Transferring at least a portion of the plurality of electronic elements (2) from the carrier substrate (3) to an interposer layer(5) comprising a plurality of through contacts (6) , such that at least one of the plurality of through contacts (6) is electrically coupled to one of the plurality of electronic elements (2) , respectively;Processing a side of the at least portion of the plurality of electronic elements (2) opposite the interposer layer (5) to provide an outcoupling structure and / or outcoupling element (7) and / or electric contact on a side of each of the electronic elements (2) opposite the interposer layer (5) ; andArranging the interposer layer (5) on the target substrate (4) comprising an integrated circuit and a plurality of contact pads (8) , such that at least one of the plurality of through contacts(6) is electrically coupled to one of the plurality of contact pads (8) , respectively.

2. The transfer method according to claim 1, wherein the step of processing a side of the at least portion of the plurality of electronic elements (2) opposite the interposer layer (5) comprises an at least partial removal of the carrier substrate (3) .

3. The transfer method according to claim 1 or 2, wherein the plurality of electronic elements (2) is manufactured on the carrier substrate ( 3 ) .

4. The transfer method according to any one of claims 1 to 3, wherein the step of processing a side of the at least portion of the plurality of electronic elements (2) opposite the interposer layer (5) comprises to provide an outcoupling structure and / or outcoupling element (7) of the carrier substrate (3) .2024PF005755. The transfer method according to any one of claims 1 to 4, wherein the target substrate (4) is a CMOS wafer.

6. The transfer method according to any one of claims 1 to 5, wherein the step of processing a side of the at least portion of the plurality of electronic elements (2) opposite the interposer layer (5) comprises to provide a common electric contact for the electronic elements (2) on a side of the electronic elements (2) opposite the interposer layer (5) .

7. The transfer method according to any one of claims 1 to 6, wherein the interposer layer (5) is of silicon.

8. The transfer method according to any one of claims 1 to 7, wherein the interposer layer (5) comprises a reflective material.

9. Transfer method according to claim 5, wherein the step of transferring at least a portion of the plurality of electronic elements (2) from the carrier substrate (3) to the interposer layer (5) comprises bonding the electronic elements (2) on the carrier substrate (3) to the interposer layer (5) .

10. Transfer method according to one of claims 1 to 9, wherein the step of arranging the interposer layer (5) on the target substrate (4) comprises bonding the interposer layer (5) on the target substrate ( 4 ) .

11. Transfer method according to one of claims 1 to 10, wherein the electronic elements have a different distance to each other on the target substrate (4) than the electronic elements (2) arranged on the carrier substrate (3) .

12. Transfer method according to one of claims 1 to 11, wherein the interposer layer (5) or at least portions of the interposer layer (5) not covered by electronic elements (2) is more resistant to chemical etching processes than the target substrate (4) .2024PF0057513. The transfer method according to any one of claims 1 to 12, wherein the interposer layer (5) is thinned before being arranged on the target substrate (4) .

14. Electronic device (1) comprising: a plurality of electronic elements (2) arranged in an arraylike pattern on an interposer layer (5) comprising a plurality of through contacts (6) , wherein at least one of the plurality of through contacts (6) is electrically coupled to one of the plurality of electronic elements (2) , respectively; an outcoupling structure and / or outcoupling element (7) and / or electric contact on a side of each of the electronic elements (2) opposite the interposer layer (5) ; and a target substrate (4) comprising an integrated circuit and a plurality of contact pads (8) ; wherein the interposer layer (5) is arranged between the target substrate (4) and the electronic elements (2) ; and wherein at least one of the plurality of through contacts (6) is electrically coupled to one of the plurality of contact pads (2) , respectively .

15. The electronic device according to claim 14, wherein the target substrate (4) is a CMOS wafer.

16. The electronic device according to claim 14 or 15, comprising a common electric contact for the electronic elements (2) on a side of the electronic elements (2) opposite the interposer layer (5) .

17. The electronic device according any one of claims 14 to 16, wherein the interposer layer (5) is of silicon.

18. The electronic device according any one of claims 14 to 17, wherein the interposer layer (5) comprises a reflective material .

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