Display panel and display apparatus

Abstract

A display panel and a display apparatus. A drive circuit layer (15) of the display panel comprises first pixel drive circuits (18) and second pixel drive circuits (19), wherein one first pixel drive circuit (18) is connected to a plurality of sub-pixels (22) of the same color, and one second pixel drive circuit (19) is connected to one sub-pixel (21); and per unit of time, the magnitude of a current flowing through a first drive transistor (T11) in the first pixel drive circuit (18) is greater than the magnitude of a current flowing through a second drive transistor (T12) in the second pixel drive circuit (19).

Description

Display panel and display device Technical Field

[0001] This application belongs to the field of display technology, specifically relating to a display panel and a display device. Background Technology

[0002] Pol-Less (PLP) technology significantly improves the light emission efficiency of a display panel by eliminating the polarizer on the light-emitting side, thereby increasing display brightness and reducing panel power consumption. However, after eliminating the polarizer, the reflectivity of the light-emitting side of the display panel remains high, severely affecting the display effect. To reduce reflectivity, PLP display panels use a full-surface black pixel define layer (BPDL) combined with a black matrix (BM) to block the metal pattern and cathode, with pixel openings only on the BDDL corresponding to the light-emitting pixels for light emission. This design results in almost zero transmittance of PLP display panels for all wavelengths of light, making it impossible to apply various light sensors to the entire device without special design.

[0003] Currently, to improve the local transmittance of PLP-type display panels, an array wiring design is typically used to form at least one light-transmitting area, and openings are made on the BPDL and BM corresponding to this area to enhance its transmittance. However, with the continuous improvement of display panel pixel resolution (PPI), the wiring space on the array substrate of high-definition panel products such as FHD and WQ is insufficient, resulting in poor improvement in the panel's local transmittance. Therefore, a solution is needed that can effectively improve local transmittance without affecting the display effect of the panel. Invention Overview

[0004] This application provides a display panel and a display device that effectively improves local light transmittance without affecting the overall display effect of the display panel.

[0005] In a first aspect, this application provides a display panel, including a first display area and a second display area, wherein the first display area is provided with at least one light-transmitting area;

[0006] The display panel includes:

[0007] The driving circuit layer includes a plurality of first pixel driving circuits located in the first display area and disposed away from the light-transmitting area, and a plurality of second pixel driving circuits located at least in the second display area; and

[0008] A light-emitting layer is located on one side of the driving circuit layer and includes a plurality of pixel units located in the first display area and the second display area. The pixel unit includes at least three sub-pixels of different colors. In the first display area, in at least two of the pixel units, at least two sub-pixels of the same color are electrically connected to the same first pixel driving circuit. In the second display area, each second pixel driving circuit is electrically connected to only one sub-pixel.

[0009] The first pixel driving circuit includes a first driving transistor, and the second pixel driving circuit includes a second driving transistor. When the display panel is in the light-emitting stage, the first driving transistor is electrically connected to the anode of the corresponding plurality of sub-pixels, and the second driving transistor is electrically connected to the anode of the corresponding sub-pixel. The current flowing through the first driving transistor per unit time is greater than the current flowing through the second driving transistor.

[0010] Secondly, this application provides a display device, including optical elements and the display panel described above, wherein the optical elements are disposed corresponding to the light-transmitting area. Attached Figure Description

[0011] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0012] Figure 1 is a schematic diagram of an exemplary wire-wound design on an array substrate.

[0013] Figure 2 is a top view of a display panel provided in an embodiment of this application.

[0014] Figure 3 is a schematic diagram of the cross-sectional structure at point M-M' in Figure 2.

[0015] Figure 4 is a schematic diagram of the cross-sectional structure at N-N' in Figure 2.

[0016] Figure 5 is a schematic diagram of the first pixel driving circuit provided in an embodiment of this application.

[0017] Figure 6 is a schematic diagram of the second pixel driving circuit provided in an embodiment of this application.

[0018] Figure 7 is a schematic diagram showing the distribution of the first pixel driving circuit and the second pixel driving circuit in the first display area and the second display area provided in the embodiments of this application.

[0019] Figure 8 is a schematic diagram showing another distribution of the first pixel driving circuit and the second pixel driving circuit in the first display area and the second display area provided in the embodiments of this application.

[0020] Figure 9 is a schematic diagram of the arrangement of sub-pixels in the first display area and the second display area provided in the embodiments of this application.

[0021] Figure 10 is a schematic diagram of the distribution of a pixel driving circuit with an 8T3C architecture provided for an embodiment of this application.

[0022] Figure 11 is a schematic diagram of the structure of the first driving transistor and the first switching transistor in the first pixel driving circuit and the second driving transistor and the second switching transistor in the second pixel driving circuit provided in the embodiments of this application.

[0023] Figure 12 is a schematic diagram of the structure of the first storage capacitor, the first boost capacitor, and the first adjustment capacitor in the first pixel driving circuit provided in the embodiments of this application, and the second storage capacitor, the second boost capacitor, and the second adjustment capacitor in the second pixel driving circuit.

[0024] Figure 13 is a schematic diagram showing the distribution of the first high-potential signal line, the second high-potential signal line, and the first reset signal line provided in an embodiment of this application.

[0025] Figure 14 is a schematic diagram showing the distribution of the second high-potential signal line and the first reset signal line provided in an embodiment of this application.

[0026] Figure 15 is a timing diagram of the first pixel driving circuit provided in the embodiment of this application during operation.

[0027] Figure 16 is a schematic diagram of the structure of a display device provided in an embodiment of this application. Embodiments of the present invention

[0028] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0029] Figure 1 illustrates an exemplary wire-wound design on an array substrate. As shown in Figure 1, high-transmittance areas 4 are reserved by wire-wound design of the horizontal traces 2 (e.g., scan lines) and vertical traces 3 (e.g., data lines or power signal lines) on the array substrate 1, thereby achieving local light transmission. This solution is highly feasible for pixel designs below 420 PPI. However, with the increase in PPI or the increasing complexity of pixel driving circuit designs (e.g., 8T driving circuit design / FIAA design / Ramless design, etc.), the trace density in the display area continues to increase, resulting in limited wire-wound space on the array substrate, making it impossible to improve the local light transmittance of the display panel through wire-wound design. Furthermore, while solving the problem of local light transmittance of the display panel, it is also necessary to ensure consistent display brightness in different areas.

[0030] To address the aforementioned technical problems, embodiments of this application provide a display panel and display device. By using the same pixel driving circuit to drive multiple sub-pixels of at least some of the same color in the display area where the high transmittance area is located (i.e., "one-drive-multiple" design), the number of pixel driving circuits in that area is reduced, thereby reducing the area occupied by the pixel driving circuits in that area. The space saved can then be used as a light-transmitting area, thus effectively solving the problem of local light transmittance of the display panel.

[0031] Meanwhile, the "one-to-many" design can lead to insufficient brightness in corresponding sub-pixels. Specifically, when a single pixel driving circuit drives multiple sub-pixels of the same color simultaneously, its current output capability is limited, causing the connected sub-pixels to fail to reach the preset high brightness value. This results in inconsistent display brightness in this area compared to other normally driven (e.g., "one-to-one" design) display areas, thus affecting the overall display effect. To address this issue, this application also optimizes the design of some film layers in the display area corresponding to the "one-to-many" pixel driving circuit, ensuring consistent display brightness across different areas of the display panel and effectively improving the overall display effect.

[0032] As shown in Figures 2 to 9, this application embodiment provides a display panel 10, which includes a first display area 11 and a second display area 12. The first display area 11 has at least one light-transmitting area 13. It is understood that the light-transmitting area 13 is used to house optical elements, and the light-transmitting area 13 has a large light transmittance, which can provide sufficient light for the optical elements and help improve the sensitivity of the optical elements.

[0033] Specifically, as shown in Figures 3 and 4, the display panel 10 includes a substrate layer 14 and a driving circuit layer 15, a light-emitting layer 16, and an encapsulation layer 17 stacked on the substrate layer 14.

[0034] In some embodiments, the display panel 10 is an OLED panel, but it is not limited thereto. This application will use an OLED panel as an example for illustration.

[0035] In some embodiments, substrate 14 includes a rigid substrate or a flexible substrate, without limitation herein. When substrate 14 is a rigid substrate, substrate 14 includes a glass substrate, but is not limited thereto. When substrate 14 is a flexible substrate, substrate 14 includes at least one polyimide (PI) layer, but is not limited thereto.

[0036] In some embodiments, the display panel 10 further includes a buffer layer (not shown) located between the substrate layer 14 and the driving circuit layer 15.

[0037] Specifically, as shown in Figures 3, 4, 7, and 8, the driving circuit layer 15 includes a plurality of first pixel driving circuits 18 located in the first display area 11 and avoiding the light-transmitting area 13, and a plurality of second pixel driving circuits 19 located at least in the second display area 12. As shown in Figures 3, 4, and 9, the light-emitting layer 16 is located on the side of the driving circuit layer 15 facing away from the substrate layer 14, and the light-emitting layer 16 includes a plurality of pixel units 26 located in the first display area 11 and the second display area 12. Each pixel unit 26 includes at least three sub-pixels of different colors. In the first display area 11, in at least two pixel units 26, at least two sub-pixels of the same color are electrically connected to the same first pixel driving circuit 18. In at least the second display area 12, each second pixel driving circuit 19 is electrically connected to only one sub-pixel.

[0038] In other words, each first pixel driving circuit 18 is connected to multiple sub-pixels with the same emission color and is used to drive these sub-pixels to emit light simultaneously; each second pixel driving circuit 19 is connected to a sub-pixel and is used to drive this sub-pixel to emit light.

[0039] For ease of description, the sub-pixels connected to the first pixel driving circuit 18 will be referred to as first-type sub-pixels 22, and the sub-pixels connected to the second pixel driving circuit 19 will be referred to as second-type sub-pixels 21. Since each sub-pixel is a light-emitting unit or light-emitting element, each first-type sub-pixel and each second-type sub-pixel is a light-emitting unit or a light-emitting element.

[0040] It is understandable that at least some of the pixel driving circuits located in the first display area 11 are designed as one-to-many, and all the pixel driving circuits located in the second display area 12 are designed as one-to-one.

[0041] For example, as shown in Figures 7 and 9, each pixel unit 26 includes a first sub-pixel 26a, a second sub-pixel 26b, and a third sub-pixel 26c, wherein the first sub-pixel 26a is a blue sub-pixel (B), the second sub-pixel 26b is a red sub-pixel (R), and the third sub-pixel 26c is a green sub-pixel (G). The first sub-pixel 26a located in the first display area 11 is a first type of sub-pixel 22, and the first sub-pixel 26a located in the second display area 12, the second sub-pixel 26b located in the first display area 11, and the third sub-pixel 26c located in the second display area 12 are second type of sub-pixels 21. In the first display area 11, each first pixel driving circuit 18 is electrically connected to two blue sub-pixels (B) in the column direction; in the second display area 12, each blue sub-pixel (B) is connected to a corresponding second pixel driving circuit 19; in both the first and second display areas 11 and 12, each red sub-pixel (R) is connected to a corresponding second pixel driving circuit 19, and each green sub-pixel (G) is connected to a corresponding second pixel driving circuit 19. Therefore, in the first display area 11, there is a blank area between two adjacent first pixel driving circuits 18 in the column direction, which is used to set the light-transmitting area 13.

[0042] Understandably, the difference between Figure 7 and Figure 8 lies in the different distribution positions of the first pixel driving circuit 18, and correspondingly, the different distribution positions of the blue sub-pixel (B) electrically connected to the first pixel driving circuit 18.

[0043] Referring to Figures 3 to 5, the first pixel driving circuit 18 includes a first driving transistor T11, the first electrode of which is connected to node A1, and the second electrode of which is connected to node B1. Referring to Figures 3 to 6, the second pixel driving circuit 19 includes a second driving transistor T12, the first electrode of which is connected to node A2, and the second electrode of which is connected to node B2.

[0044] As shown in Figures 5 and 6, when the display panel is in the light-emitting stage, the first electrode of the first driving transistor T11 is electrically connected to the first high-potential signal terminal VDD1, and the second electrode of the first driving transistor T11 is electrically connected to the anode of the corresponding plurality of first-type sub-pixels 22. At the same time, the first electrode of the second driving transistor T12 is electrically connected to the second high-potential signal terminal VDD2, and the second electrode of the second driving transistor T12 is electrically connected to the anode of the corresponding second-type sub-pixel 21. Moreover, the current flowing through the first driving transistor T11 per unit time is greater than the current flowing through the second driving transistor T12.

[0045] Understandably, by increasing the amount of current flowing through the first driving transistor T11 per unit time, the current output capability of the first pixel driving circuit 18 can be improved, which is beneficial to improving the light emission brightness of the multiple sub-pixels connected to it, so that the display brightness of the first display area 11 and the second display area 12 tends to be consistent.

[0046] In one specific embodiment, as shown in FIG11, the first driving transistor T11 includes a first active portion 23, and the second driving transistor T12 includes a second active portion 24; the ratio of the channel width W1 to the channel length L1 of the first active portion 23 is greater than the ratio of the channel width W2 to the channel length L2 of the second active portion 24, such that the current flowing through the first driving transistor T11 per unit time is greater than the current flowing through the second driving transistor T12.

[0047] Understandably, the embodiments of this application differentiate the channel width to channel length ratio of the driving transistors of the first pixel driving circuit 18 and the second pixel driving circuit 19, so that the current flowing through the first driving transistor T11 of the first pixel driving circuit 18 in the same time is greater than the current flowing through the second driving transistor T12 of the second pixel driving circuit 19. This can effectively increase the current flowing through the first driving transistor T11 when it is working, thereby effectively improving the current output capability of the first pixel driving circuit 18. This is beneficial to improving the display brightness of the multiple sub-pixels connected to the first pixel driving circuit 18, thereby making the display brightness of the first display area 11 and the second display area 12 tend to be consistent.

[0048] Specifically, the first electrode is either the source or the drain, and the second electrode is either the source or the drain, but not the first electrode. This application uses an example where the first electrode is the source and the second electrode is the drain.

[0049] Specifically, as shown in Figures 5 and 6, the gate of the first driving transistor T11 is connected to node Q1 to receive the first driving gate signal, and the gate of the second driving transistor T12 is connected to node Q2 to receive the second driving gate signal. The first driving gate signal and the second driving gate signal can be the same or different.

[0050] Specifically, as shown in Figure 5, the anode of the first type of sub-pixel 22 is connected to node C1 in the first pixel driving circuit 18, and the cathode of the first type of sub-pixel 22 is connected to the first low-potential signal terminal VSS1 to receive the first low-potential power signal. As shown in Figure 6, the anode of the second type of sub-pixel 21 is connected to node C2 in the second pixel driving circuit 19, and the cathode of the second type of sub-pixel 21 is connected to the second low-potential signal terminal VSS2 to receive the second low-potential power signal. The first low-potential power signal and the second low-potential power signal can be the same or different.

[0051] When the display panel is in the light-emitting stage, nodes C1 and B1 are turned on, allowing the current flowing through the first driving transistor T11 to reach the anode of the corresponding first type of sub-pixel 22 through nodes B1 and C1, thereby driving the first type of sub-pixel 22 to emit light. At the same time, nodes C2 and B2 are turned on, allowing the current flowing through the second driving transistor T12 to reach the anode of the corresponding second type of sub-pixel 21 through nodes B2 and C2, thereby driving the second type of sub-pixel 21 to emit light.

[0052] In some embodiments, as shown in FIG11, the channel of the first active portion 23 is arranged in a straight line, and the channel of the second active portion 24 is arranged in a bent or curved shape. This design can effectively reduce the channel length L1 of the first active portion 23 and effectively increase the channel length L2 of the second active portion 24, thereby making it easier to achieve a ratio of the channel width W1 to the channel length L1 of the first active portion 23 greater than the ratio of the channel width W2 to the channel length L2 of the second active portion 24.

[0053] Of course, in other embodiments, the ratio of the channel width W1 to the channel length L1 of the first active portion 23 can be made greater than the ratio of the channel width W2 to the channel length L2 of the second active portion 24 by increasing the channel width W1 of the first active portion 23 and / or decreasing the channel width W2 of the second active portion 24.

[0054] In one specific embodiment, the ratio of the channel width W1 to the channel length L1 of the first active part 23 is 3.5 / 12, and the ratio of the channel width W2 to the channel length L2 of the second active part 24 is 3 / 25. The units of channel width and channel length can be micrometers, but are not limited thereto.

[0055] In some embodiments, the first pixel driving circuit 18 and the second pixel driving circuit 19 have the same architecture, with only some components (e.g., transistors and / or capacitors) or wiring being differentiated. This design allows the pixel driving circuits of the first display area 11 and the second display area 12 to be formed in the same process, which helps to simplify the fabrication of the driving circuit layer 15. This application embodiment does not limit the architecture of the first pixel driving circuit 18 and the second pixel driving circuit 19; it can be a 7T (containing 7 transistors) circuit architecture or an 8T (containing 8 transistors) circuit architecture, but is not limited thereto. This application embodiment will use the 8T3C architecture as an example to specifically describe the structure of the first pixel driving circuit 18 and the second pixel driving circuit 19.

[0056] In some embodiments, as shown in FIG5, the first pixel driving circuit 18 further includes a first switching transistor T21. The first electrode of the first switching transistor T21 is connected to the first data signal terminal Data1, and the second electrode of the first switching transistor T21 is connected to the first electrode of the first driving transistor T11, for example, the two are connected at node A1. As shown in FIG6, the second pixel driving circuit 19 further includes a second switching transistor T22. The first electrode of the second switching transistor T22 is connected to the second data signal terminal Data2, and the second electrode of the second switching transistor T22 is connected to the first electrode of the second driving transistor T12, for example, the two are connected at node A2. As shown in FIG11, the first switching transistor T21 includes a third active portion 57, and the second switching transistor T22 includes a fourth active portion 58. The first driving transistor T11 and the second driving transistor T12 are both P-type thin film transistors, and the ratio of the channel width W3 to the channel length L3 of the third active portion 57 is less than the ratio of the channel width W4 to the channel length L4 of the fourth active portion 58.

[0057] Understandably, P-type thin-film transistors turn on at low potentials and turn off at high potentials. Therefore, the first driving transistor T11 and the second driving transistor T12 can be turned on when a low voltage value is applied to their driving gate terminals. In this embodiment, the channel width to channel length ratio of the switching transistors in the first pixel driving circuit 18 and the second pixel driving circuit 19 is also designed differently. This can weaken the writing capability of the first data signal terminal to the Q1 node (i.e., the gate terminal of the first driving transistor T11), thereby reducing the operating potential of the Q1 node and making the first driving transistor T11 turn on more fully, which is beneficial to further improve the current output capability of the first pixel driving circuit 18.

[0058] In some embodiments, as shown in FIG11, the differential design of the active channel width-to-length ratio of the first switching transistor T21 and the second switching transistor T22 can be achieved by reducing the channel width W3 of the third active portion 57 and / or increasing the channel length L3 of the third active portion 57.

[0059] In one specific embodiment, the ratio of the channel width W3 to the channel length L3 of the third active part 57 is 1.6 / 6, and the ratio of the channel width W4 to the channel length L4 of the fourth active part 58 is 1.8 / 4. The units of channel width and channel length can be micrometers, but are not limited thereto.

[0060] In some embodiments, as shown in FIG5, the first pixel driving circuit 18 further includes a first storage capacitor C11 and a first boost capacitor C21. One end of the first storage capacitor C11 is connected to the first high-potential signal terminal VDD1, and the other end is connected to the gate of the first driving transistor T11. The first end of the first boost capacitor C21 is connected to the gate of the first switching transistor T21, and the other end is connected to the gate of the first driving transistor T11. As shown in FIG6, the second pixel driving circuit 19 further includes a second storage capacitor C12 and a second boost capacitor C22. One end of the second storage capacitor C12 is connected to the second high-potential signal terminal VDD2, and the other end is connected to the gate of the second driving transistor T12. The first end of the second boost capacitor C22 is connected to the gate of the second switching transistor T22, and the other end is connected to the gate of the second driving transistor T12. The first switching transistor T21 and the second switching transistor T22 are both P-type thin-film transistors. The capacitance value of the first storage capacitor C11 is greater than the capacitance value of the second storage capacitor C12, and the capacitance value of the first boost capacitor C21 is less than the capacitance value of the second boost capacitor C22.

[0061] Specifically, the gate of the first switching transistor T21 is connected to the first scan control signal terminal Pscan11, and the gate of the second switching transistor T22 is connected to the second scan control signal terminal Pscan12. Since both the first switching transistor T21 and the second switching transistor T22 are P-type thin-film transistors, when the first scan control signal terminal Pscan11 and the second scan control signal terminal Pscan12 provide a low-level scan signal, the first switching transistor T21 and the second switching transistor T22 are turned on, and when the first scan control signal terminal Pscan11 and the second scan control signal terminal Pscan12 provide a high-level scan signal, the first switching transistor T21 and the second switching transistor T22 are turned off.

[0062] Understandably, compared to the second pixel driving circuit 19, the storage capacitor in the first pixel driving circuit 18 is increased, and the boost capacitor in the first pixel driving circuit 18 is decreased. By increasing the first storage capacitor C11 in the first pixel driving circuit 18, the duration of the operating potential of node Q1 is increased, which helps to increase the current flowing through the first driving transistor T11 during operation, thereby further improving the current output capability of the first pixel driving circuit 18. By decreasing the first boost capacitor C21, the pull-up coupling amplitude of the gate control signal of the first switching transistor T21 to the potential of node Q1 is reduced during transition, which helps to lower the operating potential of node Q1, allowing the first driving transistor T11 to be turned on more fully, which further helps to improve the current output capability of the first pixel driving circuit 18.

[0063] It should be noted that the aforementioned differential design of the ratio of channel width to channel length of the active part of the driving transistor and the differential design of the capacitance values ​​of the storage capacitor and the boost capacitor can be implemented selectively or simultaneously. Their purpose is to improve the current output capability of the first pixel driving circuit 18.

[0064] In some embodiments, as shown in FIG5, the first pixel driving circuit 18 further includes a first compensation transistor T31 and a first adjustment capacitor C31. The first electrode of the first compensation transistor T31 is connected to the second electrode of the first driving transistor T11, and the second electrode of the first compensation transistor T31 is connected to the gate of the first driving transistor T11. One end of the first adjustment capacitor C31 is connected to the gate of the first driving transistor T11, and the other end is connected to the gate of the first compensation transistor T31. As shown in FIG6, the second pixel driving circuit 19 further includes a second compensation transistor T32 and a second adjustment capacitor C32. The first electrode of the second compensation transistor T32 is connected to the second electrode of the second driving transistor T12, and the second electrode of the second compensation transistor T32 is connected to the gate of the second driving transistor T12. One end of the second adjustment capacitor C32 is connected to the gate of the second driving transistor T12, and the other end is connected to the gate of the second compensation transistor T32. Both the first compensation transistor T31 and the second compensation transistor T32 are N-type thin-film transistors, and the capacitance value of the first adjustment capacitor C31 is greater than the capacitance value of the second adjustment capacitor C32.

[0065] Specifically, the gate of the first compensation transistor T31 is connected to the third scan control signal terminal Nscan11, and the gate of the second compensation transistor T32 is connected to the fourth scan control signal terminal Nscan12. Since both the first compensation transistor T31 and the second compensation transistor T32 are N-type thin-film transistors, when the third scan control signal terminal Nscan11 and the fourth scan control signal terminal Nscan12 provide a high-level scan signal, the first compensation transistor T31 and the second compensation transistor T32 are turned on, and when the third scan control signal terminal Nscan11 and the fourth scan control signal terminal Nscan12 provide a low-level scan signal, the first compensation transistor T31 and the second compensation transistor T32 are turned off.

[0066] Specifically, the first compensation transistor T31 and the second compensation transistor T32 are in the on state during the data signal writing phase. On one hand, the first compensation transistor T31 is used to compensate the threshold voltage of the first driving transistor T11, and the second compensation transistor T32 is used to compensate the threshold voltage of the second driving transistor T12; on the other hand, the first compensation transistor T31 is used to provide a path for data writing to the first pixel driving circuit 18, and the second compensation transistor T32 is used to provide a path for data writing to the second pixel driving circuit 19.

[0067] Specifically, a first regulating capacitor C31 is provided between the gate of the first compensation transistor T31 and the gate of the first driving transistor T11, so that when the gate of the first compensation transistor T31 transitions from a high potential to a low potential, it has a pull-down coupling effect on the potential of node Q1; a second regulating capacitor C32 is provided between the gate of the second compensation transistor T32 and the gate of the second driving transistor T12, so that when the gate of the second compensation transistor T32 transitions from a high potential to a low potential, it has a pull-down coupling effect on the potential of node Q2. This design helps to reduce the operating potential of nodes Q1 and Q2, thereby facilitating the turn-on of the corresponding driving transistors.

[0068] Understandably, the regulating capacitor in the first pixel driving circuit 18 is larger than that in the second pixel driving circuit 19. By increasing the first regulating capacitor C31, the coupling amplitude of the gate control signal of the first compensation transistor T31 to the potential of node Q1 can be increased, thereby further reducing the operating potential of node Q1. This allows the first driving transistor T11 to be turned on more fully, which is beneficial to further improving the current output capability of the first pixel driving circuit 18.

[0069] It should be noted that the differentiated design of the capacitance values ​​of the first regulating capacitor C31 in the first pixel driving circuit 18 and the second regulating capacitor C32 in the second pixel driving circuit 19 can be implemented separately or simultaneously with the other schemes mentioned above. The purpose of both is to improve the current output capability of the first pixel driving circuit 18.

[0070] In one specific embodiment, the capacitance value of each capacitor is adjusted by adjusting the electrode coverage area of ​​each capacitor. For example, as shown in FIG12, the area of ​​the orthographic projection of the first storage capacitor C11 in the thickness direction of the display panel 10 is larger than the area of ​​the orthographic projection of the second storage capacitor C12 in the thickness direction of the display panel 10, so that the capacitance value of the first storage capacitor C11 is greater than the capacitance value of the second storage capacitor C12. The area of ​​the orthographic projection of the first boost capacitor C21 in the thickness direction of the display panel 10 is smaller than the area of ​​the orthographic projection of the second boost capacitor C22 in the thickness direction of the display panel 10, so that the capacitance value of the first boost capacitor C21 is smaller than the capacitance value of the second boost capacitor C22. The area of ​​the orthographic projection of the first adjusting capacitor C31 in the thickness direction of the display panel 10 is larger than the area of ​​the orthographic projection of the second adjusting capacitor C32 in the thickness direction of the display panel 10, so that the capacitance value of the first adjusting capacitor C31 is greater than the capacitance value of the second adjusting capacitor C32. Of course, in other embodiments, the capacitance value can also be adjusted by adjusting the spacing between the two electrodes of the capacitor.

[0071] In some embodiments, when the display panel 10 is in the light-emitting stage, the power supply voltage value connected to the first high-potential signal terminal VDD1 is greater than the power supply voltage value connected to the second high-potential signal terminal VDD2, and the power supply voltage value connected to the second high-potential signal terminal VDD2 is greater than 0. By increasing the power supply voltage value connected to the first high-potential signal terminal VDD1, it is beneficial to further improve the driving capability of the first pixel driving circuit 18.

[0072] It should be noted that the differentiated design of the power supply voltage values ​​connected to the first high-potential signal terminal VDD1 and the second high-potential signal terminal VDD2 can be implemented separately or simultaneously with the other schemes mentioned above. The purpose is to improve the current output capability of the first pixel driving circuit 18.

[0073] In some embodiments, as shown in FIG13, the driving circuit layer 15 further includes a first high-potential signal line LVDD1 and a second high-potential signal line LVDD2 spaced apart from each other. The first high-potential signal line LVDD1 is connected to the first high-potential signal terminal VDD1, and the second high-potential signal line LVDD2 is connected to the second high-potential signal terminal VDD2. When the display panel 10 is in the light-emitting stage, the first high-potential signal line LVDD1 provides a first high-potential power supply voltage to the first high-potential signal terminal VDD1, and the second high-potential signal line LVDD2 provides a second high-potential power supply voltage to the second high-potential signal terminal VDD2, wherein the value of the first high-potential power supply voltage is greater than the value of the second high-potential power supply voltage.

[0074] In one specific embodiment, as shown in FIG13, the first high-potential signal line LVDD1 and the second high-potential signal line LVDD2 extend in the same direction and are arranged in the same layer.

[0075] This design allows the high-potential power signals of the first pixel driving circuit 18 and the second pixel driving circuit 19 to be provided independently through two different high-potential signal lines, thereby providing different high-potential power signals to the first pixel driving circuit 18 and the second pixel driving circuit 19, which is beneficial to achieving consistent display brightness in the first display area 11 and the second display area 12.

[0076] In some embodiments, as shown in Figures 5, 6, and 14, the first pixel driving circuit 18 further includes a first reset transistor T81, the second pixel driving circuit 19 further includes a second reset transistor T82, and the driving circuit layer 15 further includes a second high-potential signal line LVDD2, a first reset signal line 25, and a second reset signal line (not shown in the figures). The first electrode of the first reset transistor T81 is connected to the first reset signal line 25, and the second electrode of the first reset transistor T81 is connected to the first electrode of the first driving transistor T11. The first electrode of the second reset transistor T82 is connected to the second reset signal line, and the second electrode of the second reset transistor T82 is connected to the first electrode of the second driving transistor T12. The first reset signal line 25 is also connected to the first high-potential signal terminal VDD1; the second high-potential signal line LVDD2 is connected to the second high-potential signal terminal VDD2.

[0077] When the display panel 10 is in the light-emitting stage, the first reset signal line 25 provides a first high-potential power supply voltage to the first high-potential signal terminal VDD1, and the second high-potential signal line LVDD2 provides a second high-potential power supply voltage to the second high-potential signal terminal VDD2, and the value of the first high-potential power supply voltage is greater than the value of the second high-potential power supply voltage.

[0078] Understandably, in this embodiment, it is not necessary to set an additional high-potential signal line for the first pixel driving circuit 18. Instead, the first reset signal line 25 is multiplexed as the high-potential signal line of the first pixel driving circuit 18, which can further save pixel space and help to further increase the area of ​​the light-transmitting area 13, thereby further improving the light transmittance of the first display area 11.

[0079] In some embodiments, the first reset transistor T81 and the second reset transistor T82 are both P-type thin-film transistors. The gate of the first reset transistor T81 is connected to the fifth scan control signal terminal Pscan21, and the gate of the second reset transistor T82 is connected to the sixth scan control signal terminal Pscan22.

[0080] In some embodiments, as shown in FIG5, the first pixel driving circuit 18 further includes a third reset transistor T41, a fourth reset transistor T71, a first light-emitting control transistor T51, and a second light-emitting control transistor T61. As shown in FIG6, the second pixel driving circuit 19 further includes a fifth reset transistor T42, a sixth reset transistor T72, a third light-emitting control transistor T52, and a fourth light-emitting control transistor T62.

[0081] As shown in Figure 5, the first electrode of the third reset transistor T41 is connected to the first reset signal terminal Vi_11, and the second electrode of the third reset transistor T41 is connected to node Q1. The first electrode of the fourth reset transistor T71 is connected to the second reset signal terminal Vi_21, and the second electrode of the fourth reset transistor T71 is connected to node C1. The first electrode of the first light-emitting control transistor T51 is connected to the first high-potential signal terminal VDD1, and the second electrode of the first light-emitting control transistor T51 is connected to node A1. The first electrode of the first driving transistor T11 is also connected to node A1. The first electrode of the second light-emitting control transistor T61 and the second electrode of the first driving transistor T11 are both connected to node B1, and the second electrode of the second light-emitting control transistor T61 is connected to node C1.

[0082] As shown in Figure 6, the first electrode of the fifth reset transistor T42 is connected to the third reset signal terminal Vi_12, and the second electrode of the fifth reset transistor T42 is connected to node Q2. The first electrode of the sixth reset transistor T72 is connected to the fourth reset signal terminal Vi_22, and the second electrode of the sixth reset transistor T72 is connected to node C2. The first electrode of the third light-emitting control transistor T52 is connected to the second high-potential signal terminal VDD2, and the second electrode of the third light-emitting control transistor T52 is connected to node A2. The first electrode of the second driving transistor T12 is also connected to node A2. The first electrode of the fourth light-emitting control transistor T62 and the second electrode of the second driving transistor T12 are both connected to node B2, and the second electrode of the fourth light-emitting control transistor T62 is connected to node C2.

[0083] In some embodiments, the third reset transistor T41 and the fifth reset transistor T42 are both N-type thin-film transistors, and the fourth reset transistor T71, the first light-emitting control transistor T51, the second light-emitting control transistor T61, the sixth reset transistor T72, the third light-emitting control transistor T52, and the fourth light-emitting control transistor T62 are all P-type thin-film transistors.

[0084] The gate of the third reset transistor T41 is connected to the seventh scan control signal terminal Nscan21, the gate of the fourth reset transistor T71 is connected to the fifth scan control signal terminal Pscan21, the gate of the fifth reset transistor T42 is connected to the eighth scan control signal terminal Nscan22, the gate of the sixth reset transistor T72 is connected to the sixth scan control signal terminal Pscan22, the gate of the first light-emitting control transistor T51 and the gate of the second light-emitting control transistor T61 are both connected to the first light-emitting control signal terminal EM1, and the gates of the third light-emitting control transistor T52 and the fourth light-emitting control transistor T62 are both connected to the second light-emitting control signal terminal EM2.

[0085] The first electrode of the first reset transistor T81 is connected to the fifth reset signal terminal Vi_31, and the first reset signal line 25 inputs an electrical signal to the first reset transistor T81 through the fifth reset signal terminal Vi_31; the first electrode of the second reset transistor T82 is connected to the sixth reset signal terminal Vi_32, and the second reset signal line inputs an electrical signal to the second reset transistor T82 through the sixth reset signal terminal Vi_32.

[0086] As can be seen from the above, the architecture of the first pixel driving circuit 18 and the second pixel driving circuit 19 is the same. In this embodiment, the active channel width-to-length ratio of the driving thin film transistor and / or the switching thin film transistor in the first pixel driving circuit 18 and the second pixel driving circuit 19 can be set differently. The capacitance values ​​of the three capacitors in the first pixel driving circuit 18 and the second pixel driving circuit 19 can also be designed differently. The voltage value of the high potential signal terminal can also be designed differently. The purpose of the differentiated design is to improve the driving capability of the "one-drive-multiple" pixel driving circuit, thereby improving the consistency of the display brightness of the first display area 11 and the second display area 12.

[0087] Figure 10 is a schematic diagram of the wiring distribution of an exemplary 8T3C architecture pixel driving circuit. The architecture of the first pixel driving circuit 18 and the second pixel driving circuit 19 in this embodiment is the same as that shown in Figure 10. Specifically, in Figure 10, T1 is a driving transistor, T2 is a switching transistor, T3 is a compensation transistor, T4 is a second reset transistor, T5 is a first light-emitting control transistor, T6 is a second light-emitting control transistor, T7 is a third reset transistor, T8 is a first reset transistor, C1 is a storage capacitor, C2 is a boost capacitor, and C3 is an adjustment capacitor.

[0088] It should be noted that the wiring diagram of the second pixel driving circuit 19 in this embodiment can be referenced to FIG. 10, but is not limited thereto. This embodiment uses the pixel driving circuit shown in FIG. 10 as the second pixel driving circuit 19 as an example to describe the differences between the first pixel driving circuit 18 and the second pixel driving circuit 19.

[0089] As shown in Figure 15, the operation of the first pixel driving circuit 18 of the 8T3C architecture described above sequentially includes a first reset stage, a data writing and compensation stage, a second reset stage, and a light emission stage. The first reset stage includes stages 1, 1-1, 2, and 2-1 in the timing diagram; the data writing and compensation stage is stage 3 in the timing diagram; the second reset stage is stage 4 in the timing diagram; and the light emission stage is stage 5 in the timing diagram.

[0090] In the first reset phase, stage 1, the fifth scan control signal terminal Pscan21 is connected to a low-level signal, controlling the first reset transistor T81 and the fourth reset transistor T71 to turn on. This resets nodes A1 and B1 via the fifth reset signal terminal Vi_31, and node C1 via the second reset signal terminal Vi_21. In stage 1-1 of the first reset phase, the third scan control signal terminal Nscan11 is connected to a high-level signal, and the fifth scan control signal terminal Pscan21 is connected to a low-level signal, controlling the first compensation transistor T31 to turn on. This resets node Q1 via the fifth reset signal terminal Vi_31. In stage 2 of the first reset phase, the seventh scan control signal terminal Nscan21 is connected to a high-level signal, controlling the third reset transistor T41 to turn on, resetting node Q1. In stage 2-1 of the first reset phase, both the third scan control signal terminal Nscan11 and the seventh scan control signal terminal Nscan21 are connected to high-level signals, controlling the first compensation transistor T31 and the third reset transistor T41 to turn on, resetting nodes Q1 and B1.

[0091] During the data writing and compensation phase, the third scan control signal terminal Nscan11 is connected to a high-potential signal, and the first scan control signal terminal Pscan11 is connected to a low-potential signal, controlling the first driving transistor T11, the first switching transistor T21 and the first compensation transistor T31 to turn on, and the data signal is written to node Q1.

[0092] During the second reset phase, the fifth scan control signal terminal Pscan21 is connected to a low-potential signal, which controls the first reset transistor T81 and the fourth reset transistor T71 to turn on. The fifth reset signal terminal Vi_31 resets nodes A1 and B1, and the second reset signal terminal Vi_21 resets node C1.

[0093] During the light emission stage, the first light emission control signal terminal EM1 is connected to a low-potential signal, which controls the first light emission control transistor T51 and the second light emission control transistor T61 to turn on. The first high-potential signal flows sequentially through nodes A1, B1 and C1 to the anode of the corresponding sub-pixel and drives the sub-pixel to emit light.

[0094] It is understandable that the structure of the second pixel driving circuit 19 is the same as that of the first pixel driving circuit 18, so their working processes are the same. The working process of the second pixel driving circuit 19 can be referred to the working process of the first pixel driving circuit 18 described above, and will not be repeated here.

[0095] In some embodiments, as shown in FIG3 and FIG4, the driving circuit layer 15 includes a first semiconductor layer 27, a first gate insulating layer 28, a first gate layer 29, a second gate insulating layer 30, a second gate layer 31, a first interlayer insulating layer 32, a second semiconductor layer 33, a third gate insulating layer 34, a third gate layer 35, a second interlayer insulating layer 36, a first source / drain electrode layer 37, a first organic planarization layer 38, a second source / drain electrode layer 39, a second planarization layer 40, and a third planarization layer 41 stacked on the substrate layer 14.

[0096] The first electrode and the second electrode mentioned above can be located in the first source-drain electrode layer 37, the gate can be located in any one of the first gate layer 29, the second gate layer 31 and the third gate layer 35, and the active part is located in the first semiconductor layer 27 or the second semiconductor layer 33.

[0097] In some embodiments, the first driving transistor T11 is a dual-gate low-temperature polycrystalline silicon thin-film transistor, which includes an active portion 27a located in the first semiconductor layer 27, a first gate 29a located in the first gate layer 29, a second gate 31a located in the second gate layer 31, and a source and a drain located in the first source-drain electrode layer 37. The first compensation thin-film transistor T31 is a metal-oxide-slim thin-film transistor, which includes an active portion located in the second semiconductor layer 33, a third gate 31b located in the second gate layer 31, a fourth gate 35a located in the third gate layer 35, and a source and a drain located in the first source-drain electrode layer 37.

[0098] In some embodiments, the material of the first semiconductor layer 27 is polysilicon, and the material of the second semiconductor layer 33 includes indium gallium zinc oxide (IGZO).

[0099] In some embodiments, the second driving transistor T12 is disposed on the same layer as the first driving transistor T11. For example, the active portion, gate, source, and drain of the second driving transistor T12 are respectively located on the same film layer as the active portion, gate, source, and drain of the first driving transistor T11. Similarly, the second compensation thin-film transistor T32 is also disposed on the same layer as the first compensation thin-film transistor T31.

[0100] In some embodiments, the light-emitting layer 16 is located on the third planarization layer 41.

[0101] In some embodiments, as shown in FIG3, the light-emitting layer 16 includes a pixel defining layer 42 located in the first display area 11 and the second display area 12. The pixel defining layer 42 is provided with a plurality of pixel openings located in the first display area 11 and the second display area 12, and a plurality of first light-transmitting openings 44 located in the first display area 11. Specifically, depending on the type of pixel driving circuit, the pixel openings can be divided into a plurality of first pixel openings 43 located in the first display area 11 and a plurality of second pixel openings 45 located in the second display area 12. First type sub-pixels 22 are located in the first pixel openings 43, and second type sub-pixels 21 are located in the second type sub-pixels 21. The first light-transmitting openings 44 are aligned with the light-transmitting area 13. The first type sub-pixels 22 include a first type anode block 46 exposed at least in the first pixel openings 43. The first type anode blocks 46 of the plurality of first type sub-pixels 22 electrically connected to the same first pixel driving circuit 18 are arranged in the same layer and interconnected. The second type of sub-pixel 21 includes a second type of anode block 47 exposed in the second pixel opening 45. The second type of anode blocks 47 of a plurality of second type sub-pixels 21 electrically connected to different second pixel driving circuits 19 are spaced apart from each other.

[0102] When the display panel 10 is in the light-emitting stage, the first driving transistor T11 is electrically connected to the first anode block 46 of the corresponding plurality of first type sub-pixels 22, and the second driving transistor T12 is electrically connected to the second anode block 47 of the corresponding second type sub-pixel 21.

[0103] In some embodiments, the sub-pixels in the light-emitting layer 16 include OLED devices, but are not limited thereto. This application embodiment uses OLED devices as an example for illustration; in this case, each sub-pixel includes an anode, a light-emitting functional layer, and a cathode. Depending on the material of the light-emitting functional layer, the sub-pixels emit different colors of light.

[0104] In some embodiments, the display panel 10 further includes a color filter layer 48 located on the side of the light-emitting layer 16 opposite to the driving circuit layer 15. The color filter layer 48 includes a light-shielding layer 49 and a color resist layer 50. The light-shielding layer 49 has a light-emitting opening aligned with a pixel opening and a second light-transmitting opening 51 aligned with a first light-transmitting opening 44. Specifically, the light-emitting opening can be divided into a first light-emitting opening aligned with a first pixel opening 43 and a second light-emitting opening aligned with a second pixel opening 45. The color resist layer 50 includes a first color resist unit 50a located in the first pixel opening 43 and a second color resist unit 50b located in the second pixel opening 45.

[0105] Understandably, the color of each color resist unit is the same as the color of the sub-pixel in the corresponding pixel aperture.

[0106] Among multiple color resist units of the same color, the thickness of the color resist unit corresponding to the sub-pixel electrically connected to the first pixel driving circuit 18 is less than the thickness of the color resist unit corresponding to the sub-pixel electrically connected to the second pixel driving circuit 19.

[0107] For example, when the first color resist unit 50a and the second color resist unit 50b have the same color, the thickness of the first color resist unit 50a, which is provided corresponding to the first type of sub-pixel 22, is less than the thickness of the second color resist unit 50b, which is provided corresponding to the second type of sub-pixel 21.

[0108] It is understood that the present application embodiment uses a color filter layer 48 instead of the existing polarizer. That is to say, the display panel 10 provided in the present application embodiment is a PLP type display panel 10. This design can significantly improve the light emission efficiency of the display panel 10, thereby improving the display brightness of the display panel 10, and can reduce the power consumption of the display panel 10.

[0109] In some embodiments, the pixel defining layer 42 in the light-emitting layer 16 is made of a light-shielding material; in this case, the pixel defining layer 42 can be referred to as a black pixel defining layer (BPDL). The pixel defining layer 42 in the light-emitting layer 16 and the light-shielding layer 49 in the color filter layer 48 cooperate to block the first pixel driving circuit 18 and the second pixel driving circuit 19, allowing light to be emitted only at the pixel opening and transmitted through the light-transmitting opening. This design can improve the light emission efficiency of the display panel 10 while reducing reflectivity and increasing local transmittance.

[0110] In some embodiments, the encapsulation layer 17 is disposed between the light-emitting layer 16 and the color filter layer 48 to protect the light-emitting layer 16.

[0111] In some embodiments, as shown in FIG9, in the first display area 11 and the second display area 12, a plurality of pixel units 26 are arranged in multiple rows and columns in the row direction and the column direction, and the row direction and the column direction are perpendicular to each other. Each pixel unit 26 includes a first sub-pixel 26a, a second sub-pixel 26b and a third sub-pixel 26c of different colors; the light-transmitting area 13 is located between two adjacent pixel units 26.

[0112] In the first display area 11 and the second display area 12, multiple first sub-pixels 26a are arranged in multiple rows and columns in both row and column directions, multiple second sub-pixels 26b are arranged in multiple rows and columns in both row and column directions, and multiple third sub-pixels 26c are arranged in multiple rows and columns in both row and column directions. Between any two adjacent rows of first sub-pixels 26a, there is a row of second sub-pixels 26b and a row of third sub-pixels 26c; any row of first sub-pixels 26a and the adjacent row of second sub-pixels 26b are staggered, and any row of second sub-pixels 26b and the adjacent row of third sub-pixels 26c are arranged in a one-to-one correspondence.

[0113] In the first display area 11, at least two sub-pixels of the same color are electrically connected to the same first pixel driving circuit 18 in the column direction or row direction.

[0114] Understandably, any color subpixel located in the first display area 11 can adopt a "one-to-many" design. Of course, only some color subpixels can adopt a "one-to-many" design.

[0115] In some embodiments, the first sub-pixel 26a includes any one of a red sub-pixel (R), a green sub-pixel (G), and a blue sub-pixel (B), the second sub-pixel 26b includes any one of a red sub-pixel (R), a green sub-pixel (G), and a blue sub-pixel (B) that is different from the first sub-pixel 26a, and the third sub-pixel 26c includes any one of a red sub-pixel (R), a green sub-pixel (G), and a blue sub-pixel (B) that is different from the first sub-pixel 26a and the second sub-pixel 26b.

[0116] In one specific embodiment, the first sub-pixel 26a is a blue sub-pixel (B), the second sub-pixel 26b is a red sub-pixel (R), and the third sub-pixel 26c is a green sub-pixel (G). Below each row of blue sub-pixels (B) are a row of red sub-pixels (R) and a row of green sub-pixels (G). In the column direction, each row of red sub-pixels (R) corresponds one-to-one with the adjacent row of green sub-pixels (G), and each row of red sub-pixels (R) and the adjacent row of blue sub-pixels (B) are staggered. Each row of blue sub-pixels (B), together with the row of red sub-pixels (R) and the row of green sub-pixels (G) below it, constitutes a row of pixel units 26. Each pixel unit 26 includes blue sub-pixels (B), red sub-pixels (R), and green sub-pixels (G) arranged in a triangle.

[0117] In one specific embodiment, any two adjacent red sub-pixels (R) in the row are symmetrically arranged about the axis of symmetry L extending along the column direction, and the blue sub-pixels (B) adjacent to these two red sub-pixels (R) are located on the axis of symmetry L.

[0118] The following explanation will take the first sub-pixel 26a in the first display area 11 as an example of adopting a "one-drive-multiple" design.

[0119] In some embodiments, in the first display area 11, at least two adjacent first sub-pixels 26a are electrically connected to the same first pixel driving circuit 18 in the column direction. A second pixel driving circuit 19 is also located in the first display area 11 and is disposed away from the light-transmitting area 13. In the first display area 11, a plurality of second sub-pixels 26b and a plurality of third sub-pixels 26c are electrically connected to a plurality of second pixel driving circuits 19 in a one-to-one correspondence. In this embodiment, only the first sub-pixel 26a adopts a "one-to-many" design.

[0120] In one specific embodiment, in the first display area 11, in any column of first sub-pixels 26a, at least two adjacent first sub-pixels 26a constitute a first sub-pixel group 20, and multiple first sub-pixels 26a in each first sub-pixel group 20 are electrically connected to the same first pixel driving circuit 18.

[0121] Specifically, each column of first sub-pixels 26a constitutes multiple first sub-pixel groups 20, and the multiple first sub-pixel groups 20 located in adjacent columns are set to correspond to each other or to be staggered.

[0122] In the column direction, a light-transmitting area 13 is provided between every two adjacent first sub-pixel groups 20. Of course, it is also possible to provide a light-transmitting area 13 only between partially adjacent two first sub-pixel groups 20.

[0123] In this embodiment of the application, in order to improve the light transmittance, a light-transmitting area 13 is provided between each two adjacent first sub-pixel groups 20, and multiple light-transmitting areas 13 are arranged in multiple columns. The multiple light-transmitting areas 13 located in adjacent columns are arranged correspondingly to each other or staggered to each other.

[0124] Understandably, since the subpixels in the same first subpixel group 20 are driven by the same first pixel driving circuit 18, the number of pixel driving circuits in the first display area 11 is greatly reduced, thereby significantly reducing the coverage area of ​​the driving circuits. This allows the pixel driving circuits in the first display area 11 to easily avoid the light-transmitting area 13. Therefore, the light-transmitting area 13 can be set in the area between two adjacent first subpixel groups 20, achieving local high light transmittance while providing sufficient space for the pixel driving circuits. At this time, the first light-transmitting opening 44 on the pixel limiting layer 42 and the second light-transmitting opening 51 on the light-shielding layer 49 can be aligned and set between two adjacent first subpixel groups 20, thereby forming the light-transmitting area 13.

[0125] In some embodiments, the first sub-pixel 26a located in the first display area 11 and the second display area 12 includes a first anode block 59a. The display panel 10 also includes a plurality of first connection electrodes 52a and a plurality of first connection holes 53a located in the first display area 11, and a plurality of second connection electrodes 52b and a plurality of second connection holes 53b located in the second display area 12. The first connection electrodes 52a and the second connection electrodes 52b are disposed in the same layer as the first anode block 59a, and both the first connection electrodes 52a and the second connection electrodes 52b extend along the column direction.

[0126] The first connecting electrode 52a is located between any two adjacent first anode blocks 59a in the same first sub-pixel group 20, and the two ends of the first connecting electrode 52a are respectively connected to the two adjacent first anode blocks 59a; a plurality of first connecting holes 53a are provided in a one-to-one correspondence with a plurality of first sub-pixel groups, and the first connecting hole 53a is connected to one of the first connecting electrodes 52a in the corresponding first sub-pixel group, and the first pixel driving circuit 18 is connected to the corresponding first connecting electrode 52a through the first connecting hole 53a, thereby realizing electrical connection with the corresponding first anode block 59a.

[0127] Each first anode block 59a located in the second display area 12 is provided with a second connecting electrode 52b and a second connecting hole 53b on its periphery. One end of the second connecting electrode 52b is connected to the corresponding first anode block 59a, and the other end is connected to the corresponding second connecting hole 53b. A second pixel driving circuit 19 is electrically connected to the corresponding second connecting electrode 52b through the second connecting hole 53b, thereby realizing electrical connection with the corresponding first anode block 59a.

[0128] In one specific embodiment, the first sub-pixel group 20 includes two first sub-pixels 26a arranged adjacently in the column direction. A first connecting electrode 52a is located between the two first sub-pixels 26a in the same first sub-pixel group 20. A first connecting hole 53a is located between the two first sub-pixels 26a in the same first sub-pixel group 20 and is connected to the first connecting electrode 52a. In the first display area 11, a plurality of first connecting holes 53a are arranged in an array in both the row and column directions. Any two adjacent rows of first connecting holes 53a are arranged in a one-to-one correspondence in the column direction, or any two adjacent rows of first connecting holes 53a are arranged alternately in the column direction. In the second display area 12, a plurality of second connecting holes 53b are arranged in an array in both the row and column directions, and any two adjacent rows of second connecting holes 53b are arranged in a one-to-one correspondence in the column direction. Each row of first connecting holes 53a and each row of second connecting holes 53b are arranged in the same row direction.

[0129] In some embodiments, the second sub-pixel 26b located in the first display area 11 and the second display area 12 includes a second anode block 59b, and the third sub-pixel 26c located in the first display area 11 and the second display area 12 includes a third anode block 59c. The display panel 10 also includes a plurality of third connecting electrodes 52c, a plurality of fourth connecting electrodes 52d, a plurality of third connecting holes 53c, and a plurality of fourth connecting holes 53d. Each second anode block 59b has a third connecting electrode 52c and a third connecting hole 53c on its periphery, and each third anode block 59c has a fourth connecting electrode 52d and a fourth connecting hole 53d on its periphery.

[0130] One end of the third connecting electrode 52c is connected to the corresponding second anode block 59b, and the other end is connected to the corresponding third connecting hole 53c. A second pixel driving circuit 19 is electrically connected to the corresponding third connecting electrode 52c through the third connecting hole 53c, thereby achieving electrical connection with the corresponding second anode block 59b. One end of the fourth connecting electrode 52d is connected to the corresponding third anode block 59c, and the other end is connected to the corresponding fourth connecting hole 53d. A second pixel driving circuit 19 is electrically connected to the corresponding fourth connecting electrode 52d through the fourth connecting hole 53d, thereby achieving electrical connection with the corresponding third anode block 59c.

[0131] In one specific embodiment, the third connecting electrode 52c and the fourth connecting electrode 52d are arranged in parallel, and the angle between the third connecting electrode 52c and the column direction is greater than 0 and less than 90°; the third connecting hole 53c and the fourth connecting hole 53d, which are respectively provided corresponding to the second sub-pixel 26b and the third sub-pixel 26c in the same pixel unit 26, are arranged in the same row direction.

[0132] In some embodiments, in the first display area 11, each row of first connecting holes 53a is arranged in the same row as each row of third connecting holes 53c and fourth connecting holes 53d. In the second display area 12, second connecting holes 53b, third connecting holes 53c, and fourth connecting holes 53d, which are respectively provided corresponding to the first sub-pixel 26a, second sub-pixel 26b, and third sub-pixel 26c in the same pixel unit 26, are arranged in the same row.

[0133] In some embodiments, the first display area 11 can be divided into a wiring area 11a and a non-wiring area 11b according to the distribution of the driving circuit layer. The orthographic projection of the light-transmitting area 13 in the thickness direction of the display panel 10 is located in the orthographic projection of the non-wiring area 11b in the thickness direction of the display panel 10. The first pixel driving circuit 18 and the second pixel driving circuit 19 located in the first display area 11 are both located in the wiring area 11a.

[0134] Understandably, the second display area 12 is a wiring area.

[0135] In some embodiments, the orthographic projections of the second sub-pixel 26b and the third sub-pixel 26c located in the first display area 11 in the thickness direction of the display panel 10 are located in the orthographic projection of the trace area 11a in the thickness direction of the display panel 10. The orthographic projections of a portion of the first sub-pixel 26a located in the first display area 11 in the thickness direction of the display panel 10 are located in the orthographic projection of the trace area 11a in the thickness direction of the display panel 10. The orthographic projections of another portion of the first sub-pixel 26a located in the first display area 11 in the thickness direction of the display panel 10 are located in the orthographic projection of the non-trace area 11b in the thickness direction of the display panel 10.

[0136] In one specific embodiment, the orthographic projection of one of the first sub-pixels 26a in the first sub-pixel group 20, which is located near the light-transmitting area 13, in the thickness direction of the display panel 10 is located in the orthographic projection of the non-trace area 11b in the thickness direction of the display panel 10.

[0137] In some embodiments, the display panel 10 further includes a touch layer 54 located between the encapsulation layer 17 and the color filter layer 48. The touch layer 54 includes a touch electrode layer 55 and a touch insulating layer 56. The touch electrodes are disposed corresponding to the light-shielding layer 49, and the touch insulating layer 56 is located between the touch electrodes and the color filter layer 48.

[0138] In this embodiment, the first display area 11 is provided with a light-transmitting area 13. By designing at least some of the pixel driving circuits in the first display area 11 as "one-to-many", one first pixel driving circuit 18 in the first display area 11 can simultaneously drive multiple sub-pixels of the same color to emit light. This effectively reduces the number of pixel driving circuits in the first display area 11, thereby reducing the coverage area of ​​the pixel driving circuits in the first display area 11 and increasing the area of ​​the light-transmitting area 13 in the first display area 11, which is beneficial to improving the local light transmittance of the first display area 11. Meanwhile, to avoid insufficient brightness of sub-pixels in the first display area 11 due to the "one-drive-multiple" design, which would lead to uneven display brightness between the first display area 11 and the second display area 12, this embodiment of the application differentiates the current flowing through the first driving transistor of the first pixel driving circuit 18 and the second driving transistor of the second pixel driving circuit 19 per unit time. This results in a larger current flowing through the first driving transistor per unit time, thereby improving the current output capability of the first pixel driving circuit 18. This is beneficial for improving the display brightness of sub-pixels electrically connected to the first pixel driving circuit in the first display area 11, ensuring consistent display brightness between the first display area 11 and the second display area 12, and thus improving the overall display effect of the display panel 10. Therefore, this embodiment of the application can effectively improve the local light transmittance of the display panel 10 without affecting the overall display effect of the display panel 10.

[0139] As shown in FIG16, this application embodiment also provides a display device 60, which includes at least one optical element 61 and the display panel 10 described in the above embodiments, wherein the optical element 61 is disposed corresponding to the light-transmitting area 13.

[0140] In some embodiments, the optical element 61 is disposed inside the display panel 10; in other embodiments, the optical element 61 is disposed on the back of the display panel 10 and is disposed corresponding to the first display area 11. This application does not limit this, as long as the optical element 61 is disposed corresponding to the light-transmitting area 13, it is within the protection scope of this application.

[0141] In some embodiments, when the optical element is disposed inside the display panel 10, the number of optical elements can be one, which is then disposed corresponding to the first display area 11; the number of optical elements can also be multiple, and they are disposed one-to-one with the light-transmitting area 13.

[0142] In some embodiments, optical element 61 includes, but is not limited to, a camera, an infrared sensor, an ambient light sensor, or a fingerprint reader.

[0143] In this embodiment, the light transmittance of the first display area 11 of the display panel 10 is improved, which increases the sensitivity of the optical element 61. At the same time, the display effect of different areas of the display device 60 remains consistent.

[0144] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0145] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0146] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0147] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, comprising a first display area and a second display area, wherein the first display area has at least one light-transmitting area; The display panel includes: The driving circuit layer includes a plurality of first pixel driving circuits located in the first display area and disposed away from the light-transmitting area, and a plurality of second pixel driving circuits located at least in the second display area; as well as A light-emitting layer is located on one side of the driving circuit layer and includes a plurality of pixel units located in the first display area and the second display area. The pixel unit includes at least three sub-pixels of different colors. In the first display area, in at least two of the pixel units, at least two sub-pixels of the same color are electrically connected to the same first pixel driving circuit. In the second display area, each second pixel driving circuit is electrically connected to only one sub-pixel. The first pixel driving circuit includes a first driving transistor, and the second pixel driving circuit includes a second driving transistor. When the display panel is in the light-emitting stage, the first driving transistor is electrically connected to the anode of the corresponding plurality of sub-pixels, and the second driving transistor is electrically connected to the anode of the corresponding sub-pixel. The current flowing through the first driving transistor per unit time is greater than the current flowing through the second driving transistor.

2. The display panel according to claim 1, wherein, The first driving transistor includes a first active portion, the second driving transistor includes a second active portion, and the ratio of the channel width to the channel length of the first active portion is greater than the ratio of the channel width to the channel length of the second active portion.

3. The display panel according to claim 2, wherein, The channel of the first active part is arranged in a straight line, while the channel of the second active part is arranged in a bent or curved shape.

4. The display panel according to claim 1, wherein, The first pixel driving circuit further includes a first switching transistor, the first electrode of the first switching transistor is connected to the first data signal terminal, and the second electrode of the first switching transistor is connected to the first electrode of the first driving transistor. The second pixel driving circuit further includes a second switching transistor, the first electrode of the second switching transistor is connected to the second data signal terminal, and the second electrode of the second switching transistor is connected to the first electrode of the second driving transistor; When the display panel is in the light-emitting stage, the second electrode of the first driving transistor is electrically connected to the anode of the corresponding plurality of sub-pixels, and the second electrode of the second driving transistor is electrically connected to the anode of the corresponding sub-pixel. Wherein, the first driving transistor and the second driving transistor are P-type transistors, the first switching transistor includes a third active part, the second switching transistor includes a fourth active part, and the ratio of the channel width to the channel length of the third active part is less than the ratio of the channel width to the channel length of the fourth active part.

5. The display panel according to any one of claims 1 to 4, wherein, The first pixel driving circuit further includes a first switching transistor, a first storage capacitor, and a first boost capacitor; the first electrode of the first switching transistor is connected to a first data signal terminal, and the second electrode of the first switching transistor is connected to the first electrode of the first driving transistor; one end of the first storage capacitor is connected to a first high-potential signal terminal, and the other end is connected to the gate of the first driving transistor; the first end of the first boost capacitor is connected to the gate of the first switching transistor, and the other end is connected to the gate of the first driving transistor. The second pixel driving circuit further includes a second switching transistor, a second storage capacitor, and a second boost capacitor; the first electrode of the second switching transistor is connected to a second data signal terminal, and the second electrode of the second switching transistor is connected to the first electrode of the second driving transistor; one end of the second storage capacitor is connected to a second high-potential signal terminal, and the other end is connected to the gate of the second driving transistor; the first end of the second boost capacitor is connected to the gate of the second switching transistor, and the other end is connected to the gate of the second driving transistor. When the display panel is in the light-emitting stage, the first electrode of the first driving transistor is electrically connected to the first high-potential signal terminal, the second electrode of the first driving transistor is electrically connected to the anode of the corresponding plurality of sub-pixels, the first electrode of the second driving transistor is electrically connected to the second high-potential signal terminal, and the second electrode of the second driving transistor is electrically connected to the anode of the corresponding sub-pixel. In this configuration, both the first and second switching transistors are P-type thin-film transistors, the capacitance of the first storage capacitor is greater than the capacitance of the second storage capacitor, and the capacitance of the first boost capacitor is less than the capacitance of the second boost capacitor.

6. The display panel according to claim 5, wherein, The first pixel driving circuit further includes a first compensation transistor and a first adjustment capacitor; the first electrode of the first compensation transistor is connected to the second electrode of the first driving transistor, and the second electrode of the first compensation transistor is connected to the gate of the first driving transistor; one end of the first adjustment capacitor is connected to the gate of the first driving transistor, and the other end is connected to the gate of the first compensation transistor. The second pixel driving circuit further includes a second compensation transistor and a second adjustment capacitor; the first electrode of the second compensation transistor is connected to the second electrode of the second driving transistor, and the second electrode of the second compensation transistor is connected to the gate of the second driving transistor; one end of the second adjustment capacitor is connected to the gate of the second driving transistor, and the other end is connected to the gate of the second compensation transistor. Wherein, both the first compensation transistor and the second compensation transistor are N-type thin-film transistors, and the capacitance value of the first regulating capacitor is greater than the capacitance value of the second regulating capacitor.

7. The display panel according to claim 1, wherein, When the display panel is in the light-emitting stage, the first electrode of the first driving transistor is electrically connected to the first high-potential signal terminal, the second electrode of the first driving transistor is electrically connected to the anode of the corresponding plurality of sub-pixels, the first electrode of the second driving transistor is electrically connected to the second high-potential signal terminal, the second electrode of the second driving transistor is electrically connected to the anode of the corresponding sub-pixel, the power supply voltage value connected to the first high-potential signal terminal is greater than the power supply voltage value connected to the second high-potential signal terminal, and the power supply voltage value connected to the second high-potential signal terminal is greater than 0.

8. The display panel according to claim 7, wherein, The driving circuit layer further includes a first high-potential signal line and a second high-potential signal line that are spaced apart from each other. The first high-potential signal line is connected to the first high-potential signal terminal, and the second high-potential signal line is connected to the second high-potential signal terminal.

9. The display panel according to claim 7, wherein, The first pixel driving circuit layer further includes a first reset transistor, the second pixel driving circuit further includes a second reset transistor, and the driving circuit layer further includes a second high-potential signal line, a first reset signal line, and a second reset signal line; The first electrode of the first reset transistor is connected to the first reset signal line, and the second electrode of the first reset transistor is connected to the first electrode of the first driving transistor; the first electrode of the second reset transistor is connected to the second reset signal line, and the second electrode of the second reset transistor is connected to the first electrode of the second driving transistor. The first reset signal line is also connected to the first high-potential signal terminal, and the second high-potential signal line is connected to the second high-potential signal terminal.

10. The display panel according to claim 1, wherein, The light-emitting layer includes a pixel-defining layer located in the first display area and the second display area, and the pixel-defining layer is provided with a plurality of pixel openings located in the first display area and the second display area, and a plurality of first light-transmitting openings located in the first display area; The sub-pixel is located in the pixel opening, and the first light-transmitting opening is aligned with the light-transmitting area; The sub-pixel includes an anode block that is at least partially exposed in the pixel opening. The anode blocks of a plurality of sub-pixels electrically connected to the same first pixel driving circuit are disposed on the same layer and interconnected with each other. The anode blocks of a plurality of sub-pixels electrically connected to different second pixel driving circuits are disposed at intervals. When the display panel is in the light-emitting stage, the first driving transistor is electrically connected to the anode block of the corresponding plurality of sub-pixels, and the second driving transistor is electrically connected to the anode block of the corresponding sub-pixel.

11. The display panel according to claim 10, wherein, The display panel further includes a color filter layer located on the side of the light-emitting layer opposite to the driving circuit layer; the color filter layer includes a light-shielding layer and a color resist layer; the light-shielding layer has a light-emitting opening aligned with the pixel opening and a second light-transmitting opening aligned with the first light-transmitting opening; the color resist layer includes a color resist unit located in the light-emitting opening, and the color of the color resist unit is the same as the color of the sub-pixel in the corresponding pixel opening. Among the multiple color resist units of the same color, the thickness of the color resist unit corresponding to the sub-pixel electrically connected to the first pixel driving circuit is less than the thickness of the color resist unit corresponding to the sub-pixel electrically connected to the second pixel driving circuit.

12. The display panel according to claim 1, wherein, In the first display area and the second display area, a plurality of pixel units are arranged in multiple rows and columns in the row direction and the column direction, and the row direction and the column direction are perpendicular to each other; each pixel unit includes a first sub-pixel, a second sub-pixel and a third sub-pixel of different colors; the light-transmitting area is located between two adjacent pixel units; In the first display area and the second display area, a plurality of first sub-pixels are arranged in multiple rows and columns in the row direction and the column direction, a plurality of second sub-pixels are arranged in multiple rows and columns in the row direction and the column direction, and a plurality of third sub-pixels are arranged in multiple rows and columns in the row direction and the column direction; between any two adjacent rows of first sub-pixels, there is a row of second sub-pixels and a row of third sub-pixels; any row of first sub-pixels and the adjacent row of second sub-pixels are staggered, and any row of second sub-pixels and the adjacent row of third sub-pixels are arranged in a one-to-one correspondence; In the first display area, in the column direction or the row direction, at least two sub-pixels of the same color are electrically connected to the same first pixel driving circuit.

13. The display panel according to claim 12, wherein, In the first display area, in the column direction, at least two adjacent first sub-pixels are electrically connected to the same first pixel driving circuit; The second pixel driving circuit is also located in the first display area and is disposed away from the light-transmitting area; in the first display area, a plurality of second sub-pixels and a plurality of third sub-pixels are electrically connected to a plurality of second pixel driving circuits in a one-to-one correspondence.

14. The display panel according to claim 13, wherein, In the first display area, in any column of first sub-pixels, at least two adjacent first sub-pixels form a first sub-pixel group, and multiple first sub-pixels in each first sub-pixel group are electrically connected to the same first pixel driving circuit. Each column of first sub-pixels constitutes a plurality of first sub-pixel groups, and the plurality of first sub-pixel groups located in adjacent columns are arranged correspondingly to each other or staggered to each other; in the column direction, a light-transmitting area is provided between each pair of adjacent first sub-pixel groups.

15. The display panel according to claim 14, wherein, The first sub-pixel located in the first display area and the second display area includes a first anode block. The display panel also includes a plurality of first connecting electrodes and a plurality of first connecting holes located in the first display area, and a plurality of second connecting electrodes and a plurality of second connecting holes located in the second display area. The first connecting electrodes and the second connecting electrodes are disposed in the same layer as the first anode block, and both the first connecting electrodes and the second connecting electrodes extend along the column direction. The first connecting electrode is located between any two adjacent first anode blocks in the same first sub-pixel group, and the two ends of the first connecting electrode are respectively connected to the two adjacent first anode blocks; a plurality of first connecting holes are provided in a one-to-one correspondence with a plurality of first sub-pixel groups, the first connecting hole is connected to one of the first connecting electrodes in the corresponding first sub-pixel group, and the first pixel driving circuit is connected to the corresponding first connecting electrode through the first connecting hole; Each of the first anode blocks located in the second display area is provided with a second connecting electrode and a second connecting hole on its periphery. One end of the second connecting electrode is connected to the corresponding first anode block, and the other end is connected to the corresponding second connecting hole. A second pixel driving circuit is electrically connected to the corresponding second connecting electrode through the second connecting hole.

16. The display panel according to claim 15, wherein, The first sub-pixel group includes two first sub-pixels arranged adjacent to each other in the column direction, the first connecting electrode is located between the two first sub-pixels in the same first sub-pixel group, and the first connecting hole is located between the two first sub-pixels in the same first sub-pixel group and connected to the first connecting electrode; In the first display area, a plurality of first connection holes are arrayed in the row direction and the column direction. Any two adjacent rows of first connection holes are arranged in a one-to-one correspondence in the column direction, or any two adjacent rows of first connection holes are arranged alternately in the column direction. In the second display area, a plurality of second connection holes are arrayed in the row direction and the column direction, and any two adjacent rows of second connection holes are arranged in a one-to-one correspondence in the column direction; each row of first connection holes and each row of second connection holes are arranged in the same row direction.

17. The display panel according to claim 16, wherein, The second sub-pixel located in the first display area and the second display area includes a second anode block, and the third sub-pixel located in the first display area and the second display area includes a third anode block; the display panel also includes a plurality of third connecting electrodes, a plurality of fourth connecting electrodes, a plurality of third connecting holes and a plurality of fourth connecting holes; each second anode block is provided with a third connecting electrode and a third connecting hole on its periphery, and each third anode block is provided with a fourth connecting electrode and a fourth connecting hole on its periphery; One end of the third connecting electrode is connected to the corresponding second anode block, and the other end is connected to the corresponding third connecting hole. A second pixel driving circuit is electrically connected to the corresponding third connecting electrode through the third connecting hole. One end of the fourth connecting electrode is connected to the corresponding third anode block, and the other end is connected to the corresponding fourth connecting hole. A second pixel driving circuit is electrically connected to the corresponding fourth connecting electrode through the fourth connecting hole. The third connecting electrode and the fourth connecting electrode are arranged in parallel, and the angle between the third connecting electrode and the column direction is greater than 0 and less than 90°; the third connecting hole and the fourth connecting hole, which are respectively provided corresponding to the second sub-pixel and the third sub-pixel in the same pixel unit, are arranged in the same row direction.

18. The display panel according to claim 17, wherein, In the first display area, each row of the first connecting hole is arranged in the same row as the row of the third connecting hole and the fourth connecting hole; In the second display area, the second connecting hole, the third connecting hole and the fourth connecting hole, which are respectively provided corresponding to the first sub-pixel, the second sub-pixel and the third sub-pixel in the same pixel unit, are arranged in the same row direction.

19. A display device, comprising optical elements and a display panel; the display panel comprising a first display area and a second display area, wherein the first display area has at least one light-transmitting area; The optical element is positioned corresponding to the light-transmitting area; The display panel includes: The driving circuit layer includes a plurality of first pixel driving circuits located in the first display area and disposed away from the light-transmitting area, and a plurality of second pixel driving circuits located at least in the second display area; and A light-emitting layer is located on one side of the driving circuit layer and includes a plurality of pixel units located in the first display area and the second display area. The pixel unit includes at least three sub-pixels of different colors. In the first display area, in at least two of the pixel units, at least two sub-pixels of the same color are electrically connected to the same first pixel driving circuit. In the second display area, each second pixel driving circuit is electrically connected to only one sub-pixel. The first pixel driving circuit includes a first driving transistor, and the second pixel driving circuit includes a second driving transistor. When the display panel is in the light-emitting stage, the first driving transistor is electrically connected to the anode of the corresponding plurality of sub-pixels, and the second driving transistor is electrically connected to the anode of the corresponding sub-pixel. The current flowing through the first driving transistor per unit time is greater than the current flowing through the second driving transistor.

20. The display device according to claim 19, wherein, The optical element includes any one of a camera, an infrared sensor, an ambient light sensor, and a fingerprint reader.

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