Display panel and display terminal

Abstract

Disclosed in the embodiments of the present application are a display panel and a display terminal. The display panel comprises a plurality of sub-pixels arranged in an array, and further comprises a substrate and shielding electrodes. The sub-pixels are located on the substrate, and the shielding electrodes are located between the substrate and the sub-pixels. Each sub-pixel comprises a pixel electrode, and at least part of each shielding electrode is located in an opening region of the sub-pixel; a first side edge of the shielding electrode does not overlap with a first side edge of the pixel electrode, the first side edge of the shielding electrode is a side edge of the shielding electrode close to a non-opening region of the sub-pixel, and the first side edge of the pixel electrode is a side edge of the pixel electrode close to the non-opening region.

Description

Display panel and display terminal

[0001] This application claims priority to Chinese patent application No. 202411500974.6, filed on October 25, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display technology, specifically to a display panel and a display terminal. Background Technology

[0003] Current liquid crystal displays (LCDs) typically use metal as the array-side common electrode to reduce the impact of parasitic capacitance on display quality. However, the opacity of the metal layer reduces the light-emitting area, thus lowering the LCD's transmittance. To address this, the transparent shielding and storage electrode (TSS) structure, by adding a transparent electrode layer to replace part of the original metal electrode, serves as both a storage capacitor and a shielding electrode. This reduces pixel dark areas, increases aperture ratio, and ultimately improves the LCD's transmittance.

[0004] However, the superposition of transparent electrode layers with other metal layers can lead to complex edge fields in the pixel structure, causing disorder in liquid crystal sorting and resulting in suboptimal light output. Invention Overview

[0005] The embodiments of this application provide a display panel and a display terminal to at least solve the technical problem that the edge field of the pixel structure is complex due to the superposition of metal layers in the existing pixel structure, which causes the liquid crystal sorting to be disordered and thus results in unsatisfactory light output.

[0006] In a first aspect, embodiments of this application provide a display panel, the display panel including a plurality of sub-pixels arranged in an array, the display panel further including: a substrate, the sub-pixels being located on the substrate; a shielding electrode, the shielding electrode being located between the substrate and the sub-pixels; wherein, the sub-pixel includes a pixel electrode, at least a portion of the shielding electrode is located in an opening region of the sub-pixel, a first side of the shielding electrode and a first side of the pixel electrode do not overlap, the first side of the shielding electrode being a side of the shielding electrode near the non-opening region of the sub-pixel, and the first side of the pixel electrode being a side of the pixel electrode near the non-opening region.

[0007] Secondly, embodiments of this application also provide a display terminal, including a display panel, the display panel including: a plurality of sub-pixels arranged in an array; a substrate, the sub-pixels being located on the substrate; a shielding electrode, the shielding electrode being located between the substrate and the sub-pixels; wherein, the sub-pixel includes a pixel electrode, at least a portion of the shielding electrode is located in an opening region of the sub-pixel, a first side of the shielding electrode and a first side of the pixel electrode do not overlap, the first side of the shielding electrode being a side of the shielding electrode near the non-opening region of the sub-pixel, and the first side of the pixel electrode being a side of the pixel electrode near the non-opening region. Attached Figure Description

[0008] Figure 1 is a schematic diagram of a display panel provided in an optional embodiment of this application;

[0009] Figure 2 is a schematic diagram of the structure of a sub-pixel provided in an optional embodiment of this application;

[0010] Figure 3 is a schematic diagram of the structure of the boundary region between the opening area and the non-opening area of ​​a sub-pixel provided in an optional embodiment of this application;

[0011] Figure 4 is a schematic diagram of the pixel structure of a display panel provided in an optional embodiment of this application;

[0012] Figure 5 is a schematic diagram of section AA in Figure 4;

[0013] Figure 6 is a schematic diagram of the structure of the spacing region between adjacent sub-pixels provided in an optional embodiment of this application;

[0014] Figure 7 is a cross-sectional schematic diagram of the spacing region between adjacent sub-pixels provided in another optional embodiment of this application;

[0015] Figure 8 is a simulation diagram of an alignment improvement effect provided in an optional embodiment of this application;

[0016] Figure 9 is a schematic diagram of the structure of a display terminal provided in an optional embodiment of this application.

[0017] Explanation of reference numerals in the attached figures

[0018] 1. Display panel;

[0019] 10, Substrate; 11, Subpixel; A, Aperture area; B, Non-aperture area; 111, Common electrode trace; 1111, First side of common electrode trace; 112, Shielding electrode; 1121, First side of shielding electrode; 113, Pixel electrode; 1130, First side of pixel electrode; 1131, First main branch; 1132, Second main branch; 1133, First branch; 1134, Second branch; 1135, Pixel electrode border; 114, First metal layer; 1141, First trace; 1142, Data line; 115, Via; 116, Color resist layer; 1161, First color resist layer; 1162, Second color resist layer; 117, Liquid crystal;

[0020] 20, Opposite substrate;

[0021] 2. Display terminal;

[0022] 3; Terminal main body. Embodiments of the present invention

[0023] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings. The described technical solutions are for illustrative purposes only and should not be construed as limiting the scope of protection of this application.

[0024] Furthermore, in the embodiments of this application, "multiple" refers to two or more. The terms "first" and "second," etc., in the embodiments of this application are used to distinguish different technical features and do not indicate any order, quantity, or importance.

[0025] The directional terms used in this application, such as "up", "down", "front", "back", "left", "right", "inner", "outer", and "side", are only for the directions shown in the accompanying drawings. The directional terms used herein are for the purpose of explaining and illustrating this application, and not for limiting the scope of protection of this application.

[0026] In the accompanying drawings, components with the same structure are indicated by the same numerical designation, and components with similar structures or functions are indicated by similar numerical designations. Furthermore, for ease of understanding and description, the dimensions and thicknesses of each component shown in the drawings are arbitrary, and this application does not limit the dimensions and thicknesses of each component.

[0027] The various embodiments provided in this application are similar, and features in different embodiments can be combined with each other.

[0028] The order in which the following embodiments are described is not intended to limit the preferred order of the embodiments.

[0029] Referring to Figure 1, an embodiment of this application provides a display panel 1, including a display area AA and a non-display area NA. The display panel 1 further includes a plurality of sub-pixels 11 arranged in an array, with the sub-pixels 11 located within the display area AA. Each sub-pixel 11 corresponds to one of the three colors: red, green, and blue. In this embodiment, a rectangular sub-pixel structure is used as an example for explanation.

[0030] The display panel 1 of this application has a vertical alignment (VA) technology driving architecture. Referring to Figures 1 and 5, the display panel 1 includes an array substrate 10, a liquid crystal layer 117, and a counter substrate 20 (which may be a color filter substrate) arranged sequentially. The common electrode on the counter substrate 20 and the pixel electrode of the array substrate 10 form a vertical electric field after being subjected to different voltages, thereby driving the liquid crystal in the liquid crystal layer 117 to deflect, thus realizing image display.

[0031] Referring to Figures 2 and 3, the display panel 1 further includes: a substrate 10, with sub-pixels 11 located on the substrate 10; and a shielding electrode 112 located between the substrate 10 and the sub-pixels 11. The sub-pixels 11 include a pixel electrode 113, at least a portion of the shielding electrode 112 is located in the opening region A of the sub-pixels 11, the first side 1121 of the shielding electrode 112 and the first side 1131 of the pixel electrode 113 do not overlap, the first side 1121 of the shielding electrode 112 is the side of the shielding electrode 112 near the non-opening region B of the sub-pixels 11, and the first side 1130 of the pixel electrode is the side of the pixel electrode 113 near the non-opening region B.

[0032] In this embodiment, metal traces such as TFTs and common electrodes are generally located in the non-aperture area of ​​the sub-pixel. The voltage difference between the transparent shielding electrode (TSS ITO) and the pixel electrode can cause edge electric field disturbance on the short side of the sub-pixel. Therefore, in the short side region of the sub-pixel (which can be understood as the non-aperture area B), the complex terrain of the short side of the sub-pixel can be improved by the staggered design of each film layer, and the influence of the complex edge electric field on the center electric field of the normal display area can be reduced. In this embodiment, in the non-aperture area B of the sub-pixel, the first side 1121 of the shielding electrode and the first side 1130 of the pixel electrode do not overlap. That is, the shielding electrode is moved up or down to avoid the pixel electrode at the via, which can effectively avoid the electric field effect between the shielding electrode 112 and the pixel electrode 113, prevent liquid crystal sorting disorder, and thus improve light extraction efficiency.

[0033] In an optional embodiment, the non-opening region B includes a thin-film transistor 116, and the pixel electrode 113 is connected to the thin-film transistor 116 through a via 115 located in the non-opening region B; wherein, the distance from the first side 1121 of the shielding electrode to the via 115 is greater than the distance from the first side 1131 of the pixel electrode to the via 115.

[0034] In an optional embodiment, the distance L1 between the first side 1121 of the shielding electrode and the via 115 satisfies the following range: L1 ≥ 5 μm. For example, L1 can be set to 5 μm, 6 μm, or 7 μm, etc., so that by moving the shielding electrode 112 up or down to avoid the pixel electrode 113 at the via 115, the electric field effect between the shielding electrode and the pixel electrode can be effectively avoided, preventing liquid crystal sorting disorder, thereby improving light extraction efficiency.

[0035] The shielding electrode 112 can be a TSS transparent electrode, which can be used in vertically aligned liquid crystal displays (VA-LCDs) to replace traditional shielding and storage metal electrodes. The shielding electrode 112 can be a full-surface metal layer with holes punched in the opening areas and some non-opening areas of the sub-pixels. Its main purpose is to improve the transmittance and optical efficiency of the display, thereby achieving energy savings. In traditional liquid crystal displays, the shielding and storage electrodes are usually made of metal materials, which absorb some light and reduce the transmittance of the display. The TSS transparent electrode, by using a transparent material, reduces light absorption, thereby improving transmittance.

[0036] In an optional embodiment, the display panel 1 further includes a common electrode, which includes a common electrode trace 111 located between the substrate 10 and the shielding electrode 112, and located at the boundary between the opening region A and the non-opening region B; wherein the distance from the first side 1111 of the common electrode trace to the via 115 is less than the distance from the first side 1121 of the shielding electrode to the via 115, and the first side 1111 of the common electrode trace is the side of the common electrode trace 111 away from the via 115.

[0037] Referring to Figures 2 and 3, in an optional embodiment, the pixel electrode 113 includes a pixel electrode border 1135, a first main stem 1131 disposed along the length direction of the sub-pixel 11 (as shown in the Y direction), one or more second main stems 1132 disposed perpendicular to the first main stem 1131, a plurality of first branches 1133, and second branches 1134 connected to the first branches. The first main stem 1131 and the second main stem 1132 divide the sub-pixel 11 into multi-domain regions. The first branches 1133 are arranged parallel to each other and spaced apart in each domain region at a preset angle. The orthographic projection of the portion of the first branch 1133 that connects to the second branch 1134 on the substrate 10 does not overlap with the orthographic projection of the shielding electrode 1121 on the substrate 10.

[0038] It should be noted that the sub-pixel 11 in this embodiment is a multi-domain pixel, such as a four-domain, six-domain, or eight-domain pixel, which can be selected according to the actual application, and this application does not limit it. In this embodiment, a four-domain sub-pixel is used as an example for description in conjunction with the accompanying drawings. That is, the pixel electrode 113 in this embodiment includes a first main branch 1131 and a second main branch 1132 perpendicular to the first main branch 1131, dividing the sub-pixel 11 into four regions.

[0039] By designing the staggered layers of each film, the complex topography of the short side of the sub-pixel (which can be understood as the non-opening area B) can be improved, and the influence of the complex edge electric field of the short side on the center electric field of the normal display area can be reduced. The orthographic projection of the part where the first branch 1133 and the second branch 1134 are connected on the substrate 10 does not overlap with the orthographic projection of the common electrode trace 111 on the substrate 10. That is, the corner of the pixel electrode 113 in the short side area of ​​the sub-pixel (as shown in the elliptical dashed box in Figure 3) is staggered from the common electrode trace 111, which can effectively avoid the electric field effect between the pixel electrode and the common electrode, prevent liquid crystal sorting disorder, and thus improve the light extraction efficiency.

[0040] Referring again to Figures 2 and 3, in an optional embodiment, the display panel further includes a first metal layer 114, which is disposed between the common electrode trace 111 and the shielding electrode 112. The first metal layer 114 includes a first trace 1141 disposed on the sub-pixel 11, and the first trace 1141 is connected to the second branch 1134 of the pixel electrode through a via 115; wherein, the orthographic projection of the portion of the first branch 1133 of the pixel electrode that is in contact with the second branch 1134 on the substrate 10 does not overlap with the orthographic projection of the via 115 on the substrate 10.

[0041] By designing the staggered layers, the complex topography of the non-aperture area B of the sub-pixel can be improved, and the influence of the complex edge electric field of the short side of the non-aperture area B on the center electric field of the normal display area can be reduced. The orthographic projection of the part where the first branch 1133 and the second branch 1134 meet on the substrate 10 does not overlap with the orthographic projection of the via 115 on the substrate 10. That is, the pixel electrode 113 is staggered from the via 115 at the corner of the non-aperture area of ​​the sub-pixel. This can effectively prevent the pixel electrode 113 from forming a complex edge electric field between the position of the via 115 and the first trace 1141 of the first metal layer 114 and the second branch 1134 of the pixel electrode, thus preventing liquid crystal sorting disorder and improving light extraction efficiency.

[0042] In an alternative embodiment, the orthographic projection of the shielding electrode 112 on the substrate 10 does not overlap with the orthographic projection of the via 115 on the substrate 10.

[0043] In an alternative embodiment, the orthographic projection of the common electrode trace 111 on the substrate 10 does not overlap with the orthographic projection of the via 115 on the substrate 10.

[0044] By staggering the shielding electrode 112 or the common electrode trace 111 with the via 115, complex edge electric fields can be effectively avoided between multiple film layers, preventing liquid crystal sorting disorder and thus improving light extraction efficiency.

[0045] In an optional embodiment, the distance between the first side 1121 of the shielding electrode and the first side 1111 of the common electrode trace in the first direction (Y direction as shown in FIG3) ranges from 1 to 3 μm. By offsetting the TSS downward or upward, the electric field at the short edge can be controlled, thereby reducing the dark ripples at the short edge.

[0046] Figure 4 is a schematic diagram of the pixel structure of a display panel provided in an optional embodiment of this application, and Figure 5 is a cross-sectional view of AA in Figure 4. It should be noted that Figure 4 shows a single sub-pixel, while Figure 5 shows a cross-sectional view of the adjacent long edges of two adjacent sub-pixels. Referring to Figures 4 and 5, the first metal layer 114 also includes data lines 1142 disposed between adjacent sub-pixels. The gap between the data lines 1142 and the pixel electrodes 113 between adjacent sub-pixels is too large. For example, the horizontal distance between the data lines 1142 and the left and right pixel electrodes 113 is approximately 1.4 μm. A lateral electric field exists between the shielding electrode 1121 and the pixel electrode 113. The deflection of the liquid crystal 117 between the data lines 1142 and the outer edge of the frame 1135 of the pixel electrode causes light leakage from the pixel, which in turn causes color shift in the panel.

[0047] To solve the above problems, referring to Figures 2 to 7, in the embodiments of this application, the orthographic projection of the data line 1142 on the substrate 10 and the orthographic projection of the pixel electrode border 1135 on the substrate 10 partially overlap in the width direction of the data line 1142.

[0048] In one embodiment, the non-aperture region includes a thin-film transistor 116, and the pixel electrode 113 is connected to the thin-film transistor 116 through a via 115 located in the non-aperture region B. The distance from the first side 1121 of the shielding electrode to the via 115 is less than the distance from the first side 1131 of the pixel electrode to the via 115. The edge of the shielding electrode 112 near the via 115 is offset from the edge of the pixel electrode 113 near the via 115. Moving the shielding electrode 112 upwards or downwards to avoid the pixel electrode 113 at the via 115 effectively avoids the electric field effect between the shielding electrode 112 and the pixel electrode 113, preventing liquid crystal sorting disorder and thus improving light extraction efficiency.

[0049] In one embodiment, the display panel 1 further includes a data line 1142 disposed between adjacent sub-pixels 11. The data line 1142 is located between the substrate 10 and the shielding electrode 112. The orthographic projection of the data line 1142 on the substrate 10 and the orthographic projection of the frame 1135 of the pixel electrode on the substrate 10 partially overlap in the width direction of the data line 1142.

[0050] In one embodiment, the overlap width between the orthographic projection of the data line 1142 on the substrate 10 and the orthographic projection of the pixel electrode border 1135 on the substrate 10 is set to L2, and the pixel spacing between two adjacent sub-pixels 11 is set to L3. The ratio of L3 to L2 satisfies: L3 / L2 > 1.6. By controlling the range of the ratio of L2 to L3, for example, setting the ratio to 1.65, 1.7, 1.75, etc., the disordered tilting of the liquid crystal under the TSS electric field can be reduced, making the azimuth angle of the liquid crystal closer to 45°, optimizing the alignment dark lines, and thus improving the transmittance Tr%. As shown in Table 1 below, when L3 / L2 > 1.6, Tr% is effectively improved, from 4.46% to 4.75%.

[0051] Table 1

[0052] Penetration rate before improvement: Tr% 4.46% After improvement: 4.75%

[0053] Provided that L3 / L2 > 1.6, or even without considering the ratio of L3 / L2, the transmittance of the display panel can be improved and color shift reduced by setting the value ranges of L2 and L3 respectively.

[0054] Referring again to Figures 6 and 7, in one embodiment, the overlap width L2 between the orthographic projection of the data line 1142 on the substrate 10 and the orthographic projection of the pixel electrode border 1135 on the substrate 10 satisfies: L2 ≤ 3 μm. In an optional embodiment, the overlap width between the trunk portion and the data line can also be adjusted by widening the width L4 of the data line 1142. Optionally, the overlap width L2 between the orthographic projection of the data line 1142 on the substrate 10 and the orthographic projection of the pixel electrode border 1135 (equivalent to the trunk portion shown in Figure 6) on the substrate can be less than or equal to 3 μm, for example, set to 1.5 to 3 μm.

[0055] In one embodiment, the pixel spacing L3 between two adjacent sub-pixels 11 satisfies the following condition: L3 ≥ 5 μm. Referring to FIG7, in an optional embodiment, the pixel spacing L3 between two adjacent sub-pixels can be greater than or equal to 5 μm, for example, set to 5 μm, 6 μm, or 7 μm, and the width of the data line 1142 can be greater than the pixel spacing between two adjacent sub-pixels. By setting an appropriate pixel spacing, color shift problems caused by color resist interfering with adjacent sub-pixels due to process fluctuations can be avoided.

[0056] The first branch 1133 of the pixel electrode 113 can be connected together at the edge to form a vertically elongated trunk structure, i.e., the frame 1135 of the pixel electrode. Referring to the dashed box in FIG6, it can also be understood that the entire pixel electrode 113 is a whole rectangular ITO electrode, which includes parallel and spaced cutouts in the segmented multi-domain region. In this embodiment, the width of the trunk structure can be appropriately reduced, for example, the width of the trunk structure can be set to 2.5 to 4 μm, so that the trunk structure and the data line 1142 overlap further in the width direction. By matching the width of the trunk structure appropriately, the dark lines caused by the edge field of the long side of the sub-pixel can be improved, the light-emitting area of ​​the normal display area can be larger, and the light extraction efficiency can be improved.

[0057] Choosing the appropriate trunk width can effectively reduce interference between signal lines. Too narrow a width may exacerbate electromagnetic interference, while too wide a width may increase circuit board complexity and cost. Simultaneously, when designing data lines, ensure they completely block edge light leakage. This can be achieved through an overlay design between the data line and the pixel, where the data line covers the edge of the pixel to prevent light leakage. With an overlay design, the data line can completely block edge light leakage, reducing light leakage from the edges and thus improving display quality. Furthermore, ensure the distance between pixels is appropriate to avoid color resistivity crosstalk caused by excessive proximity. In display panels, color resistivity crosstalk refers to color interference between different pixels due to resistance variations. Optimizing the distance between pixels can reduce this interference. On one hand, appropriate pixel spacing can reduce color resistivity crosstalk under process fluctuations, ensuring display stability. On the other hand, during manufacturing, process fluctuations may cause changes in resistance and capacitance, affecting display quality. Proper design can reduce the impact of these fluctuations on display quality.

[0058] During the design process, this application embodiment determines the optimal trunk width and data line layout through simulation and testing. This ensures the data lines completely cover the pixel edges, reducing light leakage. Based on actual test results, the distance between pixels (which can be understood as the distance between adjacent sub-pixels) is adjusted to ensure good display performance under different grayscale levels and viewing angles. Referring to Table 2 below, when the overlap width L2 of the orthographic projection of the data line 1142 on the substrate 10 and the orthographic projection of the pixel electrode border 1135 on the substrate 10 satisfies L2≤3μm and the pixel spacing L3≥5μm, the contrast ratio viewing angle is effectively improved. Contrast ratio viewing angle (CR) refers to the change in contrast of the display under different viewing angles. Contrast ratio is the ratio of the brightness of the display when showing the brightest (white) and the darkest (black) image. High contrast ratio means clearer images and more vivid colors. CR(-30) represents the contrast value measured at a -30 degree viewing angle. -30 degree and +30 degree viewing angles refer to positions deviating 30 degrees to the left or right from directly in front of the display. A higher contrast ratio indicates that the display maintains good contrast and image quality even at a -30 degree viewing angle. In the embodiments of this application, reasonable pixel interval values ​​are set. The CR(-30) before improvement is 38.8%, and the CR(-30) after improvement is 55.4%. The CR(+30) before improvement is 37.3%, and the CR(+30) after improvement is 54.9%, indicating that the contrast of the display is significantly improved at a -30 degree viewing angle, and the image quality is improved.

[0059] Table 2

[0060] Contrast and viewing angle improvement: Before improvement, CR (-30) 38.80% 55.40%; After improvement, CR (+30) 37.30% 54.90%.

[0061] Referring to Figure 8, which is a simulation diagram of the alignment improvement effect provided in an optional embodiment of this application, it can be seen that the display panel structure provided in this embodiment effectively improves the dark patterns and color shifts on the short and long sides of the pixels, and the images displayed in the light-emitting areas are all normal images.

[0062] Referring to FIG5, in an optional embodiment, the display panel further includes an amorphous silicon layer 118 disposed on the side of the data line 1142 near the substrate 10; wherein, between adjacent sub-pixels 11, the orthographic projection of the data line 1142 on the substrate 10 covers the orthographic projection of the amorphous silicon layer 118 on the substrate 10.

[0063] In one embodiment, the display panel further includes a color resist layer 116 disposed on the side of the shielding electrode 112 near the substrate 10.

[0064] In this embodiment, the color resist layer 116 may include multiple red, green, and blue color resists. Each color resist in the color resist layer is used to convert white light into the corresponding colored light. In the display area, one color resist is correspondingly set to one sub-pixel 11. Referring to FIG7, the color resist layers of two adjacent sub-pixels are of different colors. For example, color resist layers 1161 and 1162 can be blue and red, or green and red, respectively. Sub-pixel 11 with a red color resist is a red sub-pixel, sub-pixel 11 with a green color resist is a green sub-pixel, and sub-pixel 11 with a blue color resist is a blue sub-pixel. The color resist layer 116 is typically composed of tiny red, green, and blue (RGB) filters, which are precisely placed on each sub-pixel of the liquid crystal panel. Each sub-pixel corresponds to a color, and by controlling the color and brightness of the light passing through the sub-pixel, a full-color image is finally formed. The structure of a color resist layer typically includes: a filter, made of organic dyes or inorganic pigments, used to filter light of a specific wavelength; a black matrix, placed between the filters, used to absorb excess light, prevent interference between colors, and improve the contrast and clarity of the display; and a protective layer, covering the filters and the black matrix, to prevent physical damage and environmental impact.

[0065] It should be understood that in this embodiment, the display panel 1 is a COA (Color Filter on Array) architecture panel, and the color filter substrate 20 is disposed relative to the substrate 10 (Array substrate). By setting the display panel 1 as a COA architecture panel, the color resist layer 116 and the pixel electrode 113 can be disposed on the same substrate 10, thereby avoiding the loss of aperture ratio caused by the alignment deviation of the two substrates when the color resist layer 116 and the pixel electrode 113 are disposed on different substrates. That is, the use of the COA architecture helps to increase the alignment accuracy of the color resist layer 116 and the pixel electrode 113, and improve the aperture ratio of the display panel 1.

[0066] The display panel in this embodiment may further include an insulating layer, a passivation layer, or a planarization layer disposed between different metal layers. The insulating layer may be composed of inorganic materials, such as glass, quartz, ceramic, alumina, boron nitride, magnesium oxide, calcium silicate, borate glass, etc. The passivation layer may be formed using inorganic materials, such as silicon nitride. The planarization layer is used to smooth the substrate surface to reduce surface roughness and unevenness, thereby providing better conditions for subsequent manufacturing processes. The materials for the planarization layer typically include oxides, nitrides, polycrystalline silicon, polymers, etc. The selection of these materials depends on the required electrical, mechanical, and chemical properties. The manufacturing processes for the planarization layer include chemical vapor deposition (CVD), physical vapor deposition (PVD), spin coating, spraying, etc. These processes ensure that the planarization layer is uniformly distributed on the substrate, forming a smooth surface. In this embodiment, the planarization layer is used to ensure the uniformity and consistency of the display panel.

[0067] The shielding electrode 112 and the pixel electrode 113 can be transparent metals, such as ITO (indium tin oxide), IZO (indium zinc oxide), IZTO (indium zinc tin oxide), IAZO (indium aluminum zinc oxide), IGZO (indium gallium zinc oxide), IGTO (indium gallium tin oxide), AZO (aluminum zinc oxide), ATO (antimony tin oxide), IGZTO (indium gallium zinc tin oxide), etc.

[0068] Referring to FIG9, another embodiment of this application provides a display terminal 2, including a display panel 1 and a terminal body 3 as described in any of the above embodiments, wherein the display panel 1 and the terminal body 3 are integrated into one unit. The terminal body 3 may include a backlight module, which is disposed on the side of the substrate 10 of the display panel 1 facing away from the color resist layer 116. The backlight module is used to provide a light source for the display panel 1.

[0069] The display terminal can be any product or component with display function, such as mobile phones, tablets, televisions, monitors, laptops, digital photo frames, and navigators.

[0070] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A display panel, the display panel comprising a plurality of sub-pixels arranged in an array, the display panel further comprising: A substrate, wherein the sub-pixels are located on the substrate; A shielding electrode is located between the substrate and the sub-pixel; The sub-pixel includes a pixel electrode, at least a portion of the shielding electrode is located in the opening region of the sub-pixel, the first side of the shielding electrode and the first side of the pixel electrode do not overlap, the first side of the shielding electrode is the side of the shielding electrode close to the non-opening region of the corresponding sub-pixel, and the first side of the pixel electrode is the side of the pixel electrode close to the non-opening region.

2. The display panel according to claim 1, wherein, The non-aperture region includes a thin-film transistor, and the pixel electrode is connected to the thin-film transistor through a via located in the non-aperture region; The distance from the first side of the shielding electrode to the via is greater than the distance from the first side of the pixel electrode to the via.

3. The display panel according to claim 2, wherein, The distance L1 between the first side of the shielding electrode and the via satisfies: L1≥5μm.

4. The display panel according to claim 2, wherein, The display panel further includes a common electrode, which includes a common electrode trace located between the substrate and the shielding electrode, and located at the boundary between the opening area and the non-opening area; Wherein, the distance from the first side of the common electrode trace to the via is less than the distance from the first side of the shielding electrode to the via, and the first side of the common electrode trace is the side of the common electrode trace away from the via.

5. The display panel according to claim 1, wherein, The non-aperture region includes a thin-film transistor, and the pixel electrode is connected to the thin-film transistor through a via located in the non-aperture region; Wherein, the distance from the first side of the shielding electrode to the via is less than the distance from the first side of the pixel electrode to the via.

6. The display panel according to claim 1, wherein, The display panel also includes a data line disposed between adjacent sub-pixels. The data line is located between the substrate and the shielding electrode. The orthographic projection of the data line on the substrate and the orthographic projection of the frame of the pixel electrode on the substrate partially overlap in the width direction of the data line.

7. The display panel according to claim 1, wherein, The overlap width between the orthographic projection of the data line on the substrate and the orthographic projection of the pixel electrode border on the substrate is set to L2, and the pixel spacing between two adjacent sub-pixels is set to L3. The ratio of L3 to L2 satisfies the following relationship: L3 / L2 > 1.

6.

8. The display panel according to claim 7, wherein, The overlap width L2 between the orthographic projection of the data line on the substrate and the orthographic projection of the pixel electrode frame on the substrate satisfies: L2≤3μm.

9. The display panel according to claim 7, wherein, The pixel spacing L3 between two adjacent sub-pixels satisfies the following condition: L3≥5μm.

10. The display panel according to any one of claims 1 to 9, wherein, The display panel also includes a color resist layer, which is disposed on the side of the shielding electrode near the substrate.

11. A display terminal, comprising a display panel, the display panel comprising: Multiple sub-pixels arranged in an array; A substrate, wherein the sub-pixels are located on the substrate; A shielding electrode is located between the substrate and the sub-pixel; The sub-pixel includes a pixel electrode, at least a portion of the shielding electrode is located in the opening region of the sub-pixel, the first side of the shielding electrode and the first side of the pixel electrode do not overlap, the first side of the shielding electrode is the side of the shielding electrode closer to the non-opening region of the sub-pixel, and the first side of the pixel electrode is the side of the pixel electrode closer to the non-opening region.

12. The display terminal according to claim 11, wherein, The non-aperture region includes a thin-film transistor, and the pixel electrode is connected to the thin-film transistor through a via located in the non-aperture region; The distance from the first side of the shielding electrode to the via is greater than the distance from the first side of the pixel electrode to the via.

13. The display terminal according to claim 12, wherein, The distance L1 between the first side of the shielding electrode and the via satisfies: L1≥5μm.

14. The display terminal according to claim 12, wherein, The display panel further includes a common electrode, which includes a common electrode trace located between the substrate and the shielding electrode, and located at the boundary between the opening area and the non-opening area; Wherein, the distance from the first side of the common electrode trace to the via is less than the distance from the first side of the shielding electrode to the via, and the first side of the common electrode trace is the side of the common electrode trace away from the via.

15. The display terminal according to claim 11, wherein, The non-aperture region includes a thin-film transistor, and the pixel electrode is connected to the thin-film transistor through a via located in the non-aperture region; Wherein, the distance from the first side of the shielding electrode to the via is less than the distance from the first side of the pixel electrode to the via.

16. The display terminal according to claim 11, wherein, The display panel also includes a data line disposed between adjacent sub-pixels. The data line is located between the substrate and the shielding electrode. The orthographic projection of the data line on the substrate and the orthographic projection of the frame of the pixel electrode on the substrate partially overlap in the width direction of the data line.

17. The display terminal according to claim 11, wherein, The overlap width between the orthographic projection of the data line on the substrate and the orthographic projection of the pixel electrode border on the substrate is set to L2, and the pixel spacing between two adjacent sub-pixels is set to L3. The ratio of L3 to L2 satisfies the following relationship: L3 / L2 > 1.

6.

18. The display terminal according to claim 17, wherein, The overlap width L2 between the orthographic projection of the data line on the substrate and the orthographic projection of the pixel electrode frame on the substrate satisfies: L2≤3μm.

19. The display terminal according to claim 17, wherein, The pixel spacing L3 between two adjacent sub-pixels satisfies the following condition: L3≥5μm.

20. The display terminal according to any one of claims 11 to 19, wherein, The display panel also includes a color resist layer, which is disposed on the side of the shielding electrode near the substrate.

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