Printed wiring board and method for manufacturing printed wiring board

Abstract

A printed wiring board (100) is provided with a base film (10) having a main surface (10a), and wiring (20) disposed on the main surface. The wiring has a base layer (22) disposed on the main surface, and a first electrolytic plating layer (23) disposed on the base layer. The width (W1) of the bottom surface of the first electrolytic plating layer is greater than the width (W2) of the top surface of the first electrolytic plating layer. The width of the first electrolytic plating layer at a central position (P) between the top surface of the first electrolytic plating layer and the bottom surface of the first electrolytic plating layer is 0.91 to 1 times the average value of the width (W2) of the wiring on the top surface of the first electrolytic plating layer and the width (W1) of the first electrolytic plating layer on the bottom surface of the first electrolytic plating layer.

Description

Printed Wiring Board and Method of Manufacturing the Same

[0001] The present disclosure relates to a printed wiring board and a method of manufacturing the same.

[0002] International Publication No. 2023 / 243500 (Patent Document 1) describes a printed wiring board. The printed wiring board described in Patent Document 1 has a base film and wiring. The wiring has a base conductive layer disposed on the main surface of the base film and an electrolytically plated copper layer disposed on the base conductive layer.

[0003] International Publication No. 2023 / 243500

[0004] The printed wiring board of the present disclosure includes a base film having a main surface and wiring disposed on the main surface. The wiring has a base layer disposed on the main surface and a first electrolytically plated layer disposed on the base layer. The width at the bottom surface of the first electrolytically plated layer is larger than the width at the top surface of the first electrolytically plated layer. The width of the first electrolytically plated layer at the central position between the top surface and the bottom surface of the first electrolytically plated layer is 0.91 times or more and 1 time or less the average value of the width of the wiring at the top surface of the first electrolytically plated layer and the width of the first electrolytically plated layer at the bottom surface of the first electrolytically plated layer.

[0005] FIG. 1 is a first plan view of the printed wiring board 100. FIG. 2 is a second plan view of the printed wiring board 100. FIG. 3 is a cross-sectional view taken along III-III of FIG. 1. FIG. 4 is a manufacturing process diagram of the printed wiring board 100. FIG. 5 is a cross-sectional view for explaining the electroless plating process S2. FIG. 6 is a cross-sectional view for explaining the resist pattern forming process S3. FIG. 7 is a cross-sectional view for explaining the electrolytic plating process S4. FIG. 8 is a cross-sectional view for explaining the resist pattern removing process S5. FIG. 9 is a cross-sectional view for explaining the resist pattern forming process S3 in the method of manufacturing the printed wiring board 200. FIG. 10 is a cross-sectional view for explaining the resist pattern forming process S3 in the method of manufacturing the printed wiring board 300. FIG. 11 is a cross-sectional view of the printed wiring board 100A. FIG. 12 is a manufacturing process diagram of the printed wiring board 100A.

[0006] [Problems this disclosure aims to solve] In order to reduce wiring resistance, it is necessary to increase the height of the wiring. In the printed circuit board of Patent Document 1, in order to increase the height of the wiring, it is necessary to form a thick resist pattern when forming the electrolytic copper plating layer. However, when the resist pattern is formed thickly, contamination on the underlying conductive layer increases. In this case, even if an attempt is made to clean the surface of the portion of the underlying conductive layer exposed from the opening of the resist pattern using plasma after the formation of the resist pattern but before the formation of the electrolytic copper plating layer, the plasma has difficulty reaching the surface of the underlying conductive layer, and sufficient cleaning cannot be performed. As a result, there is a risk of void formation between the underlying conductive layer and the electrolytic copper plating layer, and peeling of the wiring caused by these voids.

[0007] This disclosure provides a printed circuit board capable of suppressing void generation at the interface between the underlayer and the electrolytic copper plating layer.

[0008] [Effects of this disclosure] According to the printed circuit board of this disclosure, it is possible to suppress the generation of voids at the interface between the substrate layer and the electrolytic copper plating layer.

[0009] [Description of Embodiments of the Disclosure] First, embodiments of the disclosure will be listed and described.

[0010] (1) The printed circuit board according to the embodiment comprises a base film having a main surface and wiring arranged on the main surface. The wiring comprises a base layer arranged on the main surface and a first electroplating layer arranged on the base layer. The width of the bottom surface of the first electroplating layer is greater than the width of the top surface of the first electroplating layer. The width of the first electroplating layer at the central position between the top surface and the bottom surface of the first electroplating layer is 0.91 times or more and 1 time or less of the average value of the width of the wiring at the top surface of the first electroplating layer and the width of the first electroplating layer at the bottom surface of the first electroplating layer. According to the printed circuit board of (1) above, void generation at the interface between the base layer and the electroplated copper layer can be suppressed.

[0011] (2) In the printed circuit board described in (1) above, the height of the first electroplating layer may be 60 μm or more and 300 μm or less.

[0012] (3) In the printed circuit board described in (1) or (2) above, the width of the bottom surface of the first electroplating layer may be 10 μm or more and 100 μm or less.

[0013] (4) In the printed circuit boards described in (1) to (3) above, the void ratio at the interface between the underlayer and the first electroplating layer is 40 μm ２ It may be less than / μm.

[0014] (5) In the printed circuit boards described in (1) to (4) above, the wiring may further have a second electroplating layer that covers the sides of the base layer, the sides of the first electroplating layer, and the top surface of the first electroplating layer.

[0015] (6) In the printed circuit board described in (5) above, the height of the wiring may be 120 μm or more and 300 μm or less.

[0016] (7) In the printed circuit boards described in (1) to (6) above, the wiring may have a first wiring section and a second wiring section where the wiring is adjacent to each other. The minimum distance between the first electroplating layer of the first wiring section and the first electroplating layer of the second wiring section may be 20 μm or less.

[0017] (8) In the printed circuit boards described in (1) to (7) above, the width of the wiring on the top surface of the first electroplating layer may be 0.3 times or more and 0.8 times or less the width of the first electroplating layer on the bottom surface of the first electroplating layer.

[0018] (9) A method for manufacturing a printed circuit board according to the embodiment comprises the steps of: preparing a base film having a main surface on which a base layer is arranged; forming a resist pattern on the base layer having a first surface facing the base layer and a second surface opposite the first surface, and having openings that partially expose the base layer; forming a first electroplating layer on the portion of the base layer exposed from the openings; removing the resist pattern; and removing the portion of the base layer that was beneath the resist pattern by etching. The step of forming the resist pattern comprises the steps of placing a laminate made of a plurality of dry film resists stacked on the base layer, and exposing and developing the laminate to form openings. The width of the opening on the first surface is greater than the opening width of the opening on the second surface. According to the method for manufacturing a printed circuit board of the above (9), the generation of voids at the interface between the base layer and the electroplating layer can be suppressed.

[0019] (10) In the method for manufacturing printed circuit boards described in (9) above, the height of the laminate may be 60 μm or more. The laminate may have three or more dry film resists.

[0020] (11) The method for manufacturing a printed circuit board according to (9) or (10) above may further include a step of cleaning the surface of the underlying layer exposed from the opening using plasma after the resist pattern has been formed but before the first electroplating layer has been formed.

[0021] (12) The methods for manufacturing printed circuit boards described in (9) to (11) above may further include the step of forming a second electroplating layer that covers the sides of the base layer, the sides of the first electroplating layer, and the top surface of the first electroplating layer after forming the first electroplating layer.

[0022] [Details of Embodiments of the Disclosure] Details of embodiments of the disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts will be denoted by the same reference numerals, and redundant descriptions will not be repeated.

[0023] (First Embodiment) A printed circuit board according to the first embodiment will be described. The printed circuit board according to the first embodiment will be referred to as printed circuit board 100.

[0024] <Configuration of Printed Circuit Board 100> The configuration of the printed circuit board 100 is described below.

[0025] Figure 1 is a first plan view of the printed circuit board 100. Figure 2 is a second plan view of the printed circuit board 100. Figure 2 shows a plan view of the printed circuit board 100 viewed from the opposite side to that of Figure 1. As shown in Figures 1 and 2, the printed circuit board 100 has a base film 10, wiring 20 and wiring 21.

[0026] The base film 10 has a main surface 10a and a main surface 10b. The main surface 10b is the opposite surface to the main surface 10a. The base film 10 is made of a flexible, electrically insulating material. For example, the base film 10 is made of polyimide. Viewing the printed circuit board 100 along the direction normal to the main surface 10a is called a plan view.

[0027] The wiring 20 is arranged on the main surface 10a. The wiring 20 has, for example, a coil portion 20a and lands 20b and lands 20c. The wiring 21 is arranged on the main surface 10b. The wiring 21 has, for example, a coil portion 21a and lands 21b and lands 21c.

[0028] In the coil section 20a, the wiring 20 is wound in a spiral shape in a plan view. Lands 20b and 20c are located at both ends of the wiring 20. Land 20b is connected to the outermost part of the coil section 20a. Land 20c is connected to the innermost part of the coil section 20a.

[0029] In the coil section 21a, the wiring 21 is wound in a spiral shape in a plan view. Lands 21b and 21c are located at both ends of the wiring 21. Land 21b is connected to the innermost circumference of the coil section 20a. In a plan view, land 21b overlaps with land 20c. Land 21c is connected to the outermost circumference of the coil section 21a.

[0030] Figure 3 is a cross-sectional view taken along the line III-III in Figure 1. Figure 3 shows a cross-sectional view perpendicular to the direction in which the wiring 20 extends. As shown in Figure 3, each of the wirings 20 and 21 has a base layer 22 and a first electroplating layer 23.

[0031] The base layer 22 includes, for example, a seed layer 22a and an electroless plating layer 22b. The seed layer 22a is located on the main surface of the base film 10. More specifically, the seed layer 22a for wiring 20 is located on the main surface 10a, and the seed layer 22a for wiring 21 is located on the main surface 10b.

[0032] The electroless plating layer 22b is positioned on the seed layer 22a. Although not shown, through holes are formed in the seed layer 22a and the base film 10. These through holes overlap the lands 20c and lands 21b in a plan view. The electroless plating layer 22b is also positioned on the inner wall surface of these through holes. The electroless plating layer 22b positioned on the inner wall surface of these through holes electrically connects the wiring 20 and the wiring 21.

[0033] The seed layer 22a is a layer formed by, for example, sputtering. The electroless plating layer 22b is a layer formed by electroless plating. The electroless plating layer 22b is formed of, for example, copper or a copper alloy.

[0034] The first electroplating layer 23 is placed on the electroless plating layer 22b (underlayer 22). The first electroplating layer 23 is a layer formed by electroplating. The first electroplating layer 23 is formed of, for example, copper or a copper alloy.

[0035] Let W1 be the width of the bottom surface of the first electroplating layer 23. Let W2 be the width of the top surface of the first electroplating layer 23. W1 is greater than W2. W2 is, for example, 0.3 times or more and 0.8 times or less than or equal to W1. W1 is, for example, 10 μm or more and 100 μm or less.

[0036] Position P is defined as the central position between the bottom surface and the top surface of the first electroplating layer 23. Width W3 is defined as the width of the first electroplating layer 23 at position P. Width W3 is between 0.91 and 1 times the average value of widths W1 and W2, that is, the value obtained by dividing the sum of widths W1 and W2 by 2. If the first electroplating layer 23 is an ideal trapezoid, the average value of widths W1 and W2 corresponds to the width of the trapezoid at position P. The width of the first electroplating layer 23 is measured in a plan view along a direction perpendicular to the extension direction of the wiring 20 (wiring 21).

[0037] The height of the first electroplating layer 23 is defined as height H1. Height H1 is the distance between the bottom surface and the top surface of the first electroplating layer 23. Height H1 is, for example, 60 μm or more and 300 μm or less.

[0038] Each of the coil section 20a and coil section 21a has a plurality of wiring sections arranged in a direction perpendicular to the direction in which the wiring 20 (wiring 21) extends. One of two adjacent wiring sections is designated as wiring section 24a, and the other of two adjacent wiring sections is designated as wiring section 24b. The minimum distance between the first electroplating layer 23 of wiring section 24a and the first electroplating layer 23 of wiring section 24b is defined as distance DIS. Distance DIS is, for example, 5 μm or more and 20 μm or less.

[0039] The void ratio at the interface between the underlayer 22 and the first electroplating layer 23 is, for example, 40 μm. ２ It is less than or equal to / μm. Also, the void ratio at the interface between the underlayer 22 and the first electroplating layer 23 is 20 μm. ２ The void ratio may be less than or equal to / μm. Voids do not need to be formed at the interface between the underlayer 22 and the first electroplating layer 23. That is, the void ratio at the interface between the underlayer 22 and the first electroplating layer 23 is 0 μm. ２ It may also be / μm. The void ratio at the interface between the underlayer 22 and the first electroplating layer 23 is measured by the following method.

[0040] First, in a cross-section perpendicular to the main surface of the base film 10, a cross-sectional image of the interface between the underlayer 22 and the first electrolytic plating layer 23 is obtained using a SEM (Scanning Electron Microscope). Second, in this cross-sectional image, the total area (S, unit: μm ２ ) of voids formed within the range of the observation length (L, unit: μm) is calculated. S is obtained by binarizing the above cross-sectional image so that the voids become black using image processing software (for example, GNU Image Manipulation Program), and calculating the ratio of black based on the brightness histogram obtained using the image processing software. Then, the value obtained by dividing S by L (S / L) becomes the void ratio at the interface between the underlayer 22 and the first electrolytic plating layer 23.

[0041] <Manufacturing Method of Printed Wiring Board 100> The manufacturing method of the printed wiring board 100 will be described below.

[0042] FIG. 4 is a manufacturing process diagram of the printed wiring board 100. As shown in FIG. 4, the manufacturing method of the printed wiring board 100 includes a preparation step S1, an electroless plating step S2, a resist pattern formation step S3, an electrolytic plating step S4, a resist pattern removal step S5, and an etching step S6.

[0043] In the preparation step S1, the base film 10 is prepared. In the base film 10 prepared in the preparation step S1, the seed layer 22a is disposed on the main surface 10a and the main surface 10b. In the preparation step S1, after the base film 10 is prepared, through holes are formed in the base film 10 and the seed layer 22a. The formation of the through holes is performed, for example, by laser processing, drill processing, or the like.

[0044] FIG. 5 is a cross-sectional view for explaining the electroless plating step S2. As shown in FIG. 5, in the electroless plating step S2, an electroless plating layer 22b is formed on the seed layer 22a by performing electroless plating. At this time, the electroless plating layer 22b is also formed on the inner wall surface of the through holes formed in the preparation step S1.

[0045] FIG. 6 is a cross-sectional view for explaining the resist pattern forming step S3. As shown in FIG. 6, in the resist pattern forming step S3, a resist pattern 30 is formed on the electroless plating layer 22b (on the base layer 22). The resist pattern 30 has a first surface 30a and a second surface 30b. The first surface 30a faces the base layer 22. The second surface 30b is the opposite surface of the first surface 30a. The resist pattern 30 has an opening 31. The base layer 22 is partially exposed from the opening 31.

[0046] Let the opening width of the opening 31 on the first surface 30a be the opening width W4. Let the opening width of the opening 31 on the second surface 30b be the opening width W4. The opening width W4 is larger than the opening width W5. That is, the opening 31 has an inverse taper shape.

[0047] In the resist pattern forming step S3, first, a laminate 32 is disposed on the base layer 22. The laminate 32 is formed by laminating a plurality of dry film resists 33. Let the height of the laminate 32 (resist pattern 30) be the height H2. The height H2 is larger than the height H1. The height H2 is, for example, 60 μm or more. In the example shown in FIG. 6, the number of dry film resists 33 included in the laminate 32 is three, but the number of dry film resists 33 included in the laminate 32 is not limited to this.

[0048] In the resist pattern forming step S3, second, exposure and development of the laminate 32 are performed. As a result, for example, the exposed portion is removed to form the opening 31, and the laminate 32 becomes the resist pattern 30. The inverse taper shape of the opening 31 is formed, for example, by adjusting exposure conditions (such as the focus position).

[0049] In the resist pattern forming step S3, after the resist pattern 30 is formed, the surface of the base layer 22 exposed from the opening 31 is cleaned using plasma. Thereby, the contamination on the surface of the base layer 22 exposed from the opening 31 generated during development is removed.

[0050] Figure 7 is a cross-sectional view illustrating the electroplating process S4. As shown in Figure 7, in the electroplating process S4, the first electroplating layer 23 is formed on the portion of the underlayer 22 exposed from the opening 31. Figure 8 is a cross-sectional view illustrating the resist pattern removal process S5. As shown in Figure 8, in the resist pattern removal process S5, the resist pattern 30 is removed.

[0051] In etching step S6, the portion of the underlayer 22 that was beneath the resist pattern 30 is removed by etching. As a result, the structure of the printed circuit board 100 shown in Figures 1 to 3 is formed.

[0052] <Effects of Printed Wiring Board 100> The effects of printed wiring board 100 will be explained below in comparison with the comparative examples. The printed wiring board according to the first comparative example will be referred to as printed wiring board 200. The printed wiring board according to the second comparative example will be referred to as printed wiring board 300.

[0053] Figure 9 is a cross-sectional view illustrating the resist pattern formation step S3 in the manufacturing method of the printed circuit board 200. As shown in Figure 9, in the resist pattern formation step S3 in the manufacturing method of the printed circuit board 300, the opening 31 is formed such that the opening width W4 and the opening width W5 are approximately equal.

[0054] In order to reduce the electrical resistance of wiring 20 and wiring 21, it is necessary to increase the height H1. To do this, it is necessary to increase the height H2. As described above, after forming the resist pattern 30 and before forming the first electroplating layer 23, plasma cleaning is performed on the portion of the base layer 22 exposed from the opening 31. However, if the height H2 is large, the plasma collides with the inner wall surface of the opening 31 and has difficulty reaching the base layer 22. If the cleaning of the portion of the base layer 22 exposed from the opening 31 is insufficient, it can cause voids to form at the interface between the base layer 22 and the first electroplating layer 23, and these voids can cause the first electroplating layer 23 to peel off from the base layer 22.

[0055] In the resist pattern formation step S3 of the manufacturing method of the printed circuit board 100, the opening 31 is formed such that the opening width W4 is larger than the opening width W5. As a result, the plasma used for cleaning is less likely to collide with the inner wall surface of the opening 31 and can easily reach the base layer 22. Therefore, the printed circuit board 100 can suppress the generation of voids at the interface between the base layer 22 and the first electroplating layer 23.

[0056] Figure 10 is a cross-sectional view illustrating the resist pattern formation step S3 in the manufacturing method of the printed circuit board 300. As shown in Figure 10, in the resist pattern formation step S3 in the manufacturing method of the printed circuit board 300, a resist pattern 30 is formed by exposing and developing a single dry film resist 33.

[0057] A dry film resist 33 with a greater thickness retains more solvent compared to a dry film resist 33 with a smaller thickness, making it more prone to bleeding during exposure. As a result, when a resist pattern 30 with a large height H2 is formed using a single dry film resist 33, the inner wall surface of the opening 31 protrudes. If the inner wall surface of the opening 31 protrudes, even if the opening width W4 is larger than the opening width W5, the plasma used for cleaning may collide with the protruding inner wall surface of the opening 31, potentially resulting in insufficient cleaning of the exposed portion of the underlying layer 22 from the opening 31. Therefore, compared to the printed circuit board 300, the printed circuit board 100 can suppress the generation of voids at the interface between the underlying layer 22 and the first electroplating layer 23.

[0058] The shape of the opening 31 is reflected in the shape of the first electroplating layer 23. Therefore, if the inner wall surface of the opening 31 protrudes, the deviation of the cross-sectional shape of the first electroplating layer 23 from a trapezoidal shape becomes large. In other words, when a resist pattern 30 with a large height H2 is formed with a single dry film resist 33, as in the manufacturing method of the printed circuit board 300, the first electroplating layer 23 narrows near position P, and the difference between the width W3 and the average value of widths W1 and W2 becomes large (specifically, the width W3 becomes less than 0.91 times the average value of widths W1 and W2). From another perspective, if the width W3 is between 0.91 times and 1 time the average value of widths W1 and W2, it can be seen that the first electroplating layer 23 is formed with a resist pattern 30 having an opening 31 whose inner wall surface does not protrude.

[0059] <Example> Samples 1 to 6 were prepared to evaluate the effect of the ratio of width W3 to the average values ​​of widths W1 and W2. In samples 1 to 6, the ratio of width W3 to the average values ​​of widths W1 and W2 was changed. The ratio of width W3 to the average values ​​of widths W1 and W2 is shown in the "Ratio" column in the table and is calculated by dividing width W3 by the average values ​​of widths W1 and W2. In samples 1 to 6, width W1, width W2, height H1, and height of position P were kept constant. In samples 1 to 6, the electrolytic plating process S4 was performed using a resist pattern 30 with a height H2 of 150 μm, which was formed by laminating three dry film resists with a thickness of 50 μm. Details of samples 1 to 6 are shown in Table 1.

[0060]

[0061] For samples 1 through 6, the void ratio at the interface between the underlayer 22 and the first electroplating layer 23 was measured, and the presence or absence of delamination of wiring 20 and wiring 21 was observed. These results are shown in the "Void Ratio" and "Circuit Delamination" columns in the table. As shown in Table 1, delamination of wiring 20 and wiring 21 occurred in samples 1 and 2. On the other hand, delamination of wiring 20 and wiring 21 did not occur in samples 3 through 6. In samples 3 through 6, the void ratio at the interface between the underlayer 22 and the first electroplating layer 23 was smaller than in samples 1 and 2.

[0062] In samples 1 and 2, the ratio of width W3 to the average values ​​of widths W1 and W2 was less than 0.91. On the other hand, in samples 3 to 6, the ratio of width W3 to the average values ​​of widths W1 and W2 was within the range of 0.91 to 1. From this comparison, it became clear that by setting width W3 to 0.91 to 1 times the average values ​​of widths W1 and W2, the void ratio at the interface between the base layer 22 and the first electroplating layer 23 is reduced, and peeling of wiring 20 and wiring 21 is suppressed.

[0063] Samples 7 and 8 were prepared to evaluate the effect of forming the resist pattern 30 by laminating multiple dry film resists. In Sample 7, a resist pattern 30 with a height H2 of 150 μm was formed from a single dry film resist. In Sample 8, a resist pattern 30 with a height H2 of 150 μm was formed by laminating three dry film resists with a thickness of 50 μm. In Samples 7 and 8, the width W1, width W2, height H1, and position P height were kept constant. Details of Samples 7 and 8 are shown in Table 2.

[0064]

[0065] In sample 7, the inner wall surface of the opening 31 protruded, making it impossible to keep the ratio of width W3 to the average values ​​of widths W1 and W2 within the range of 0.91 to 1. As a result, in sample 7, the void ratio at the interface between the base layer 22 and the first electroplating layer 23 increased, causing the wiring 20 and wiring 21 to peel off. On the other hand, in sample 8, the protrusion of the inner wall surface of the opening 31 was suppressed, making it possible to keep the ratio of width W3 to the average values ​​of widths W1 and W2 within the range of 0.91 to 1. As a result, in sample 8, the void ratio at the interface between the base layer 22 and the first electroplating layer 23 decreased, suppressing the peeling of wiring 20 and wiring 21. This comparison revealed that forming the resist pattern 30 using multiple dry film resists suppresses the protrusion of the inner wall surface of the opening 31, reduces the void ratio at the interface between the base layer 22 and the first electroplating layer 23, and suppresses the peeling of the wiring 20 and wiring 21.

[0066] (Second Embodiment) A printed circuit board according to the second embodiment will be described. The printed circuit board according to the second embodiment will be referred to as printed circuit board 100A. Here, the differences from printed circuit board 100 will be mainly described, and redundant explanations will not be repeated.

[0067] Figure 11 is a cross-sectional view of the printed circuit board 100A. As shown in Figure 11, each of the wirings 20 and 21 further has a second electroplating layer 25. The second electroplating layer 25 covers the side surface of the underlayer 22, the side surface of the first electroplating layer 23, and the top surface of the first electroplating layer 23. The second electroplating layer 25 is made of, for example, copper or a copper alloy. The height of each of the wirings 20 and 21 is denoted as height H3. The height H3 is, for example, 120 μm or more and 300 μm or less. With the printed circuit board 100A, the cross-sectional area of ​​the wirings 20 and 21 is increased by the second electroplating layer 25, making it possible to reduce the resistance of the wirings 20 and 21.

[0068] Figure 12 is a diagram illustrating the manufacturing process of the printed circuit board 100A. As shown in Figure 12, the manufacturing method of the printed circuit board 100A further includes an electroplating step S7. The electroplating step S7 is performed after the etching step S6. In the electroplating step S7, a second electroplating layer 25 is formed by electroplating so as to cover the sides of the underlayer 22, the sides of the first electroplating layer 23, and the top surface of the first electroplating layer 23. This forms the structure of the printed circuit board 100A shown in Figure 11.

[0069] The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of the present invention is indicated by the claims rather than by the embodiments described above, and all modifications within the meaning and scope of equivalents of the claims are intended to be included.

[0070] 100 Printed circuit board, 10 Base film, 10a Main surface, 10b Main surface, 20 Wiring, 20a Coil section, 20b, 20c Land, 21 Wiring, 21a Coil section, 21b, 21c Land, 22 Underlayer, 22a Seed layer, 22b Electroless plating layer, 23 First electrolytic plating layer, 24a, 24b Wiring section, 25 Second electrolytic plating layer, 30 Resist pattern, 30a First surface, 30b Second surface, 31 Opening, 32 Laminate, 33 Dry film resist, 100A Printed circuit board, 200, 300 Printed circuit board, DIS Distance, H1, H2, H3 Height, P Position, S1 Preparation process, S2 Electroless plating process, S3 Resist pattern formation process, S4 Electrolytic plating process, S5 Resist pattern removal process, S6 Etching process, S7 electrolytic plating process, W1, W2, W3 widths, W4, W5 aperture widths.

Claims

1. A printed circuit board comprising a base film having a main surface, and wiring disposed on the main surface, wherein the wiring has a base layer disposed on the main surface and a first electroplating layer disposed on the base layer, the width of the bottom surface of the first electroplating layer is greater than the width of the top surface of the first electroplating layer, and the width of the first electroplating layer at the central position between the top surface and the bottom surface of the first electroplating layer is 0.91 times or more and 1 time or less the average value of the width of the wiring at the top surface of the first electroplating layer and the width of the first electroplating layer at the bottom surface of the first electroplating layer.

2. The printed circuit board according to claim 1, wherein the height of the first electroplating layer is 60 μm or more and 300 μm or less.

3. The printed circuit board according to claim 1 or claim 2, wherein the width of the bottom surface of the first electroplating layer is 10 μm or more and 100 μm or less.

4. The void ratio at the interface between the underlayer and the first electroplating layer is 40 μm. ２ A printed circuit board according to any one of claims 1 to 3, wherein the thickness is less than or equal to / μm.

5. The printed circuit board according to any one of claims 1 to 4, wherein the wiring further comprises a second electroplating layer covering the side surface of the underlayment layer, the side surface of the first electroplating layer, and the top surface of the first electroplating layer.

6. The printed circuit board according to claim 5, wherein the height of the wiring is 120 μm or more and 300 μm or less.

7. The printed circuit board according to any one of claims 1 to 6, wherein the wiring has a first wiring section and a second wiring section that are adjacent to each other, and the minimum distance between the first electroplating layer of the first wiring section and the first electroplating layer of the second wiring section is 20 μm or less.

8. The printed circuit board according to any one of claims 1 to 7, wherein the width of the wiring on the top surface of the first electroplating layer is 0.3 times or more and 0.8 times or less the width of the first electroplating layer on the bottom surface of the first electroplating layer.

9. A method for manufacturing a printed circuit board, comprising the steps of: preparing a base film having a main surface on which a base layer is disposed; forming a resist pattern on the base layer having a first surface facing the base layer and a second surface opposite the first surface, and having openings that partially expose the base layer; forming a first electroplating layer on the portion of the base layer exposed through the openings; removing the resist pattern; and removing the portion of the base layer that was beneath the resist pattern by etching, wherein the step of forming the resist pattern comprises the steps of arranging a laminate formed by stacking a plurality of dry film resists on the base layer, and exposing and developing the laminate to form the openings, and the width of the opening on the first surface is greater than the opening width of the opening on the second surface.

10. The method for manufacturing a printed circuit board according to claim 9, wherein the height of the laminate is 60 μm or more, and the laminate has three or more dry film resists.

11. The method for manufacturing a printed circuit board according to claim 9 or 10, further comprising the step of cleaning the surface of the underlying layer exposed from the opening using plasma after the resist pattern has been formed but before the first electroplating layer has been formed.

12. A method for manufacturing a printed circuit board according to any one of claims 9 to 11, further comprising the step of forming a second electroplating layer that covers the side surface of the underlayer, the side surface of the first electroplating layer, and the top surface of the first electroplating layer after forming the first electroplating layer.

Images