Defect detection device and distance measurement device

Abstract

[Problem] To quickly and accurately detect a defect occurrence location by using a simple circuit configuration. [Solution] This defect detection device comprises a holding circuit that holds a target signal for defect detection, among a plurality of signals that are used for light emission control of a light emission element, at a timing at which the logic of at least one signal other than the target signal for defect detection changes.

Description

Defect detection device and distance measurement device

[0001] The present disclosure relates to a defect detection device and a distance measurement device.

[0002] A VCSEL (Vertical Cavity Surface Emitting Laser) in which a plurality of light-emitting elements are arranged in a two-dimensional direction can scan the light-emitting direction without a scanning device, and thus is expected to be applied to autonomous driving technology and the like.

[0003] In a VCSEL, it is necessary to route a large number of fine wiring patterns connected to a plurality of light-emitting elements on a semiconductor substrate, and there is a risk of defects such as disconnection and short-circuit of the wiring patterns.

[0004] When defects such as disconnection and short-circuit of the wiring pattern occur, light emission defects occur in which each light-emitting element does not emit light at a desired light emission luminance and at a desired light emission timing. Therefore, a technique for accurately and simply identifying a defective location is desired.

[0005] Patent Document 1 discloses a detection unit that generates a detection value based on outputs of a plurality of wirings, and an abnormality determination unit that determines an abnormality of the plurality of wirings according to a comparison result between the detection value of the detection unit and an expected value preset according to inputs to the plurality of wirings.

[0006] Japanese Unexamined Patent Application Publication No. 2007-316020

[0007] The technique of Patent Document 1 requires an expected value comparison table in which expected values are registered in advance. Also, a reference clock is required when comparing with the expected value using the expected value comparison table. Furthermore, it is necessary to provide a test period for comparing with the expected value. Also, since the comparison of a plurality of signals with the expected value is performed collectively, it is difficult to identify the location where an abnormality occurs.

[0008] Therefore, the present disclosure provides a defect detection device and a distance measurement device that can quickly and accurately detect a defective location with a simple circuit configuration.

[0009] To solve the above problems, the present disclosure provides a fault detection device that includes a holding circuit that holds one of the multiple signals used to control the light emission of a light-emitting element, which is the signal to be faulty, at the timing when the logic of one or more signals other than the signal to be faulty changes.

[0010] The system may include multiple holding circuits, each of which may hold a different fault detection target signal from among the multiple signals at the timing when the logic of one or more signals other than the fault detection target changes.

[0011] The holding circuit may hold the fault detection target signal at the timing when the logic of one signal other than the fault detection target changes, or at the timing when the logic of a signal obtained by combining two or more signals other than the fault detection target changes.

[0012] The signal to be detected as faulty may include at least one of the following: a first signal that instructs the emission of light from a plurality of the light-emitting elements; a second signal that specifies a drive period for sequentially driving the plurality of light-emitting elements arranged in at least one direction; or a third signal that specifies a drive period for sequentially driving all of the plurality of light-emitting elements arranged in at least one direction.

[0013] The holding circuit may hold the first signal at the timing when the logic of one or more signals other than the first signal among the plurality of signals changes.

[0014] The holding circuit may hold the first signal at the timing when the second signal changes from first logic to second logic.

[0015] The holding circuit may change the logic of the holding signal when the first signal is fixed high or low, by holding the first signal at the timing when the logic of the second signal, or a signal obtained by combining the second signal and the third signal, changes.

[0016] The holding circuit may hold the second signal at the timing when the logic of one or more signals other than the second signal among the plurality of signals changes.

[0017] The holding circuit may hold the second signal at the timing when the logic of the third signal changes.

[0018] The holding circuit may hold the second signal at the timing when the logic of the first signal changes.

[0019] The holding circuit may hold the third signal at the timing when the logic of one or more signals other than the third signal among the plurality of signals changes.

[0020] The holding circuit may change the logic of the holding signal when the number of times the logic of the second signal has changed exceeds a predetermined number of times.

[0021] The holding circuit may hold the third signal at the timing when the logic of the second signal changes.

[0022] The holding circuit may hold a fourth signal, which indicates whether or not the light emission control circuit that controls the light emission of the light-emitting element performs light emission control of the light-emitting element, at the timing when the logic of the signals other than the fourth signal among the plurality of signals changes.

[0023] The holding circuit may hold the fourth signal at the timing when the logic of the third signal changes.

[0024] A fault detection circuit may be provided that determines whether the signal to be detected as faulty is faulty or not based on the holding signal of the holding circuit.

[0025] The fault detection circuit may determine whether the signal to be detected as faulty has at least one fault, such as being fixed low, fixed high, or short-circuited with another signal.

[0026] According to this disclosure, a fault detection device is provided which includes a holding circuit that inputs the signal to be faulty to a data input terminal, inputs the other signals to a clock node, and holds the signal to be faulty at the rising or falling edge of the other signals, among a plurality of signals used to control the light emission of a light-emitting element.

[0027] The signal to be detected as faulty may include at least one of the following: a first signal that instructs the emission of light from a plurality of the light-emitting elements; a second signal that specifies a drive period for sequentially driving the plurality of light-emitting elements arranged in at least one direction; or a third signal that specifies a drive period for sequentially driving all of the plurality of light-emitting elements arranged in at least one direction.

[0028] According to this disclosure, a distance measuring device is provided, comprising: a light-emitting element that emits light toward an object; a light-emitting control circuit that controls the emission of light from the light-emitting element; and a distance measuring unit that receives light reflected by the object and measures the distance to the object, wherein the light-emitting control circuit has a holding circuit that holds the signal to be detected as faulty among a plurality of signals used to control the emission of light from the light-emitting element at the timing when the logic of the signals other than the signal to be detected as faulty changes.

[0029] Circuit diagram of a light-emitting device according to one embodiment. Cross-sectional view showing an example of the cross-sectional structure of a light-emitting device with a VCSEL structure. Block diagram of a fault detection device according to the first embodiment. Timing diagram of a light-emitting device. Circuit diagram of a fault detection circuit according to the first example of the first embodiment. Timing diagram when the light-emitting signal is normal. Timing diagram when the light-emitting signal malfunctions and is fixed at high. Timing diagram for detecting a fault in the light-emitting signal that is fixed at low. Circuit diagram of a fault detection circuit according to the second example of the first embodiment. Timing diagram when the light-emitting signal is normal. Timing diagram when the light-emitting signal malfunctions and is fixed at low. Timing diagram for detecting a fault in the horizontal synchronization signal that is fixed at high. Circuit diagram of a fault detection circuit according to the third example of the first embodiment. Timing diagram when the horizontal synchronization signal is normal. Timing diagram when the horizontal synchronization signal malfunctions and is fixed at high. Timing diagram for detecting a fault in the horizontal synchronization signal that is fixed at low. Circuit diagram of a fault detection circuit according to the fourth example of the first embodiment. Timing diagram when the horizontal synchronization signal is normal. Timing diagram when the horizontal synchronization signal malfunctions and is fixed at low. Timing diagram for detecting a fault in the vertical synchronization signal that is fixed at high. Circuit diagram of a fault detection circuit according to the fifth example of the first embodiment. Timing diagram when the vertical synchronization signal is normal. Timing diagram when the vertical synchronization signal is fixed high. Timing diagram for detecting a fault where the vertical synchronization signal is fixed low. Circuit diagram of a fault detection circuit according to the sixth example of the first embodiment. Timing diagram when the vertical synchronization signal is normal. Timing diagram when the vertical synchronization signal is fixed low. Timing diagram of a fault detection circuit according to the first embodiment that can detect faults in the high and low fixed states of the light emission signal, the high and low fixed states of the horizontal synchronization signal, and the high and low fixed states of the vertical synchronization signal. Flowchart showing the processing operation of a fault detection device according to the first embodiment that can detect faults in the high and low fixed states of the light emission signal, the high and low fixed states of the horizontal synchronization signal, and the high and low fixed states of the vertical synchronization signal. Circuit diagram of a fault detection circuit according to the first example of the second embodiment. Timing diagram when the Enable signal is normal. Timing diagram when the Enable signal is fixed high. Timing diagram of a fault detection circuit that has a function to detect a low fault in the Enable signal. Circuit diagram of a fault detection circuit according to a second example of the second embodiment. Timing diagram when the Enable signal is normal. Timing diagram when the Enable signal is fixed low.A timing diagram of a fault detection circuit according to a second embodiment, capable of detecting faults in the high and low fixed positions of the light emission signal, the high and low fixed positions of the horizontal synchronization signal, the high and low fixed positions of the vertical synchronization signal, and the high and low fixed positions of the Enable signal. A flowchart showing the processing operation of a fault detection device according to a first embodiment, capable of detecting faults in the high and low fixed positions of the light emission signal, the high and low fixed positions of the horizontal synchronization signal, the high and low fixed positions of the vertical synchronization signal, and the high and low fixed positions of the Enable signal. A block diagram showing the schematic configuration of a distance measuring device incorporating a fault detection device according to a third embodiment. A block diagram showing an example of the configuration of a distance measuring device. An explanatory diagram of the STL method. An explanatory diagram of the distance measuring principle of the STL method. A block diagram showing an example of the schematic configuration of a vehicle control system. An explanatory diagram showing an example of the installation position of the external information detection unit and the imaging unit.

[0030] The embodiments of the fault detection device and the distance measuring device will be described below with reference to the drawings. The following description will focus on the main components of the fault detection device and the distance measuring device, but there may be components and functions not shown or described. The following description does not exclude any components or functions not shown or described.

[0031] A defect detection device according to one embodiment of this disclosure is, for example, built into a light-emitting device. The light-emitting device has, for example, a plurality of light-emitting elements arranged in a two-dimensional direction and a light-emitting control unit. The plurality of light-emitting elements are, for example, VCSELs. The light-emitting control unit controls the light emission timing of the plurality of light-emitting elements. The defect detection device according to one embodiment is provided, for example, inside the light-emitting control unit.

[0032] Figure 1 is a circuit diagram of a light-emitting device 30 according to one embodiment. As shown in Figure 1, the light-emitting device 30 according to one embodiment comprises a plurality of light-emitting elements 20 arranged in a two-dimensional array, and a plurality of transistors electrically connected to these light-emitting elements 20. These transistors are, for example, N-type MOS transistors. Figure 1 shows an example in which the light-emitting device 30 according to one embodiment comprises 9 × 9 light-emitting elements 20 and 9 × 9 transistors. Therefore, the light-emitting device 30 shown in Figure 1 comprises a 9ch (channel) × 9ch light-emitting element array. The number of channels in the light-emitting element array is arbitrary.

[0033] A light-emitting device 30 according to one embodiment further comprises, as shown in Figure 1, a first anode wiring 31, a second anode wiring 32, a third anode wiring 33, a plurality of first capacitors 34, a plurality of second capacitors 35, a plurality of third capacitors 36, a first selection circuit 37, a second selection circuit 38, a third selection circuit 39, a plurality of cathode wirings 41, and a plurality of gate wirings 42. The first to third anode wirings 31 to 33 are examples of first terminal wirings of the present disclosure, and the cathode wiring 41 is an example of second terminal wirings of the present disclosure. The first to third capacitors 34 to 36 are examples of first to M capacitors of the present disclosure, and the first to third selection circuits 37 to 39 are examples of first to M selection circuits of the present disclosure (M is an integer of 2 or more). Figure 1 shows an example where M is 3.

[0034] The first terminal wiring includes M first wires (M is an integer of 2 or more) 31a, 32a, 33a extending in a first direction X, and N second wires (N is an integer of 2 or more) 31b, 32b, 33b extending in a second direction Y intersecting the first direction X and electrically connected to the M first wires 31a, 32a, 33a, respectively. Figure 1 shows an example where M = N = 3. The first terminal wiring is electrically connected to the first terminals of a plurality of light-emitting elements 20. In this specification, the first wires 31a and 31b connected to each other are called the first anode wiring 31, the first wires 32a and 32b connected to each other are called the second anode wiring 32, and the third wires 33a and 33b connected to each other are called the third anode wiring 33. In this specification, the first direction X may also be called the lateral direction, and the second direction Y may be called the vertical direction. Furthermore, in the following, the first terminal wiring and one of the multiple second terminal wirings may be referred to as the anode wiring, and the other of the first terminal wiring and the multiple second terminal wirings may be referred to as the cathode wiring.

[0035] In one embodiment, the light-emitting device 30 includes first to third anode wirings 31 to 33 in sets of L (where L is an integer of 1 or more), where L is the first to third anode wiring. Figure 1 shows an example where L = 5.

[0036] Each of the five sets of first anode wiring 31 has a plurality (e.g., five) of first wirings 31a that extend in a first direction X (lateral direction) and are arranged along a second direction Y (vertical direction), and a plurality (e.g., five) of second wirings 31b that extend in a second direction Y (vertical direction) and are arranged along a first direction X (lateral direction). In this specification, the first wiring 31a may be referred to as the first lateral wiring 31a, and the second wiring 31b may be referred to as the first vertical wiring 31b.

[0037] Each of the five sets of second anode wiring 32 has a plurality (e.g., five) of first wiring 32a that extends in a first direction X (lateral direction) and is arranged along a second direction Y (vertical direction), and a plurality (e.g., five) of second wiring 32b that extends in a second direction Y (vertical direction) and is arranged along a first direction X (lateral direction). In this specification, the first wiring 32a may be referred to as the second lateral wiring 32a, and the second wiring 32b may be referred to as the second vertical wiring 32b.

[0038] Each of the five sets of third anode wiring 33 comprises a plurality (e.g., five) of first wiring 33a extending in a first direction X (lateral direction) and arranged along a second direction Y (vertical direction), and a plurality (e.g., five) of second wiring 33b extending in a second direction Y (vertical direction) and arranged along a first direction X (lateral direction). In this specification, the first wiring 33a may be referred to as the third lateral wiring 33a, and the second wiring 33b may be referred to as the third vertical wiring 33b.

[0039] Figure 1 shows an example of a light-emitting device 30 according to one embodiment, comprising five first horizontal wires 31a, five first vertical wires 31b, five second horizontal wires 32a, five second vertical wires 32b, five third horizontal wires 33a, and five third vertical wires 33b. Figure 1 shows an example in which M first wires and N second wires are provided in L sets. The number of light-emitting elements 20 shown in Figure 1 is M(L-2) × N(L-2) when expressed as L, M, and N.

[0040] The first to third anode wirings 31 to 33 may include the first to M horizontal wirings of the La group and the first to N vertical wirings of the Lb group (La and Lb are integers of 2 or more satisfying La ≠ Lb). In this case, the number of light-emitting elements 20 of the light-emitting device 30 will be M(La-2) × N(Lb-2).

[0041] The first selection circuit 37 includes transistors 37a and 37b connected in series. Similarly, the second selection circuit 38 includes transistors 38a and 38b connected in series. Similarly, the third selection circuit 39 includes transistors 39a and 39b connected in series. Transistors 37a, 38a, and 39a are, for example, P-type MOS transistors. Transistors 37b, 38b, and 39b are, for example, N-type MOS transistors. Transistors 37a, 38a, and 39a are examples of the first switch of this disclosure. Transistors 37b, 38b, and 39b are examples of the second switch of this disclosure.

[0042] [First to Third Anode Wiring 31-33] In Figure 1, to distinguish the first to third anode wirings 31-33 from each other, the first anode wiring 31 is shown with a thick solid line, the second anode wiring 32 with a thick dashed line, and the third anode wiring 33 with a thin solid line.

[0043] The first anode wiring 31 has a structure in which a plurality of first horizontal wirings 31a and a plurality of first vertical wirings 31b are arranged in a mesh shape. These first horizontal wirings 31a and first vertical wirings 31b are electrically connected to each other at locations where the first horizontal wiring 31a and the first vertical wiring 31b intersect. Similarly, the second anode wiring 32 includes a plurality of second horizontal wirings 32a and a plurality of second vertical wirings 32b that are electrically connected to each other, and the third anode wiring 33 includes a plurality of third horizontal wirings 33a and a plurality of third vertical wirings 33b that are electrically connected to each other. On the other hand, the first to third anode wirings 31 to 33 are electrically insulated from each other.

[0044] The first to third horizontal wirings 31a to 33a extend in the first direction X (horizontal direction) and are adjacent to each other in the second direction Y (vertical direction). In FIG. 1, the first to third horizontal wirings 31a to 33a extend linearly in the first direction X, but they may extend curvilinearly in the first direction X. That is, the first to third horizontal wirings 31a to 33a may include bent portions.

[0045] On the other hand, the first to third vertical wirings 31b to 33b extend in the second direction Y and are adjacent to each other in the first direction X. In FIG. 1, the first to third vertical wirings 31b to 33b extend linearly in the second direction Y, but they may extend curvilinearly in the second direction Y. That is, the first to third vertical wirings 31b to 33b may also include bent portions.

[0046] FIG. 1 shows five sets of the first to third horizontal wirings (first wirings) 31a to 33a. In FIG. 1, the first to third horizontal wirings 31a to 33a of the first set, second set, third set, fourth set, and fifth set are arranged in order from top to bottom. In each set, the first horizontal wiring 31a, the second horizontal wiring 32a, and the third horizontal wiring 33a are arranged in order from top to bottom. The first to third horizontal wirings 31a to 33a of the first set and the first to third horizontal wirings 31a to 33a of the fifth set are arranged so as to sandwich 9×9 light-emitting elements 20. Each of the first to third horizontal wirings 31a to 33a of the second to fourth sets is arranged along one row (nine) of the light-emitting elements 20.

[0047] FIG. 1 further shows five sets of first to third vertical wirings (second wirings) 31b to 33b. In FIG. 1, the first to third vertical wirings 31b to 33b of the first set, the second set, the third set, the fourth set, and the fifth set are arranged in order from left to right. In each set, the first vertical wiring 31b, the second vertical wiring 32b, and the third vertical wiring 33b are arranged in order from left to right. The first to third vertical wirings 31b to 33b of the first set and the first to third vertical wirings 31b to 33b of the fifth set are arranged so as to sandwich 9×9 light-emitting elements 20. Each of the first to third vertical wirings 31b to 33b of the second to fourth sets is arranged along one row (nine) of the light-emitting elements 20.

[0048] The anode of each light-emitting element 20 is electrically connected to any one of the first to third vertical wirings 31b to 33b. For example, the light-emitting element 20 in the leftmost column is electrically connected to the first vertical wiring 31b within the first to third vertical wirings 31b to 33b of the second set. Also, the light-emitting element 20 in the rightmost column is electrically connected to the third vertical wiring 33b within the first to third vertical wirings 31b to 33b of the fourth set. Note that, instead of being electrically connected to any one of the first to third vertical wirings 31b to 33b, the anode of each light-emitting element 20 may be electrically connected to any one of the first to third horizontal wirings 31a to 33a. The anode is an example of the first terminal of the present disclosure.

[0049] [Cathode Wiring 41] Each cathode wiring 41 extends in the first direction X and is electrically connected to the cathodes of three light-emitting elements 20. Specifically, each cathode wiring 41 is electrically connected to one light-emitting element 20 electrically connected to the first vertical wiring 31b, one light-emitting element 20 electrically connected to the second vertical wiring 32b, and one light-emitting element 20 electrically connected to the third vertical wiring 33b. These three light-emitting elements 20 are adjacent to each other in the first direction X. FIG. 1 shows 27 cathode wirings 41 for 81 light-emitting elements 20. The cathode is an example of the second terminal of the present disclosure. The number of light-emitting elements 20 connected to each cathode wiring 41 is not limited to three. As long as the cathodes of P (P is an integer of 2 or more) light-emitting elements 20 are electrically connected to each cathode wiring 41.

[0050] In the above description, an example was given in which multiple light-emitting elements 20 are connected to the first to M horizontal wiring, the first to N vertical wiring, and a plurality of P electrically connected second terminal wirings. However, the light-emitting device according to this disclosure does not need to have all of the first to M horizontal wiring, the first to N vertical wiring, and the plurality of P electrically connected second terminal wirings. For example, a configuration in which multiple light-emitting devices are connected to the first to M horizontal wiring, a single vertical wiring, and a single second terminal wiring is also possible.

[0051] Each light-emitting element 20 is provided between a corresponding anode wire, i.e., one of the first to third anode wires 31 to 33, and a corresponding cathode wire, i.e., one of the multiple cathode wires 41. Each light-emitting element 20 emits light when current flows between the corresponding anode wire and the corresponding cathode wire.

[0052] [Gate Wiring 42] Each gate wire 42 extends in a first direction X and is electrically connected to the gates of three transistors. The sources of these three transistors are electrically connected to the ground wire (GND), and the drains of these three transistors are electrically connected to the same single cathode wire 41. These three transistors form a single drive circuit E. Figure 1 shows 27 gate wires 42 for 81 transistors.

[0053] Each drive circuit E is electrically connected to the cathodes of three light-emitting elements 20 via a single cathode wire 41. Each drive circuit E (output stage) E is used to drive the light-emitting elements 20 and generate (output) light from them. For example, to generate light from a certain light-emitting element 20, a predetermined signal is applied to the gate wire 42 of the drive circuit E for that light-emitting element 20. This causes the source and drain of each transistor in the drive circuit E to conduct, making it possible to flow current through the light-emitting element 20. When current flows through the light-emitting element 20, light is generated from it. The light-emitting device 30 shown in Figure 1 is equipped with 27 drive circuits E for 81 light-emitting elements 20.

[0054] [First to Third Selection Circuits 37-39] The first to third selection circuits 37-39 are each electrically connected to the first to third horizontal wirings 31a-33a of the first to third anode wirings 31-33. The first selection circuit 37 is used to select the light-emitting element 20 electrically connected to the first anode wiring 31 as the light-emitting element 20 that generates light. The second selection circuit 38 is used to select the light-emitting element 20 electrically connected to the second anode wiring 32 as the light-emitting element 20 that generates light. The third selection circuit 39 is used to select the light-emitting element 20 electrically connected to the third anode wiring 33 as the light-emitting element 20 that generates light. The first to third selection circuits 37-39 may each be electrically connected to the first to third vertical wirings 31b-33b of the first to third anode wirings 31-33 instead of the first to third horizontal wirings 31a-33a of the first to third anode wirings 31-33.

[0055] The first selection circuit 37 includes a transistor 37a having a source electrically connected to the power supply wiring (VDD) and a transistor 37b having a source electrically connected to the ground wiring. The drains of transistor 37a and transistor 37b are electrically connected to the first anode wiring 31. The first selection circuit 37 is electrically connected to each first capacitor 34 via the first anode wiring 31.

[0056] Transistor 37a is used to store charge in each first capacitor 34. Transistor 37b is used to discharge charge from each first capacitor 34. When a predetermined signal is applied to the gate of transistor 37a, charge is stored in each first capacitor 34. When a predetermined signal is applied to the gate of transistor 37b, charge is discharged from each first capacitor 34. Therefore, according to this embodiment, by selectively storing charge in the first capacitor 34 among the first to third capacitors 34 to 36 using the first selection circuit 37, current can be supplied to each light-emitting element 20 electrically connected to the first anode wiring 31.

[0057] The structures of the second and third selection circuits 38 and 39 are the same as those of the first selection circuit 37, as shown in Figure 1. Therefore, according to this embodiment, by accumulating charge in each second capacitor 35 using the second selection circuit 38, current can be supplied to each light-emitting element 20 electrically connected to the second anode wiring 32. Furthermore, according to this embodiment, by accumulating charge in each third capacitor 36 using the third selection circuit 39, current can be supplied to each light-emitting element 20 electrically connected to the third anode wiring 33.

[0058] [First to Third Capacitors 34-36] The first to third capacitors 34-36 are each electrically connected to the first to third anode wirings 31-33. Each first capacitor 34 stores charge to be supplied to the light-emitting element 20 electrically connected to the first anode wiring 31. Each second capacitor 35 stores charge to be supplied to the light-emitting element 20 electrically connected to the second anode wiring 32. Each third capacitor 36 stores charge to be supplied to the light-emitting element 20 electrically connected to the third anode wiring 33. According to this embodiment, current can be supplied to each light-emitting element 20 by supplying charge from the first to third capacitors 34-36 to each light-emitting element 20. Each of the first to third capacitors 34-36 includes one electrode electrically connected to any of the first to third anode wirings 31-33 and the other electrode electrically connected to the ground wiring.

[0059] The light-emitting device 30 shown in Figure 1 includes a light-emitting element array containing 9 × 9 light-emitting elements 20 arranged in a two-dimensional array. The shape of this light-emitting element array is roughly square in plan view, as shown in Figure 1. The light-emitting device 30 shown in Figure 1 includes four sets of first to third capacitors 34 to 36 near the four sides of this square. Specifically, the light-emitting device 30 shown in Figure 1 includes the first set of first to third capacitors 34 to 36 near the top side of the square, the second set of first to third capacitors 34 to 36 near the right side of the square, the third set of first to third capacitors 34 to 36 near the bottom side of the square, and the fourth set of first to third capacitors 34 to 36 near the left side of the square. These first to third capacitors 34 to 36 are examples of the first to Nth capacitors of the K sets of this disclosure (K is an integer of 2 or more). Figure 1 shows an example where K is 4.

[0060] The first and third sets of capacitors 34-36 are electrically connected to the first to third horizontal wirings 31a-33a of the first to third anode wirings 31-33, respectively. On the other hand, the second and fourth sets of capacitors 34-36 are electrically connected to the first to third vertical wirings 31b-33b of the first to third anode wirings 31-33, respectively. As a result, the first to third capacitors 34-36 shown in Figure 1 are electrically connected to the first to third anode wirings 31-33, respectively.

[0061] In each set, the first to third capacitors 34 to 36 are arranged in a clockwise direction. For example, in the first set, the first capacitor 34, the second capacitor 35, and the third capacitor 36 are located on the left, center, and right sides near the top edge of the square, respectively. Similarly, in the second set, the first capacitor 34, the second capacitor 35, and the third capacitor 36 are located on the top, center, and bottom sides near the right edge of the square, respectively. As a result, the four sets of first to third capacitors 34 to 36 shown in Figure 1 are arranged symmetrically with respect to the center of the square. The center of the square is roughly located at the position of the fifth row and fifth column of the 9x9 light-emitting elements 20. In Figure 1, the arrangement of the four sets of first to third capacitors 34 to 36 exhibits four-fold rotational symmetry (90-degree rotational symmetry).

[0062] According to this embodiment, it is possible to set the average distance between each light-emitting element 20 and the corresponding four capacitors to a value close to the average distance between another light-emitting element 20 and the corresponding four capacitors.

[0063] For example, the light-emitting element 20 at the upper left is close to the upper first capacitor 34 but far from the lower first capacitor 34. On the other hand, the light-emitting element 20 at the lower right is close to the right third capacitor 36 but far from the left third capacitor 36. Therefore, the average distance between the light-emitting element 20 at the upper left and the four first capacitors 34 is close to the average distance between the light-emitting element 20 at the lower right and the four third capacitors 36. This is also true for the other 79 light-emitting elements 20. This makes it possible to reduce the impedance difference between the wiring of different light-emitting elements 20 with respect to the anode wiring between each light-emitting element 20 and the four corresponding capacitors.

[0064] In this embodiment, the light-emitting device 30 may be equipped with first to third capacitors 34 to 36 only near one, two, or three of the four sides of the square. However, in this case, it is desirable that the first to third capacitors 34 to 36 are also arranged symmetrically or nearly symmetrically with respect to the center of the square. Therefore, it is desirable that the light-emitting device 30 in this embodiment is equipped with first to third capacitors 34 to 36 on two or more of the four sides of the square. For example, by arranging two sets of first to third capacitors 34 to 36 near the top and bottom sides of the square, it is possible to achieve a 2-fold rotational symmetry (180-degree rotational symmetry) arrangement.

[0065] Figure 2 is a cross-sectional view showing an example of the cross-sectional structure of a VCSEL-structured light-emitting device 30. The light-emitting device 30 in Figure 2 is constructed, for example, by stacking LD (Laser Diode) chips 21 on an LDD (LDD: Laser Diode Driver) substrate 22. In this specification, the LDD substrate 22 may be referred to as the light-emitting control unit 22. The LD chip 21 comprises a substrate 24, a laminated film 25, a plurality of light-emitting elements 20 formed using the laminated film 25, a plurality of anode electrodes 26, and a cathode electrode 27.

[0066] The substrate 24 of the LD chip 21 is a substrate made of a compound semiconductor material such as GaAs (gallium arsenide). The surface of the substrate 24 facing the LDD substrate (light emission control unit) 22 is the front surface S2, and the laser light is emitted from the back surface S3 of the substrate 24. The laminated film 25 includes a first multilayer reflector, a first spacer layer, an active layer, a second spacer layer, and a second multilayer reflector. The laser light generated in the active layer is resonated between the first multilayer reflector and the second multilayer reflector to improve the light intensity, and is emitted from the back surface S3 of the substrate. Thus, the LD chip 21 in Figure 2 is a back-illuminated type. In this specification, a light-emitting element 20 with the layer configuration shown in Figure 2 is called a VCSEL structure.

[0067] The multiple light-emitting elements 20 have a mesa structure formed by processing the laminated film 25 into a mesa shape. Viewed from the substrate 24 side, an anode electrode (second pad) 47 is arranged on the upper surface of each light-emitting element 20. Similarly, viewed from the substrate 24 side, cathode electrodes 27 are arranged on the upper and side surfaces of the laminated film 25 located on the edge side of the LD chip 21. A cathode electrode 27 is also arranged on the bottommost layer side of the laminated film 25 of the multiple light-emitting elements 20, viewed from the substrate 24 side. In Figure 2, the arrangement of the anode electrode 26 and the cathode electrode 27 may be reversed. In Figure 2, the common electrode is the cathode electrode 27, but the common electrode may be the anode electrode 26 and cathode electrodes 27 may be provided on each mesa portion 23.

[0068] The LDD substrate (light emission control unit) 22 has a plurality of pads 29 for supplying drive signals to a plurality of light-emitting elements 20 of the LD chip 21. The pads 29 are arranged along a surface S1 of the LDD substrate (light emission control unit) 22 that is positioned opposite the LD chip 21. A bonding layer 28 is placed on these pads 29, and the pads 29 of the LDD substrate (light emission control unit) 22 are bonded to the pads of the corresponding anode electrodes 26 of the LD chip 21 via the bonding layer 28. The LDD substrate (light emission control unit) 22 has a plurality of drive circuits E as shown in Figure 1.

[0069] The substrate 24 of the LD chip 21 is, for example, a compound semiconductor substrate such as a GaAs (gallium arsenide) substrate. Figure 2 shows the surface S2 of the substrate 24 facing the -Z direction and the back surface S3 of the substrate 24 facing the +Z direction. The surface S2 and back surface S3 shown in Figure 2 are perpendicular to the Z direction. In Figure 2, the surface S2 is the bottom surface of the substrate 24, and the back surface S3 is the top surface of the substrate 24.

[0070] The light-emitting element 20 is provided on the surface S2 of the substrate 24 as part of the laminated film 25. The light-emitting element 20 in this embodiment has a VCSEL structure and emits light in the +Z direction. As shown in Figure 2, the light emitted from the light-emitting element 20 passes through the substrate 24 from the surface S2 to the back surface S3.

[0071] Each light-emitting element 20 is positioned between the anode electrode 26 and the cathode electrode 27, which are connected to the anode wiring 31-33. Each light-emitting element 20 emits light when an electric current flows between the anode electrode 26 and the cathode electrode 27.

[0072] (First Embodiment) The fault detection device according to the first embodiment includes a fault detection circuit. The fault detection device according to the first embodiment detects faults in the signal to be fault detected. Faults include, for example, the signal to be fault detected being fixed high (heaven fault), fixed low (ground fault), or short-circuit with other signals. The fault detection device according to the first embodiment is built into, for example, a light-emitting device.

[0073] Figure 3 is a block diagram of the defect detection device 1 according to the first embodiment. As shown in Figure 3, the defect detection device 1 according to the first embodiment comprises a defect detection circuit 2 and a defect determination circuit 3.

[0074] The fault detection circuit 2 includes a holding circuit that holds the signal to be faulty among the multiple signals used to control the light emission of the light-emitting element 20 at the timing when the logic of one or more signals other than the faulty signal changes. The holding circuit holds the signal to be faulty when the logic of one of the signals other than the faulty signal changes, or when the logic of a signal formed by combining two or more signals other than the faulty signal changes. The fault detection circuit 2 may have multiple holding circuits. In this case, each of the multiple holding circuits holds a different signal to be faulty among the multiple signals at the timing when the logic of one or more signals other than the faulty signal changes.

[0075] The fault detection circuit 3 determines whether the signal to be detected as faulty is faulty based on the output signal of the fault detection circuit 2. If the fault detection circuit 3 determines that the signal to be detected as faulty is faulty, it may notify a host device (not shown) or the like that it is faulty. Alternatively, the fault detection circuit 3 may stop the light emission of the light-emitting device 30, which incorporates the fault detection circuit 2. The fault detection circuit determines whether the signal to be detected as faulty is at least one of the following faults: fixed low, fixed high, or short circuit with another signal.

[0076] The signal to be detected for malfunction includes at least one of the following: a first signal (e.g., a light emission signal) that instructs the emission of light from a plurality of light-emitting elements 20; a second signal (e.g., a horizontal synchronization signal) that specifies a drive period for sequentially driving a plurality of light-emitting elements 20 arranged in at least one direction (e.g., a row direction); or a third signal (e.g., a vertical synchronization signal) that specifies a drive period for sequentially driving all of the plurality of light-emitting elements 20 arranged in at least one direction.

[0077] For example, a holding circuit holds the first signal at the timing when the logic of one or more signals other than the first signal changes. In a specific example, the holding circuit holds the first signal at the timing when the second signal changes from the first logic to the second logic. Alternatively, the holding circuit changes the logic of the holding signal when the first signal is fixed high or low by holding the first signal at the timing when the logic of the second signal, or a signal obtained by combining the second and third signals, changes. Alternatively, the holding circuit holds the second signal at the timing when the logic of one or more signals other than the second signal changes. In a specific example, the holding circuit holds the second signal at the timing when the logic of the third signal changes. Alternatively, the holding circuit holds the second signal at the timing when the logic of the first signal changes. Alternatively, the holding circuit holds the third signal at the timing when the logic of one or more signals other than the third signal changes. In a specific example, the holding circuit changes the logic of the holding signal when the number of times the logic of the second signal has changed exceeds a predetermined number of times. Alternatively, the holding circuit holds the third signal at the timing when the logic of the second signal changes. Alternatively, the holding circuit holds the fourth signal, which indicates whether or not the light emission control circuit will perform light emission control of the light-emitting element, at the timing when the logic of the signals other than the fourth signal among the multiple signals changes. In a specific example, the holding circuit holds the fourth signal at the timing when the logic of the third signal changes.

[0078] The fault detection device 1 has a holding circuit that holds the signal to be faulty among the multiple signals used to control the light emission of the light-emitting element 20 at the timing when the logic of one or more signals other than the faulty signal changes. Below, the fault detection circuits 2 according to the first to sixth examples will be described in order. As will be described later, the fault detection device 1 includes one or any number of fault detection circuits 2 from the fault detection circuits 2 according to the first to sixth examples.

[0079] (Detection of malfunction in fixed high position of light emission signal) Figure 4 is a timing diagram of the light emission device 30, showing the timing for detecting a malfunction in fixed high position of the light emission signal. Figure 4 illustrates the timing waveforms of the vertical synchronization signal, the horizontal synchronization signal, and the light emission signal. The vertical synchronization signal is at a high level during the period when each light-emitting element 20 in the light emission device 30 is sequentially emitting light (times t1 to t6), and temporarily goes low each time all the light-emitting elements 20 in the light emission device 30 have finished emitting light. The horizontal synchronization signal remains high during the emission period of one row of light-emitting elements 20 (times t2 to t4), and temporarily goes low before the next row of light-emitting elements 20 begins emitting light after the light-emitting elements 20 in each row have finished emitting light (times t4 to t5).

[0080] The light emission signal temporarily becomes high level when each light-emitting element 20 is illuminated. The lower part of Figure 7 shows a detailed timing waveform for the period from time t1 to t5.

[0081] When the light-emitting device 30 is operating normally, the light-emitting signal is low when the horizontal synchronization signal transitions from high to low, as shown by the dashed box in Figure 4. However, for some reason, a malfunction may occur where the light-emitting signal remains fixed at high. This malfunction can be detected by holding the light-emitting signal at the timing when the horizontal synchronization signal transitions from high to low. If the held signal is high, it can be determined that there is a malfunction where the light-emitting signal is fixed at high.

[0082] Figure 5 is a circuit diagram of a fault detection circuit 2 according to a first example of the first embodiment. The fault detection circuit 2 according to the first example is characterized by detecting a fault where the light emission signal is fixed high. The fault detection circuit 2 according to the first example shown in Figure 5 has a holding circuit 4, an OR circuit 5, a first inverter 6, and a second inverter 7. The holding circuit 4 is, for example, a D-type flip-flop (hereinafter referred to as D-F / F) 4. The OR circuit 5 outputs a logical OR signal between the light emission signal and the Q node of the D-F / F 4. This logical OR signal is input to the D node of the D-F / F 4. The clock node of the D-F / F 4 is input to a signal obtained by inverting the horizontal synchronization signal with the first inverter 6. The reset node of the D-F / F 4 is input to a signal obtained by inverting the fault reset signal with the second inverter 7. In this manner, the holding circuit (D-F / F) 4 inputs the signal to be detected as faulty from among the multiple signals used to control the light emission of the light-emitting element to the data input terminal, and inputs the signals other than those to be detected as faulty to the clock node, and holds the signal to be detected as faulty on the rising or falling edge of the signals other than those to be detected as faulty.

[0083] D-F / F4 holds the light emission signal when the horizontal synchronization signal transitions from high to low. If the light emission signal is low at this time, the Q signal of D-F / F4 remains low. On the other hand, if the light emission signal is high at this time, the Q signal of D-F / F4 transitions from low to high. Once the Q signal of D-F / F4 becomes high, it remains high until the fault reset signal becomes high.

[0084] A transition of the D-F / F4 Q signal to high indicates that the light emission signal has malfunctioned by remaining fixed at high. Therefore, the D-F / F4 Q signal makes it easy to detect when the light emission signal malfunctions by remaining fixed at high.

[0085] Figures 6A and 6B are timing diagrams of the fault detection circuit 2 in Figure 5. Figure 6A shows the timing when the light emission signal is normal, and Figure 6B shows the timing when the light emission signal malfunctions and is fixed at high. Figures 6A and 6B illustrate the timing waveforms of the vertical synchronization signal, horizontal synchronization signal, light emission signal, and the Q signal TH_SHORT of D-F / F4.

[0086] At time t1, the vertical synchronization signal goes high. The vertical synchronization signal remains high until all light-emitting elements 20 in the light-emitting device 30 have been driven. At time t2, the horizontal synchronization signal goes high. The horizontal synchronization signal remains high until all light-emitting elements 20 in one row have been driven. From time t3, the light-emitting signal periodically goes high, and each light-emitting element 20 in one row is driven sequentially and emits light.

[0087] When the driving of each light-emitting element 20 in one row is complete, the horizontal synchronization signal transitions to low at time t4. When the driving of each light-emitting element 20 in all rows of the light-emitting device 30 is complete, the vertical synchronization signal transitions to low at time t5, and then to high at time t6. After that, the same process as at time t1 is repeated.

[0088] In the fault detection circuit 2 shown in Figure 5, a high fault reset signal is input to the reset node of D-F / F4 during initial setup. As a result, D-F / F4 is reset during initial setup, and the Q signal TH_SHORT becomes low. Therefore, the output of OR circuit 5 becomes the same logic as the light emission signal, and the signal output from OR circuit 5 and input to the D node of D-F / F4 is high only for the period when the light emission signal is high.

[0089] At time t4, when the horizontal synchronization signal transitions from high to low, D-F / F4 holds a signal with the same logic as the light emission signal. Therefore, when the light emission signal is normal, the Q signal TH_SHORT remains low, as shown in Figure 6A. On the other hand, if the light emission signal malfunctions and remains fixed at high, the Q signal TH_SHORT transitions from low to high at time t4, as shown in Figure 6B.

[0090] Thus, the fault detection circuit 2 in the first example shown in Figure 5 can quickly and accurately detect whether or not a fault has occurred where the light emission signal is fixed at high, using a simple circuit configuration, by holding the light emission signal on the falling edge of the horizontal synchronization signal.

[0091] (Detection of defects in the low-level fixation of the light emission signal) Figure 7 is a timing diagram of the light emission device 30, showing the timing for detecting defects in the low-level fixation of the light emission signal. Similar to Figure 4, the lower part of Figure 7 shows detailed timing waveforms for the period from time t1 to t5.

[0092] During the period when the horizontal synchronization signal is high, the light emission signal intermittently goes high to drive each of the light-emitting elements 20 in one row (times t3 to t4 in Figure 7). However, if the light emission signal malfunctions and remains fixed at low, no current flows to each light-emitting element 20, and they stop emitting light.

[0093] Figure 8 is a circuit diagram of a fault detection circuit 2 according to a second example of the first embodiment. The fault detection circuit 2 according to the second example is characterized by detecting a fault in which the light emission signal is fixed to low.

[0094] The fault detection circuit 2 according to the second example shown in Figure 8 includes a holding circuit 4, an AND circuit 8, a NOR circuit 5A, a first inverter 6, and a second inverter 7.

[0095] The holding circuit 4 includes, for example, a first D-F / F 4a and a second D-F / F 4b. The D node of the first D-F / F 4a is connected to the power supply voltage VDD node. The output signal of the AND circuit 8 is input to the clock node of the first D-F / F 4a. The output signal of the NOR circuit 5A is input to the reset node of the first D-F / F 4a. The AND circuit 8 outputs a logical AND signal of the horizontal synchronization signal and the light emission signal. The NOR circuit 5A outputs a negative logical OR signal of the fault reset signal and the output signal of the first inverter 6. The first inverter 6 outputs an inverted signal of the horizontal synchronization signal. The / Q signal TL_CHK of the first D-F / F 4a is a signal that transitions from high to low when the light emission signal transitions from low to high, and then transitions from low to high when the horizontal synchronization signal transitions from high to low.

[0096] The / Q signal from the first D-F / F4a is input to the D node of the second D-F / F4b. The output signal from the first inverter 6 is input to the clock node of the second D-F / F4b. The output signal from the second inverter 7 is input to the reset node of the second D-F / F4b. The second inverter 7 outputs an inverted signal of the faulty reset signal. The Q signal TL_SHORT of the second D-F / F4b is a signal that transitions from low to high when the light emission signal is fixed low.

[0097] Figures 9A and 9B are timing diagrams of the fault detection circuit 2 in Figure 8. Figure 9A shows the timing when the light emission signal is normal, and Figure 9B shows the timing when the light emission signal malfunctions and is fixed at low. Figures 9A and 9B illustrate the timing waveforms of the vertical synchronization signal, horizontal synchronization signal, light emission signal, the Q signal TL_CHK of the first D-F / F4a, and the Q signal TL_SHORT of the second D-F / F4b.

[0098] Both the first D-F / F4a and the second D-F / F4b are reset when the fault reset signal goes high. When the light emission signal is normal, as shown in Figure 9A, at time t3, both the horizontal synchronization signal and the light emission signal go high, the output signal of the AND circuit 8 transitions from low to high, and a rising edge is input to the clock node of the first D-F / F4a. As a result, the / Q signal TL_SHORT of the first D-F / F4a transitions from high to low.

[0099] Subsequently, when the horizontal synchronization signal transitions from high to low at time t4, a rising edge is input to the clock node of the second D-F / F4b. At this point, the / Q signal TL_CHK of the first D-F / F4a is low, so the Q signal TL_SHORT of the second D-F / F4b remains low.

[0100] If the light emission signal malfunctions and remains fixed low, as shown in Figure 9B, the output of the AND circuit 8 will be fixed low, no rising edge will be input to the clock node of the first D-F / F 4a, and the Q signal TL_SHORT of the first D-F / F 4a will be fixed high. Therefore, when the horizontal synchronization signal transitions from high to low at time t4 and a rising edge is input to the clock node of the second D-F / F 4b, the Q signal TL_SHORT of the second D-F / F 4b will transition from low to high.

[0101] Thus, in the second example of the fault detection circuit 2 shown in Figure 8, when the light emission signal transitions from low to high, the / Q signal TL_CHK of the first D-F / F4a transitions from high to low, and then, when the horizontal synchronization signal transitions from high to low, the / Q signal TL_CHK of the first D-F / F4a is held by the second D-F / F4b. Therefore, if the Q signal TL_SHORT of the second D-F / F4b transitions from low to high, it is possible to quickly and accurately detect, with a simple circuit configuration, that a fault has occurred where the light emission signal is fixed at low.

[0102] (Detection of defects in the fixed high position of the horizontal synchronization signal) Figure 10 is a timing diagram of the light-emitting device 30, showing the timing for detecting defects in the fixed high position of the horizontal synchronization signal. Similar to Figure 4, the lower part of Figure 10 shows detailed timing waveforms for times t1 to t5.

[0103] The horizontal synchronization signal goes low during the period from time t4 to t5 after each light-emitting element 20 in one row has finished being driven. If the horizontal synchronization signal malfunctions and remains fixed at high, it will also remain high during the period from time t4 to t5, which may prevent the light emission signal from being output at the correct timing.

[0104] Figure 11 is a circuit diagram of a fault detection circuit 2 according to a third example of the first embodiment. The fault detection circuit 2 according to the third example is characterized by detecting a fault in the horizontal synchronization signal being fixed at high.

[0105] The fault detection circuit 2 according to the third example shown in Figure 11 includes a holding circuit 4, an OR circuit 5, a first inverter 6, and a second inverter 7.

[0106] The holding circuit 4 includes, for example, a D-F / F4. The D node of the D-F / F4 receives the output signal of the OR circuit 5. The clock node of the D-F / F4 receives the output signal of the first inverter 6. The reset node of the D-F / F4 receives the output signal of the second inverter 7.

[0107] OR circuit 5 outputs a logical OR signal of the Q signal of D-F / F4 and the horizontal synchronization signal. The first inverter 6 inverts the vertical synchronization signal and inputs it to the clock node of D-F / F4. The second inverter 7 inverts the fault reset signal and inputs it to the reset node of D-F / F4.

[0108] Figures 12A and 12B are timing diagrams of the fault detection circuit 2 in Figure 11. Figure 12A shows the timing when the horizontal synchronization signal is normal, and Figure 12B shows the timing when the horizontal synchronization signal malfunctions and is fixed at high. Figures 12A and 12B illustrate the timing waveforms of the vertical synchronization signal, horizontal synchronization signal, light emission signal, and the Q signal HH_SHORT of D-F / F4.

[0109] D-F / F4 is reset by a faulty reset signal during initial setup, and the Q signal HH_SHORT becomes low. At time t6 in Figure 12A, when the vertical synchronization signal transitions from high to low, D-F / F4 holds the horizontal synchronization signal. Under normal circumstances, the horizontal synchronization signal is low at time t6 in Figure 12A, and the Q signal HH_SHORT remains low.

[0110] If the horizontal synchronization signal malfunctions and remains fixed at high, the output of OR circuit 5 will become high. Therefore, at time t6 in Figure 12B, the Q signal HH_SHORT of D-F / F4 will transition from low to high.

[0111] In this way, if the horizontal synchronization signal malfunctions by remaining fixed at high, the malfunction can be quickly and accurately detected with a simple circuit configuration at the moment the vertical synchronization signal transitions from high to low.

[0112] (Detection of failure to fix the horizontal synchronization signal to low) Figure 13 is a timing diagram of the light-emitting device 30, showing the timing for detecting a failure to fix the horizontal synchronization signal to low. When the horizontal synchronization signal fails to fix to low, it becomes low level during the period from time t2 to t4, and the light-emitting signal does not transition to high.

[0113] Figure 14 is a circuit diagram of a fault detection circuit 2 according to the fourth example of the first embodiment. The fault detection circuit 2 according to the fourth example is characterized by detecting a fault in the horizontal synchronization signal being fixed to low.

[0114] The fault detection circuit 2 according to the fourth example shown in Figure 14 includes a holding circuit 4, an OR circuit 5, a first inverter 6, and a second inverter 7. The holding circuit 4 includes, for example, a D-F / F4. The output signal of the OR circuit 5 is input to the D node of the D-F / F4. The OR circuit 5 outputs a logical OR signal of the D signal HL_SHORT of the D-F / F4 and the output signal of the first inverter 6. The first inverter 6 outputs an inverted horizontal synchronization signal. The light emission signal is input to the clock node of the D-F / F4. The output signal of the second inverter 7 is input to the reset node of the D-F / F4. The second inverter 7 outputs an inverted fault reset signal.

[0115] The fault detection circuit 2 in Figure 14 holds the inverted signal of the horizontal synchronization signal at the timing when the light emission signal transitions from low to high. If the horizontal synchronization signal malfunctions and remains fixed at low, the output signal of the fault detection circuit 2 becomes high.

[0116] Figures 15A and 15B are timing diagrams of the fault detection circuit 2 in Figure 14. Figure 15A shows the timing when the horizontal synchronization signal is normal, and Figure 15B shows the timing when the horizontal synchronization signal malfunctions and is fixed at low. Figures 15A and 15B illustrate the timing waveforms of the vertical synchronization signal, horizontal synchronization signal, light emission signal, and the Q signal HL_SHORT of D-F / F4.

[0117] D-F / F4 is reset by a faulty reset signal during initial setup, and the Q signal HL_SHORT becomes low. At time t3, when the light emission signal transitions from low to high, D-F / F4 holds the inverted signal of the horizontal synchronization signal. If the horizontal synchronization signal is normal, it is high at time t6. Therefore, the D signal of D-F / F4 becomes low, and the Q signal remains low.

[0118] On the other hand, if the horizontal synchronization signal malfunctions and remains fixed at low, at time t3, the D signal of D-F / F4 will become high, and the Q signal will transition from low to high.

[0119] Thus, in the fourth example, the fault detection circuit 2 holds the inverted signal of the horizontal synchronization signal at D-F / F4 at the timing when the light emission signal transitions from low to high. Therefore, if a fault occurs where the horizontal synchronization signal is fixed at low, the output of the fault detection circuit 2 can be transitioned from low to high, and a fault where the horizontal synchronization signal is fixed at low can be detected quickly and accurately with a simple circuit configuration.

[0120] (Detection of faulty high-fixed vertical synchronization signal) Figure 16 is a timing diagram of the light-emitting device 30, showing the timing for detecting a faulty high-fixed vertical synchronization signal. Similar to Figure 4, the lower part of Figure 16 shows detailed timing waveforms for times t1 to t5.

[0121] Figure 16 shows an example where the vertical synchronization signal transitions from high to low after the horizontal synchronization signal's high period is repeated 511 times. If the vertical synchronization signal does not go low even after the horizontal synchronization signal's high period is repeated 512 times or more, it can be determined that the vertical synchronization signal has malfunctioned by remaining fixed at high.

[0122] Figure 17 is a circuit diagram of a fault detection circuit 2 according to the fifth example of the first embodiment. The fault detection circuit 2 according to the fifth example includes a counter 9, a first AND circuit 8a, a second AND circuit 8b, an OR circuit 5, a first inverter 6, and a second inverter 7.

[0123] The counter 9 is constructed by cascading multiple hold circuits 4. For example, the counter 9 is a 10-bit counter constructed by cascading 10 hold circuits 4. The output signal of the first AND circuit 8a is input to the clock node of each hold circuit 4 in the counter 9. The counter 9 performs a count-up operation each time the output signal of the first AND circuit 8a transitions from low to high. The first AND circuit 8a outputs a logical AND signal of the vertical synchronization signal and the horizontal synchronization signal inverted by the first inverter 6.

[0124] Counter 9 counts the number of times the horizontal sync signal transitions from high to low while the vertical sync signal is high. When the count reaches, for example, 512 or more, Counter 9 transitions the output signal VH_SHORT from low to high.

[0125] The output signal of the second AND circuit 8b is input to the reset node of counter 9. The second AND circuit 8b outputs a logical AND signal of the signal obtained by inverting the faulty reset signal with the second inverter 7 and the output signal of OR circuit 5. OR circuit 5 outputs a logical OR signal of the output signal VH_SHORT of counter 9 and the vertical synchronization signal.

[0126] OR circuit 5 sets its output signal high when the output signal VH_SHORT of counter 9 is high. At this time, if the fault reset signal is high, the output signal of the second AND circuit 8b becomes low, counter 9 is reset, and the output signal VH_SHORT transitions to low.

[0127] Figures 18A and 18B are timing diagrams of the fault detection circuit 2 in Figure 17. Figure 18A is the timing diagram when the vertical synchronization signal is normal, and Figure 18B is the timing diagram when the vertical synchronization signal is fixed at high (a fault). Figures 18A and 18B illustrate the timing waveforms of the vertical synchronization signal, horizontal synchronization signal, light emission signal, the output signal HH_CHK of the OR circuit 5, and the output signal VH_SHORT of the counter 9.

[0128] When the vertical synchronization signal is normal, as shown in Figure 18A, the output signal of the first AND circuit 8a goes low at time t2, then goes high at time t4 when the horizontal synchronization signal goes low, and then goes low at time t5 when the horizontal synchronization signal goes high. Thereafter, each time the horizontal synchronization signal goes from high to low, the counter 9 performs a count-up operation. When the vertical synchronization signal is normal, the counter 9 performs count amplifier operation 511 times, and the output signal VH_SHORT of the counter 9 remains low. Therefore, the counter 9 is reset when the faulty reset signal goes high.

[0129] If the vertical synchronization signal is fixed at high due to a malfunction, the counter 9 will perform 512 or more count-up operations, as shown in Figure 18B. When the counter 9 performs its 512th count-up operation, the output signal VH_SHORT transitions from low to high.

[0130] Thus, the fault detection circuit 2 in the fifth example can quickly and accurately detect, with a simple circuit configuration, that the vertical synchronization signal is fixed at a high fault by transitioning the output signal VH_SHORT of the counter 9 from low to high when the count value of the counter 9 reaches a predetermined value.

[0131] (Detection of failure to fix the vertical synchronization signal to low) Figure 19 is a timing diagram of the light-emitting device 30, showing the timing for detecting a failure to fix the vertical synchronization signal to low. If the vertical synchronization signal fails to fix to low, it will not go high after time t1, and therefore the horizontal synchronization signal may not go high at time t2.

[0132] Figure 20 is a circuit diagram of a fault detection circuit 2 according to the sixth example of the first embodiment. The fault detection circuit 2 according to the sixth example is characterized by detecting a fault in the vertical synchronization signal being fixed to low.

[0133] The fault detection circuit 2 according to the sixth example shown in Figure 20 includes a holding circuit 4, an OR circuit 5, a first inverter 6, and a second inverter 7. The holding circuit 4 includes, for example, a D-F / F4. The output signal of the OR circuit 5 is input to the D node of the D-F / F4. The OR circuit 5 outputs a logical OR signal of the Q signal of the D-F / F4 and the output signal of the first inverter 6. The horizontal synchronization signal is input to the clock node of the D-F / F4. The output signal of the second inverter 7 is input to the reset node of the D-F / F4. The second inverter 7 outputs an inverted signal of the fault reset signal.

[0134] In Figure 20, D-F / F4 holds the inverted signal of the vertical sync signal at the timing when the horizontal sync signal transitions from low to high. More specifically, the output signal of D-F / F4 transitions from low to high when the vertical sync signal malfunctions and remains fixed at low.

[0135] Figures 21A and 21B are timing diagrams of the fault detection circuit 2 in Figure 20. Figure 21A shows the timing when the vertical synchronization signal is normal, and Figure 21B shows the timing when the vertical synchronization signal malfunctions and is fixed at low. Figures 21A and 21B illustrate the timing waveforms of the vertical synchronization signal, horizontal synchronization signal, light emission signal, and the Q signal VL_SHORT of D-F / F4.

[0136] D-F / F4 is reset by a faulty reset signal during initial setup, and the Q signal VL_SHORT becomes low. When the vertical synchronization signal is normal, as shown in Figure 21A, D-F / F4 holds the inverted signal of the vertical synchronization signal at the timing when the horizontal synchronization signal transitions from low to high at time t2, and the Q signal VL_SHORT becomes low. Thus, when the vertical synchronization signal is normal, the Q signal of D-F / F4 remains low.

[0137] If the vertical synchronization signal malfunctions and remains fixed at low, as shown in Figure 21B, at time t2, when the horizontal synchronization signal transitions from low to high, the Q signal VL_SHORT of D-F / F4 also transitions from low to high. In this way, when the Q signal VL_SHORT of D-F / F4 transitions from low to high, it is possible to detect that the vertical synchronization signal malfunctions and remains fixed at low.

[0138] A fault detection circuit 2 can be provided that includes all of the fault detection circuits 2 according to the first to sixth examples shown in Figures 5, 8, 11, 14, 17, and 20. In this case, faults such as high-fixed and low-fixed signals for the light emission signal, high-fixed and low-fixed horizontal synchronization signal, and high-fixed and low-fixed vertical synchronization signal can be detected. Furthermore, faults where multiple signals are short-circuited, resulting in a high-fixed or low-fixed signal, can also be detected.

[0139] Figure 22 is a timing diagram of a fault detection circuit 2 according to the first embodiment, which can detect faults in the fixed high and low states of the light emission signal, the fixed high and low states of the horizontal synchronization signal, and the fixed high and low states of the vertical synchronization signal. The fault detection circuit 2 in Figure 22 detects a fault in the fixed high state of the light emission signal by holding the light emission signal at the timing when the horizontal synchronization signal transitions from high to low at time t4. It also detects a fault in the fixed low state of the light emission signal at the timing when the logical AND signal of the horizontal synchronization signal and the light emission signal transitions from low to high at time t2. Furthermore, it detects a fault in the fixed high state of the horizontal synchronization signal at the timing when the vertical synchronization signal transitions from high to low at time t6. Furthermore, it detects a fault in the fixed low state of the horizontal synchronization signal at the timing when the light emission signal transitions from low to high at time t3. In addition, the fault detection circuit 2 in the fixed high state of the vertical synchronization signal detects a fault in the fixed high state of the vertical synchronization signal by counting the number of times the horizontal synchronization signal transitions from high to low during the period when the vertical synchronization signal is high using a counter 9, and when the counted number exceeds a predetermined number (for example, 511 times), the output signal of the counter 9 transitions to high. Furthermore, at time t2, when the horizontal synchronization signal transitions from low to high, a malfunction in the vertical synchronization signal's low fixation is detected.

[0140] Figure 23 is a flowchart showing the processing operation of the defect detection device 1 according to the first embodiment, which can detect defects in the high and low fixed positions of the light emission signal, the high and low fixed positions of the horizontal synchronization signal, and the high and low fixed positions of the vertical synchronization signal.

[0141] First, at time t1, the vertical synchronization signal is transitioned from low to high (step S1). Next, at time t2, the horizontal synchronization signal is transitioned from low to high (step S2). Then, based on the timing of the horizontal synchronization signal transition from low to high, i.e., the result of holding the vertical synchronization signal at the rising edge of the horizontal synchronization signal, it is determined whether the vertical synchronization signal is fixed at low or not (step S3). If it is fixed at low or not, the light emission of the light-emitting element 20 is stopped to notify that the vertical synchronization signal is faulty (step S4). The recipient of the notification in step S4 is not specified.

[0142] If it is determined in step S3 that there is no fault in being fixed low, the light emission signal is periodically set to high at time t3, and each light-emitting element 20 is driven in sequence to emit light (step S5). Based on the timing of the transition of the light emission signal from low to high, that is, the result of holding the horizontal synchronization signal at the rising edge of the light emission signal, it is determined whether or not the horizontal synchronization signal is faulty in being fixed low (step S6). If there is a fault in being fixed low, the light emission of the light-emitting elements 20 is stopped, and a notification that the horizontal synchronization signal is faulty is sent (step S7). The recipient of the notification in step S7 is not specified.

[0143] If it is determined in step S6 that there is no defect in being fixed low, the light emission signal is fixed low once the driving of one row of light-emitting elements 20 is complete (step S8). Next, the horizontal synchronization signal is transitioned from high to low (step S9). At the timing of the transition of the horizontal synchronization signal from high to low, i.e., on the falling edge of the horizontal synchronization signal, it is determined whether the light emission signal is defective in being fixed high or low (step S10). If it is determined that the light emission signal is defective in being fixed high or low, the light emission of each light-emitting element 20 is stopped to notify that the light emission signal is defective (step S11). The recipient of the notification in step S11 is not specified.

[0144] Before or after the determination process in step S10, the timing at which the horizontal synchronization signal transitions from high to low, i.e., the falling edge of the horizontal synchronization signal, determines whether the vertical synchronization signal is stuck at high (step S12). If it is determined that the signal is stuck at high, the process in step S4 is performed.

[0145] If it is determined that there is no defect in steps S10 and S12, the vertical sync signal is transitioned from high to low at time t6 (step S13). Based on the result of holding the horizontal sync signal at the timing when the vertical sync signal is transitioned from high to low, i.e., at the falling edge of the vertical sync signal, it is determined whether the horizontal sync signal is fixed at high and therefore defective (step S14).

[0146] If a high-fixation defect is determined in step S14, the process in step S7 is performed. If it is determined in step S14 that there is no high-fixation defect, or if the processes in steps S4, S7, or S11 have been completed, the process shown in Figure 23 is terminated.

[0147] As described above, in the first embodiment, a fault detection circuit 2 is provided that holds the signal to be faulty at the timing when the logic of signals other than the signal to be faulty changes. This allows for quick and accurate detection of whether the signal to be faulty is faulty with a simple circuit configuration. The signal to be faulty includes, for example, at least one of a light emission signal, a horizontal synchronization signal, or a vertical synchronization signal. According to this embodiment, a fault in at least one of the light emission signal, horizontal synchronization signal, or vertical synchronization signal, whether it is fixed high or low, can be quickly and accurately detected with a simple circuit configuration. More specifically, according to this embodiment, by inputting the signal to be faulty to the D node of D-F / F4 and inputting signals other than the signal to be faulty to the clock node of D-F / F4, the fault detection result can be output from the Q or / Q signal of D / F / F.

[0148] (Second Embodiment) The fault detection device 1 according to the second embodiment is characterized by comprising a fault detection circuit 2 that performs fault detection of the Enable signal in addition to the light emission signal, vertical synchronization signal, and horizontal synchronization signal.

[0149] Figure 24 is a circuit diagram of a fault detection circuit 2 according to the first example of the second embodiment. The fault detection circuit 2 in Figure 24, similar to that in Figure 17, includes a counter 9, a first AND circuit 8a, a second AND circuit 8b, an OR circuit 5, a first inverter 6, and a second inverter 7.

[0150] The counter 9 is constructed by cascading multiple hold circuits 4. For example, the counter 9 is a 10-bit counter constructed by cascading 10 hold circuits 4. The output signal of the first AND circuit 8a is input to the clock node of each hold circuit 4 in the counter 9. The counter 9 performs a count-up operation each time the output signal of the first AND circuit 8a transitions from low to high. The first AND circuit 8a outputs a logical AND signal of the Enable signal and the horizontal synchronization signal inverted by the first inverter 6. The counter 9 counts the number of times the horizontal synchronization signal transitions from low to high while the Enable signal is high. When the count reaches, for example, 512 or more, the counter 9 transitions the output signal TH_SHORT from low to high. The output signal of the second AND circuit 8b is input to the reset node of the counter 9. The second AND circuit 8b outputs a logical AND signal of the signal obtained by inverting the fault reset signal with the second inverter 7 and the output signal of the OR circuit 5. The OR circuit 5 outputs a logical OR signal of the output signal TH_SHORT of the counter 9 and the Enable signal. The OR circuit 5 sets its output signal high when the output signal TH_SHORT of the counter 9 is high. At this time, if the fault reset signal is high, the output signal of the second AND circuit 8b becomes low, the counter 9 is reset, and the output signal TH_SHORT transitions to low.

[0151] If the Enable signal is normal, the Enable signal will transition from high to low after the horizontal synchronization signal transitions from high to low on the 511th time, and in conjunction with this, the output signal HH_CHK of inverter 10 will transition to high. If the Enable signal is fixed at high due to a malfunction, the output signal TH_SHORT of counter 9 will transition to high at the timing when the horizontal synchronization signal transitions from high to low on the 512th time.

[0152] Figures 25A and 25B are timing diagrams of the fault detection circuit 2 in Figure 24. Figure 25A shows the timing when the Enable signal is normal, and Figure 25B shows the timing when the Enable signal is fixed at high. Figures 25A and 25B illustrate the timing waveforms of the Enable signal, horizontal synchronization signal, light emission signal, and the Q signal TH_SHORT of D-F / F4.

[0153] If the Enable signal is normal, as shown in Figure 25A, the Enable signal transitions from low to high at time t1 and then to low at time t6, so the output signal HH_CHK of the inverter 10 transitions to high at time t6.

[0154] If the Enable signal malfunctions by remaining fixed at high, as shown in Figure 25B, at time t9, when the horizontal synchronization signal transitions from high to low for the 512th time, the output signal TH-SHORT of the counter 9 transitions from low to high. This allows for quick and accurate detection of a malfunction where the Enable signal remains fixed at high using a simple circuit.

[0155] The fault detection circuit 2 according to the second embodiment may have a function to detect a low fault in the Enable signal. Figure 26 is a timing diagram of the fault detection circuit 2 that has a function to detect a low fault in the Enable signal. The Enable signal is held at the timing when the vertical synchronization signal transitions from low to high (for example, time t2), and if the held Enable signal is at a low level, it is determined that the Enable signal is a fault that is fixed at low. Alternatively, instead of the timing when the vertical synchronization signal transitions from low to high, the Enable signal may be held at the timing when the horizontal synchronization signal transitions from low to high, and if the held Enable signal is at a low level, it may be determined that the Enable signal is a fault that is fixed at low.

[0156] Figure 27 is a circuit diagram of a fault detection circuit 2 according to a second example of the second embodiment. The fault detection circuit 2 in Figure 27 includes a D-F / F4, an OR circuit 5, a first inverter 6, and a second inverter 7. The output signal of the OR circuit 5 is input to the D node of the D-F / F4. The OR circuit 5 outputs a logical OR signal of the Q signal of the D-F / F4 and the output signal of the first inverter 6. The first inverter 6 outputs an inverted signal of the Enable signal. The vertical synchronization signal is input to the clock node of the D-F / F4. The output signal of the second inverter 7 is input to the reset node of the D-F / F4. The second inverter 7 outputs an inverted signal of the fault reset signal.

[0157] When the Enable signal is normal, the D-F / F4 maintains a low Enable signal at the timing when the vertical sync signal transitions from low to high, and therefore the Q signal remains low. When the Enable signal is fixed at low due to a malfunction, the Q signal of the D-F / F4 transitions from low to high at the timing when the vertical sync signal transitions from low to high.

[0158] Figures 28A and 28B are timing diagrams of the fault detection circuit 2 in Figure 27. Figure 28A shows the timing when the Enable signal is normal, and Figure 28B shows the timing when the Enable signal is fixed at low. Figures 28A and 28B illustrate the timing waveforms of the vertical synchronization signal, horizontal synchronization signal, light emission signal, and the Q signal VL_SHORT of D-F / F4.

[0159] When the Enable signal is normal, as shown in Figure 28A, the Enable signal transitions from low to high at time t0. Therefore, at time t1, when the vertical synchronization signal transitions from low to high, the output of OR circuit 5 becomes low, and the Q signal of D-F / F4 remains low.

[0160] If the Enable signal malfunctions and remains fixed at low, as shown in Figure 28B, at time t1, when the Enable signal transitions from low to high, the Q signal of D-F / F4 also transitions from low to high.

[0161] Figure 29 is a timing diagram of a fault detection circuit 2 according to a second embodiment, which can detect faults in the fixed high and low states of the light emission signal, the fixed high and low states of the horizontal synchronization signal, the fixed high and low states of the vertical synchronization signal, and the fixed high and low states of the Enable signal. The fault detection circuit 2 in Figure 29 detects a fault in the fixed high state of the light emission signal by holding the light emission signal at the timing when the horizontal synchronization signal transitions from high to low at time t4. It also detects a fault in the fixed low state of the light emission signal at the timing when the logical AND signal of the horizontal synchronization signal and the light emission signal transitions from low to high at time t3. Furthermore, it detects a fault in the fixed high state of the horizontal synchronization signal at the timing when the Enable signal transitions from high to low at time t6. Finally, it detects a fault in the fixed low state of the horizontal synchronization signal at the timing when the light emission signal transitions from low to high at time t3. Furthermore, the counter 9 counts the number of times the horizontal synchronization signal transitions from high to low during the period when the vertical synchronization signal is high. When the count exceeds a predetermined number (for example, 511 times), the output signal of the counter 9 transitions to high, thereby detecting a malfunction in the vertical synchronization signal's high-fixation. Additionally, a malfunction in the vertical synchronization signal's low-fixation is detected at time t2 when the horizontal synchronization signal transitions from low to high. Furthermore, a malfunction in the vertical synchronization signal's high-fixation is detected at time t6 when the Enable signal transitions from high to low. Additionally, a malfunction in the Enable signal's low-fixation is detected at time t1 when the vertical synchronization signal transitions from low to high.

[0162] Figure 30 is a flowchart showing the processing operation of a defect detection device 1 according to the first embodiment, which can detect defects in the high and low fixed positions of the light emission signal, the high and low fixed positions of the horizontal synchronization signal, the high and low fixed positions of the vertical synchronization signal, and the high and low fixed positions of the Enable signal.

[0163] In the following section, we will focus on explaining the process in Figure 30, specifically the process that differs from that in Figure 23.

[0164] First, the Enable signal is initially set to high (step S21). Step S22 is the same as step S2 in Figure 23. Next, at the timing when the vertical synchronization signal transitions from low to high, it is determined whether the Enable signal is low or not (step S23).

[0165] If it is determined to be low in step S23, it is indicated that the Enable signal is faulty (step S24).

[0166] If it is determined that the result is not low in step S23, the same process as in steps S2 to S14 in Figure 23 is then performed (steps S25 to S37).

[0167] Before or after the processing in step S37, it is determined whether the Enable signal is high or low at the timing when the vertical synchronization signal transitions from high to low (the falling edge of the vertical synchronization signal) (step S38). If it is determined to be high in step S38, the processing in step S24 is performed. If it is determined not to be high in step S38, the processing in Figure 30 is terminated.

[0168] Thus, in the second embodiment, defects in the high or low fixed state of the Enable signal, as well as the light emission signal, horizontal synchronization signal, and vertical synchronization signal, can be detected quickly and accurately with a simple circuit configuration.

[0169] (Third Embodiment) The defect detection device 1 according to the first and second embodiments described above can, for example, detect defects in a light-emitting device 30 used in a distance measuring device.

[0170] Figure 31 is a block diagram showing the schematic configuration of a distance measuring device 40 incorporating a defect detection device 1 according to the third embodiment. The defect detection device 1 according to the third embodiment has the same configuration and functions as the defect detection device 1 according to the first or second embodiment.

[0171] The distance measuring device 40 in Figure 31 comprises a light-emitting device 30 and a light-receiving device 50. The light-emitting device 30 has a VCSEL (LD chip) 21 having a plurality of light-emitting elements 20 arranged in two dimensions, and a light-emitting control unit (LDD substrate) 22. The light-receiving device 50 has a plurality of SPADs (Single Photon Avalanche Diodes) arranged in two dimensions. The light-emitting control unit 22 incorporates a defect detection device 1 according to the third embodiment.

[0172] The distance measuring device 40 in Figure 31 is a True Solid State LiDAR (Light Detection and Ranging) without an optical scanning device. By sequentially driving the multiple light-emitting elements 20 of the VCSEL in any order, the direction of propagation of the light emitted from the light-emitting device 30 can be switched, causing the light to be scanned within a predetermined two-dimensional range 51. The distance measuring device 40 of this disclosure may also scan the light using an optical scanning device. The light-receiving device 50 has, for example, a plurality of SPADs arranged in a two-dimensional direction.

[0173] (Configuration of the distance measuring device 40) Figure 32 is a block diagram showing an example configuration of the distance measuring device 40 as one implementation example of the light-emitting device 30 according to this embodiment.

[0174] As shown in the figure, the distance measuring device 40 includes a light-emitting unit 11, a drive unit 12, a power supply circuit 13, a light-emitting optical system 14, a light-receiving optical system 15, a light-receiving unit 16, a signal processing unit 17, a control unit 18, and a temperature detection unit 19.

[0175] The light-emitting unit 11 emits light from multiple light sources. The light-emitting unit 11 and the light-emitting optical system 14 correspond to the light-emitting device 30 described above. As will be described later, the light-emitting unit 11 in this example has light-emitting elements 20, each of which is a VCSEL (Vertical Cavity Surface Emitting Laser), and these light-emitting elements 20 are arranged in a predetermined manner, such as a matrix.

[0176] The drive unit 12 is configured to have a power supply circuit 13 for driving the light-emitting unit 11. The power supply circuit 13 generates a power supply voltage (drive voltage Vd, described later) for the drive unit 12 based on an input voltage (input voltage Vin, described later) from, for example, a battery (not shown) provided in the distance measuring device 40. The drive unit 12 drives the light-emitting unit 11 based on this power supply voltage.

[0177] Light emitted from the light-emitting unit 11 is irradiated onto the subject (object) S, which is the target of the distance measurement, via the light-emitting optical system 14. The reflected light from the subject S, thus irradiated, is then incident on the light-receiving surface of the light-receiving unit 16 via the light-receiving optical system 15.

[0178] The light-receiving unit 16 has a light-receiving element such as a CCD (Charge Coupled Device) sensor or a CMOS (Complementary Metal Oxide Semiconductor) sensor, and as described above, it receives reflected light from the subject S incident via the light-receiving optical system 15, converts it into an electrical signal, and outputs it. The light-receiving unit 16 and the light-receiving optical system 15 constitute the light-receiving device 50.

[0179] The light receiving unit 16 performs processes such as CDS (Correlated Double Sampling) and AGC (Automatic Gain Control) on the electrical signal obtained by photoelectric conversion of the received light, and further performs A / D (Analog / Digital) conversion. It then outputs the signal as digital data to the subsequent signal processing unit 17.

[0180] Furthermore, the light-receiving unit 16 in this example outputs a frame synchronization signal Fs to the drive unit 12. This enables the drive unit 12 to cause the light-emitting element 20 in the light-emitting unit 11 to emit light at a timing corresponding to the frame period of the light-receiving unit 16.

[0181] The signal processing unit 17 includes a signal processing processor such as a DSP (Digital Signal Processor). The signal processing unit 17 performs various signal processing operations on the digital signal input from the light receiving unit 16.

[0182] The control unit 18 includes, for example, a microcomputer having a CPU (Central Processing Unit), ROM (Read Only Memory), RAM (Random Access Memory), etc., or an information processing device such as a DSP, and controls the drive unit 12 for controlling the light emission operation by the light emission unit 11, and controls the light receiving operation by the light receiving unit 16.

[0183] The control unit 18 functions as a distance measuring unit 18a. The distance measuring unit 18a measures the distance to the subject S based on the signal input via the signal processing unit 17 (i.e., the signal obtained by receiving reflected light from the subject S). In this example, the distance measuring unit 18a measures the distance to each part of the subject S in order to identify the three-dimensional shape of the subject S.

[0184] The specific distance measurement method used in the distance measuring device 40 will be explained in more detail later.

[0185] The temperature detection unit 19 detects the temperature of the light-emitting unit 11. The temperature detection unit 19 performs temperature detection using, for example, a diode.

[0186] In this example, the temperature information detected by the temperature detection unit 19 is supplied to the drive unit 12, which enables the drive unit 12 to drive the light-emitting unit 11 based on the temperature information.

[0187] (Distance measurement method) As for the distance measurement method in the distance measuring device 40, for example, the STL (Structured Light) method or the ToF (Time of Flight) method can be adopted.

[0188] The STL method is a method of measuring distance based on an image of an object S illuminated with light having a predetermined light / dark pattern, such as a dot pattern or a grid pattern.

[0189] Figure 33A is an explanatory diagram of the STL method. In the STL method, a pattern light Lp with a dot pattern, such as that shown in Figure 33A, is shone onto the subject S. The pattern light Lp is divided into multiple blocks BL, and each block BL is assigned a different dot pattern (the dot patterns do not overlap between blocks BL).

[0190] Figure 33B is an explanatory diagram of the distance measurement principle of the STL method.

[0191] In this example, the wall W and the box BX placed in front of it are considered the subject S, and pattern light Lp is irradiated onto the subject S. In the figure, "G" schematically represents the field of view of the light receiving unit 16.

[0192] Furthermore, in the figure, "BLn" refers to the light of a certain block BL in the pattern light Lp, and "dn" refers to the dot pattern of block BLn projected in the light-receiving image by the light-receiving unit 16.

[0193] Here, if box BX does not exist in front of wall W, the dot pattern of block BLn is projected at the position "dn'" in the diagram in the received image. In other words, the position in which the pattern of block BLn is projected in the received image differs depending on whether box BX is present or not, and specifically, pattern distortion occurs.

[0194] The STL method utilizes the fact that the irradiated pattern is distorted by the object's shape to determine the shape and depth of the subject S. Specifically, it determines the shape and depth of the subject S from the way the pattern is distorted.

[0195] When the STL method is adopted, the light receiving unit 16 is, for example, an IR (Infrared) light receiving unit 16 using a global shutter method. In the case of the STL method, the distance measuring unit 18a controls the drive unit 12 so that the light emitting unit 11 emits pattern light, and also detects pattern distortion in the image signal obtained via the signal processing unit 17, and calculates the distance based on the pattern distortion.

[0196] Next, the Time of Flight (ToF) method is a method of measuring the distance to an object by detecting the time of flight (time difference) of light emitted from the light-emitting unit 11, reflected by the object, and reaching the light-receiving unit 16.

[0197] When the so-called direct ToF (dTOF) method is adopted as the ToF method, a SPAD (Single Photon Avalanche Diode) is used as the light receiving unit 16, and the light emitting unit 11 is pulse-driven. In this case, the distance measuring unit 18a calculates the time difference from emission to reception of light emitted from the light emitting unit 11 and received by the light receiving unit 16 based on the signal input via the signal processing unit 17, and calculates the distance to each part of the subject S based on this time difference and the speed of light.

[0198] Furthermore, when adopting the so-called indirect ToF (iTOF) method (phase difference method) as the ToF method, a light-receiving unit 16 capable of receiving IR light, for example, is used.

[0199] <Examples of application to mobile devices> The technology disclosed herein (this technology) can be applied to various products. For example, the technology disclosed herein may be implemented as a device mounted on any type of mobile device such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots.

[0200] Figure 34 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0201] The vehicle control system 12000 comprises a plurality of electronic control units connected via a communication network 12001. In the example shown in Figure 34, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0202] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0203] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0204] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0205] The imaging unit 12031 is a light sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0206] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that captures images of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0207] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following driving based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0208] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0209] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0210] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 34, the output devices are exemplified as an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0211] Figure 35 shows an example of the installation position of the imaging unit 12031.

[0212] In Figure 35, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0213] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0214] Figure 35 shows an example of the imaging range of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0215] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0216] For example, the microcomputer 12051, based on distance information obtained from the imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to the vehicle 12100). In particular, it can extract the closest object on the vehicle 12100's path that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, where the vehicle drives autonomously without driver intervention, can be performed.

[0217] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0218] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0219] The above describes an example of a vehicle control system to which the technology described herein can be applied. The technology described herein can be applied to, for example, the external information detection unit 12030, among the configurations described above. By applying the technology described herein to the external information detection unit 12030, defects in the light emission signal, horizontal synchronization signal, vertical synchronization signal, etc., generated by the external information detection unit 12030 can be detected quickly and accurately with a simple circuit configuration.

[0220] Furthermore, this technology can take the following configurations: (1) A fault detection device comprising a holding circuit that holds the signal to be fault detected among a plurality of signals used for controlling the light emission of a light-emitting element at the timing when the logic of one or more signals other than the fault detection target changes. (2) The fault detection device according to (1), comprising a plurality of the holding circuits, wherein each of the plurality of holding circuits holds a different signal to be fault detected among the plurality of signals at the timing when the logic of one or more signals other than the fault detection target changes. (3) The fault detection device according to (1) or (2), wherein the holding circuit holds the signal to be fault detected at the timing when the logic of one signal other than the fault detection target changes, or holds it at the timing when the logic of a signal obtained by combining two or more signals other than the fault detection target changes. (4) A fault detection device according to any one of (1) to (3), wherein the signal to be fault detected includes at least one of a first signal that instructs the emission of light from a plurality of the light-emitting elements, a second signal that specifies a drive period for sequentially driving a plurality of the light-emitting elements arranged in at least one direction, or a third signal that specifies a drive period for sequentially driving all of the plurality of light-emitting elements arranged in at least one direction. (5) A fault detection device according to (4), wherein the holding circuit holds the first signal at the timing when the logic of one or more of the plurality of signals other than the first signal changes. (6) A fault detection device according to (5), wherein the holding circuit holds the first signal at the timing when the logic of the second signal changes from first logic to second logic. (7) A fault detection device according to (5), wherein the holding circuit holds the first signal at the timing when the logic of the second signal, or a signal obtained by combining the second signal and the third signal, changes, thereby changing the logic of the holding signal when the first signal is faulty, either fixed high or fixed low. (8) The fault detection device according to (4), wherein the holding circuit holds the second signal at the timing when the logic of one or more signals other than the second signal among the plurality of signals changes. (9) The fault detection device according to (8), wherein the holding circuit holds the second signal at the timing when the logic of the third signal changes.(10) The fault detection device according to (8), wherein the holding circuit holds the second signal at the timing when the logic of the first signal changes. (11) The fault detection device according to (4), wherein the holding circuit holds the third signal at the timing when the logic of one or more signals other than the third signal among the plurality of signals changes. (12) The fault detection device according to (11), wherein the holding circuit changes the logic of the holding signal when the number of times the logic of the second signal has changed exceeds a predetermined number. (13) The fault detection device according to (11), wherein the holding circuit holds the third signal at the timing when the logic of the second signal changes. (14) The fault detection device according to (4), wherein the holding circuit holds a fourth signal that indicates whether or not the light emission control circuit that controls the light emission of the light-emitting element performs light emission control of the light-emitting element at the timing when the logic of a signal other than the fourth signal among the plurality of signals changes. (15) The fault detection device according to (14), wherein the holding circuit holds the fourth signal at the timing when the logic of the third signal changes. (16) The fault detection device according to any one of (1) to (15), further comprising a fault determination circuit that determines whether the signal to be fault detected is faulty or not based on the holding signal of the holding circuit. (17) The fault detection device according to (16), wherein the fault determination circuit determines whether the signal to be fault detected is at least one fault, such as being fixed low, fixed high, or short-circuited with another signal. (18) The fault detection device comprising a holding circuit that inputs the signal to be fault detected from among a plurality of signals used for controlling the emission of a light-emitting element to a data input terminal, inputs signals other than the signal to be fault detected to a clock node, and holds the signal to be fault detected on the rising or falling edge of the signals other than the signal to be fault detected. (19) The defect detection device according to (18), wherein the signal to be detected as a defect includes at least one of a first signal that instructs the emission of light from a plurality of light-emitting elements, a second signal that specifies a drive period for sequentially driving a plurality of light-emitting elements arranged in at least one direction, or a third signal that specifies a drive period for sequentially driving all of the plurality of light-emitting elements arranged in at least one direction.(20) A distance measuring device comprising: a light-emitting element that emits light toward an object; a light-emitting control circuit that controls the emission of light from the light-emitting element; and a distance measuring unit that receives light reflected by the object and measures the distance to the object, wherein the light-emitting control circuit has a holding circuit that holds the signal to be detected as faulty among a plurality of signals used for controlling the emission of light from the light-emitting element at the timing when the logic of the signals other than the signal to be detected as faulty changes.

[0221] The aspects of this disclosure are not limited to the individual embodiments described above, but include various modifications that a person skilled in the art could conceive, and the effects of this disclosure are not limited to those described above. In other words, various additions, modifications, and partial deletions are possible, as long as they do not depart from the conceptual idea and spirit of this disclosure derived from the claims and their equivalents.

[0222] 1. Fault detection device, 2. Fault detection circuit, 3. Fault judgment circuit, 4. Holding circuit (D-F / F), 5. OR circuit, 5A. NOR circuit, 6. First inverter, 7. Second inverter, 8. AND circuit, 8a. First AND circuit, 8b. Second AND circuit, 9. Counter, 11. Light-emitting unit, 12. Drive unit, 13. Power supply circuit, 14. Light-emitting optical system, 15. Light-receiving optical system, 16. Light-receiving unit, 17. Signal processing unit, 18. Control unit, 18a. Distance measuring unit, 19. Temperature detection unit, 20. Light-emitting element, 21. LD chip, 22. LDD substrate (light-emitting control unit), 23. Mesa unit, 24. Substrate, 25. Multilayer film, 26. Anode electrode, 27. Cathode electrode, 28. Bonding layer, 29. Pad, 30. Light-emitting device, 31. First anode wiring, 31a. First lateral wiring, 31b. First vertical wiring, 32. 32a Second anode wiring, 32b Second transverse wiring, 33 Second vertical wiring, 33 Third anode wiring, 33a Third transverse wiring, 33b Third vertical wiring, 34 First capacitor, 35 Second capacitor, 36 Third capacitor, 37 First selection circuit, 37a Transistor, 37b Transistor, 38 Second selection circuit, 38a Transistor, 38b Transistor, 39 Third selection circuit, 39a Transistor, 39b Transistor, 40 Distance measuring device, 41 Cathode wiring, 42 Gate wiring, 47 Anode electrode (second pad), 50 Light receiving device, 51 Two-dimensional range

Claims

1. A fault detection device comprising a holding circuit that holds, among multiple signals used for controlling the light emission of a light-emitting element, the signal to be faulty, at the timing when the logic of one or more signals other than the faulty signal changes.

2. The defect detection device according to claim 1, comprising a plurality of holding circuits, wherein each of the plurality of holding circuits holds a different signal from the plurality of signals that is to be detected as a defect at the timing when the logic of one or more signals other than the signal to be detected as a defect changes.

3. The fault detection device according to claim 1, wherein the holding circuit holds the fault detection target signal at the timing when the logic of one signal other than the fault detection target changes, or holds the fault detection device at the timing when the logic of a signal obtained by combining two or more signals other than the fault detection target changes.

4. The defect detection device according to claim 1, wherein the signal to be detected as defective includes at least one of a first signal that instructs the emission of light from a plurality of light-emitting elements, a second signal that specifies a drive period for sequentially driving the plurality of light-emitting elements arranged in at least one direction, or a third signal that specifies a drive period for sequentially driving all of the plurality of light-emitting elements arranged in at least one direction.

5. The fault detection device according to claim 4, wherein the holding circuit holds the first signal at the timing when the logic of one or more signals other than the first signal among the plurality of signals changes.

6. The fault detection device according to claim 5, wherein the holding circuit holds the first signal at the timing when the second signal changes from first logic to second logic.

7. The fault detection device according to claim 5, wherein the holding circuit holds the first signal at the timing when the logic of the second signal, or a signal obtained by combining the second signal and the third signal, changes, thereby changing the logic of the holding signal when the first signal is fixed high or fixed low.

8. The fault detection device according to claim 4, wherein the holding circuit holds the second signal at the timing when the logic of one or more signals other than the second signal among the plurality of signals changes.

9. The fault detection device according to claim 8, wherein the holding circuit holds the second signal at the timing when the logic of the third signal changes.

10. The fault detection device according to claim 8, wherein the holding circuit holds the second signal at the timing when the logic of the first signal changes.

11. The fault detection device according to claim 4, wherein the holding circuit holds the third signal at the timing when the logic of one or more signals other than the third signal among the plurality of signals changes.

12. The fault detection device according to claim 11, wherein the holding circuit changes the logic of the holding signal when the number of times the logic of the second signal has changed exceeds a predetermined number of times.

13. The fault detection device according to claim 11, wherein the holding circuit holds the third signal at the timing when the logic of the second signal changes.

14. The defect detection device according to claim 4, wherein the holding circuit holds a fourth signal that indicates whether or not the light emission control circuit that controls the light emission of the light-emitting element performs light emission control of the light-emitting element, at the timing when the logic of the signals other than the fourth signal among the plurality of signals changes.

15. The fault detection device according to claim 14, wherein the holding circuit holds the fourth signal at the timing when the logic of the third signal changes.

16. The defect detection device according to claim 1, further comprising a defect determination circuit that determines whether the signal to be detected as defective is defective or not based on the holding signal of the holding circuit.

17. The fault detection device according to claim 16, wherein the fault detection circuit determines whether the signal to be detected as faulty is fixed low, fixed high, or short-circuited with another signal, and determines whether or not there is at least one fault.

18. A fault detection device comprising a holding circuit that inputs the signal to be faulty to a data input terminal, inputs the other signals to a clock node, and holds the signal to be faulty at the rising or falling edge of the other signals, among a plurality of signals used to control the light emission of a light-emitting element.

19. The defect detection device according to claim 18, wherein the signal to be detected as a defect includes at least one of a first signal that instructs the emission of light from a plurality of light-emitting elements, a second signal that specifies a drive period for sequentially driving the plurality of light-emitting elements arranged in at least one direction, or a third signal that specifies a drive period for sequentially driving all of the plurality of light-emitting elements arranged in at least one direction.

20. A distance measuring device comprising: a light-emitting element that emits light toward an object; a light-emitting control circuit that controls the emission of light from the light-emitting element; and a distance measuring unit that receives light reflected by the object and measures the distance to the object, wherein the light-emitting control circuit has a holding circuit that holds the signal to be detected as faulty among a plurality of signals used to control the emission of light from the light-emitting element at the timing when the logic of the signals other than the signal to be detected as faulty changes.

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