Magnetoresistive element, storage device, and method for manufacturing magnetoresistive element

Abstract

A magnetoresistive element according to an embodiment of the present invention is provided with: a pillar section having a first magnetic layer, a first non-magnetic layer laminated on the first magnetic layer, and a second magnetic layer laminated on the first non-magnetic layer; a second non-magnetic layer formed on a side surface of the pillar section; and a third non-magnetic layer formed between the side surface of the pillar section and the second non-magnetic layer, wherein the third non-magnetic layer contains any one of a plurality of elements constituting the pillar section.

Description

Magnetoresistive Element, Memory Device, and Method for Manufacturing Magnetoresistive Element

[0007] ,

[0006] ,

[0001] The present disclosure relates to a magnetoresistive element, a memory device, and a method for manufacturing a magnetoresistive element.

[0002] A magnetoresistive element, MRAM (Magnetoresistive Random Access Memory), includes an MTJ element (magnetic tunnel junction element) as a main constituent element. The MTJ element is, for example, a laminated film including a laminated structure such as a B absorption layer / CoFeB / MgO / CoFeB / B absorption layer. In such an MTJ element, crystallization from CoFeB to CoFe occurs due to B diffusion into the B absorption layer by heat treatment, and read performance and retention performance are manifested.

[0003] J.O. Rantschler et al., "Effect of 3d, 4d, and 5d transition metal doping on damping in permalloy thin films", Journal of Applied Physics, February 2007, 101(3) 033911

[0004] By increasing the thickness of the aforementioned B absorption layer, read performance and retention performance are improved. On the other hand, when the B absorption layer is thickened, a trade-off occurs in that the write voltage increases.

[0005] Therefore, the present disclosure provides a magnetoresistive element, a memory device, and a method for manufacturing a magnetoresistive element capable of suppressing an increase in write voltage while realizing or maintaining an improvement in read performance and retention performance.

[0006] The magnetoresistive element according to the embodiment includes a pillar portion having a first magnetic layer, a first non-magnetic layer laminated on the first magnetic layer, and a second magnetic layer laminated on the first non-magnetic layer, a second non-magnetic layer formed on a side surface of the pillar portion, and a third non-magnetic layer formed between the side surface of the pillar portion and the second non-magnetic layer, and the third non-magnetic layer includes any one of a plurality of elements constituting the pillar portion.

[0007] The memory device according to the embodiment includes a magnetoresistive element, the magnetoresistive element having a pillar portion having a first magnetic layer, a first non-magnetic layer laminated on the first magnetic layer, and a second magnetic layer laminated on the first non-magnetic layer, a second non-magnetic layer formed on the side surface of the pillar portion, and a third non-magnetic layer formed between the side surface of the pillar portion and the second non-magnetic layer, the third non-magnetic layer containing any of the multiple elements constituting the pillar portion.

[0008] A method for manufacturing a magnetoresistive element according to an embodiment includes forming a second non-magnetic layer that absorbs any of the multiple elements constituting the pillar portion on the side surface of a pillar portion having a first magnetic layer, a first non-magnetic layer laminated on the first magnetic layer, and a second magnetic layer laminated on the first non-magnetic layer, and forming a third non-magnetic layer containing any of the multiple elements between the side surface of the pillar portion and the second non-magnetic layer by heat treatment.

[0009] This figure shows an example of the configuration of a magnetoresistive element according to the first embodiment. This figure shows an example of the configuration change of the magnetoresistive element according to the first embodiment during heat treatment. This figure shows an example of the configuration of a magnetoresistive element according to the second embodiment. This figure shows an example of the configuration of a magnetoresistive element according to the third embodiment. This figure shows an example of the configuration of a magnetoresistive element according to the fourth embodiment. This figure shows an example of the configuration of a magnetoresistive element according to the fifth embodiment. This figure shows an example of the configuration of a magnetoresistive element according to the sixth embodiment. This figure shows an example of the configuration of a magnetoresistive element according to the seventh embodiment. This figure shows an example of the configuration of a magnetoresistive element according to the eighth embodiment. This figure shows an example of the configuration of a magnetoresistive element according to the ninth embodiment. This figure shows the B concentration of the protective layer, the film thickness of the absorption layer, the MR ratio, the Δ ratio, and the Vc ratio according to comparative examples and examples. This figure shows an example of the configuration of a magnetoresistive element according to comparative examples and examples. This figure shows examples of the elemental concentrations of the protective layer and the memory layer of the magnetoresistive element according to examples. This figure shows a flow of the manufacturing process example of the magnetoresistive element according to each of the above embodiments. This figure shows a flow of the manufacturing process example of the magnetoresistive element according to each of the above embodiments. This figure shows a flow of the manufacturing process example of the magnetoresistive element according to each of the above embodiments. This figure shows an example of the configuration of a memory device according to each of the above embodiments. This figure shows an example of the memory cell configuration of the above memory device. This figure is for explaining an example of the writing operation of the above memory cell to the magnetoresistive element. This is a diagram illustrating an example of read operation on the magnetoresistive element of the memory cell mentioned above. This is a diagram showing the flow of the write process example of the memory device mentioned above. This is a diagram showing an example of application of the memory device mentioned above. This is a diagram showing an example of the configuration of an imaging device related to the application example. This is a diagram showing an example of the configuration of a distance measuring device related to the application example.

[0010] Embodiments of this disclosure will be described in detail below with reference to the drawings. Embodiments include examples and modifications. However, the technology relating to this disclosure is not limited by the embodiments. In addition, in the following embodiments, the same reference numerals are used for essentially the same parts to omit redundant explanations.

[0011] This disclosure will be described in the following order of items. 1. First Embodiment 1-1. Example of Magnetoresistive Element Configuration 1-2. Example of Configuration Change during Heat Treatment of Magnetoresistive Element 2. Second Embodiment 2-1. Example of Magnetoresistive Element Configuration 3. Third Embodiment 3-1. Example of Magnetoresistive Element Configuration 4. Fourth Embodiment 4-1. Example of Magnetoresistive Element Configuration 5. Fifth Embodiment 5-1. Example of Magnetoresistive Element Configuration 6. Sixth Embodiment 6-1. Example of Magnetoresistive Element Configuration 7. Seventh Embodiment 7-1. Example of Magnetoresistive Element Configuration 8. Eighth Embodiment 8-1. Example of Magnetoresistive Element Configuration 9. Ninth Embodiment 9-1. Example of Magnetoresistive Element Configuration 10. Comparative Examples and Examples of Each Embodiment 11. Example of Manufacturing Process for Magnetoresistive Element according to Each Embodiment 12. Storage Devices according to Each Embodiment 12-1. Example of Storage Device Configuration 12-2. Example of Memory Cell Configuration 12-3. Example of Write Operation and Read Operation 12-4. Writing Process Example 13. Operation and Effects of Each Embodiment 14. Other Embodiments 15. Application Examples 15-1. Various Devices 15-2. Imaging Device 15-3. Distancing Device 16. Notes

[0012] <1. First Embodiment> <1-1. Example of Magnetoresistive Element Configuration> An example of the configuration of the magnetoresistive element 1 according to the first embodiment will be described with reference to Figure 1. Figure 1 is a diagram showing an example of the configuration of the magnetoresistive element 1 according to the first embodiment.

[0013] As shown in Figure 1, the magnetoresistive element 1 according to the first embodiment comprises a lower electrode 10, a reference layer 20, a barrier layer 30, a storage layer 40, an upper electrode 50, and a protective layer (sidewall protective layer) 60.

[0014] In the example shown in Figure 1, the lower electrode 10, reference layer 20, barrier layer 30, memory layer 40, and upper electrode 50 are stacked in the order described to form a pillar portion 1a, and a protective layer 60 is formed to cover the side surface (outer periphery) of the pillar portion 1a. The magnetoresistive element 1 is also referred to as a magnetoresistive effect element or magnetic memory element, for example.

[0015] Figure 1 also shows the XYZ coordinate system. The X-axis and Y-axis directions (XY plane direction) correspond to the plane direction of the layer, and the Z-axis direction (vertical direction) corresponds to the thickness direction of the layer (the same applies to other drawings). In the example in Figure 1, the multiple layers in the stacked state are adjacent to each other, and each adjacent layer is in surface contact. Note that the term "layer" may be interpreted as "film," and the terms "layer" and "film" may be appropriately substituted within a range that does not contradict each other.

[0016] The lower electrode 10 and the upper electrode 50 are positioned to sandwich the laminate of the reference layer 20, the barrier layer 30, and the storage layer 40. These lower electrodes 10 and upper electrodes 50 function as conductive layers for supplying voltage to the laminate of the reference layer 20, the barrier layer 30, and the storage layer 40. The lower electrode 10 and upper electrode 50 may be made of metals such as Au, Cu, Al, Ti, Mo, Ru, Ta, Pt, Ir, W, or alloys of these metals.

[0017] The reference layer 20 is a ferromagnetic layer that has magnetic anisotropy and an invariant magnetization direction. The magnetization direction of this reference layer 20 is controlled perpendicular to the layer surface (film surface) by magnetic anisotropy, for example. The reference layer 20 may contain at least one element from among Ti, V, Cr, Mn, Fe, Co, and Ni, and may also contain at least one element from among Ir, Ru, Os, Re, Cr, Mo, W, Ta, Pt, and Pd. The reference layer 20 may be, for example, an artificial ferrimagnetic material due to antiferromagnetic coupling. The reference layer 20 is also referred to as a fixed layer or magnetization fixed layer, for example. The reference layer 20 is an example of a first magnetic layer.

[0018] The barrier layer 30 is provided adjacent to the reference layer 20 and the storage layer 40, and is located between the reference layer 20 and the storage layer 40. The barrier layer 30 may contain at least one element from, for example, Mg, Ca, Li, Si, Al, Sr, Zr, Hf, Ti, Zn, Sc, La, Ta, Eu, Cu, Ba, Mo, W, V, Y, Ni, Co, Mn, Cr, Fe, B, and C. The barrier layer 30 may be an oxide, nitride, fluoride, or a mixture of oxides, nitrides, and fluorides, or a laminate of oxides, nitrides, and fluorides. As an example, the barrier layer 30 may be made of MgO. The barrier layer 30 is also referred to as, for example, a tunnel barrier layer or an insulating layer. The barrier layer 30 is an example of a first non-magnetic layer.

[0019] The memory layer 40 is a ferromagnetic layer having magnetic anisotropy and a variable magnetization direction. In this memory layer 40, for example, the magnetization direction is controlled perpendicular to the layer surface (film surface) by magnetic anisotropy. The memory layer 40 is, for example, a layer having a VCMA (Voltage-Controlled Magnetic Anisotropy) effect. The memory layer 40 may contain at least one element from among Ti, V, Cr, Mn, Fe, Co, and Ni, and may also contain at least one element from among Ir, Ru, Os, Re, Cr, Mo, W, Ta, Pt, and Pd. The memory layer 40 may be, for example, an artificial ferrimagnetic material with antiferromagnetic coupling. As an example, the memory layer 40 may be composed of CoFeB. The memory layer 40 is also called, for example, a free layer. The memory layer 40 is an example of a second magnetic layer.

[0020] The protective layer 60 covers and protects the side surface (outer circumferential surface) of the pillar portion 1a, which is a laminate. This protective layer 60 is formed in an annular shape, for example, so as to surround the pillar portion 1a in a plan view. Furthermore, the protective layer 60 has the function (crystallization promoting function) of absorbing at least one element (for example, B) from among the multiple elements (for example, CoFeB) that constitute the pillar portion 1a (for example, memory layer 40). For this reason, the protective layer 60 of the magnetoresistive element 1 after heat treatment has a compound layer 61 containing the absorbed element. The protective layer 60 is an example of a second non-magnetic layer, and the compound layer 61 is an example of a third non-magnetic layer.

[0021] The compound layer 61 is a region containing the absorbed element, i.e., a compound region. This compound region is formed when a part of the protective layer 60 absorbs the element. The compound layer 61 is formed, for example, between the pillar portion 1a and the protective layer 60, so as to cover the side surface (outer circumferential surface) of the memory layer 40. For example, the compound layer 61 is formed in an annular shape so as to surround the memory layer 40 in a plan view. In the example in Figure 1, the compound layer 61 covers a part of the side surface of the reference layer 20, all of the side surface of the barrier layer 30, all of the side surface of the memory layer 40, and a part of the side surface of the upper electrode 50, and is formed in an annular shape in a plan view.

[0022] The thickness of the compound layer 61 relative to the side surface of the pillar portion 1a is preferably, for example, 1 nm or more and 5 nm or less. The thickness of the compound layer 61 relative to the side surface of the pillar portion 1a is the thickness of the compound layer 61 relative to the side surface of the pillar portion 1a, and is the length (for example, the maximum value) in the compound layer 61 in the direction perpendicular to the side surface of the pillar portion 1a (normal direction). Furthermore, the length in the compound layer 61 in the direction along the side surface of the pillar portion 1a (direction parallel to the side surface of the pillar portion 1a) is preferably longer than the thickness of the memory layer 40 (length in the Z-axis direction of the memory layer 40).

[0023] The protective layer 60 contains, for example, at least one element from among Si, N, and O. For example, the protective layer 60 may be made of SiN. The protective layer 60 also contains at least one element from among Mo, Ta, W, Hf, Zr, Cr, V, and Ti. Mo, Ta, W, Hf, Zr, Cr, V, and Ti are elements that, for example, have a lower enthalpy of formation of B compound than FeB and also have the function of absorbing B.

[0024] The compound layer 61 contains the same elements as the protective layer 60, plus elements absorbed from the pillar portion 1a. For example, if the memory layer 40, which is part of the pillar portion 1a, is CoFeB, then the compound layer 61 contains the same elements as the protective layer 60, plus B absorbed from the CoFeB of the memory layer 40. The compound layer 61 may be amorphous, for example. It is desirable that the electrical conductivity of the compound layer 61 be lower than that of the pillar portion 1a.

[0025] The basic structure of the magnetoresistive element 1 described above is a sandwich structure in which a non-magnetic insulating layer (barrier layer 30) is sandwiched between two magnetic layers (reference layer 20 and memory layer 40) made of magnetic thin films. This structure is called a magnetic tunnel junction (MTJ). Because the thickness of the non-magnetic thin film is very thin, about a few nanometers, a tunnel current flows when a voltage is applied across both ends of the element. A characteristic of this tunnel current is that its magnitude depends on the relative angle of magnetization of the two magnetic layers. This is called the tunnel magnetoresistance (TMR) effect. In MRAM, the magnetization direction of one of the two magnetic layers, the reference layer 20, is fixed, and the magnetization direction of the other, the memory layer 40, is controlled. For example, the magnetization direction of the memory layer 40 can be changed by applying a voltage to the magnetoresistive element 1. The tunnel magnetoresistance effect is used to read out the state.

[0026] In such a magnetoresistive element 1, the resistance state (resistance value) of the magnetoresistive element 1 is switched between a low-resistance state (low resistance value) and a high-resistance state (high resistance value), and data (e.g., 0 or 1) is written. The low-resistance state is when the magnetization direction of the reference layer 20 and the magnetization direction of the memory layer 40 are the same (parallel state), and the high-resistance state is when the magnetization direction of the reference layer 20 and the magnetization direction of the memory layer 40 are different (antiparallel state). For example, the magnetization direction of the memory layer 40 is reversed between the positive Z-axis direction and the negative Z-axis direction, and the resistance state of the magnetoresistive element 1 is switched between a low-resistance state and a high-resistance state. For example, the data corresponding to the low-resistance state is 0, and the data corresponding to the high-resistance state is 1. The magnetoresistive element 1 is an MTJ element that can reverse the magnetization of the memory layer 40 by utilizing, for example, the VCMA effect.

[0027] Although the reference layer 20, barrier layer 30, and memory layer 40 are stacked in the order they are described, they may also be stacked in the reverse order. In other words, the memory layer 40, barrier layer 30, and reference layer 20 may be stacked in the order they are described. In this case, the memory layer 40 becomes the first magnetic layer, and the reference layer 20 becomes the second magnetic layer.

[0028] Furthermore, the reference layer 20 and the memory layer 40 may contain the same element or different elements, and may be formed from the same material or different materials. For example, the reference layer 20 and the memory layer 40 may be formed from CoFeB. In this case, since the protective layer 60 absorbs B from both the reference layer 20 and the memory layer 40, the length of the compound layer 61 in the direction along the side surface of the pillar portion 1a becomes longer than the combined thickness of the reference layer 20 and the memory layer 40.

[0029] Furthermore, the pillar portion 1a of the magnetoresistive element 1 includes at least a reference layer 20, a barrier layer 30, and a memory layer 40, and may have other layers in addition to the aforementioned layers. The magnetoresistive element 1 may also have, for example, a magnetic field generating layer that functions as a bias layer. The magnetic field generating layer generates a magnetic field applied in the XY plane direction (horizontal direction), for example. In addition, methods other than a magnetic field generating layer may be used to generate the magnetic field. For example, methods such as providing a magnet layer above or below the magnetoresistive element 1 or arranging permanent magnets around the magnetoresistive element 1 may be used.

[0030] <1-2. Examples of Configuration Changes During Heat Treatment of Magnetoresistive Elements> Examples of configuration changes during heat treatment of the magnetoresistive element 1 according to the first embodiment will be explained with reference to Figure 2. Figure 2 is a diagram showing examples of configuration changes during heat treatment of the magnetoresistive element 1 according to the first embodiment. In the example in Figure 2, the upper magnetoresistive element 1b is before heat treatment, the middle magnetoresistive element 1c is during heat treatment, and the lower magnetoresistive element 1 is after heat treatment.

[0031] As shown in Figure 2, the magnetoresistive element 1b before heat treatment (upper section) comprises, as described above, a lower electrode 10, a reference layer 20, a barrier layer 30, a memory layer 40, an upper electrode 50, and a protective layer 60. The protective layer 60 has an absorption function that absorbs one of the elements (e.g., B) among the multiple elements (e.g., CoFeB) that make up the memory layer 40 during heat treatment. Heat treatment is performed on the magnetoresistive element 1b with this configuration. In the magnetoresistive element 1c during heat treatment (middle section), the protective layer 60 absorbs a predetermined element (e.g., B) from the memory layer 40. As a result, in the magnetoresistive element 1c after heat treatment (lower section), a compound layer 61 containing the absorbed predetermined element is formed on the protective layer 60. In this way, the crystallization of the memory layer 40 (e.g., solid-phase epitaxial growth) is promoted.

[0032] As described above, according to the first embodiment, a protective layer 60 having an absorption function is provided on the side surface of the pillar portion 1a. As a result, predetermined elements are absorbed from the storage layer 40 of the pillar portion 1a by the protective layer 60, thereby promoting the crystallization of the storage layer 40. Furthermore, the compound layer 61 containing the absorbed predetermined elements is formed outside the pillar portion 1a. In other words, since the compound layer 61 does not exist inside the pillar portion 1a, an increase in the write voltage can be suppressed. Therefore, it is possible to suppress an increase in the write voltage while improving or maintaining read performance and retention performance.

[0033] <2. Second Embodiment> <2-1. Example of Magnetoresistive Element Configuration> An example of the configuration of the magnetoresistive element 1 according to the second embodiment will be described with reference to Figure 3. Figure 3 is a diagram showing an example of the configuration of the magnetoresistive element 1 according to the second embodiment. The second embodiment is basically the same as the first embodiment (see Figure 1), but the differences will be explained.

[0034] As shown in Figure 3, the magnetoresistive element 1 according to the second embodiment includes a contact layer 70 in addition to the layers according to the first embodiment. The contact layer 70 is provided between the memory layer 40 and the upper electrode 50. The contact layer 70 is an example of a fourth non-magnetic layer.

[0035] In the example shown in Figure 3, the lower electrode 10, reference layer 20, barrier layer 30, memory layer 40, contact layer 70, and upper electrode 50 are stacked in the order described, forming the pillar portion 1a. The same effects as in the first embodiment can be obtained with the configuration of the second embodiment.

[0036] <3. Third Embodiment> <3-1. Example of Magnetoresistive Element Configuration> An example of the configuration of the magnetoresistive element 1 according to the third embodiment will be described with reference to Figure 4. Figure 4 is a diagram showing an example of the configuration of the magnetoresistive element 1 according to the third embodiment. The third embodiment is basically the same as the second embodiment (see Figure 3), but the differences will be explained.

[0037] As shown in Figure 4, the magnetoresistive element 1 according to the third embodiment includes, in addition to the layers according to the second embodiment, a fixed layer 75, a spacer layer 80, and a storage layer 85. The storage layer 85 is an example of a fourth non-magnetic layer.

[0038] In the example shown in Figure 4, the lower electrode 10, fixed layer 75, spacer layer 80, reference layer 20, barrier layer 30, memory layer 40, storage layer 85, contact layer 70, and upper electrode 50 are stacked in the order described, forming the pillar portion 1a. The same effects as in the first embodiment can be obtained with the configuration of the third embodiment.

[0039] The fixed layer 75 is laminated on the lower electrode 10 and is a ferromagnetic layer having magnetic anisotropy and a fixed magnetization direction. The magnetization direction of this fixed layer 75 is controlled perpendicular to the layer surface (film surface) by magnetic anisotropy. The magnetization direction of the fixed layer 75 is, for example, antiparallel to the magnetization direction of the reference layer 20. Therefore, the fixed layer 75 has the function of canceling out the leakage magnetic field from the reference layer 20 to the storage layer 40. The fixed layer 75 may contain, for example, at least one element from among Co, Fe, Ni, Pt, Pd, Cr, Ir, Sm, and Nd.

[0040] The spacer layer 80 is provided between the fixed layer 75 and the reference layer 20, and is a layer that separates the fixed layer 75 and the reference layer 20. This spacer layer 80 is, for example, a layer for magnetically coupling the magnetization directions of the fixed layer 75 and the reference layer 20 in an antiparallel manner. The spacer layer 80 may include, for example, at least one or more elements among Ru, Ir, Rh, and Re. The spacer layer 80 is also referred to as a separation layer, for example.

[0041] The accumulation layer 85 is provided between the memory layer 40 and the contact layer 70, and is a layer that accumulates spin electrons. The accumulation layer 85 may include a conductor such as a metal, an alloy (for example, an alloy layer), or a doped semiconductor. Further, the accumulation layer 85 may include at least one or more of silver, copper, aluminum, and graphene.

[0042] <4. Fourth Embodiment> <4-1. Configuration Example of Magnetic Resistance Element> A configuration example of the magnetic resistance element 1 according to the fourth embodiment will be described with reference to FIG. 5. FIG. 5 is a diagram showing a configuration example of the magnetic resistance element 1 according to the fourth embodiment. The fourth embodiment is basically the same as the third embodiment (see FIG. 4), but the differences will be described.

[0043] As shown in FIG. 5, in the magnetic resistance element 1 according to the fourth embodiment, there are two memory layers 40 and 41, and an absorption layer (crystallization promotion layer) 90 is provided between these memory layers 40 and 41. The absorption layer 90 absorbs an element (for example, B) among a plurality of elements (for example, CoFeB) constituting the memory layer 40 and the memory layer 41 during heat treatment. Due to the presence of this absorption layer 90, it is possible to surely promote the crystallization of the memory layer 40 and the memory layer 41. In order to suppress an increase in the write voltage, it is desirable that the thickness of the absorption layer 90 be as thin as possible.

[0044] In the example of FIG. 5, the lower electrode 10, the fixed layer 75, the spacer layer 80, the reference layer 20, the barrier layer 30, the memory layer 40, the absorption layer 90, the memory layer 41, the accumulation layer 85, the contact layer 70, and the upper electrode 50 are laminated in that order of description, and a pillar portion 1a is formed. Even with the configuration of the fourth embodiment, the same effects as those of the first embodiment can be obtained.

[0045] <5. Fifth Embodiment> <5-1. Configuration Example of Magnetoresistive Element> A configuration example of the magnetoresistive element 1 according to the fifth embodiment will be described with reference to FIG. 6. FIG. 6 is a diagram showing a configuration example of the magnetoresistive element 1 according to the fifth embodiment. The fifth embodiment is basically the same as the fourth embodiment (see FIG. 5), but the differences will be described.

[0046] As shown in FIG. 6, in the magnetoresistive element 1 according to the fifth embodiment, there is one memory layer 40, and an absorption layer 90 is provided between the memory layer 40 and the storage layer 85.

[0047] In the example of FIG. 6, the lower electrode 10, the fixed layer 75, the spacer layer 80, the reference layer 20, the barrier layer 30, the memory layer 40, the absorption layer 90, the storage layer 85, the contact layer 70, and the upper electrode 50 are laminated in the order of description, and the pillar portion 1a is formed. With the configuration of the fifth embodiment, the same effects as those of the first embodiment can be obtained.

[0048] <6. Sixth Embodiment> <6-1. Configuration Example of Magnetoresistive Element> A configuration example of the magnetoresistive element 1 according to the sixth embodiment will be described with reference to FIG. 7. FIG. 7 is a diagram showing a configuration example of the magnetoresistive element 1 according to the sixth embodiment. The sixth embodiment is basically the same as the fifth embodiment (see FIG. 6), but the differences will be described.

[0049] As shown in FIG. 7, in the magnetoresistive element 1 according to the sixth embodiment, there are two reference layers 20 and 21, and an absorption layer 90 is provided between these reference layers 20 and 21.

[0050] In the example of FIG. 7, the lower electrode 10, the fixed layer 75, the spacer layer 80, the reference layer 20, the absorption layer 90, the reference layer 21, the barrier layer 30, the memory layer 40, the storage layer 85, the contact layer 70, and the upper electrode 50 are laminated in the order of description, and the pillar portion 1a is formed. With the configuration of the sixth embodiment, the same effects as those of the first embodiment can be obtained.

[0051] <7. Seventh Embodiment> <7-1. Example of Magnetoresistive Element Configuration> An example of the configuration of the magnetoresistive element 1 according to the seventh embodiment will be described with reference to Figure 8. Figure 8 is a diagram showing an example of the configuration of the magnetoresistive element 1 according to the seventh embodiment. The seventh embodiment is basically the same as the third embodiment (see Figure 4), but the differences will be explained.

[0052] As shown in Figure 8, in the magnetoresistive element 1 according to the seventh embodiment, the contact layer 70a has an absorption function. That is, the contact layer 70a functions as an absorption layer and, during heat treatment, absorbs one of the elements (e.g., B) among the multiple elements (e.g., CoFeB) that constitute the memory layer 40. The presence of this contact layer 70a ensures that the crystallization of the memory layer 40 is promoted.

[0053] In the example shown in Figure 8, the lower electrode 10, fixed layer 75, spacer layer 80, reference layer 20, barrier layer 30, memory layer 40, storage layer 85, contact layer 70a, and upper electrode 50 are stacked in the order listed, forming the pillar portion 1a. The same effects as in the first embodiment can be obtained with the configuration of the seventh embodiment.

[0054] <8. Eighth Embodiment> <8-1. Example of Magnetoresistive Element Configuration> An example of the configuration of the magnetoresistive element 1 according to the eighth embodiment will be described with reference to Figure 9. Figure 9 is a diagram showing an example of the configuration of the magnetoresistive element 1 according to the eighth embodiment. The eighth embodiment is basically the same as the fourth embodiment (see Figure 5), but the differences will be explained.

[0055] As shown in Figure 9, the magnetoresistive element 1 according to the eighth embodiment has three memory layers 40, 41, and 42, and two absorption layers 90, and 91. These memory layers 40, 41, and 42 and absorption layers 90, and 91 are arranged alternately.

[0056] In the example shown in Figure 9, the lower electrode 10, fixed layer 75, spacer layer 80, reference layer 20, barrier layer 30, memory layer 40, absorption layer 90, memory layer 41, absorption layer 91, memory layer 42, storage layer 85, contact layer 70, and upper electrode 50 are stacked in the order listed, forming the pillar portion 1a. The same effects as in the first embodiment can be obtained with the configuration of the eighth embodiment.

[0057] In the eighth embodiment, three memory layers 40, 41, and 42 and two absorption layers 90, 91 are arranged alternately, but the number of these layers is not limited. Furthermore, each of the three memory layers 40, 41, and 42 may contain the same element or different elements, and each of the two absorption layers 90, 91 may contain the same element or different elements.

[0058] <9. Ninth Embodiment> <9-1. Example of Magnetoresistive Element Configuration> An example of the configuration of the magnetoresistive element 1 according to the ninth embodiment will be described with reference to Figure 10. Figure 10 is a diagram showing an example of the configuration of the magnetoresistive element 1 according to the ninth embodiment. The ninth embodiment is basically the same as the third embodiment (see Figure 4), but the differences will be explained.

[0059] As shown in Figure 10, the magnetoresistive element 1 according to the ninth embodiment has two memory layers 40 and 41 and two storage layers 85 and 86. These memory layers 40 and 41 and storage layers 85 and 86 are arranged alternately.

[0060] In the example shown in Figure 10, the lower electrode 10, fixed layer 75, spacer layer 80, reference layer 20, barrier layer 30, memory layer 40, storage layer 85, memory layer 41, storage layer 86, contact layer 70, and upper electrode 50 are stacked in the order listed, forming a pillar portion 1a. The same effects as in the first embodiment can be obtained with the configuration of the ninth embodiment.

[0061] In the ninth embodiment, two memory layers 40, 41 and two storage layers 85, 86 are arranged alternately, but the number of these layers is not limited. Also, each of the three memory layers 40, 41, and 42 may contain the same element or different elements, and each of the two absorption layers 90, 91 may contain the same element or different elements.

[0062] <10. Comparative Examples and Examples According to Each Embodiment> Comparative examples and examples according to each embodiment will be described with reference to Figures 11 to 13. Figure 11 is a diagram showing the B concentration of the protective layer 60, the film thickness of the absorption layer 90, the MR ratio (readout), the Δ ratio (data retention), and the Vc ratio (writeout) according to Comparative Examples 1 to 2 and Examples 1 to 2. Figure 12 is a diagram showing the configuration examples of each magnetoresistive element 1A to 1D according to Comparative Examples 1 to 2 and Examples 1 to 2. Figure 13 is a diagram showing the elemental concentrations of the protective layer 60 and the memory layer 40 of the magnetoresistive element 1D according to Example 2.

[0063] As shown in Figure 11, there are Comparative Example 1 (reference), Comparative Example 2, Example 1, and Example 2. For each of Comparative Example 1 (reference), Comparative Example 2, Example 1, and Example 2, the protective layer B concentration, absorption layer thickness, MR ratio (read), Δ ratio (data retention), and Vc ratio (write) are shown. The MR ratio is the magnetoresistance ratio. The higher this MR ratio, the lower the read error rate. The Δ ratio is the band ratio. The higher this Δ ratio, the higher the data retention power. The Vc ratio is the write voltage ratio. The lower this Vc ratio, the lower the write voltage, i.e., the write energy.

[0064] Here, as shown in Figure 12, the basic configurations of the magnetoresistive element 1A according to Comparative Example 1, the magnetoresistive element 1B according to Comparative Example 2, the magnetoresistive element 1C according to Example 1, and the magnetoresistive element 1D according to Example 2 are the same as the configuration of the fifth embodiment (see Figure 6). However, the compound layer 61 is absent in the magnetoresistive element 1A according to Comparative Example 1 and the magnetoresistive element 1B according to Comparative Example 2. The difference between the magnetoresistive element 1A and the magnetoresistive element 1B is the difference in the film thickness (thickness) of the absorption layer 90. On the other hand, the compound layer 61 is present in the magnetoresistive element 1C according to Example 1 and the magnetoresistive element 1D according to Example 2. The difference between the magnetoresistive element 1C and the magnetoresistive element 1D is the difference in the film thickness of the absorption layer 90.

[0065] In the example shown in Figure 11, the B concentration of the protective layer 60 in Comparative Example 1 is zero, and the thickness of the absorption layer 90 is thin. The MR ratio, Δ ratio, and Vc ratio of Comparative Example 1 are all 1 times the reference value. The B concentration of the protective layer 60 in Comparative Example 2 is zero, and the thickness of the absorption layer 90 is thick. In Comparative Example 2, the MR ratio is 1.2 times, and the Δ ratio and Vc ratio are all 1.3 times. Therefore, as the thickness of the absorption layer 90 increases, the MR ratio, Δ ratio, and Vc ratio all increase. In other words, the read error rate is lower and the data retention capacity is higher, but the write energy also increases.

[0066] On the other hand, in Example 1, the B concentration of the protective layer 60 is high, and the thickness of the absorption layer 90 is thin. In this Example 1, the MR ratio is 1.2 times, the Δ ratio is 1.3 times, and the Vc ratio is 1 time. Therefore, when the thickness of the absorption layer 90 is thin and the compound layer 61 is present, the MR ratio and Δ ratio increase, and the Vc ratio does not change. In other words, the read error rate is low, the data retention capacity is high, and the write energy is maintained. Therefore, it is possible to improve read performance and retention performance while suppressing the increase in write energy.

[0067] Furthermore, the B concentration of the protective layer 60 in Example 2 is high, and the film thickness of the absorption layer 90 is extremely thin. In this Example 2, the MR ratio and Δ ratio are both 1, and the Vc ratio is 0.8. Therefore, when the film thickness of the absorption layer 90 is extremely thin and the compound layer 61 is present, the MR ratio and Δ ratio do not change, and the Vc ratio becomes low. In other words, the increase in the read error rate and data retention capacity are maintained, and furthermore, the write energy is reduced. Therefore, it is possible to suppress the increase in write energy while maintaining read performance and retention performance.

[0068] As shown in Figure 13, in the magnetoresistive element 1D according to Example 2, when a portion of both the protective layer 60 and the memory layer 40 is inspected by the scanning position SCAN, a graph G1 showing the concentration of each element is obtained. The vertical axis of this graph G1 represents the concentration of the element. The concentration is shown, for example, as atomic fraction per volume (at%). The horizontal axis of graph G1 represents distance (nm) with zero as the reference point.

[0069] In the example shown in Figure 13, the boundary between the compound layer 61 of the protective layer 60 and the memory layer 40 is approximately 4.5 nm. The memory layer 40 contains elements such as N, K, Si, L, Fe, and B. The protective layer 60 also contains elements such as N, K, Si, L, and Fe, as well as B. This protective layer 60 contains either or both Mo and Ta and has the function of absorbing B. Therefore, it can be seen that during heat treatment, the B in the memory layer 40 is absorbed by the protective layer 60, and a compound layer 61 containing B is formed in the protective layer 60. The concentration of B in the compound layer 61 is preferably 1 at% or more in terms of atomic fraction per volume, and more preferably 5 at% or more.

[0070] <11. Examples of Manufacturing Processes for Magnetoresistive Elements According to Each Embodiment> Examples of manufacturing processes for magnetoresistive elements 1 according to each embodiment will be described with reference to Figures 14 to 16. Each of Figures 14 to 16 is a diagram showing the flow of the manufacturing process example for magnetoresistive elements 1 according to each embodiment described above.

[0071] As shown in Figure 14, a semiconductor layer 202 is stacked on a low dielectric constant layer 201. For example, SiC is used as the semiconductor layer 202. For example, a metal layer (metal portion) 201a is formed on the low dielectric constant layer 201. For example, Cu is used as the metal layer 201a. The low dielectric constant layer 201 and the semiconductor layer 202 function as a semiconductor substrate including, for example, wiring and transistors.

[0072] Next, an insulating layer 203 is laminated on the semiconductor layer 202, and a lower electrode layer 204 is laminated on the insulating layer 203. For example, SiO is used as the insulating layer 203. For example, a metal layer (metal portion) 203a is formed on the semiconductor layer 202 and the insulating layer 203. The metal layer 203a functions as a contact layer that electrically connects the lower electrode layer 204 and the metal layer 201a. For example, W is used as the metal layer 203a. For example, TaN is used as the lower electrode layer 204.

[0073] Next, an MTJ layer 205 is formed on the lower electrode layer 204, and an upper electrode layer 206 is laminated on the MTJ layer 205. For example, Ta is used as the upper electrode layer 206. The MTJ layer 205 corresponds to, for example, the layers between the lower electrode 10 and the upper electrode 50 of the magnetoresistive element 1 according to each of the above embodiments. For example, various materials can be used as the MTJ layer 205.

[0074] Subsequently, a protective layer 207 is laminated on the upper electrode layer 206, and an insulating layer 208 is laminated on the protective layer 207. The protective layer 207 and the insulating layer 208 function, for example, as a hard mask. For example, SiN is used as the protective layer 207. For example, SiO is used as the insulating layer 208.

[0075] As shown in Figure 15, the protective layer 207 and the insulating layer 208 are processed based on a predetermined pattern. At this time, the upper electrode layer 206 is also processed based on a predetermined pattern. The predetermined pattern is, for example, a pattern for forming a plurality of magnetoresistive elements 1 in a two-dimensional matrix shape in a plan view.

[0076] Next, the MTJ layer 205 and the insulating layer 203 are processed by etching to form a plurality of pillar portions 1a, and a protective layer 209 is laminated on each pillar portion 1a and the insulating layer 203. The protective layer 209 corresponds, for example, to the protective layer 60 of the magnetoresistive element 1 according to each of the embodiments described above. For example, SiN is used as the protective layer 209.

[0077] Next, an insulating layer 210 is laminated on the protective layer 209. The insulating layer 210 functions, for example, as an inter-element film between each pillar portion 1a (each magnetoresistive element 1). For example, SiO is used as the insulating layer 210.

[0078] Here, the insulating layer 210 is an example of a fifth non-magnetic layer. The insulating layer 210 may be composed of a dielectric material including, for example, Si, Al, Ta, Hf, Nb, lanthanides, or actinides. It is desirable that the dielectric breakdown voltage of the insulating layer 210 is greater than that of the protective layer 209 (protective layer 60).

[0079] As shown in Figure 16, a plurality of contact holes 210b are formed in the insulating layer 210. These contact holes 210b are provided, for example, above the metal layer 203a and each pillar portion 1a.

[0080] Next, a metal layer (metal portion) 210a is formed in each contact hole 210b. The metal layer 210a functions, for example, as a contact layer. For example, W is used as the metal layer 210a. In the process of forming this metal layer 210a, each pillar portion 1a is heat-treated, and a compound layer 61 is formed on the protective layer 209 for each pillar portion 1a. The compound layer 61 is formed around each pillar portion 1a.

[0081] Next, a metal layer (metal portion) 211 is laminated on the insulating layer 210 and the metal layer 210a. The metal layer 211 functions, for example, as wiring. For example, Cu is used as the metal layer 211.

[0082] In the aforementioned manufacturing process, CMP (chemical mechanical polishing) and cleaning are performed as appropriate. Furthermore, various etching methods are used for patterning. In addition, various manufacturing methods such as sputtering, ion beam deposition, physical vapor deposition (PVD), and chemical vapor deposition (CVD) may be used in the aforementioned manufacturing process.

[0083] <12. Storage Devices According to Each Embodiment> <12-1. Examples of Storage Device Configurations> Examples of the configurations of the storage devices 100 according to each embodiment described above will be explained with reference to Figure 17. Figure 17 is a diagram showing examples of the configurations of the storage devices 100 according to each embodiment described above.

[0084] As shown in Figure 17, the storage device 100 includes a memory cell array 110. This storage device 100 is an example of a storage device having a magnetoresistive element 1 according to any of the embodiments described above.

[0085] The memory cell array 110 includes a plurality of memory cells 11. Each memory cell 11 is arranged in a two-dimensional matrix. Each of these memory cells 11 stores data. Each of the memory cells 11 is connected to a bit line BL, a source line SL, and a word line WL. For example, each of the plurality of word lines WL is wired to extend in the row direction, and each of the plurality of bit lines BL and the plurality of source lines SL is wired to extend in the column direction. Each of the bit lines BL, source lines SL, and word lines WL functions, for example, as a control line.

[0086] Each memory cell 11 has a magnetoresistive element (magnetoresistive effect element) 1 and a selection transistor 2. The magnetoresistive element 1 is a magnetoresistive element according to any of the embodiments described above. In the example of Figure 17, each memory cell 11 shares one source line SL for every two columns in the column direction. That is, each memory cell 11 arranged in two columns in the column direction is connected to two bit lines BL and one source line SL (2BL / 1SL). Note that each memory cell 11 may have one source line SL for each column in the column direction. That is, each memory cell 11 arranged in one column in the column direction may be connected to one bit line BL and one source line SL (1BL / 1SL).

[0087] The magnetoresistive element 1 is electrically connected between the bit line BL and the source line SL. In the example shown in Figure 17, one end of the magnetoresistive element 1 is connected to the bit line BL, and the other end is connected to the source line SL via the selection transistor 2.

[0088] The selection transistor 2 is an example of a selection element for selecting a memory cell 11 from a plurality of memory cells 11 to be used for reading or writing data. Various types of transistors, such as field-effect transistors, can be used as the selection transistor 2. The function of the selection transistor 2 is also referred to as a selector function.

[0089] The selection transistor 2 switches between a state that allows data access (reading and writing data) to the corresponding magnetoresistive element 1 and a state that prevents data access. In the example in Figure 17, one of the source and drain of the selection transistor 2 is connected to the magnetoresistive element 1, and the other is connected to the source line SL. The gate of the selection transistor 2 is connected to the word line WL. When the selection transistor 2 is turned on (conducting), data access to the magnetoresistive element 1 to which the selection transistor 2 is connected becomes possible. When the selection transistor 2 is turned off (non-conducting), data access to the magnetoresistive element 1 to which the selection transistor 2 is connected is prevented.

[0090] The memory device 100 includes various peripheral circuits in addition to the memory cell array 110. In the example shown in Figure 17, the peripheral circuits include an I / O (input / output circuit) 12, a control circuit 13, a voltage generation circuit 14, a bit line address decoder 15, a bit line control circuit 16, a word line address decoder 17, a word line control circuit 18, and a sense amplifier 19. Since the basic configuration and operation of such a memory device 100 are well known, its basic configuration and operation will be briefly explained.

[0091] I / O 12 enables the exchange of commands related to reading and writing data, the address of the memory cell 11 to be accessed, and data between the external circuitry of the storage device 100 (for example, the central processing unit, the arithmetic circuit, etc.) and the control circuit 13 of the storage device 100.

[0092] The control circuit 13 controls the writing and reading of data to the memory cell 11, specifically the magnetoresistive element 1 within the memory cell 11, in accordance with commands. For example, the control circuit 13 receives commands (such as write and read commands) from an external circuit and controls the writing and reading of data based on the received commands.

[0093] The voltage generation circuit 14 generates voltages used for writing and reading data from the memory cell 11 (e.g., data writing voltage and data reading voltage), and supplies the generated voltages (e.g., pulse voltage) to the bit line control circuit 16.

[0094] The bit line address decoder 15 selects a bit line BL of the memory cell array 110 based on a control signal from the control circuit 13. For example, the bit line address decoder 15 obtains the address of the bit line BL corresponding to the address received by the I / O 12 described above.

[0095] The bit line control circuit 16 selects and controls the bit line BL corresponding to the address of the bit line address decoder 15. Each bit line BL is connected to the bit line control circuit 16.

[0096] For example, writing data to the memory cell 11 using the data writing voltage generated by the voltage generation circuit 14, and reading data from the memory cell 11 using the data reading voltage generated by the voltage generation circuit 14, are performed via the bit line control circuit 16 or the like.

[0097] The word line address decoder 17 selects a word line WL of the memory cell array 110 based on a control signal from the control circuit 13. For example, the word line address decoder 17 obtains the address of the word line WL corresponding to the address received by the I / O 12 described above.

[0098] The word line control circuit 18 selects and controls the word line WL corresponding to the address of the word line address decoder 17. Each word line WL is connected to the word line control circuit 18.

[0099] The sense amplifier 19 detects the data read from the memory cell 11 via the source line SL, that is, the resistance state (resistance value) of the magnetoresistive element 1. Each source line SL is connected to the sense amplifier 19.

[0100] <12-2. Example of Memory Cell Configuration> An example of the configuration of the memory cell 11 of the memory device 100 described above will be explained with reference to Figure 18. Figure 18 is a diagram showing an example of the configuration of the memory cell 11 of the memory device 100 described above. In addition to the magnetoresistive element 1 and the selection transistor 2 of the memory cell 11, Figure 18 shows the magnetic field generating layer 3, the contact layer 4, the semiconductor substrate 5, the bit line BL, the word line WL, and the source line SL.

[0101] The selection transistor 2 includes a source region 2a, a drain region 2b, and a gate electrode. The source region 2a and drain region 2b are formed on the semiconductor substrate 5. In the example in Figure 18, the gate electrode is the word line WL.

[0102] The magnetic field generating layer 3 applies a magnetic field to the magnetoresistive element 1 in the horizontal direction (XY plane direction), for example. The magnetic field generating layer 3 is used to apply an external magnetic field to the magnetoresistive element 1. In the example shown in Figure 18, the magnetic field generating layer 3 is positioned above the magnetoresistive element 1 (on the positive Z-axis side). However, the magnetic field generating layer 3 may also be positioned below the magnetoresistive element 1 (on the positive Z-axis side). The magnetic field generating layer 3 is also referred to as a ferromagnetic bias layer, for example.

[0103] The magnetic field generating layer 3 may be placed for each magnetoresistive element 1, or it may be placed in common across multiple magnetoresistive elements 1. Alternatively, instead of the magnetic field generating layer 3, a method may be used in which a magnetic field is applied to the entire memory cell array 110 including the memory cell 11, or a method may be used that utilizes a magnetic field induced by wiring and current for magnetic field application.

[0104] The contact layer 4 is a layer that electrically connects several elements and is composed of, for example, vias. In the example in Figure 18, three contact layers 4 are shown: a contact layer 4 connecting the magnetic field generating layer 3 and the bit line BL, a contact layer 4 connecting the magnetoresistive element 1 and the source region 2a, and a contact layer 4 connecting the drain region 2b and the source line SL.

[0105] <12-3. Examples of Writing and Reading Operations> Examples of writing and reading operations will be explained with reference to Figures 19 and 20. Figure 19 is a diagram illustrating an example of writing to the magnetoresistive element 1 of the memory cell 11 described above. Figure 20 is a diagram illustrating an example of reading to the magnetoresistive element 1 of the memory cell 11 described above. For convenience, data corresponding to a low resistance state is 0, and data corresponding to a high resistance state is 1.

[0106] (Writing Operation) As shown in Figure 19, during the writing operation, when writing 0 (when 0 is written to the magnetoresistive element 1), a data writing voltage is applied to the magnetoresistive element 1 so that current flows from the lower electrode 10 to the upper electrode 50. This writes 0 to the magnetoresistive element 1. On the other hand, during the writing operation, when writing 1 (when 1 is written to the magnetoresistive element 1), a data writing voltage is applied to the magnetoresistive element 1 so that current flows from the upper electrode 50 to the lower electrode 10. This writes 1 to the magnetoresistive element 1. Thus, the direction of the current during writing may be changed depending on the data to be written.

[0107] (Read Operation) As shown in Figure 20, during the read operation, when reading data, a data read voltage is applied to the magnetoresistive element 1 so that current flows from the lower electrode 10 to the upper electrode 50, and the resistance value of the magnetoresistive element 1 is detected. As a result, data is read from the magnetoresistive element 1. The current during the read operation is smaller than the current during the write operation.

[0108] <12-4. Example of Writing Process> An example of the writing process of the storage device 100 described above will be explained with reference to Figure 21. Figure 21 is a diagram showing the flow of the writing process example of the storage device 100 described above.

[0109] The control circuit 13 (for example, the state machine within the control circuit 13) controls the writing process. The flowchart starts when a write command and write data are input to the control circuit 13 from I / O 12. For convenience, data corresponding to a low resistance state is 0, and data corresponding to a high resistance state is 1.

[0110] As shown in Figure 21, in step S1, an initial read operation is performed. In step S2, a comparison is performed between the read data and the write data. In step S3, it is determined whether the read data matches the write data. If it is determined that the read data matches the write data (step S3: Yes), the process ends. On the other hand, if it is determined in step S3 that the read data does not match the write data (step S3: No), in step S4, a write voltage is applied to the selected cell (selected memory cell 11). In step S5, a verify read operation is performed, and the process returns to step S2. After that, the process from step S2 onwards is executed again.

[0111] In the example in Figure 21, the number of iterations for verifying reads is not set, but it is possible to pre-set a maximum number of iterations. Alternatively, the process may be terminated without performing a verifying read. Note that while the example in Figure 21 shows an example of writing including initial reads and verifying reads, various read methods may be used for reading.

[0112] <13. Effects and Effects of Each Embodiment> As described above, the magnetoresistive element 1 according to the embodiment comprises a pillar portion 1a having a first magnetic layer (e.g., a reference layer 20), a first non-magnetic layer laminated on the first magnetic layer (e.g., a barrier layer 30), and a second magnetic layer laminated on the first non-magnetic layer (e.g., a memory layer 40), a second non-magnetic layer (e.g., a protective layer 60) formed on the side surface of the pillar portion 1a, and a third non-magnetic layer (e.g., a compound layer 61) formed between the side surface of the pillar portion 1a and the second non-magnetic layer, wherein the third non-magnetic layer contains any of the multiple elements constituting the pillar portion 1a (see Figure 1, etc.). This enables crystallization of the pillar portion 1a (e.g., the reference layer 20, the memory layer 40, etc.). Furthermore, the third non-magnetic layer is not present within the pillar portion 1a, which suppresses the increase in write voltage. Therefore, it is possible to suppress the increase in write voltage while improving or maintaining read performance and retention performance.

[0113] Furthermore, the third non-magnetic layer may contain any of the elements that constitute one or both of the first and second magnetic layers (see Figure 1, etc.). This makes it possible to achieve crystallization of one or both of the first and second magnetic layers.

[0114] Furthermore, the third non-magnetic layer may also contain element B, one of the aforementioned elements (see Figures 1, 11 to 13, etc.). This ensures that when one or both of the first and second magnetic layers contain element B, crystallization of one or both of the first and second magnetic layers can be reliably achieved.

[0115] Furthermore, the third non-magnetic layer may contain Si, N, and O in addition to B (see Figures 1, 11 to 13, etc.). This ensures that crystallization of one or both of the first and second magnetic layers can be reliably achieved.

[0116] Furthermore, the concentration of B in the third non-magnetic layer may be 1 at% or more in terms of atomic fraction per volume (see Figures 11 to 13, etc.). This ensures that crystallization of one or both of the first and second magnetic layers can be reliably achieved.

[0117] Furthermore, the length of the third nonmagnetic layer in the direction along the side surface of the pillar portion 1a may be longer than the thickness of one or both of the first magnetic layer and the second magnetic layer (see Figure 1, etc.). This ensures that crystallization of the pillar portion 1a is reliably achieved.

[0118] Furthermore, the side-reference thickness of the pillar portion 1a in the third non-magnetic layer may be 1 nm or more and 5 nm or less (see Figure 1, etc.). This ensures that crystallization of the pillar portion 1a is reliably achieved.

[0119] Furthermore, the third nonmagnetic layer may be amorphous (see Figure 1, etc.). This ensures that the crystallization of the pillar portion 1a is reliably achieved.

[0120] Furthermore, the electrical conductivity of the third non-magnetic layer may be lower than that of the pillar portion 1a (see Figure 1, etc.). This ensures that the increase in writing voltage is reliably suppressed while reliably improving or maintaining read and hold performance.

[0121] Furthermore, the pillar portion 1a may further have a fourth non-magnetic layer (for example, a contact layer 70 or a storage layer 85) laminated on the second magnetic layer (see Figures 3 and 4, etc.). This ensures that the increase in writing voltage is reliably suppressed while reliably improving or maintaining read performance and retention performance.

[0122] Furthermore, the pillar portion 1a may further have an absorption layer 90 containing any of the multiple elements that constitute one or both of the first magnetic layer and the second magnetic layer (see Figures 5 to 7, etc.). This ensures that the increase in write voltage is reliably suppressed while reliably improving or maintaining read performance and retention performance.

[0123] Furthermore, the first or second magnetic layer may contain at least one element from among Ti, V, Cr, Mn, Fe, Co, and Ni (see Figure 1, etc.). This ensures that the increase in write voltage is reliably suppressed while reliably improving or maintaining read and hold performance.

[0124] Furthermore, the first or second magnetic layer may contain at least one element from among Ir, Ru, Os, Re, Cr, Mo, W, Ta, Pt, and Pd (see Figure 1, etc.). This ensures that the increase in write voltage is reliably suppressed while reliably improving or maintaining read and hold performance.

[0125] Furthermore, the first or second magnetic layer may be an artificial ferrimagnetic material (see Figure 1, etc.). This ensures that the increase in write voltage is reliably suppressed while reliably improving or maintaining read and hold performance.

[0126] Furthermore, the first non-magnetic layer may be an oxide, nitride, fluoride, a mixture of oxide, nitride and fluoride, or a laminate of oxide, nitride and fluoride (see Figure 1, etc.). This ensures that the increase in write voltage is reliably suppressed while reliably improving or maintaining read and hold performance.

[0127] Furthermore, the magnetoresistive element 1 may further include a fifth non-magnetic layer (for example, an insulating layer 210) covering the second non-magnetic layer (see Figures 15 and 16, etc.). This ensures that the increase in write voltage is reliably suppressed while reliably improving or maintaining read and hold performance.

[0128] Furthermore, the fifth non-magnetic layer may be composed of a dielectric material including Si, Al, Ta, Hf, Nb, lanthanides, or actinides (see Figures 15 and 16, etc.). This ensures that the increase in write voltage is reliably suppressed while reliably improving or maintaining read and hold performance.

[0129] Furthermore, the dielectric breakdown voltage of the fifth non-magnetic layer may be greater than that of the second non-magnetic layer (see Figures 15 and 16, etc.). This ensures that the increase in write voltage is reliably suppressed while reliably improving or maintaining read and hold performance.

[0130] <14. Other Embodiments> The configurations and processes described in the above-described embodiments (including examples and modifications) may be implemented in various other forms besides those described above. For example, the configurations and processes may be in various forms, not limited to the examples described above. Also, for example, the configurations, processing procedures, specific names, and information including various data and parameters shown in the above document and drawings may be changed at will unless otherwise specified.

[0131] Furthermore, the configurations and processes described in the above-mentioned embodiments (including examples and modifications) do not necessarily have to be physically configured as shown in the figures. In other words, the specific forms of distribution or integration of each configuration and process are not limited to those shown in the figures, and all or part of them may be functionally or physically distributed or integrated in any unit depending on various loads and usage conditions.

[0132] Furthermore, the various configurations and processes described in the above-mentioned embodiments (including examples and modifications) may be combined as appropriate. For example, at least a part of one embodiment may be combined with at least a part of another embodiment as appropriate. Also, the effects described in the embodiments are merely illustrative and not limiting, and other effects may also occur.

[0133] <15. Application Examples> <15-1. Various Devices> Application examples of the storage device 100 according to each of the embodiments described above (including examples and modified versions) will be explained with reference to Figure 22. Figure 22 is a diagram showing the application examples of the storage device 100 described above. The storage device 100 may be applied to various cases, i.e., various devices (electronic devices), as follows.

[0134] As shown in Figure 22, the memory device 100 is used in, for example, "devices that capture images for viewing purposes, such as digital cameras and portable devices with camera functions," "devices used for traffic purposes, such as in-vehicle sensors that capture images of the front, rear, surroundings, and interior of a vehicle for safe driving such as automatic stopping and recognition of the driver's condition, surveillance cameras that monitor moving vehicles and roads, and distance measuring sensors that measure distances between vehicles," "devices used in home appliances such as TVs, refrigerators, and air conditioners to capture user gestures and perform device operations according to those gestures," "devices used for medical and healthcare purposes, such as endoscopes and devices that perform angiography by receiving infrared light," "devices used for security purposes, such as surveillance cameras for crime prevention and cameras for person recognition," "devices used for beauty purposes, such as skin measuring devices that capture images of the skin and microscopes that capture images of the scalp," "devices used for sports purposes, such as action cameras and wearable cameras for sports use," and "devices used for agriculture, such as cameras for monitoring the condition of fields and crops."

[0135] Furthermore, the technology disclosed herein can be applied to a variety of products. For example, the technology disclosed herein may be implemented as electronic equipment mounted on any type of mobile device, such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, robots, construction machinery, or agricultural machinery (tractors). Alternatively, for example, the technology disclosed herein may be implemented as electronic equipment mounted on endoscopic surgical systems or microsurgical systems.

[0136] <15-2. Imaging Device> The imaging device 300 according to the application example will be described with reference to Figure 23. Figure 23 is a diagram showing an example configuration of the imaging device 300 according to the application example. This imaging device 300 is, for example, an example of an electronic device to which the storage device 100 described above is applied. Examples of imaging devices 300 include digital still cameras, video cameras, smartphones and mobile phones with imaging functions, and other electronic devices.

[0137] As shown in Figure 23, the imaging device 300 includes an optical system 301, a shutter device 302, an image sensor 303, a control circuit (drive circuit) 304, a signal processing circuit 305, a monitor 306, and a memory 307. This imaging device 300 is capable of capturing both still and moving images.

[0138] The optical system 301 has one or more lenses. This optical system 301 guides light from the subject (incident light) to the image sensor 303 and forms an image on the light-receiving surface of the image sensor 303.

[0139] The shutter device 302 is positioned between the optical system 301 and the image sensor 303. The shutter device 302 controls the light illumination period and the light shielding period for the image sensor 303 according to the control of the control circuit 304.

[0140] The image sensor 303 accumulates signal charge for a certain period of time in response to light formed on the light-receiving surface via the optical system 301 and shutter device 302. The signal charge accumulated in the image sensor 303 is transferred according to a drive signal (timing signal) supplied from the control circuit 304. As the image sensor 303, a solid-state imaging device such as an image sensor is used, for example.

[0141] The control circuit 304 drives the image sensor 303 and the shutter device 302 by outputting drive signals that control the transfer operation of the image sensor 303 and the shutter operation of the shutter device 302.

[0142] The signal processing circuit 305 performs various signal processing operations on the signal charge output from the image sensor 303. The image (image data) obtained by the signal processing circuit 305 is supplied to the monitor 306 and also to the memory 307.

[0143] The monitor 306 displays video or still images captured by the image sensor 303 based on image data supplied from the signal processing circuit 305. For example, the monitor 306 may be a panel-type display device such as a liquid crystal panel or an organic EL (Electro-Luminescence) panel.

[0144] The memory 307 stores image data supplied from the signal processing circuit 305, that is, image data of moving or still images captured by the image sensor 303. For example, the aforementioned storage device 100 is used as the memory 307.

[0145] In the imaging device 300 configured in this way, the same effects as in the above embodiment can be obtained by applying the aforementioned storage device 100 as the memory 307.

[0146] <15-3. Distance Measuring Device> The distance measuring device 400 according to the application example will be described with reference to Figure 24. Figure 24 is a diagram showing an example of the configuration of the distance measuring device 400 according to the application example. This distance measuring device 400 is, for example, an example of an electronic device to which the storage device 100 described above is applied.

[0147] As shown in Figure 24, the distance measuring device (distance image sensor) 400 comprises a light source unit 401, an optical system 402, an image sensor 403, a control circuit (drive circuit) 404, a signal processing circuit 405, a monitor 406, and a memory 407. This distance measuring device 400 can acquire a distance image corresponding to the distance to the subject by projecting light from the light source unit 401 toward the subject and receiving the light (modulated light or pulsed light) reflected from the surface of the subject.

[0148] The light source unit 401 projects light toward the subject. The light source unit 401 can be, for example, a vertical cavity surface-emitting laser (VCSEL) array that emits laser light as a surface light source, or a laser diode array in which laser diodes are arranged in a line. The laser diode array is supported by a predetermined drive unit (not shown) and scanned in a direction perpendicular to the arrangement of the laser diodes.

[0149] The optical system 402 has one or more lenses. This optical system 402 guides light from the subject (incident light) to the image sensor 403 and forms an image on the light-receiving surface (sensor part) of the image sensor 403.

[0150] The image sensor 403 accumulates signal charge in response to light formed on the light-receiving surface via the optical system 402. A distance signal indicating the distance, determined from the light-receiving signal (APD OUT) output from the image sensor 403, is supplied to the signal processing circuit 405. As the image sensor 403, for example, a solid-state imaging device such as an image sensor is used.

[0151] The control circuit 404 outputs drive signals (control signals) that control the operation of the light source unit 401 and the image sensor 403, and drives the light source unit 401 and the image sensor 403.

[0152] The signal processing circuit 405 performs various signal processing operations on the distance signal supplied from the image sensor 403. For example, the signal processing circuit 405 performs image processing (e.g., histogram processing and peak detection processing) to construct a distance image based on the distance signal. The image (image data) obtained by the signal processing circuit 405 is supplied to the monitor 406 and also to the memory 407.

[0153] The monitor 406 displays the distance image captured by the image sensor 403 based on the image data supplied from the signal processing circuit 405. For example, a panel-type display device such as a liquid crystal panel or an organic EL panel can be used as the monitor 406.

[0154] The memory 407 stores image data supplied from the signal processing circuit 405, that is, image data of the distance image captured by the image sensor 403. For example, the aforementioned storage device 100 is used as the memory 407.

[0155] In the distance measuring device 400 configured in this way, the same effects as in the above embodiment can be obtained by applying the aforementioned storage device 100 as the memory 407.

[0156] As described above, the aforementioned storage device 100 can be implemented in various electronic devices. For example, in addition to the imaging device 300 and the distance measuring device 400, the storage device 100 may be installed in various electronic devices such as HDDs (hard disk drives), notebook PCs (personal computers), mobile devices (e.g., smartphones and tablet PCs), PDAs (personal digital assistants), wearable devices, game consoles, and music players. For example, the storage device 100 may be used as various types of memory, such as storage.

[0157] <16. Addendum> The technology can also be configured as follows: (1) A magnetoresistive element comprising: a pillar portion having a first magnetic layer, a first non-magnetic layer laminated on the first magnetic layer, and a second magnetic layer laminated on the first non-magnetic layer; a second non-magnetic layer formed on the side surface of the pillar portion; and a third non-magnetic layer formed between the side surface of the pillar portion and the second non-magnetic layer, wherein the third non-magnetic layer contains any of the multiple elements constituting the pillar portion. (2) The magnetoresistive element according to (1), wherein the third non-magnetic layer contains any of the multiple elements constituting one or both of the first magnetic layer and the second magnetic layer. (3) The magnetoresistive element according to (2), wherein the third non-magnetic layer contains B, one of the multiple elements. (4) The magnetoresistive element according to (3), wherein the third non-magnetic layer contains Si, N, and O. (5) The magnetoresistive element according to (3) or (4), wherein the content of B in the third non-magnetic layer is 1 at% or more in terms of atomic fraction per volume. (6) The magnetoresistive element according to any one of (2) to (5), wherein the length of the third non-magnetic layer in the direction along the side surface of the pillar portion is longer than the thickness of one or both of the first magnetic layer and the second magnetic layer. (7) The magnetoresistive element according to any one of (1) to (6), wherein the thickness of the third non-magnetic layer relative to the side surface of the pillar portion is 1 nm or more and 5 nm or less. (8) The magnetoresistive element according to any one of (1) to (7), wherein the third non-magnetic layer is amorphous. (9) The magnetoresistive element according to any one of (1) to (8), wherein the electrical conductivity of the third non-magnetic layer is lower than the electrical conductivity of the pillar portion. (10) The magnetoresistive element according to any one of (1) to (9), wherein the pillar portion further comprises a fourth non-magnetic layer laminated on the second magnetic layer. (11) The magnetoresistive element according to any one of (1) to (10), wherein the pillar portion further comprises an absorption layer containing any of the multiple elements that constitute one or both of the first magnetic layer and the second magnetic layer.(12) The magnetoresistive element according to any one of (1) to (11), wherein the first magnetic layer or the second magnetic layer contains at least one element from among Ti, V, Cr, Mn, Fe, Co, and Ni. (13) The magnetoresistive element according to any one of (1) to (12), wherein the first magnetic layer or the second magnetic layer contains at least one element from among among Ir, Ru, Os, Re, Cr, Mo, W, Ta, Pt, and Pd. (14) The magnetoresistive element according to any one of (1) to (13), wherein the first magnetic layer or the second magnetic layer is an artificial ferrimagnetic material. (15) The magnetoresistive element according to any one of (1) to (14), wherein the first non-magnetic layer is an oxide, nitride, fluoride, or a mixture of oxide, nitride and fluoride, or a laminate of oxide, nitride and fluoride. (16) A magnetoresistive element according to any one of (1) to (15), further comprising a fifth non-magnetic layer covering the second non-magnetic layer. (17) The magnetoresistive element according to (16), wherein the fifth non-magnetic layer has a dielectric including Si, Al, Ta, Hf, Nb, a lanthanide, or an actinide. (18) The magnetoresistive element according to (16) or (17), wherein the dielectric breakdown voltage of the fifth non-magnetic layer is greater than the dielectric breakdown voltage of the second non-magnetic layer. (19) A memory device comprising a magnetoresistive element, the magnetoresistive element having a pillar portion having a first magnetic layer, a first non-magnetic layer laminated on the first magnetic layer, and a second magnetic layer laminated on the first non-magnetic layer, a second non-magnetic layer formed on the side surface of the pillar portion, and a third non-magnetic layer formed between the side surface of the pillar portion and the second non-magnetic layer, wherein the third non-magnetic layer includes any of the multiple elements constituting the pillar portion. (20) A method for manufacturing a magnetoresistive element, comprising: forming a second non-magnetic layer that absorbs any of the multiple elements constituting the pillar portion on the side surface of a pillar portion having a first magnetic layer, a first non-magnetic layer laminated on the first magnetic layer, and a second magnetic layer laminated on the first non-magnetic layer; and forming a third non-magnetic layer containing any of the multiple elements between the side surface of the pillar portion and the second non-magnetic layer by heat treatment.(21) A memory device comprising a magnetoresistive element according to any one of (1) to (18). (22) A method for manufacturing a magnetoresistive element, comprising manufacturing a magnetoresistive element according to any one of (1) to (18). (23) An electronic device comprising a memory device according to (21).

[0158] 1 Magnetoresistive element 1a Pillar portion 10 Lower electrode 20 Reference layer 21 Reference layer 30 Barrier layer 40 Memory layer 41 Memory layer 42 Memory layer 50 Upper electrode 60 Protective layer 61 Compound layer 70 Contact layer 70a Contact layer 75 Fixed layer 80 Spacer layer 85 Storage layer 86 Storage layer 90 Absorption layer 91 Absorption layer 100 Memory device 201 Low dielectric constant layer 201a Metal layer (metal portion) 202 Semiconductor layer 203 Insulating layer 203a Metal layer 204 Lower electrode layer 205 MTJ layer 206 Upper electrode layer 207 Protective layer 208 Insulating layer 209 Protective layer 210 Insulating layer 210a Metal layer 210b Contact hole 211 metal layer

Claims

1. A magnetoresistive element comprising: a pillar portion having a first magnetic layer, a first non-magnetic layer laminated on the first magnetic layer, and a second magnetic layer laminated on the first non-magnetic layer; a second non-magnetic layer formed on the side surface of the pillar portion; and a third non-magnetic layer formed between the side surface of the pillar portion and the second non-magnetic layer, wherein the third non-magnetic layer contains any of the elements constituting the pillar portion.

2. The magnetoresistive element according to claim 1, wherein the third non-magnetic layer comprises any of the elements that constitute one or both of the first magnetic layer and the second magnetic layer.

3. The magnetoresistive element according to claim 2, wherein the third non-magnetic layer contains B among the plurality of elements.

4. The magnetoresistive element according to claim 3, wherein the third non-magnetic layer comprises Si, N, and O.

5. The magnetoresistive element according to claim 3, wherein the content of B in the third non-magnetic layer is 1 at% or more in terms of atomic fraction per volume.

6. The magnetoresistive element according to claim 2, wherein the length of the third nonmagnetic layer in the direction along the side surface of the pillar portion is longer than the thickness of one or both of the first magnetic layer and the second magnetic layer.

7. The magnetoresistive element according to claim 1, wherein the thickness of the pillar portion in the third nonmagnetic layer is 1 nm or more and 5 nm or less.

8. The magnetoresistive element according to claim 1, wherein the third non-magnetic layer is amorphous.

9. The magnetoresistive element according to claim 1, wherein the electrical conductivity of the third non-magnetic layer is lower than that of the pillar portion.

10. The magnetoresistive element according to claim 1, wherein the pillar portion further comprises a fourth non-magnetic layer laminated on the second magnetic layer.

11. The magnetoresistive element according to claim 1, wherein the pillar portion further comprises an absorption layer containing any of the multiple elements that constitute one or both of the first magnetic layer and the second magnetic layer.

12. The magnetoresistive element according to claim 1, wherein the first magnetic layer or the second magnetic layer contains at least one element selected from Ti, V, Cr, Mn, Fe, Co, and Ni.

13. The magnetoresistive element according to claim 1, wherein the first magnetic layer or the second magnetic layer contains at least one element from among Ir, Ru, Os, Re, Cr, Mo, W, Ta, Pt, and Pd.

14. The magnetoresistive element according to claim 1, wherein the first magnetic layer or the second magnetic layer is an artificial ferrimagnetic material.

15. The magnetoresistive element according to claim 1, wherein the first non-magnetic layer is an oxide, nitride, fluoride, or a mixture of an oxide, nitride and fluoride, or a laminate of an oxide, nitride and fluoride.

16. The magnetoresistive element according to claim 1, further comprising a fifth non-magnetic layer covering the second non-magnetic layer.

17. The magnetoresistive element according to claim 16, wherein the fifth nonmagnetic layer has a dielectric material including Si, Al, Ta, Hf, Nb, a lanthanide, or an actinide.

18. The magnetoresistive element according to claim 16, wherein the dielectric breakdown voltage of the fifth non-magnetic layer is greater than the dielectric breakdown voltage of the second non-magnetic layer.

19. A memory device comprising a magnetoresistive element, wherein the magnetoresistive element has a pillar portion having a first magnetic layer, a first non-magnetic layer laminated on the first magnetic layer, and a second magnetic layer laminated on the first non-magnetic layer, a second non-magnetic layer formed on the side surface of the pillar portion, and a third non-magnetic layer formed between the side surface of the pillar portion and the second non-magnetic layer, the third non-magnetic layer containing any of the elements constituting the pillar portion.

20. A method for manufacturing a magnetoresistive element, comprising: forming a second non-magnetic layer that absorbs any of the multiple elements constituting the pillar portion on the side surface of a pillar portion having a first magnetic layer, a first non-magnetic layer laminated on the first magnetic layer, and a second magnetic layer laminated on the first non-magnetic layer; and forming a third non-magnetic layer containing any of the multiple elements between the side surface of the pillar portion and the second non-magnetic layer by heat treatment.

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