Display panel and display apparatus

Abstract

A display panel, the display panel comprising a virtual driving transistor (81). A gate of the virtual driving transistor (81) and a virtual common electrode (41) input a reference signal (Vcom), the virtual common electrode (41) is connected to a source of the virtual driving transistor (81), and a virtual pixel electrode (31) is electrically connected to the source of the virtual driving transistor (81), equivalent to the virtual pixel electrode (31) receiving the reference signal (Vcom). Therefore, there is no parasitic capacitance between the virtual pixel electrode (31) and the virtual common electrode (41), the virtual driving transistor (81) is turned on, and the reference signal (Vcom) is written into a suspended drain of the virtual driving transistor (81). Thus, both the drain and the gate of the virtual driving transistor (81) are reference signals (Vcom), and there is no parasitic capacitance between the drain and the gate of the virtual driving transistor (81).

Description

Display panel and display device

[0001] Cross-referencing

[0002] This disclosure claims priority to Chinese Patent Application No. 202411549404.6, filed on October 31, 2024, entitled “Display Panel and Display Device,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and more specifically, to a display panel and a display device. Background Technology

[0004] The voltage stability of the reference signal loaded on the external common signal line within the LCD panel is crucial. If the voltage of the reference signal deviates and cannot be quickly recovered, it will affect the display quality.

[0005] For virtual sub-pixels on the periphery of the display area, the load on the peripheral common signal line in the virtual pixel driving circuit is relatively large, which reduces the recovery speed of the reference signal after the voltage is pulled.

[0006] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0007] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide a display panel and display device.

[0008] According to one aspect of this disclosure, a display panel is provided, the display panel having a display area and a virtual pixel area, the virtual pixel area being disposed around the display area, the display panel including a virtual pixel driving circuit disposed in the virtual pixel area, the virtual pixel driving circuit including a virtual driving transistor, a virtual pixel electrode and a virtual common electrode, the gate of the virtual driving transistor receiving a reference signal, the drain of the virtual driving transistor being floating; the virtual pixel electrode being electrically connected to the source of the virtual driving transistor; the virtual common electrode being connected to the source of the virtual driving transistor, the virtual common electrode receiving a reference signal.

[0009] In one embodiment of the present invention, the display panel includes a substrate, a gate layer, an active layer, a source / drain conductive layer, a pixel electrode layer, and a common electrode layer. The gate layer includes a virtual gate line, and the virtual gate line includes a virtual gate portion. The active layer includes a virtual active portion, and the orthographic projection of the gate layer on the substrate overlaps with the orthographic projection of the virtual active portion on the substrate to form the gate of a virtual driving transistor. The source / drain conductive layer includes a virtual source portion, a virtual drain portion, and an internal common signal line. The orthographic projection of the virtual source portion on the substrate overlaps with the orthographic projection of the virtual active portion on the substrate to form the source of the virtual driving transistor. The orthographic projection of the virtual drain portion on the substrate overlaps with the orthographic projection of the virtual active portion on the substrate to form the drain of the virtual driving transistor. The internal common signal line is connected to the virtual source portion. The pixel electrode layer includes a virtual pixel electrode, and the virtual pixel electrode is connected to the virtual source portion. The common electrode layer includes a virtual common electrode, and the orthographic projection of the virtual common electrode on the substrate overlaps with the orthographic projection of the internal common signal line on the substrate. The virtual common electrode is connected through a first via and the internal common signal line.

[0010] In one embodiment of the present invention, the common electrode layer further includes a transition portion, which is connected to the virtual source electrode and the virtual pixel electrode respectively through a second via.

[0011] In one embodiment of the present invention, the common electrode layer is disposed on the side of the source and drain conductive layer away from the substrate, the internal common signal line extends along the column direction, the orthographic projection of the virtual common electrode on the substrate is the first orthographic projection, the orthographic projection of the internal common signal line on the substrate is the second orthographic projection, and the edge of the first orthographic projection away from the display area is closer to the display area in the row direction than the edge of the second orthographic projection away from the display area.

[0012] In one embodiment of the present invention, the common electrode layer further includes a peripheral common signal line, and the gate layer further includes a virtual gate signal line. The peripheral common signal line is located on the periphery of the common electrode and includes a first sub-peripheral common signal line and a second sub-peripheral common signal line. The first sub-peripheral common signal line is located on the gate layer and is connected to the virtual gate trace. The virtual gate trace is connected to the virtual gate portion. The second sub-peripheral common signal line is located on the common electrode layer and is connected to the virtual common electrode.

[0013] In one embodiment of the present invention, the first sub-peripheral common signal line and the second sub-peripheral common signal line are connected through a third via.

[0014] In one embodiment of the present invention, a first strip opening is provided on the first sub-common signal line, the first strip opening extends along the column direction, and the source and drain conductive layer further includes a data trace, the orthographic projection of the data trace on the substrate overlaps with the orthographic projection of the first strip opening on the substrate.

[0015] In one embodiment of the present invention, at least two first strip openings are provided on the first sub-common signal line. The portion between the edges of the two first strip openings located at both ends in the column direction and the nearest edge of the first sub-common signal line is a first channel portion. The portion between the edges of two adjacent first strip openings in the column direction is a second channel portion. The width of the second channel portion is greater than the width of the first channel portion.

[0016] In one embodiment of the present invention, a second strip opening is provided on the second sub-common signal line. The second strip opening extends along the column direction, and the orthographic projection of the data trace on the substrate overlaps with the orthographic projection of the second strip opening on the substrate.

[0017] In one embodiment of the present invention, at least two second strip openings are provided on the second sub-common signal line. The portion between the edges of the two second strip openings located at both ends in the column direction and the nearest edge of the second sub-common signal line is a third channel portion. The portion between the edges of two adjacent second strip openings in the column direction is a fourth channel portion. The width of the fourth channel portion is greater than the width of the third channel portion.

[0018] In one embodiment of the present invention, the orthographic projection of the second strip opening on the substrate coincides with the orthographic projection of the first strip opening on the substrate.

[0019] In one embodiment of the present invention, the data trace includes a trace portion, the trace portion including a first data trace segment and a second data trace segment, the width of the second data trace segment being greater than the width of the first data trace segment, the orthographic projection of the first data trace segment on the substrate overlapping with the orthographic projections of the first channel portion and the second channel portion on the substrate, the orthographic projection of the second data trace segment on the substrate overlapping with the orthographic projection of the first strip opening on the substrate, and there is a gap between the edge of the orthographic projection of the second data trace segment on the substrate and the edge of the orthographic projection of the first strip opening on the substrate.

[0020] In one embodiment of the present invention, the orthographic projection of the second data trace segment on the substrate overlaps with the orthographic projection of the first channel portion on the substrate.

[0021] In one embodiment of the present invention, the virtual driving transistor includes a first virtual driving transistor and a second virtual driving transistor; the virtual gate line includes a first virtual gate line and a second virtual gate line; the first virtual gate line includes a first virtual gate portion; the second virtual gate line includes a second virtual gate portion; the virtual active portion includes a first virtual active portion and a second virtual active portion; the virtual source portion includes a first virtual source portion and a second virtual source portion; the virtual drain portion includes a first virtual drain portion and a second virtual drain portion; the orthographic projection of the first virtual gate portion on the substrate overlaps with the orthographic projection of the first virtual active portion on the substrate. A gate is formed for a first virtual driving transistor. A first virtual source is connected to a first virtual active portion to form the source of the first virtual driving transistor. A first virtual drain is connected to the first virtual active portion to form the drain of the first virtual driving transistor. The orthographic projection of a second virtual gate on the substrate overlaps with the orthographic projection of a second virtual active portion on the substrate to form the gate of a second virtual driving transistor. A second virtual source is connected to a second virtual active portion to form the source of the second virtual driving transistor. A second virtual drain is connected to a second virtual active portion to form the drain of the second virtual driving transistor.

[0022] In one embodiment of the present invention, the virtual pixel driving circuit includes a first virtual pixel driving circuit and a second virtual pixel driving circuit. The first virtual pixel driving circuit is disposed between two adjacent rows of pixel electrodes and includes a first virtual driving transistor and a second virtual driving transistor. The second virtual pixel driving circuit is disposed between the peripheral common signal line and the virtual pixel electrode farthest from the display area and includes either the first virtual driving transistor or the second virtual driving transistor.

[0023] In one embodiment of the present invention, the data trace further includes a first support portion, which is connected between adjacent trace portions in the column direction. The width of the first support portion in the row direction is greater than the width of the trace portion. The orthographic projection of the first support portion on the substrate does not overlap with the orthographic projection of the virtual gate line on the substrate.

[0024] In one embodiment of the present invention, the data trace further includes a second support portion, which is connected between adjacent trace portions in the column direction. A first gap is formed between the orthogonal projection of the first virtual gate portion on the substrate and the orthogonal projection of the second virtual gate portion on the substrate. The orthogonal projection of the first support portion on the substrate is disposed within the first gap. A second gap is formed between the orthogonal projection of the first virtual gate portion or the second virtual gate portion on the substrate and the orthogonal projection of the internal common signal line on the substrate. The orthogonal projection of the second support portion on the substrate is located within the second gap. The width of the second support portion in the row direction is greater than the width of the first support portion.

[0025] According to another aspect of this disclosure, a display device is provided, including a display panel provided in one aspect of this disclosure.

[0026] The display panel disclosed herein includes a virtual driving transistor. A reference signal is input to the gate and a virtual common electrode of the virtual driving transistor. The virtual common electrode is connected to the source of the virtual driving transistor, and a virtual pixel electrode is electrically connected to the source of the virtual driving transistor. This is equivalent to the virtual pixel electrode being connected to the reference signal, thus eliminating parasitic capacitance between the virtual pixel electrode and the virtual common electrode. When the virtual driving transistor is turned on, the floating drain of the virtual driving transistor is written with the reference signal. Therefore, both the drain and gate of the virtual driving transistor are reference signals, and there is no parasitic capacitance between the drain and gate of the virtual driving transistor. Therefore, this display panel can effectively reduce the load on the peripheral common signal line and improve the recovery speed after the reference signal voltage is pulled.

[0027] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0028] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0029] Figure 1 shows the circuit diagram of the virtual pixel driving circuit involved in the related technology when the source input data signal of the virtual transistor, the gate of the virtual driving transistor, and the virtual common electrode input common signal.

[0030] Figure 2 is a planar schematic diagram of a display panel when the source input data signal of the virtual transistor, the gate input signal of the virtual driving transistor, and the virtual common electrode input signal are common signals.

[0031] Figure 3 shows another planar schematic diagram of the display panel involved in the related technology when the source input data signal of the virtual transistor, the gate input common signal of the virtual driving transistor, and the virtual common electrode input common signal.

[0032] Figure 4 is a planar schematic diagram of a display panel according to an embodiment of this disclosure when the gate and virtual common electrode of the virtual driving transistor are input reference signals and the source of the virtual transistor is input reference signal.

[0033] Figure 5 is a partial schematic diagram of Figure 4.

[0034] Figure 6 is another partial schematic diagram of Figure 4.

[0035] Figure 7 is a circuit diagram of the virtual pixel driving circuit involved in this embodiment of the present disclosure when the gate and virtual common electrode of the virtual driving transistor are input reference signals and the source of the virtual transistor is input reference signal.

[0036] Figure 8 is another partial schematic diagram of Figure 4.

[0037] Figure 9 is a magnified view of part A in Figure 8.

[0038] Figure 10 is a plan view of the display panel according to an embodiment of the present disclosure when the edge of the first orthographic projection is closer to the display area in the row direction than the edge of the second orthographic projection.

[0039] Figure 11 is a magnified view of part B in Figure 10.

[0040] Figure 12 is a cross-sectional schematic diagram of the display panel involved in this embodiment when the virtual common electrode breaks at the edge of the protective layer.

[0041] Figure 13 is a cross-sectional schematic diagram of the display panel involved in this embodiment when the first sub-peripheral common signal line and the second sub-peripheral common signal line are connected through a via.

[0042] Figure 14 is a planar schematic diagram of the data traces involved in the present disclosure projected onto the substrate when the first strip opening is projected onto the substrate.

[0043] Figure 15 is a planar schematic diagram of the data traces involved in the present disclosure projected onto the substrate when the second strip opening is projected onto the substrate.

[0044] Figure 16 is a schematic diagram showing the distribution of the first strip opening on the first sub-peripheral common signal line according to an embodiment of this disclosure.

[0045] Figure 17 is a schematic diagram showing the distribution of the second strip opening on the second sub-peripheral common signal line according to an embodiment of this disclosure.

[0046] Figure 18 is a partial schematic diagram of Figure 14.

[0047] Schematic diagram.

[0048] In the figure: 1-substrate, 2-driving circuit layer, 21-gate layer, 211-gate line, 212-virtual gate portion, 2121-first virtual gate portion, 2122-second virtual gate portion, 213-virtual gate signal line, 214-first sub-peripheral common signal line, 2141-first strip opening, 2142-first channel portion, 2143-second channel portion, 22-active layer, 221-virtual active portion, 2 211-First virtual active section, 2212-Second virtual active section, 23-Source / drain conductive layer, 231-Virtual source section, 2311-First virtual source section, 2312-Second virtual source section, 232-Virtual drain section, 2321-First virtual drain section, 2322-Second virtual drain section, 233-Data trace, 2331-Trace section, 2332-First data trace segment, 2333-Second data trace Segment, 2334-First support part, 2335-Second support part, 234-Internal common signal line, 3-Pixel electrode layer, 31-Virtual pixel electrode, 4-Common electrode layer, 41-Virtual common electrode, 42-Transfer part, 43-Second sub-peripheral common signal line, 431-Second strip opening, 432-Third channel part, 433-Fourth channel part, 44-Connecting line, 5-Gate insulating layer, 6-Protective layer, 71-First gap, 72-Second gap, 8-Virtual pixel driving circuit, 81-Virtual driving transistor, 811-First virtual driving transistor, 812-Second virtual driving transistor, 801-First virtual pixel driving circuit, 802-Second virtual pixel driving circuit, 9-Display pixel driving circuit, 91-Display driving transistor, 10-GOA unit, 11-First via, 12-Second via, 13-Third via. Detailed Implementation

[0049] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0050] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0051] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0052] The voltage stability of the reference signal Vcom, which is applied to the external common signal line within the LCD panel, is crucial. If the voltage of the reference signal Vcom deviates and cannot be recovered quickly, it will affect the display quality, such as causing signal interference and image retention. One important factor affecting the rapid recovery of the reference signal Vcom is the load on the external common signal line. Reducing the load on the external common signal line can improve the recovery speed of the reference signal Vcom.

[0053] The display panel has a display area and a virtual pixel area, with the virtual pixel area located around the display area. The display panel includes a virtual pixel driving circuit 8 and virtual sub-pixels. The virtual pixel driving circuit 8 is located in the virtual pixel area and drives the virtual sub-pixels. Its main function is to buffer the process. The virtual sub-pixels only resemble the display sub-pixels in shape and are not used for image display. Therefore, the signal settings of the virtual sub-pixels are not entirely consistent with those of the display sub-pixels. The signals of the virtual sub-pixels are mainly controlled by the virtual pixel driving circuit 8.

[0054] As shown in Figure 1, the virtual pixel driving circuit 8 includes a virtual driving transistor 81, a virtual pixel electrode 31, and a virtual common electrode 41. The gate of the virtual driving transistor 81 and the virtual common electrode 41 input a common signal, the drain of the virtual transistor inputs a data signal Data, and the source of the virtual transistor is connected to the virtual pixel electrode 31. The data signal Data is transmitted from the source of the virtual transistor to the source of the virtual transistor. Therefore, the pixel electrode has the data signal Data. Since the data signal Data is different from the reference signal Vcom, a first parasitic capacitance is formed between the pixel electrode and the common electrode, and a second parasitic capacitance C2 is formed between the gate and the drain of the virtual driving transistor 81.

[0055] As shown in Figures 2 and 3, the display panel includes a substrate 1, a driving circuit layer 2, and a pixel electrode layer 3. The pixel electrode layer 3 and the driving circuit layer 2 are disposed on the same side of the display panel. The driving circuit layer 2 includes a gate layer 21, an active layer 22, and a source / drain conductive layer 23. The gate layer 21 is disposed on one side of the substrate, the active layer 22 is disposed on the side of the gate layer away from the substrate 1, and the source / drain conductive layer 23 is disposed on the side of the active layer 22 away from the substrate 1. The pixel electrode layer 3 can be disposed in the same layer as the virtual gate portion 21. It should be noted that "disposed in the same layer" here only means that the gate layer 21 and the pixel electrode layer 3 are both attached to the same side of the substrate 1, that is, the pixel electrode layer 3 and the virtual gate portion 21 are both disposed between the gate insulating layer 5 and the substrate 1. However, the materials of the pixel electrode layer 3 and the gate layer 21 are not the same, as shown in Figure 13.

[0056] The pixel electrode layer 3 includes a plurality of virtual pixel electrodes 31 arranged in an array, and the gate layer 21 includes virtual gate lines 211, which are disposed between two adjacent rows of virtual pixel electrodes 31. The source-drain conductive layer 23 includes data traces 233, and two virtual pixel electrodes 31 are disposed between every two adjacent data traces 233.

[0057] The virtual gate line 211 also includes a virtual gate portion 212 and a virtual gate signal line 213. The virtual gate signal line 213 is disposed on both sides of the virtual gate portion 212 along the column direction and extends in a direction away from each other along the row direction. The active layer 22 includes a virtual active portion 221. The source-drain conductive layer 23 also includes a virtual source portion 231 and a virtual drain portion 232. The orthographic projection of the virtual active portion 221 on the substrate 1 overlaps with the orthographic projection of the virtual gate portion 212 on the substrate 1 to form the gate of the driving transistor. The virtual source portion 231 and the virtual drain portion 232 are connected to the virtual active portion 221 to form the drain of the driving transistor. One end of the virtual source portion 231 that extends beyond the virtual active portion 221 is connected to the virtual pixel electrode 31.

[0058] The virtual gate portion 212 is disposed close to the data trace 233. The virtual drain portion 232 has a U-shaped structure, and the opening of the U-shaped virtual drain portion 232 is away from the adjacent data trace 233. The virtual source portion 231 has a straight shape and is surrounded by the virtual drain portion 232. The virtual drain portion 232 extends out of the virtual drain portion 232 in the row direction away from the data trace 233. The display panel also includes a common electrode layer 4, which is disposed on the side of the source and drain conductive layer 23 away from the substrate 1. The common electrode layer 4 also includes a transition portion 42, which is connected to the virtual source portion 231 and the virtual pixel electrode 31 through vias 11.

[0059] The virtual source portion 231 is extended along the row direction, and the virtual gate signal line 213 is bent along the column direction towards the virtual pixel electrode 31. A gate compensation portion is provided on the bent portion of the virtual gate signal line 213 to overlap with the virtual source portion 231, thereby compensating for the gate-source capacitance and preventing defects such as head-shaking patterns from appearing on the display screen when the gate layer 21, active layer 22 and source-drain conductive layer 23 are offset.

[0060] The source / drain conductive layer 23 also includes an internal common signal line 234, which is connected to the virtual source portion 231. The internal common signal line 234 extends along the column direction and is located between two adjacent columns of virtual pixel electrodes 31, on both sides of the data trace 233. The common electrode layer 4 includes a virtual common electrode 41, the orthographic projection of which on the substrate 1 overlaps with the orthographic projection of which on the substrate 1 is the internal common signal line 234. The virtual common electrode 41 is connected to the internal common signal line 234 through a via 11. A connecting line 44 is provided between two adjacent rows of virtual common electrodes 41, or the connecting line 44 can be connected to the internal common signal line 234 through a via 11. The common electrode layer 4 also includes a transition portion 42, which is connected to the virtual source portion 231 and the virtual pixel electrode 31 through a via 11.

[0061] The display panel also includes peripheral common signal lines, which are located around the common electrode. The peripheral common signal lines include a first sub-peripheral common signal line 214 and a second sub-peripheral common signal line 43. The first sub-peripheral common signal line 214 is located in the gate layer 21 and is connected to the virtual gate signal line 213. The virtual gate signal line 213 is connected to the virtual gate portion 212. The second sub-peripheral common signal line 43 is located in the common electrode layer 4 and is connected to the virtual common electrode 41.

[0062] The display panel includes a display pixel driving circuit 9 and display sub-pixels. The display pixel driving circuit 9 is located in the display area and drives the display sub-pixels. The structure of the display pixel driving circuit 9 is basically the same as that of the virtual pixel driving circuit 8, except that the display pixel driving circuit 9 includes a display driving transistor 91. The gate of the display driving transistor 91 is connected to the GOA unit 10-GOA, and the gate control signal is input from the GOA unit 10-GOA. This will not be described in detail here.

[0063] A reference signal Vcom can be loaded onto the peripheral common signal line. The reference signal Vcom is transmitted to the virtual gate section 212 via the first sub-peripheral common signal line 214, and to the virtual common electrode 41 via the second sub-peripheral common signal line 43. A data signal Data can be loaded onto the data trace 233. The data signal Data is transmitted to the virtual pixel electrode 31 via the data trace 233. The first parasitic capacitance formed between the pixel electrode and the common electrode is introduced onto the peripheral common signal line. The second parasitic capacitance C2 formed between the virtual gate section 212 and the virtual drain section 232 is also introduced onto the peripheral common signal line. The introduction of these two parasitic capacitances additionally increases the load on the peripheral common signal line, which is detrimental to the recovery of the reference signal Vcom after it has been pulled.

[0064] Based on this, the present invention provides a display panel. As shown in FIG1 and FIG4 to FIG16, the display panel has a display area and a virtual pixel area. The virtual pixel area is located on the periphery of the display area. The display panel includes a virtual pixel driving circuit 8, which is located in the virtual pixel area. The virtual pixel driving circuit 8 further includes a virtual driving transistor 81, a virtual pixel electrode 31, and a virtual common electrode 41. The gate of the virtual driving transistor 81 is input with a reference signal Vcom, the drain of the virtual driving transistor 81 is floating, and the virtual pixel electrode 31 is electrically connected to the source of the virtual driving transistor 81. The virtual common electrode 41 is connected to the source of the virtual driving transistor 81 and is input with the reference signal Vcom.

[0065] The gate of the virtual driving transistor 81 and the virtual common electrode 41 are connected to the reference signal Vcom. The virtual common electrode 41 is connected to the source of the virtual driving transistor 81, and the virtual pixel electrode 31 is electrically connected to the source of the virtual driving transistor 81. This is equivalent to the virtual pixel electrode 31 being connected to the reference signal Vcom. Therefore, there is no parasitic capacitance between the virtual pixel electrode 31 and the virtual common electrode 41. When the virtual driving transistor 81 is turned on, the floating drain of the virtual driving transistor 81 is written with the reference signal Vcom. Therefore, both the drain and gate of the virtual driving transistor 81 are the reference signal Vcom, and there is no parasitic capacitance between the drain and gate of the virtual driving transistor 81. Therefore, this display panel can effectively reduce the load on the peripheral common signal line and improve the recovery speed of the reference signal Vcom after its voltage is pulled.

[0066] The display panel involved in this invention will be described in detail below with reference to specific embodiments.

[0067] As shown in Figure 4, the virtual driving transistor 81 includes a first virtual driving transistor 811 and a second virtual driving transistor 812. The virtual gate line 211 includes a first virtual gate line 211 and a second virtual gate line 211. The first virtual gate line 211 includes a first virtual gate portion 2121, and the second virtual gate line 211 includes a second virtual gate portion 2122. The virtual active portion 221 includes a first virtual active portion 2211 and a second virtual active portion 2212. The virtual source portion 231 includes a first virtual source portion 2311 and a second virtual source portion 2312. The virtual drain portion 232 includes a first virtual drain portion 2321 and a second virtual drain portion 2322. The orthographic projection of the first virtual gate portion 2121 on the substrate 1 is the same as the orthographic projection of the first virtual active portion 2211 on the substrate 1. The shadows overlap to form the gate of the first virtual driving transistor 811. The first virtual source portion 2311 is connected to the first virtual active portion 2211 to form the source of the first virtual driving transistor 811. The first virtual drain portion 2321 is connected to the first virtual active portion 2211 to form the drain of the first virtual driving transistor 811. The orthographic projection of the second virtual gate portion 2122 on the substrate 1 overlaps with the orthographic projection of the second virtual active portion 2212 on the substrate 1 to form the gate of the second virtual driving transistor 812. The second virtual source portion 2312 is connected to the second virtual active portion 2212 to form the source of the second virtual driving transistor 812. The second virtual drain portion 2322 is connected to the second virtual active portion 2212 to form the drain of the second virtual driving transistor 812.

[0068] The virtual pixel driving circuit 8 includes a first virtual pixel driving circuit 801 and a second virtual pixel driving circuit 802. The first virtual pixel driving circuit 801 is located between two adjacent rows of virtual pixel electrodes 31 and includes a first virtual driving transistor 811 and a second virtual driving transistor 812. The second virtual pixel driving circuit 802 is located between the peripheral reference signal Vcom line and the virtual pixel electrode 31 farthest from the display area and includes either the first virtual driving transistor 811 or the second virtual driving transistor 812.

[0069] For the first virtual pixel driving circuit 801, the first virtual gate portion 2121 and the second virtual gate portion 2122 are located on both sides of the data trace 233 and are staggered in the column direction. The virtual gate signal line 213 of the first virtual gate line 211 and the virtual gate signal line 213 of the second virtual gate line 211 are parallel to each other. The first virtual drain portion 2321 and the second virtual drain portion 2322 are connected to the same data trace 233 and have different orientations in the row direction. The first virtual source portion 2311 and the second virtual source portion 2312 extend in directions that are far apart from each other.

[0070] As shown in Figures 5 and 6, the virtual drain 232 is disconnected from the data trace 233, thus cutting off the connection path between the data signal Data and the virtual pixel electrode 31. The internal common signal line 234 is connected to the virtual source 231, thereby transmitting the reference signal Vcom to the virtual pixel electrode 31 through the virtual source 231, thus forming the virtual pixel driving circuit 8 shown in the figure. As shown in Figure 7, the gate of the virtual driving transistor 81 receives the reference signal Vcom, the drain of the virtual driving transistor 81 is floating, the virtual pixel electrode 31 is electrically connected to the source of the virtual driving transistor 81, the virtual common electrode 41 is connected to the source of the virtual driving transistor 81, and the virtual common electrode 41 receives the reference signal Vcom.

[0071] Referring to Figure 1, the display panel also includes peripheral common signal lines located around the common electrode. The peripheral common signal lines include a first sub-peripheral common signal line 214 and a second sub-peripheral common signal line 43. The first sub-peripheral common signal line 214 is located in the gate layer 21. The gate layer 21 also includes a virtual gate signal line 213. The first sub-peripheral common signal line 214 is connected to the virtual gate signal line 213. The virtual gate signal line 213 is connected to the virtual gate portion 212. The second sub-peripheral common signal line 43 is located in the common electrode layer 4 and is connected to the virtual common electrode 41.

[0072] A reference signal Vcom can be loaded on the peripheral common signal line. The reference signal Vcom is transmitted to the virtual gate section 212 through the first sub-peripheral common signal line 214. The reference signal Vcom is transmitted to the virtual common electrode 41 through the second sub-peripheral common signal line 43, and then from the virtual common electrode 41 to the internal common signal line 234. Finally, from the internal common signal line 234 to the source of the virtual driving transistor 81, the virtual pixel electrode 31 is electrically connected to the source of the virtual driving transistor 81. This is equivalent to the virtual pixel electrode 31 being connected to the reference signal Vcom. Therefore, there is no parasitic capacitance between the virtual pixel electrode 31 and the virtual common electrode 41.

[0073] When the virtual driving transistor 81 is an n-type transistor, its drain is floating, meaning the voltage applied to the drain is 0V. The gate is connected to the reference signal Vcom, which is typically greater than or equal to 0V. Therefore, Vgs is also greater than or equal to 0V, and Vth must be less than 0V to satisfy Vgs > Vth, effectively turning the virtual driving transistor 81 on. Since the floating drain of the virtual driving transistor 81 is written with the reference signal Vcom, both the drain and gate of the virtual driving transistor 81 are connected to the reference signal Vcom, eliminating any parasitic capacitance between them.

[0074] In other embodiments, the virtual driving transistor 81 can also be a p-type transistor. When the virtual driving transistor 81 is a p-type transistor, the drain of the virtual driving transistor 81 is connected to the reference signal Vcom, and the gate of the virtual driving transistor 81 is connected to the reference signal Vcom. At this time, Vgs is equal to or greater than 0V, which satisfies Vgs < Vth, and the virtual driving transistor 81 can also be turned on.

[0075] Referring again to Figure 4, the data trace 233 also includes a first support portion 2334 and a second support portion 2335. The first support portion 2334 and the second support portion 2335 are connected between adjacent trace portions 2331 in the column direction. The width of the first support portion 2334 in the row direction is greater than the width of the trace portion 2331. A first gap 71 is formed between the orthographic projection of the first virtual gate portion 2121 on the substrate 1 and the orthographic projection of the second virtual gate portion 2122 on the substrate 1. The orthographic projection of the first support portion 2334 on the substrate 1 is disposed within the first gap 71.

[0076] The second gap 72 is formed between the orthographic projection of the first virtual gate portion 2121 or the second virtual gate portion 2122 on the substrate 1 and the orthographic projection of the internal common signal line 234 on the substrate 1. The orthographic projection of the second support portion 2335 on the substrate 1 is located within the second gap 72. Since one virtual gate line 211 of the second virtual pixel driving circuit 802 is removed, the width of the second gap 72 is greater than the width of the first gap 71. Therefore, the width of the second support portion 2335 in the row direction is greater than the width of the first support portion 2334. By filling the second gap 72 of the second support portion 2335, the supporting function of the other virtual gate line 211 that was removed from the outermost edge is replaced as much as possible. This prevents the first virtual pixel driving circuit 801 and the display pixel driving circuit 9 from having a support difference, and avoids the virtual pixel area from having a step difference with the display area in this area, which would lead to light leakage and reddish phenomena.

[0077] The orthographic projections of the first support portion 2334 and the second support portion 2335 on the substrate 1 do not overlap with the orthographic projection of the virtual gate line 211 on the substrate 1. As shown in Figures 8 and 9, the distance between the orthographic projection of the first support portion 2334 on the substrate 1 and the orthographic projection of the first virtual gate portion 2121 on the substrate 1 is a, where a ≥ (a1^2 + a2^2 + b1^2 + b2^2)^0.5, where a1 is the position deviation value of the gate layer 21, a2 is the width fluctuation value of the gate line 211, b1 is the position deviation value of the source / drain conductive layer 23, and b2 is the width fluctuation value of the data trace 233.

[0078] As shown in Figures 10 to 12, a gate insulating layer 5 is provided between the gate layer 21 and the source / drain conductive layer 23. A protective layer 6 is provided between the source / drain conductive layer 23 and the common electrode layer 4, covering the data trace 233 and the gate insulating layer 5. The internal common signal line 234 extends along the column direction. The orthographic projection of the virtual common electrode 41 on the substrate 1 is the first orthographic projection, and the orthographic projection of the internal common signal line 234 on the substrate 1 is the second orthographic projection. To prevent the virtual common electrode 41 from breaking at the edge of the protective layer 6, the edge of the first orthographic projection is set to be closer to the display area in the row direction than the edge of the second orthographic projection. It can be understood that the edge of the virtual common electrode 41 does not exceed the edge of the internal common signal line 234, which can prevent the virtual common electrode 41 from breaking at the edge of the protective layer 6, thereby preventing the virtual common electrode 41 from partially floating. As shown in Figure 12, when the edge of the first orthographic projection is farther from the display area in the row direction than the edge of the second orthographic projection, the virtual common electrode 41 breaks at the edge of the protective layer 6.

[0079] As shown in Figure 13, the first sub-peripheral common signal line 214 and the second sub-peripheral common signal line 43 are connected through via 11. By connecting the first sub-peripheral common signal line 214 and the second sub-peripheral common signal line 43 in parallel, the resistance of the peripheral common signal line can be reduced.

[0080] As shown in Figures 14 to 17, a first strip opening 2141 is provided on the first sub-common signal line, and a second strip opening 431 is provided on the second sub-common signal line. The first strip opening 2141 and the second strip opening 431 extend along the column direction. The orthographic projection of the data trace 233 on the substrate 1 overlaps with the orthographic projections of the first strip opening 2141 and the second strip opening 431 on the substrate 1, which can reduce the parasitic capacitance between the peripheral common signal line and the data trace 233. In this embodiment, the orthographic projection of the data trace 233 on the substrate 1 is within the orthographic projections of the first strip opening 2141 and the second strip opening 431 on the substrate 1.

[0081] The orthographic projection of the second strip opening 431 on the substrate 1 coincides with the orthographic projection of the first strip opening 2141 on the substrate 1. That is, the first strip opening 2141 and the second strip opening 431 have the same shape, size, and position, and the same mask can be used to form the first strip opening 2141 and the second strip opening 431. In other embodiments, the orthographic projection of the second strip opening 431 on the substrate 1 may not coincide with the orthographic projection of the first strip opening 2141 on the substrate 1, as long as the orthographic projection of the data trace 233 on the substrate 1 is within the orthographic projection of the first strip opening 2141 and the second strip opening 431 on the substrate 1. This can also reduce the parasitic capacitance between the peripheral common signal line and the data trace 233.

[0082] The first sub-common signal line has two first strip openings 2141. The portion between the edges of the two first strip openings 2141 located at both ends in the column direction and the nearest edge of the first sub-common signal line constitutes a first channel portion 2142. The portion between the edges of two adjacent first strip openings 2141 in the column direction constitutes a second channel portion 2143. The width of the second channel portion 2143 is greater than the width of the first channel portion 2142. The second sub-common signal line has two second strip openings 431. The portion between the edges of the two second strip openings 431 located at both ends in the column direction and the nearest edge of the second sub-common signal line constitutes a third channel portion 432. The portion between the edges of two adjacent second strip openings 431 in the column direction constitutes a fourth channel portion 433. The width of the fourth channel portion 433 is greater than the width of the third channel portion 432.

[0083] The width w1 of the first channel portion 2142 and the third channel portion 432 is smaller, while the width w2 of the second channel portion 2143 and the fourth channel portion 433 is larger. The resistance of the first channel portion 2142 and the third channel portion 432 is greater than that of the second channel portion 2143 and the fourth channel portion 433. If a large static charge passes through the peripheral common signal line, it will be released preferentially through the first channel portion 2142 and the third channel portion 432, while the second channel portion 2143 and the fourth channel portion 433 will still be conductive. In this embodiment, w1 ≥ minimum process linewidth, and w2 = 5w1. In other embodiments, the width w2 of the second channel portion 2143 and the fourth channel portion 433 can also be adjusted to w2 > 5w1 or w2 < 5w1.

[0084] As shown in Figure 18, the data trace 233 includes a trace portion 2331, which includes a first data trace segment 2332 and a second data trace segment 2333. The width of the second data trace segment 2333 is greater than the width of the first data trace segment 2332. The orthographic projection of the first data trace segment 2332 on the substrate 1 overlaps with the orthographic projections of the first channel portion 2142 and the second channel portion 2143 on the substrate 1. The orthographic projection of the second data trace segment 2333 on the substrate 1 overlaps with the orthographic projection of the first strip opening 2141 on the substrate 1. The first data trace segment 2332 is set to have a smaller width to reduce the overlap area between the data trace 233 and the peripheral common signal lines, thereby further reducing the parasitic capacitance between the data trace 233 and the peripheral common signal lines. The minimum width of the first data trace segment 2332 is greater than or equal to the minimum process linewidth.

[0085] There is a gap between the edge of the orthographic projection of the second data trace segment 2333 on the substrate 1 and the edge of the orthographic projection of the first strip opening 2141 on the substrate 1. The distance along the direction between the orthographic projection of the first strip opening 2141 on the substrate 1 and the data trace 233 is d1, where d1≥(a1^2+a2^2+b1^2+b2^2)^0.5, where a1 is the position deviation value of the gate layer 21, a2 is the width fluctuation value of the gate line 211, b1 is the position deviation value of the source / drain conductive layer 23, and b2 is the width fluctuation value of the data trace 233.

[0086] The orthographic projection of the second data trace segment 2333 on the substrate 1 overlaps with the orthographic projection of the first channel portion 2142 on the substrate 1. The overlap width of the orthographic projection of the second data trace segment 2333 on the substrate 1 and the orthographic projection of the first channel portion 2142 on the substrate 1 can be d2, where d2 ≥ (a1^2 + a2^2 + b1^2 + b2^2)^0.5. The tapering process from the edge d2 of the first strip opening 2141 along the first direction is to prevent breakage of the data trace 233 at the overlap position with the first strip opening 2141.

[0087] This display panel eliminates the parasitic capacitance between the virtual pixel electrode 31 and the virtual common electrode 41, as well as the parasitic capacitance between the drain and gate of the virtual drive transistor 81, thereby reducing the parasitic capacitance between the data trace 233 and the peripheral common signal line. Therefore, it effectively reduces the load on the peripheral common signal line and improves the recovery speed of the reference signal Vcom after its voltage is pulled.

[0088] This disclosure also provides a display device, which may include the display panel mentioned above in this disclosure. The specific structure and beneficial effects of the display device can be referred to the display panel, whose specific structure and beneficial effects have been described in detail above, and therefore will not be repeated here.

[0089] It should be noted that, in addition to the display panel, the display device also includes other necessary components and parts, such as the casing, circuit board, power cord, etc. Those skilled in the art can make corresponding additions according to the specific usage requirements of the display device, which will not be elaborated here.

[0090] Display devices can be traditional electronic devices, such as mobile phones, computers, televisions, and video recorders, or emerging wearable devices, such as virtual reality devices and augmented reality devices, which will not be listed here.

[0091] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A display panel having a display area and a virtual pixel area, wherein the virtual pixel area is disposed around the periphery of the display area, wherein, The display panel includes a virtual pixel driving circuit, which is disposed in the virtual pixel area. The virtual pixel driving circuit includes: A virtual driving transistor, wherein the gate of the virtual driving transistor is input with a reference signal and the drain of the virtual driving transistor is floating; The virtual pixel electrode is electrically connected to the source of the virtual driving transistor; A virtual common electrode is connected to the source of the virtual driving transistor, and the reference signal is input to the virtual common electrode.

2. The display panel according to claim 1, wherein, The display panel includes: Substrate; A gate layer, the gate layer including a virtual gate line, the virtual gate line including a virtual gate portion; An active layer, the active layer including a virtual active portion, wherein the orthographic projection of the gate layer on the substrate and the orthographic projection of the virtual active portion on the substrate overlap to form the gate of the virtual driving transistor; A source-drain conductive layer includes a virtual source portion, a virtual drain portion, and an internal common signal line. The orthographic projection of the virtual source portion on the substrate overlaps with the orthographic projection of the virtual active portion on the substrate to form the source of the virtual driving transistor. The orthographic projection of the virtual drain portion on the substrate overlaps with the orthographic projection of the virtual active portion on the substrate to form the drain of the virtual driving transistor. The internal common signal line is connected to the virtual source portion. A pixel electrode layer, including the virtual pixel electrode, wherein the virtual pixel electrode is connected to the virtual source electrode; A common electrode layer, the common electrode layer including the virtual common electrode, the orthographic projection of the virtual common electrode on the substrate overlaps with the orthographic projection of the internal common signal line on the substrate, and the virtual common electrode is connected to the internal common signal line through a first via.

3. The display panel according to claim 2, wherein, The common electrode layer also includes a transition section, which is connected to the virtual source electrode and the virtual pixel electrode through a second via.

4. The display panel according to claim 2, wherein, The common electrode layer is disposed on the side of the source / drain conductive layer away from the substrate. The internal common signal line extends along the column direction. The orthographic projection of the virtual common electrode on the substrate is a first orthographic projection. The orthographic projection of the internal common signal line on the substrate is a second orthographic projection. The edge of the first orthographic projection away from the display area is closer to the display area in the row direction than the edge of the second orthographic projection away from the display area.

5. The display panel according to claim 4, wherein, The common electrode layer further includes peripheral common signal lines located around the common electrode. The peripheral common signal lines include a first sub-peripheral common signal line and a second sub-peripheral common signal line. The first sub-peripheral common signal line is located in the gate layer. The virtual gate line further includes a virtual gate signal line. The first sub-peripheral common signal line is connected to the virtual gate signal line, and the virtual gate signal line is connected to the virtual gate portion. The second sub-peripheral common signal line is located in the common electrode layer and is connected to the virtual common electrode.

6. The display panel according to claim 5, wherein, The first sub-peripheral common signal line and the second sub-peripheral common signal line are connected through a third via.

7. The display panel according to claim 6, wherein, The first sub-common signal line is provided with a first strip opening, which extends along the column direction. The source and drain conductive layer also includes a data trace, the orthographic projection of which overlaps with the orthographic projection of the first strip opening on the substrate.

8. The display panel according to claim 7, wherein, The first sub-common signal line is provided with at least two first strip openings. The portion between the edges of the two first strip openings located at both ends in the column direction and the nearest edge of the first sub-common signal line is a first channel portion. The portion between the edges of two adjacent first strip openings in the column direction is a second channel portion. The width of the second channel portion is greater than the width of the first channel portion.

9. The display panel according to claim 8, wherein, The second sub-common signal line is provided with a second strip opening, which extends along the column direction. The orthographic projection of the data trace on the substrate overlaps with the orthographic projection of the second strip opening on the substrate.

10. The display panel according to claim 9, wherein, The second sub-common signal line is provided with at least two second strip openings. The portion between the edges of the two second strip openings located at both ends in the column direction and the nearest edge of the second sub-common signal line is a third channel portion. The portion between the edges of two adjacent second strip openings in the column direction is a fourth channel portion. The width of the fourth channel portion is greater than the width of the third channel portion.

11. The display panel according to claim 10, wherein, The orthographic projection of the second strip opening on the substrate coincides with the orthographic projection of the first strip opening on the substrate.

12. The display panel according to claim 8, wherein, The data trace includes a trace portion, which includes a first data trace segment and a second data trace segment. The width of the second data trace segment is greater than the width of the first data trace segment. The orthographic projection of the first data trace segment on the substrate overlaps with the orthographic projections of the first channel portion and the second channel portion on the substrate. The orthographic projection of the second data trace segment on the substrate overlaps with the orthographic projection of the first strip opening on the substrate. There is a gap between the edge of the orthographic projection of the second data trace segment on the substrate and the edge of the orthographic projection of the first strip opening on the substrate.

13. The display panel according to claim 12, wherein, The orthographic projection of the second data trace segment on the substrate overlaps with the orthographic projection of the first channel portion on the substrate.

14. The display panel according to claim 12, wherein, The virtual driving transistor includes a first virtual driving transistor and a second virtual driving transistor. The virtual gate line includes a first virtual gate line and a second virtual gate line. The first virtual gate line includes a first virtual gate portion, and the second virtual gate line includes a second virtual gate portion. The virtual active portion includes a first virtual active portion and a second virtual active portion. The virtual source portion includes a first virtual source portion and a second virtual source portion. The virtual drain portion includes a first virtual drain portion and a second virtual drain portion. The orthographic projection of the first virtual gate portion on the substrate overlaps with the orthographic projection of the first virtual active portion on the substrate to form the first virtual driving transistor. The gate of the first virtual driving transistor is formed by connecting the first virtual source portion to the first virtual active portion, and the first virtual drain portion to the first virtual active portion. The orthographic projection of the second virtual gate portion on the substrate overlaps with the orthographic projection of the second virtual active portion on the substrate to form the gate of the second virtual driving transistor. The second virtual source portion is connected to the second virtual active portion to form the source of the second virtual driving transistor, and the second virtual drain portion is connected to the second virtual active portion to form the drain of the second virtual driving transistor.

15. The display panel according to claim 14, wherein, The virtual pixel driving circuit includes a first virtual pixel driving circuit and a second virtual pixel driving circuit. The first virtual pixel driving circuit is disposed between two adjacent rows of pixel electrodes and includes a first virtual driving transistor and a second virtual driving transistor. The second virtual pixel driving circuit is disposed between the peripheral common signal line and the virtual pixel electrode farthest from the display area and includes either a first virtual driving transistor or a second virtual driving transistor.

16. The display panel according to claim 15, wherein, The data trace also includes a first support portion, which is connected between adjacent trace portions in the column direction. The width of the first support portion in the row direction is greater than the width of the trace portion. The orthographic projection of the first support portion on the substrate does not overlap with the orthographic projection of the virtual gate line on the substrate.

17. The display panel according to claim 16, wherein, The data trace also includes a second support portion, which is connected between adjacent trace portions in the column direction. A first gap is formed between the orthogonal projection of the first virtual gate portion on the substrate and the orthogonal projection of the second virtual gate portion on the substrate. The orthogonal projection of the first support portion on the substrate is disposed within the first gap. A second gap is formed between the orthogonal projection of the first virtual gate portion or the second virtual gate portion on the substrate and the orthogonal projection of the internal common signal line on the substrate. The orthogonal projection of the second support portion on the substrate is located within the second gap. The width of the second support portion in the row direction is greater than the width of the first support portion.

18. A display device, wherein, Includes the display panel as described in any one of claims 1 to 17.

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