Shield gate trench transistor, manufacturing method therefor and layout thereof

Abstract

The present invention provides a shield gate trench transistor, a manufacturing method therefor, and a layout thereof. Control gate structures are formed in first trenches, shield gate structures are formed in second trenches, each first trench surrounds the corresponding second trench, and in an extension direction of a semiconductor substrate, the first trench has a regular hexagonal shape, and the second trench is located at the center of the first trench, that is, a regular hexagonal control gate structure is formed, which increases the cell channel density and reduces the specific on-resistance (Rsp). Additionally, the shield gate structure is located at the center of the control gate structure, resulting in three-dimensional (3D) depletion, which further effectively reduces the specific on-resistance, and improves the performance of the shield gate trench transistor. Furthermore, the distances between the shield gate structures are consistent, and correspondingly, the charge balance is completely matched, thereby improving the breakdown stability of the shield gate trench transistor.

Description

Shielded gate trench transistor, its manufacturing method and layout

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese patent application No. 202411548406.3, filed on October 31, 2024, entitled "Shielded Gate Trench Transistor, Method of Manufacturing Thereof and Layout", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This invention relates to the field of semiconductor manufacturing technology, and in particular to a shielded gate trench transistor, its manufacturing method and layout. Background Technology

[0004] Shielded gate trench (SGT) transistors, with their advantages such as low specific on-resistance, low Miller capacitance, low power loss, small parasitic capacitance, high switching speed, and good high-frequency characteristics, are gaining an increasingly larger market share in low- and medium-voltage applications below 250V. However, the performance of existing SGT transistors is increasingly failing to meet the demands, and how to further improve the performance of SGT transistors has been a continuous pursuit for those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide a shielded gate trench transistor, its manufacturing method and layout, so as to improve the performance of the shielded gate trench transistor.

[0006] Accordingly, the present invention provides a shielded gate trench transistor, the shielded gate trench transistor comprising:

[0007] A semiconductor substrate having a plurality of first trenches and a plurality of second trenches formed therein, each first trench surrounding a corresponding second trench; in the extending direction of the semiconductor substrate, the second trench is located at the center of the first trench, and the first trench is hexagonal;

[0008] The control gate structure located in the first trench; and,

[0009] The shielding grid structure located in the second trench.

[0010] Optionally, in the shielded gate trench transistor, the second trench is deeper than the first trench.

[0011] Optionally, in the shielded gate trench transistor, the second trench is cylindrical or hexagonal.

[0012] Optionally, in the shielded gate trench transistor, adjacent first trenches are connected in the extending direction of the semiconductor substrate.

[0013] Optionally, in the shielded gate trench transistor, the control gate structure includes a control gate dielectric layer located in the first trench and a control gate electrode located on the control gate dielectric layer; the shielded gate structure includes a shielded gate dielectric layer located in the second trench and a shielded gate electrode located on the shielded gate dielectric layer.

[0014] Optionally, in the shielded gate trench transistor, the shielded gate trench transistor further includes:

[0015] A well region located in the semiconductor substrate, the well region being located in the semiconductor substrate between the first trench and the second trench;

[0016] A source region located within the well region, wherein, in the extension direction of the semiconductor substrate, the shape of the source region is the same as the shape of the well region; and,

[0017] The contact structure includes a first contact structure and a second contact structure connected to the first contact structure. The first contact structure is electrically connected to the source region, and the second contact structure is electrically connected to the shielding gate electrode. The first contact structure surrounds the second trench and is connected to the shielding gate dielectric layer.

[0018] Optionally, in the shielded gate trench transistor, the first contact structure is circular or hexagonal in the extension direction of the semiconductor substrate, and the second contact structure is strip-shaped.

[0019] Optionally, the second contact structure extends through the shielding grid structure.

[0020] Optionally, the plurality of the first trenches are arranged in a honeycomb pattern.

[0021] Optionally, the well region in the semiconductor substrate between adjacent first trenches and second trenches forms a ring structure surrounding the control gate structure, wherein the outer boundary of the ring structure is hexagonal.

[0022] The present invention also provides a method for manufacturing a shielded gate trench transistor, the method comprising:

[0023] Provide semiconductor substrates;

[0024] The semiconductor substrate is etched to form a plurality of first trenches and a plurality of second trenches in the semiconductor substrate, each first trench surrounding a corresponding second trench; in the extension direction of the semiconductor substrate, the second trench is located at the center of the first trench, and the first trench is hexagonal; and,

[0025] A control gate structure is formed in the first trench, and a shielding gate structure is formed in the second trench.

[0026] Optionally, in the method for manufacturing the shielded gate trench transistor, the method further includes:

[0027] A first ion implantation process is performed on the semiconductor substrate to form a first ion implantation region in the semiconductor substrate; and,

[0028] A second ion implantation process is performed on the first ion implantation region to form a second ion implantation region in the first ion implantation region;

[0029] The first trench and the second trench both penetrate the first ion implantation region and the second ion implantation region, so as to divide the first ion implantation region into multiple well regions and the second ion implantation region into multiple source regions.

[0030] The present invention also provides a shielded gate trench transistor layout, the shielded gate trench transistor layout comprising:

[0031] A first layer, comprising a plurality of first patterns, wherein the first patterns are regular hexagons; and

[0032] The second layer includes a plurality of second patterns, which are located within the first pattern.

[0033] Optionally, the center of the second pattern coincides with the center of the first pattern.

[0034] Optionally, the shielded gate trench transistor layout further includes a third layer, wherein the third layer includes a plurality of third patterns, wherein the third pattern includes a first pattern portion and a second pattern portion connected to the first pattern portion.

[0035] In the shielded gate trench transistor, its manufacturing method, and layout provided by this invention, a control gate structure is formed in a first trench, and a shielded gate structure is formed in a second trench. The first trench surrounds the corresponding second trench. In the extension direction of the semiconductor substrate, the first trench is hexagonal, and the second trench is located at the center of the first trench. That is, a hexagonal control gate structure is formed, increasing the cell channel density and reducing the specific on-resistance (Rsp). At the same time, the shielded gate structure is located at the center of the control gate structure, forming three-dimensional (3D) depletion, which further effectively reduces the specific on-resistance and improves the performance of the shielded gate trench transistor. Furthermore, the consistent spacing between the shielded gate structures results in a perfectly matched charge balance, improving the breakdown stability of the shielded gate trench transistor. Attached Figure Description

[0036] Figure 1 is a schematic cross-sectional view of the shielded gate trench transistor provided in an embodiment of the present invention.

[0037] Figure 2 is a three-dimensional structural schematic diagram of the shielded gate trench transistor provided in an embodiment of the present invention.

[0038] Figure 3 is a schematic diagram of the layout of the shielded gate trench transistor provided in an embodiment of the present invention.

[0039] Figure 4 is a schematic diagram of a shielded gate trench transistor layout.

[0040] The reference numerals in the attached figures are explained as follows:

[0041] 10-Shielded gate trench transistor; 100-Semiconductor substrate; 101-Silicon substrate; 102-Silicon epitaxial layer; 110-First trench; 120-Second trench; 130-Control gate structure; 131-Control gate dielectric layer; 132-Control gate electrode; 140-Shielded gate structure; 141-Shielded gate dielectric layer; 142-Shielded gate electrode; 150-Well region; 151-First ion implantation region; 160-Source region; 161-Second ion implantation region; 170-Contact structure; 171-First contact structure; 172-Second contact structure; 180-Dielectric layer.

[0042] 21, 21' - First pattern; 31, 31A, 31B, 31C, 31D, 34E, 31F, 31G, 31', 31A', 31B', 31C' - Second pattern; 41 - Third pattern; 410, 410' - First pattern section; 411 - Second pattern section; h1, h2, h3, h4, h5, h6, h1', h2' - Distance; S - Gap. Detailed Implementation

[0043] The shielded gate trench transistor, its manufacturing method, and layout proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0044] The terminology used in this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. Unless otherwise defined in this application, the technical or scientific terms used in this invention should be understood in their ordinary sense by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, "a" or "one," and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. "A plurality" or "several" indicates two or more. Unless otherwise indicated, terms such as "upper / upper layer," "lower / lower layer," and similar terms are for ease of description only and are not limited to a location or spatial orientation. Terms such as "comprising" or "including" mean that the element or object preceding "comprising" covers the element or object listed following "comprising" or "including" and its equivalents, and does not exclude other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections and can include electrical connections, whether direct or indirect. The singular forms “a,” “the,” and “the” used in this specification and appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0045] Please refer to Figures 1 and 2. Figure 1 is a cross-sectional view of the shielded gate trench transistor provided in an embodiment of the present invention; Figure 2 is a three-dimensional view of the shielded gate trench transistor provided in an embodiment of the present invention. As shown in Figures 1 and 2, this application provides a shielded gate trench transistor 10, which includes: a semiconductor substrate 100, in which a plurality of first trenches 110 and a plurality of second trenches 120 are formed, each of the first trenches 110 surrounding a corresponding second trench 120; in the extending direction of the semiconductor substrate 100, i.e., on the horizontal plane shown in Figure 2, the second trench 120 is located at the center of the first trench 110, and the first trench 110 is hexagonal, i.e., a hexagonal ring structure surrounding the second trench 120; a control gate structure 130 located in the first trench 110; and a shielded gate structure 140 located in the second trench 120.

[0046] In this embodiment, the control gate structure 130 is located in the first trench 110, and the shielding gate structure 140 is located in the second trench 120. Correspondingly, in the extension direction of the semiconductor substrate 100, the control gate structure 130 is hexagonal, and the shielding gate structure 140 is located at the center of the control gate structure 130. The hexagonal control gate structure 130 increases the cell channel density and reduces the specific on-resistance. Furthermore, the shielding gate structure 140, located at the center of the control gate structure 130, forms a three-dimensional (3D) depletion, further effectively reducing the specific on-resistance and improving the performance of the shielded gate trench transistor 10. Simultaneously, the consistent distance between the shielding gate structures 140 ensures a perfect charge balance, improving the breakdown stability of the shielded gate trench transistor 10.

[0047] As shown in Figures 1 and 2, the second trench 120 is deeper than the first trench 110. Specifically, both the first trench 110 and the second trench 120 extend from the surface of the semiconductor substrate 100 into the semiconductor substrate 100, wherein the depth of the second trench 120 is greater than the depth of the first trench 110. That is, the depth of the shielding gate structure 140 is greater than the depth of the control gate structure 130, thereby further improving charge balance and enhancing the breakdown stability of the shielding gate trench transistor 10.

[0048] The second trench 120 can be cylindrical or hexagonal, meaning it is circular or hexagonal in the extension direction of the semiconductor substrate 100. In this embodiment, the second trench 120 is circular. Preferably, the center of the second trench 120 coincides with the center of the first trench 110 to improve the consistency of the distance between adjacent shielding gate structures 140, thereby improving charge balance and the breakdown stability of the shielding gate trench transistor 10.

[0049] In the extending direction of the semiconductor substrate 100, adjacent first trenches 110 are connected. As shown in FIG2, the plurality of first trenches 110 are arranged in a honeycomb pattern, with one first trench 110 adjacent to six first trenches 110, and one side of two adjacent first trenches 110 overlapping or adjacent to each other. This maximizes the utilization of the area resources of the semiconductor substrate 100 and improves the consistency of the distance between adjacent shielding gate structures 140.

[0050] As shown in Figures 1 and 2, the control gate structure 130 includes a control gate dielectric layer 131 located in the first trench 110 and a control gate electrode 132 located on the control gate dielectric layer 131; the shielding gate structure 140 includes a shielding gate dielectric layer 141 located in the second trench 120 and a shielding gate electrode 142 located on the shielding gate dielectric layer 141. The control gate dielectric layer 131 and the shielding gate dielectric layer 141 can be made of oxide materials, and the control gate electrode 132 and the shielding gate electrode 142 can be made of polycrystalline silicon.

[0051] As shown in Figures 1 and 2, the shielded gate trench transistor 10 further includes a well region 150 located in the semiconductor substrate 100, between the first trench 110 and the second trench 120. Here, the well region 150 is connected to both the control gate structure 130 and the shielded gate structure 140. Specifically, the well region 150 is connected to both the control gate dielectric layer 131 and the shielded gate dielectric layer 141. That is, the well region 150 forms a ring-shaped structure surrounding the control gate structure 130. In this embodiment, the inner boundary of the ring-shaped structure is circular, and the outer boundary is hexagonal.

[0052] Furthermore, the shielded gate trench transistor 10 further includes a source region 160 located in the well region 150. The source region 160 extends from the surface of the well region 150 into the well region 150, that is, the source region 160 is connected to the control gate structure 130 and the shielded gate structure 140. In the extension direction of the semiconductor substrate 100, the shape of the source region 160 is the same as the shape of the well region.

[0053] In this embodiment, the shielded gate trench transistor 10 further includes a contact structure 170, which includes a first contact structure 171 and a second contact structure 172 connected to the first contact structure 171. The first contact structure 171 is electrically connected to the source region 160, and the second contact structure 172 is connected to the shielded gate electrode 142. The first contact structure 171 surrounds the second trench 120 and is connected to the shielded gate dielectric layer 141. That is, in this embodiment, the first contact structure 171 is annular in the extension direction of the semiconductor substrate 100. In other embodiments of this application, the first contact structure 171 may also be of other shapes to match the shape of the first trench 110. In this embodiment, the second contact structure 172 is strip-shaped. Here, in the extension direction of the semiconductor substrate 100, the second contact structure 172 penetrates the shielded gate structure 140, and further, passes through the center of the shielded gate structure 140, with its two ends respectively connected to the first contact structure 171.

[0054] Here, the first contact structure 171 and the second contact structure 172 are connected and have the same potential. Correspondingly, the active regions between them cannot form a channel. In this embodiment, the first contact structure 171 is connected to the shielding gate dielectric layer 141, which minimizes the waste of the active region area between the first contact structure 171 and the shielding gate structure 140, thereby increasing the area of ​​the current-conducting semiconductor region and improving the electrical performance of the shielding gate trench transistor 10.

[0055] Furthermore, the shielded gate trench transistor 10 may also include a drain region (not shown) located in the semiconductor substrate 100. Here, the source region 160 is located on a first surface of the semiconductor substrate 100, and the drain region is located on a second surface of the semiconductor substrate 100, with the first surface and the second surface opposite to each other.

[0056] In this embodiment, the electrical performance of a 100V shielded gate trench transistor 10 was simulated and tested. Its electric field and potential distribution were uniform, and its breakdown voltage reached 108V. Furthermore, the breakdown occurred at the bottom of the shielded gate structure 140, and impact ionization mainly occurred outside the functional region. This indicates that the shielded gate trench transistor 10 possesses excellent electrical performance. Further, comparing the specific on-resistance of the 100V shielded gate trench transistor 10 (whose control gate structure is a regular hexagon, and the corresponding cell is also a regular hexagon) with the specific on-resistance of a 100V shielded gate trench transistor in the prior art (whose control gate structure is a strip, and the corresponding cell is also a strip), the specific on-resistance of the 100V shielded gate trench transistor 10 was reduced by more than 40%. Therefore, the specific on-resistance of the shielded gate trench transistor 10 in this embodiment is effectively reduced.

[0057] Furthermore, this application embodiment also provides a method for manufacturing a shielded gate trench transistor, the method comprising:

[0058] Step S10: Provide a semiconductor substrate;

[0059] Step S20: Etching the semiconductor substrate to form a plurality of first trenches and a plurality of second trenches in the semiconductor substrate, each first trench surrounding a corresponding second trench; in the extension direction of the semiconductor substrate, the second trench is located at the center of the first trench, and the first trench is hexagonal; and,

[0060] Step S30: A control gate structure is formed in the first trench, and a shielding gate structure is formed in the second trench.

[0061] In this embodiment of the application, the manufacturing method of the shielded gate trench transistor further includes:

[0062] Step S40: Perform a first ion implantation process on the semiconductor substrate to form a first ion implantation region in the semiconductor substrate; and,

[0063] Step S50: Perform a second ion implantation process on the first ion implantation region to form a second ion implantation region in the first ion implantation region.

[0064] The first trench and the second trench both penetrate the first ion implantation region and the second ion implantation region, so as to divide the first ion implantation region into multiple well regions and the second ion implantation region into multiple source regions.

[0065] In this application, steps S20 and S30 may be executed before steps S40 and S50; alternatively, steps S40 and S50 may be executed first, followed by steps S20 and S30. Further, all of step S20 may be executed first, followed by all of step S30; alternatively, a portion of step S20 may be executed first (e.g., forming the first trench), followed by a portion of step S30 (e.g., forming the control gate structure), then another portion of step S20 (e.g., forming the second trench), and finally another portion of step S30 (e.g., forming the shielding gate structure). This application does not limit the specific execution of these steps.

[0066] Please continue referring to Figures 1 and 2. Specifically, a semiconductor substrate 100 is provided first. In this embodiment, the semiconductor substrate 100 may include a silicon substrate 101 and a silicon epitaxial layer 102 formed on the silicon substrate 101. In other embodiments of this application, the semiconductor substrate 100 may also include other structures and / or materials, such as a silicon carbide substrate.

[0067] Next, in one embodiment of this application, the semiconductor substrate 100 is etched to form a plurality of first trenches 110 in the semiconductor substrate 100. Specifically, a first mask (not shown in the figure) may be used, the first mask having at least one first mask pattern, the first mask pattern being a regular hexagon, and photolithography and etching processes are performed on the semiconductor substrate 100 using the first mask to form the first trenches 110 in the semiconductor substrate 100.

[0068] Next, a control gate dielectric material layer (not shown) is formed in the first trench 110, covering the surface of the first trench 110 and further covering the surface of the semiconductor substrate 100. Next, a control gate electrode material layer (not shown) is filled into the first trench 110, situated on the control gate dielectric material layer and filling the first trench 110. Further, the control gate electrode material layer and the control gate dielectric material layer on the surface of the semiconductor substrate 100 can be removed by a polishing process to form the control gate structure 130 in the first trench 110.

[0069] Next, the semiconductor substrate 100 is etched to form a plurality of second trenches 120 in the semiconductor substrate 100. Specifically, a second mask (not shown in the figure) can be used, the second mask having at least one second mask pattern. In this embodiment, the second mask pattern is circular. Photolithography and etching processes are performed on the semiconductor substrate 100 using the second mask to form the second trenches 120 in the semiconductor substrate 100. The second trenches 120 are located at the center of the first trenches 110, and the second trenches 120 are deeper than the first trenches 110.

[0070] Then, a shielding gate dielectric material layer (not shown) is formed in the second trench 120, the shielding gate dielectric material layer covering the surface of the second trench 120 and further covering the surface of the semiconductor substrate 100. Next, a shielding gate electrode material layer (not shown) is filled in the second trench 120, the shielding gate electrode material layer being located on the shielding gate dielectric material layer and filling the second trench 120. Further, the shielding gate electrode material layer and the shielding gate dielectric material layer on the surface of the semiconductor substrate 100 can be removed by a polishing process to form the shielding gate structure 140 in the second trench 120.

[0071] In this embodiment, a first ion implantation process, which can be a P-type ion implantation process, is then performed on the semiconductor substrate 100 to form a first ion implantation region 151 in the semiconductor substrate 100. The first trench 110, the control gate structure 130, the second trench 120, and the shielding gate structure 140 are deeper than the first ion implantation region 151; that is, the first trench 110, the control gate structure 130, the second trench 120, and the shielding gate structure 140 all penetrate the first ion implantation region 151, dividing the first ion implantation region 151 into multiple well regions 150.

[0072] In this embodiment, a second ion implantation process can be performed on the first ion implantation region 151. This second ion implantation process can be an N-type ion implantation process to form a second ion implantation region 161 within the first ion implantation region 151. The second ion implantation region 161 is shallower than the first ion implantation region 151; that is, the first trench 110, the control gate structure 130, the second trench 120, and the shielding gate structure 140 all penetrate the second ion implantation region 161, dividing it into multiple source regions 160.

[0073] Referring to Figure 1, in this embodiment, a dielectric layer 180 is then formed, covering the control gate structure 130, the shielding gate structure 140, and the surface of the semiconductor substrate 100. Contact openings (not shown in the figure) are formed in the dielectric layer 180, including a first opening (not shown) and a second opening (not shown) connected to the first opening. The first opening is circular, specifically an annular shape, exposing a portion of the source region 160, specifically the portion of the source region 160 connected to the shielding gate dielectric layer 141. In this embodiment, the first opening further extends into the source region 160, exposing a portion of the well region 150 connected to the shielding gate dielectric layer 141. The second opening is strip-shaped, exposing a portion of the shielding gate electrode 142.

[0074] Next, conductive material is filled into the contact opening to form the contact structure 170, wherein the contact structure 170 includes a first contact structure 171 and a second contact structure 172 connected to the first contact structure 171. The first contact structure 171 is electrically connected to the source region 160, and the second contact structure 172 is electrically connected to the shielding gate electrode 142. The first contact structure 171 surrounds the second trench 120 and is connected to the shielding gate dielectric layer 141.

[0075] Please refer to Figure 3. Furthermore, this application embodiment also provides a shielded gate trench transistor layout. As shown in Figure 3, the shielded gate trench transistor layout includes: a first layer (not shown in the figure), the first layer including a plurality of first patterns 21, the first patterns 21 being regular hexagons; and a second layer (not shown in the figure), the second layer including a plurality of second patterns 31, the second patterns 31 being located within the first patterns 21.

[0076] In this embodiment, the second pattern 31 is circular, and the center of the second pattern 31 (i.e., the center of the circle) coincides with the center of the first pattern 21. In other embodiments of this application, the second pattern 31 may also be other shapes, such as a regular hexagon.

[0077] Furthermore, the shielded gate trench transistor layout also includes a third layer (not shown in the figure), which comprises a plurality of third patterns 41. Each third pattern 41 includes a first pattern portion 410 and a second pattern portion 411 connected to the first pattern portion 410. The first pattern portion 410 surrounds and is connected to the second pattern 31. Here, the first pattern portion 410 is also circular; more specifically, it is an annular shape with an inner diameter equal to the radius of the second pattern 31. The second pattern portion 411 is strip-shaped, extending through the second pattern 31, and its length is equal to the radius of the second pattern 31.

[0078] In this embodiment of the application, the first pattern 21 corresponds to the control gate structure 130, the second pattern 31 corresponds to the shielding gate structure 140, and the third pattern 41 corresponds to the contact structure 170.

[0079] As shown in Figure 3, taking the second pattern 31A as an example, the distances h1, h2, h3, h4, h5, and h6 between it and the six adjacent second patterns 31B, 31C, 31D, 34E, 31F, and 31G are all equal. It can be more clearly seen that the consistent distances between the shielding gate structures 140 allow for complete charge balance matching, improving the breakdown stability of the shielded gate trench transistor 10. Comparing with Figure 4, if the shape of the first pattern 21' is changed from a regular hexagon to a square, taking the second pattern 31A' as an example, the distances between it and the adjacent second patterns 31B' and 31C' are h1' and h2', respectively. These distances are unequal, with h1' being greater than h2'. Consequently, this will lead to charge imbalance, with one segment being over-depleted while the other has not yet reached depletion, thus also causing unstable breakdown voltage. As can be seen in comparison, in this embodiment, by forming a regular hexagonal control gate structure 130, hexagonal cells are formed, making the distance between the shielding gate structures 140 consistent. Consequently, the charge balance is perfectly matched, improving the breakdown stability of the shielding gate trench transistor 10.

[0080] Referring to Figure 3, in this embodiment, the first patterned portion 410 surrounds and connects to the second pattern 31, meaning the first patterned portion 410 and the second pattern 31 are in contact. This means there is no waste of active area between the corresponding first contact structure 171 and the shielding gate structure 140, increasing the area of ​​the current-conducting semiconductor region and thus improving the electrical performance of the shielded gate trench transistor 10. Comparing this to Figure 4, if the second pattern 31' is circular and the first patterned portion 410' is square, there is a gap S between them, resulting in a corresponding waste of active area. Therefore, this embodiment, through the design of the contact structure 170 and the shielding gate structure 140, minimizes the waste of active area and improves the area of ​​the current-conducting semiconductor region and the electrical performance of the shielded gate trench transistor 10.

[0081] In summary, in the shielded gate trench transistor, its manufacturing method, and layout provided by this invention, a control gate structure is formed in a first trench, and a shielded gate structure is formed in a second trench. The first trench surrounds the corresponding second trench. In the extension direction of the semiconductor substrate, the first trench is hexagonal, and the second trench is located at the center of the first trench. That is, a hexagonal control gate structure is formed, increasing the cell channel density and reducing the specific on-resistance (Rsp). At the same time, the shielded gate structure is located at the center of the control gate structure, forming three-dimensional (3D) depletion, which further effectively reduces the specific on-resistance and improves the performance of the shielded gate trench transistor. Furthermore, the consistent spacing between the shielded gate structures ensures complete charge balance matching, improving the breakdown stability of the shielded gate trench transistor. Furthermore, the first contact structure connecting the source region surrounds the shielded gate structure and is connected to the shielded gate dielectric layer, minimizing the waste of the active region area and increasing the area of ​​the current-conducting semiconductor region and the electrical performance of the shielded gate trench transistor.

[0082] In this application, references to "one embodiment" or "some embodiments" mean that a feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment or at least some embodiments of this application. Therefore, the appearance of the phrases "in one embodiment" or "in some embodiments" throughout this application does not necessarily refer to the same or the same embodiments. Furthermore, in one or more embodiments, features, structures, or characteristics can be combined in any suitable combination and / or sub-combination.

[0083] While specific embodiments of this application have been described in detail by way of examples, those skilled in the art should understand that the above examples are for illustrative purposes only and not for limiting the scope of this application. The embodiments of this application can be combined in any way without departing from the spirit and scope of this application. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of this application. The scope of this application is defined by the appended claims.

Claims

1. A shielded gate trench transistor, characterized in that, The shielded gate trench transistor includes: A semiconductor substrate having a plurality of first trenches and a plurality of second trenches formed therein, each first trench surrounding a corresponding second trench; in the extending direction of the semiconductor substrate, the second trench is located at the center of the first trench, and the first trench is hexagonal; The control gate structure located in the first trench; and, The shielding grid structure located in the second trench.

2. The shielded gate trench transistor as described in claim 1, characterized in that, The second trench is deeper than the first trench.

3. The shielded gate trench transistor as described in claim 1, characterized in that, The second groove is cylindrical or hexagonal.

4. The shielded gate trench transistor according to any one of claims 1 to 3, wherein adjacent first trenches are connected in the extension direction of the semiconductor substrate.

5. The shielded gate trench transistor as described in any one of claims 1 to 3, characterized in that, The control gate structure includes a control gate dielectric layer located in the first trench and a control gate electrode located on the control gate dielectric layer; the shielding gate structure includes a shielding gate dielectric layer located in the second trench and a shielding gate electrode located on the shielding gate dielectric layer.

6. The shielded gate trench transistor as described in claim 5, characterized in that, The shielded gate trench transistor also includes: A well region located in the semiconductor substrate, the well region being located in the semiconductor substrate between the first trench and the second trench; A source region located within the well region, wherein, in the extension direction of the semiconductor substrate, the shape of the source region is the same as the shape of the well region; and, The contact structure includes a first contact structure and a second contact structure connected to the first contact structure. The first contact structure is electrically connected to the source region, and the second contact structure is electrically connected to the shielding gate electrode. The first contact structure surrounds the second trench and is connected to the shielding gate dielectric layer.

7. The shielded gate trench transistor as described in claim 6, characterized in that, In the extending direction of the semiconductor substrate, the first contact structure is circular or hexagonal, and the second contact structure is strip-shaped.

8. The shielded gate trench transistor as described in claim 7, characterized in that, The second contact structure extends through the shielding grid structure.

9. The shielded gate trench transistor as described in claim 1, characterized in that, The multiple first trenches are arranged in a honeycomb pattern.

10. The shielded gate trench transistor as described in claim 6, characterized in that, The well region in the semiconductor substrate between adjacent first and second trenches forms a ring structure surrounding the control gate structure, wherein the outer boundary of the ring structure is hexagonal.

11. A method for manufacturing a shielded gate trench transistor, characterized in that, The method for manufacturing the shielded gate trench transistor includes: Provide semiconductor substrates; The semiconductor substrate is etched to form a plurality of first trenches and a plurality of second trenches in the semiconductor substrate, each first trench surrounding a corresponding second trench; in the extension direction of the semiconductor substrate, the second trench is located at the center of the first trench, and the first trench is hexagonal; and, A control gate structure is formed in the first trench, and a shielding gate structure is formed in the second trench.

12. The method for manufacturing a shielded gate trench transistor as described in claim 11, characterized in that, The manufacturing method of the shielded gate trench transistor further includes: A first ion implantation process is performed on the semiconductor substrate to form a first ion implantation region in the semiconductor substrate; and, A second ion implantation process is performed on the first ion implantation region to form a second ion implantation region in the first ion implantation region; The first trench and the second trench both penetrate the first ion implantation region and the second ion implantation region, so as to divide the first ion implantation region into multiple well regions and the second ion implantation region into multiple source regions.

13. A shielded gate trench transistor layout, characterized in that, The shielded gate trench transistor layout includes: A first layer, comprising a plurality of first patterns, wherein the first patterns are regular hexagons; and The second layer includes a plurality of second patterns, which are located within the first pattern.

14. The shielded gate trench transistor layout as described in claim 13, characterized in that, The center of the second pattern coincides with the center of the first pattern.

15. The shielded gate trench transistor layout as described in claim 13, characterized in that, It also includes a third layer, wherein the third layer includes a plurality of third patterns, wherein the third pattern includes a first pattern portion and a second pattern portion connected to the first pattern portion.

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